FSConfig.py revision 10747 
1# Copyright (c) 2010-2012 ARM Limited
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3#
4# The license below extends only to copyright in the software and shall
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13# Copyright (c) 2010-2011 Advanced Micro Devices, Inc.
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34# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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39#
40# Authors: Kevin Lim
41
42from m5.objects import *
43from Benchmarks import *
44from m5.util import *
45
46# Populate to reflect supported os types per target ISA
47os_types = { 'alpha' : [ 'linux' ],
48             'mips'  : [ 'linux' ],
49             'sparc' : [ 'linux' ],
50             'x86'   : [ 'linux' ],
51             'arm'   : [ 'linux',
52                         'android-gingerbread',
53                         'android-ics',
54                         'android-jellybean',
55                         'android-kitkat' ],
56           }
57
58class CowIdeDisk(IdeDisk):
59    image = CowDiskImage(child=RawDiskImage(read_only=True),
60                         read_only=False)
61
62    def childImage(self, ci):
63        self.image.child.image_file = ci
64
65class MemBus(SystemXBar):
66    badaddr_responder = BadAddr()
67    default = Self.badaddr_responder.pio
68
69def fillInCmdline(mdesc, template, **kwargs):
70    kwargs.setdefault('disk', mdesc.disk())
71    kwargs.setdefault('rootdev', mdesc.rootdev())
72    kwargs.setdefault('mem', mdesc.mem())
73    kwargs.setdefault('script', mdesc.script())
74    return template % kwargs
75
76def makeLinuxAlphaSystem(mem_mode, mdesc=None, ruby=False, cmdline=None):
77
78    class BaseTsunami(Tsunami):
79        ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
80        ide = IdeController(disks=[Parent.disk0, Parent.disk2],
81                            pci_func=0, pci_dev=0, pci_bus=0)
82
83    self = LinuxAlphaSystem()
84    if not mdesc:
85        # generic system
86        mdesc = SysConfig()
87    self.readfile = mdesc.script()
88
89    self.tsunami = BaseTsunami()
90
91    # Create the io bus to connect all device ports
92    self.iobus = IOXBar()
93    self.tsunami.attachIO(self.iobus)
94
95    self.tsunami.ide.pio = self.iobus.master
96    self.tsunami.ide.config = self.iobus.master
97
98    self.tsunami.ethernet.pio = self.iobus.master
99    self.tsunami.ethernet.config = self.iobus.master
100
101    if ruby:
102        # Store the dma devices for later connection to dma ruby ports.
103        # Append an underscore to dma_ports to avoid the SimObjectVector check.
104        self._dma_ports = [self.tsunami.ide.dma, self.tsunami.ethernet.dma]
105    else:
106        self.membus = MemBus()
107
108        # By default the bridge responds to all addresses above the I/O
109        # base address (including the PCI config space)
110        IO_address_space_base = 0x80000000000
111        self.bridge = Bridge(delay='50ns',
112                         ranges = [AddrRange(IO_address_space_base, Addr.max)])
113        self.bridge.master = self.iobus.slave
114        self.bridge.slave = self.membus.master
115
116        self.tsunami.ide.dma = self.iobus.slave
117        self.tsunami.ethernet.dma = self.iobus.slave
118
119        self.system_port = self.membus.slave
120
121    self.mem_ranges = [AddrRange(mdesc.mem())]
122    self.disk0 = CowIdeDisk(driveID='master')
123    self.disk2 = CowIdeDisk(driveID='master')
124    self.disk0.childImage(mdesc.disk())
125    self.disk2.childImage(disk('linux-bigswap2.img'))
126    self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
127                                               read_only = True))
128    self.intrctrl = IntrControl()
129    self.mem_mode = mem_mode
130    self.terminal = Terminal()
131    self.kernel = binary('vmlinux')
132    self.pal = binary('ts_osfpal')
133    self.console = binary('console')
134    if not cmdline:
135        cmdline = 'root=/dev/hda1 console=ttyS0'
136    self.boot_osflags = fillInCmdline(mdesc, cmdline)
137
138    return self
139
140def makeSparcSystem(mem_mode, mdesc=None):
141    # Constants from iob.cc and uart8250.cc
142    iob_man_addr = 0x9800000000
143    uart_pio_size = 8
144
145    class CowMmDisk(MmDisk):
146        image = CowDiskImage(child=RawDiskImage(read_only=True),
147                             read_only=False)
148
149        def childImage(self, ci):
150            self.image.child.image_file = ci
151
152    self = SparcSystem()
153    if not mdesc:
154        # generic system
155        mdesc = SysConfig()
156    self.readfile = mdesc.script()
157    self.iobus = IOXBar()
158    self.membus = MemBus()
159    self.bridge = Bridge(delay='50ns')
160    self.t1000 = T1000()
161    self.t1000.attachOnChipIO(self.membus)
162    self.t1000.attachIO(self.iobus)
163    self.mem_ranges = [AddrRange(Addr('1MB'), size = '64MB'),
164                       AddrRange(Addr('2GB'), size ='256MB')]
165    self.bridge.master = self.iobus.slave
166    self.bridge.slave = self.membus.master
167    self.rom.port = self.membus.master
168    self.nvram.port = self.membus.master
169    self.hypervisor_desc.port = self.membus.master
170    self.partition_desc.port = self.membus.master
171    self.intrctrl = IntrControl()
172    self.disk0 = CowMmDisk()
173    self.disk0.childImage(disk('disk.s10hw2'))
174    self.disk0.pio = self.iobus.master
175
176    # The puart0 and hvuart are placed on the IO bus, so create ranges
177    # for them. The remaining IO range is rather fragmented, so poke
178    # holes for the iob and partition descriptors etc.
179    self.bridge.ranges = \
180        [
181        AddrRange(self.t1000.puart0.pio_addr,
182                  self.t1000.puart0.pio_addr + uart_pio_size - 1),
183        AddrRange(self.disk0.pio_addr,
184                  self.t1000.fake_jbi.pio_addr +
185                  self.t1000.fake_jbi.pio_size - 1),
186        AddrRange(self.t1000.fake_clk.pio_addr,
187                  iob_man_addr - 1),
188        AddrRange(self.t1000.fake_l2_1.pio_addr,
189                  self.t1000.fake_ssi.pio_addr +
190                  self.t1000.fake_ssi.pio_size - 1),
191        AddrRange(self.t1000.hvuart.pio_addr,
192                  self.t1000.hvuart.pio_addr + uart_pio_size - 1)
193        ]
194    self.reset_bin = binary('reset_new.bin')
195    self.hypervisor_bin = binary('q_new.bin')
196    self.openboot_bin = binary('openboot_new.bin')
197    self.nvram_bin = binary('nvram1')
198    self.hypervisor_desc_bin = binary('1up-hv.bin')
199    self.partition_desc_bin = binary('1up-md.bin')
200
201    self.system_port = self.membus.slave
202
203    return self
204
205def makeArmSystem(mem_mode, machine_type, num_cpus=1, mdesc=None,
206                  dtb_filename=None, bare_metal=False, cmdline=None):
207    assert machine_type
208
209    if bare_metal:
210        self = ArmSystem()
211    else:
212        self = LinuxArmSystem()
213
214    if not mdesc:
215        # generic system
216        mdesc = SysConfig()
217
218    self.readfile = mdesc.script()
219    self.iobus = IOXBar()
220    self.membus = MemBus()
221    self.membus.badaddr_responder.warn_access = "warn"
222    self.bridge = Bridge(delay='50ns')
223    self.bridge.master = self.iobus.slave
224    self.bridge.slave = self.membus.master
225
226    self.mem_mode = mem_mode
227
228    if machine_type == "RealView_PBX":
229        self.realview = RealViewPBX()
230    elif machine_type == "RealView_EB":
231        self.realview = RealViewEB()
232    elif machine_type == "VExpress_EMM":
233        self.realview = VExpress_EMM()
234        if not dtb_filename:
235            dtb_filename = 'vexpress.aarch32.ll_20131205.0-gem5.%dcpu.dtb' % num_cpus
236    elif machine_type == "VExpress_EMM64":
237        self.realview = VExpress_EMM64()
238        if os.path.split(mdesc.disk())[-1] == 'linux-aarch32-ael.img':
239            print "Selected 64-bit ARM architecture, updating default disk image..."
240            mdesc.diskname = 'linaro-minimal-aarch64.img'
241        if not dtb_filename:
242            dtb_filename = 'vexpress.aarch64.20140821.dtb'
243    else:
244        print "Unknown Machine Type"
245        sys.exit(1)
246
247    self.cf0 = CowIdeDisk(driveID='master')
248    self.cf0.childImage(mdesc.disk())
249
250    # Attach any PCI devices this platform supports
251    self.realview.attachPciDevices()
252    # default to an IDE controller rather than a CF one
253    try:
254        self.realview.ide.disks = [self.cf0]
255    except:
256        self.realview.cf_ctrl.disks = [self.cf0]
257
258    self.mem_ranges = []
259    size_remain = long(Addr(mdesc.mem()))
260    for region in self.realview._mem_regions:
261        if size_remain > long(region[1]):
262            self.mem_ranges.append(AddrRange(region[0], size=region[1]))
263            size_remain = size_remain - long(region[1])
264        else:
265            self.mem_ranges.append(AddrRange(region[0], size=size_remain))
266            size_remain = 0
267            break
268        warn("Memory size specified spans more than one region. Creating" \
269             " another memory controller for that range.")
270
271    if size_remain > 0:
272        fatal("The currently selected ARM platforms doesn't support" \
273              " the amount of DRAM you've selected. Please try" \
274              " another platform")
275
276    if bare_metal:
277        # EOT character on UART will end the simulation
278        self.realview.uart.end_on_eot = True
279    else:
280        if machine_type == "VExpress_EMM64":
281            self.kernel = binary('vmlinux.aarch64.20140821')
282        elif machine_type == "VExpress_EMM":
283            self.kernel = binary('vmlinux.aarch32.ll_20131205.0-gem5')
284        else:
285            self.kernel = binary('vmlinux.arm.smp.fb.2.6.38.8')
286
287        if dtb_filename:
288            self.dtb_filename = binary(dtb_filename)
289        self.machine_type = machine_type
290        # Ensure that writes to the UART actually go out early in the boot
291        if not cmdline:
292            cmdline = 'earlyprintk=pl011,0x1c090000 console=ttyAMA0 ' + \
293                      'lpj=19988480 norandmaps rw loglevel=8 ' + \
294                      'mem=%(mem)s root=%(rootdev)s'
295
296        self.realview.setupBootLoader(self.membus, self, binary)
297        self.gic_cpu_addr = self.realview.gic.cpu_addr
298        self.flags_addr = self.realview.realview_io.pio_addr + 0x30
299
300        # This check is for users who have previously put 'android' in
301        # the disk image filename to tell the config scripts to
302        # prepare the kernel with android-specific boot options. That
303        # behavior has been replaced with a more explicit option per
304        # the error message below. The disk can have any name now and
305        # doesn't need to include 'android' substring.
306        if (os.path.split(mdesc.disk())[-1]).lower().count('android'):
307            if 'android' not in mdesc.os_type():
308                fatal("It looks like you are trying to boot an Android " \
309                      "platform.  To boot Android, you must specify " \
310                      "--os-type with an appropriate Android release on " \
311                      "the command line.")
312
313        # android-specific tweaks
314        if 'android' in mdesc.os_type():
315            # generic tweaks
316            cmdline += " init=/init"
317
318            # release-specific tweaks
319            if 'kitkat' in mdesc.os_type():
320                cmdline += " androidboot.hardware=gem5 qemu=1 qemu.gles=0 " + \
321                           "android.bootanim=0"
322
323        self.boot_osflags = fillInCmdline(mdesc, cmdline)
324
325    self.realview.attachOnChipIO(self.membus, self.bridge)
326    self.realview.attachIO(self.iobus)
327    self.intrctrl = IntrControl()
328    self.terminal = Terminal()
329    self.vncserver = VncServer()
330
331    self.system_port = self.membus.slave
332
333    return self
334
335
336def makeLinuxMipsSystem(mem_mode, mdesc=None, cmdline=None):
337    class BaseMalta(Malta):
338        ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
339        ide = IdeController(disks=[Parent.disk0, Parent.disk2],
340                            pci_func=0, pci_dev=0, pci_bus=0)
341
342    self = LinuxMipsSystem()
343    if not mdesc:
344        # generic system
345        mdesc = SysConfig()
346    self.readfile = mdesc.script()
347    self.iobus = IOXBar()
348    self.membus = MemBus()
349    self.bridge = Bridge(delay='50ns')
350    self.mem_ranges = [AddrRange('1GB')]
351    self.bridge.master = self.iobus.slave
352    self.bridge.slave = self.membus.master
353    self.disk0 = CowIdeDisk(driveID='master')
354    self.disk2 = CowIdeDisk(driveID='master')
355    self.disk0.childImage(mdesc.disk())
356    self.disk2.childImage(disk('linux-bigswap2.img'))
357    self.malta = BaseMalta()
358    self.malta.attachIO(self.iobus)
359    self.malta.ide.pio = self.iobus.master
360    self.malta.ide.config = self.iobus.master
361    self.malta.ide.dma = self.iobus.slave
362    self.malta.ethernet.pio = self.iobus.master
363    self.malta.ethernet.config = self.iobus.master
364    self.malta.ethernet.dma = self.iobus.slave
365    self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
366                                               read_only = True))
367    self.intrctrl = IntrControl()
368    self.mem_mode = mem_mode
369    self.terminal = Terminal()
370    self.kernel = binary('mips/vmlinux')
371    self.console = binary('mips/console')
372    if not cmdline:
373        cmdline = 'root=/dev/hda1 console=ttyS0'
374    self.boot_osflags = fillInCmdline(mdesc, cmdline)
375
376    self.system_port = self.membus.slave
377
378    return self
379
380def x86IOAddress(port):
381    IO_address_space_base = 0x8000000000000000
382    return IO_address_space_base + port
383
384def connectX86ClassicSystem(x86_sys, numCPUs):
385    # Constants similar to x86_traits.hh
386    IO_address_space_base = 0x8000000000000000
387    pci_config_address_space_base = 0xc000000000000000
388    interrupts_address_space_base = 0xa000000000000000
389    APIC_range_size = 1 << 12;
390
391    x86_sys.membus = MemBus()
392
393    # North Bridge
394    x86_sys.iobus = IOXBar()
395    x86_sys.bridge = Bridge(delay='50ns')
396    x86_sys.bridge.master = x86_sys.iobus.slave
397    x86_sys.bridge.slave = x86_sys.membus.master
398    # Allow the bridge to pass through:
399    #  1) kernel configured PCI device memory map address: address range
400    #     [0xC0000000, 0xFFFF0000). (The upper 64kB are reserved for m5ops.)
401    #  2) the bridge to pass through the IO APIC (two pages, already contained in 1),
402    #  3) everything in the IO address range up to the local APIC, and
403    #  4) then the entire PCI address space and beyond.
404    x86_sys.bridge.ranges = \
405        [
406        AddrRange(0xC0000000, 0xFFFF0000),
407        AddrRange(IO_address_space_base,
408                  interrupts_address_space_base - 1),
409        AddrRange(pci_config_address_space_base,
410                  Addr.max)
411        ]
412
413    # Create a bridge from the IO bus to the memory bus to allow access to
414    # the local APIC (two pages)
415    x86_sys.apicbridge = Bridge(delay='50ns')
416    x86_sys.apicbridge.slave = x86_sys.iobus.master
417    x86_sys.apicbridge.master = x86_sys.membus.slave
418    x86_sys.apicbridge.ranges = [AddrRange(interrupts_address_space_base,
419                                           interrupts_address_space_base +
420                                           numCPUs * APIC_range_size
421                                           - 1)]
422
423    # connect the io bus
424    x86_sys.pc.attachIO(x86_sys.iobus)
425
426    x86_sys.system_port = x86_sys.membus.slave
427
428def connectX86RubySystem(x86_sys):
429    # North Bridge
430    x86_sys.iobus = IOXBar()
431
432    # add the ide to the list of dma devices that later need to attach to
433    # dma controllers
434    x86_sys._dma_ports = [x86_sys.pc.south_bridge.ide.dma]
435    x86_sys.pc.attachIO(x86_sys.iobus, x86_sys._dma_ports)
436
437
438def makeX86System(mem_mode, numCPUs=1, mdesc=None, self=None, Ruby=False):
439    if self == None:
440        self = X86System()
441
442    if not mdesc:
443        # generic system
444        mdesc = SysConfig()
445    self.readfile = mdesc.script()
446
447    self.mem_mode = mem_mode
448
449    # Physical memory
450    # On the PC platform, the memory region 0xC0000000-0xFFFFFFFF is reserved
451    # for various devices.  Hence, if the physical memory size is greater than
452    # 3GB, we need to split it into two parts.
453    excess_mem_size = \
454        convert.toMemorySize(mdesc.mem()) - convert.toMemorySize('3GB')
455    if excess_mem_size <= 0:
456        self.mem_ranges = [AddrRange(mdesc.mem())]
457    else:
458        warn("Physical memory size specified is %s which is greater than " \
459             "3GB.  Twice the number of memory controllers would be " \
460             "created."  % (mdesc.mem()))
461
462        self.mem_ranges = [AddrRange('3GB'),
463            AddrRange(Addr('4GB'), size = excess_mem_size)]
464
465    # Platform
466    self.pc = Pc()
467
468    # Create and connect the busses required by each memory system
469    if Ruby:
470        connectX86RubySystem(self)
471    else:
472        connectX86ClassicSystem(self, numCPUs)
473
474    self.intrctrl = IntrControl()
475
476    # Disks
477    disk0 = CowIdeDisk(driveID='master')
478    disk2 = CowIdeDisk(driveID='master')
479    disk0.childImage(mdesc.disk())
480    disk2.childImage(disk('linux-bigswap2.img'))
481    self.pc.south_bridge.ide.disks = [disk0, disk2]
482
483    # Add in a Bios information structure.
484    structures = [X86SMBiosBiosInformation()]
485    self.smbios_table.structures = structures
486
487    # Set up the Intel MP table
488    base_entries = []
489    ext_entries = []
490    for i in xrange(numCPUs):
491        bp = X86IntelMPProcessor(
492                local_apic_id = i,
493                local_apic_version = 0x14,
494                enable = True,
495                bootstrap = (i == 0))
496        base_entries.append(bp)
497    io_apic = X86IntelMPIOAPIC(
498            id = numCPUs,
499            version = 0x11,
500            enable = True,
501            address = 0xfec00000)
502    self.pc.south_bridge.io_apic.apic_id = io_apic.id
503    base_entries.append(io_apic)
504    # In gem5 Pc::calcPciConfigAddr(), it required "assert(bus==0)",
505    # but linux kernel cannot config PCI device if it was not connected to PCI bus,
506    # so we fix PCI bus id to 0, and ISA bus id to 1.
507    pci_bus = X86IntelMPBus(bus_id = 0, bus_type='PCI')
508    base_entries.append(pci_bus)
509    isa_bus = X86IntelMPBus(bus_id = 1, bus_type='ISA')
510    base_entries.append(isa_bus)
511    connect_busses = X86IntelMPBusHierarchy(bus_id=1,
512            subtractive_decode=True, parent_bus=0)
513    ext_entries.append(connect_busses)
514    pci_dev4_inta = X86IntelMPIOIntAssignment(
515            interrupt_type = 'INT',
516            polarity = 'ConformPolarity',
517            trigger = 'ConformTrigger',
518            source_bus_id = 0,
519            source_bus_irq = 0 + (4 << 2),
520            dest_io_apic_id = io_apic.id,
521            dest_io_apic_intin = 16)
522    base_entries.append(pci_dev4_inta)
523    def assignISAInt(irq, apicPin):
524        assign_8259_to_apic = X86IntelMPIOIntAssignment(
525                interrupt_type = 'ExtInt',
526                polarity = 'ConformPolarity',
527                trigger = 'ConformTrigger',
528                source_bus_id = 1,
529                source_bus_irq = irq,
530                dest_io_apic_id = io_apic.id,
531                dest_io_apic_intin = 0)
532        base_entries.append(assign_8259_to_apic)
533        assign_to_apic = X86IntelMPIOIntAssignment(
534                interrupt_type = 'INT',
535                polarity = 'ConformPolarity',
536                trigger = 'ConformTrigger',
537                source_bus_id = 1,
538                source_bus_irq = irq,
539                dest_io_apic_id = io_apic.id,
540                dest_io_apic_intin = apicPin)
541        base_entries.append(assign_to_apic)
542    assignISAInt(0, 2)
543    assignISAInt(1, 1)
544    for i in range(3, 15):
545        assignISAInt(i, i)
546    self.intel_mp_table.base_entries = base_entries
547    self.intel_mp_table.ext_entries = ext_entries
548
549def makeLinuxX86System(mem_mode, numCPUs=1, mdesc=None, Ruby=False,
550                       cmdline=None):
551    self = LinuxX86System()
552
553    # Build up the x86 system and then specialize it for Linux
554    makeX86System(mem_mode, numCPUs, mdesc, self, Ruby)
555
556    # We assume below that there's at least 1MB of memory. We'll require 2
557    # just to avoid corner cases.
558    phys_mem_size = sum(map(lambda r: r.size(), self.mem_ranges))
559    assert(phys_mem_size >= 0x200000)
560    assert(len(self.mem_ranges) <= 2)
561
562    entries = \
563       [
564        # Mark the first megabyte of memory as reserved
565        X86E820Entry(addr = 0, size = '639kB', range_type = 1),
566        X86E820Entry(addr = 0x9fc00, size = '385kB', range_type = 2),
567        # Mark the rest of physical memory as available
568        X86E820Entry(addr = 0x100000,
569                size = '%dB' % (self.mem_ranges[0].size() - 0x100000),
570                range_type = 1),
571        ]
572
573    # Mark [mem_size, 3GB) as reserved if memory less than 3GB, which force
574    # IO devices to be mapped to [0xC0000000, 0xFFFF0000). Requests to this
575    # specific range can pass though bridge to iobus.
576    if len(self.mem_ranges) == 1:
577        entries.append(X86E820Entry(addr = self.mem_ranges[0].size(),
578            size='%dB' % (0xC0000000 - self.mem_ranges[0].size()),
579            range_type=2))
580
581    # Reserve the last 16kB of the 32-bit address space for the m5op interface
582    entries.append(X86E820Entry(addr=0xFFFF0000, size='64kB', range_type=2))
583
584    # In case the physical memory is greater than 3GB, we split it into two
585    # parts and add a separate e820 entry for the second part.  This entry
586    # starts at 0x100000000,  which is the first address after the space
587    # reserved for devices.
588    if len(self.mem_ranges) == 2:
589        entries.append(X86E820Entry(addr = 0x100000000,
590            size = '%dB' % (self.mem_ranges[1].size()), range_type = 1))
591
592    self.e820_table.entries = entries
593
594    # Command line
595    if not cmdline:
596        cmdline = 'earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1'
597    self.boot_osflags = fillInCmdline(mdesc, cmdline)
598    self.kernel = binary('x86_64-vmlinux-2.6.22.9')
599    return self
600
601
602def makeDualRoot(full_system, testSystem, driveSystem, dumpfile):
603    self = Root(full_system = full_system)
604    self.testsys = testSystem
605    self.drivesys = driveSystem
606    self.etherlink = EtherLink()
607
608    if hasattr(testSystem, 'realview'):
609        self.etherlink.int0 = Parent.testsys.realview.ethernet.interface
610        self.etherlink.int1 = Parent.drivesys.realview.ethernet.interface
611    elif hasattr(testSystem, 'tsunami'):
612        self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface
613        self.etherlink.int1 = Parent.drivesys.tsunami.ethernet.interface
614    else:
615        fatal("Don't know how to connect these system together")
616
617    if dumpfile:
618        self.etherdump = EtherDump(file=dumpfile)
619        self.etherlink.dump = Parent.etherdump
620
621    return self
622