stats.txt revision 9289
12968SN/A 22968SN/A---------- Begin Simulation Statistics ---------- 39289Sandreas.hansson@arm.comsim_seconds 1.829331 # Number of seconds simulated 49289Sandreas.hansson@arm.comsim_ticks 1829330593000 # Number of ticks simulated 59289Sandreas.hansson@arm.comfinal_tick 1829330593000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 68721SN/Asim_freq 1000000000000 # Frequency of simulated ticks 79289Sandreas.hansson@arm.comhost_inst_rate 2569577 # Simulator instruction rate (inst/s) 89289Sandreas.hansson@arm.comhost_op_rate 2569575 # Simulator op (including micro ops) rate (op/s) 99289Sandreas.hansson@arm.comhost_tick_rate 78294086451 # Simulator tick rate (ticks/s) 109289Sandreas.hansson@arm.comhost_mem_usage 295292 # Number of bytes of host memory used 119289Sandreas.hansson@arm.comhost_seconds 23.37 # Real time elapsed on the host 129289Sandreas.hansson@arm.comsim_insts 60037737 # Number of instructions simulated 139289Sandreas.hansson@arm.comsim_ops 60037737 # Number of ops (including micro ops) simulated 149289Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.inst 857856 # Number of bytes read from this memory 159289Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.data 66839296 # Number of bytes read from this memory 169079SAli.Saidi@ARM.comsystem.physmem.bytes_read::tsunami.ide 2652288 # Number of bytes read from this memory 179289Sandreas.hansson@arm.comsystem.physmem.bytes_read::total 70349440 # Number of bytes read from this memory 189289Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu.inst 857856 # Number of instructions bytes read from this memory 199289Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::total 857856 # Number of instructions bytes read from this memory 209289Sandreas.hansson@arm.comsystem.physmem.bytes_written::writebacks 7411136 # Number of bytes written to this memory 219289Sandreas.hansson@arm.comsystem.physmem.bytes_written::total 7411136 # Number of bytes written to this memory 229289Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.inst 13404 # Number of read requests responded to by this memory 239289Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.data 1044364 # Number of read requests responded to by this memory 249079SAli.Saidi@ARM.comsystem.physmem.num_reads::tsunami.ide 41442 # Number of read requests responded to by this memory 259289Sandreas.hansson@arm.comsystem.physmem.num_reads::total 1099210 # Number of read requests responded to by this memory 269289Sandreas.hansson@arm.comsystem.physmem.num_writes::writebacks 115799 # Number of write requests responded to by this memory 279289Sandreas.hansson@arm.comsystem.physmem.num_writes::total 115799 # Number of write requests responded to by this memory 289289Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.inst 468945 # Total read bandwidth from this memory (bytes/s) 299289Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.data 36537571 # Total read bandwidth from this memory (bytes/s) 309289Sandreas.hansson@arm.comsystem.physmem.bw_read::tsunami.ide 1449868 # Total read bandwidth from this memory (bytes/s) 319289Sandreas.hansson@arm.comsystem.physmem.bw_read::total 38456384 # Total read bandwidth from this memory (bytes/s) 329289Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu.inst 468945 # Instruction read bandwidth from this memory (bytes/s) 339289Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::total 468945 # Instruction read bandwidth from this memory (bytes/s) 349289Sandreas.hansson@arm.comsystem.physmem.bw_write::writebacks 4051283 # Write bandwidth from this memory (bytes/s) 359289Sandreas.hansson@arm.comsystem.physmem.bw_write::total 4051283 # Write bandwidth from this memory (bytes/s) 369289Sandreas.hansson@arm.comsystem.physmem.bw_total::writebacks 4051283 # Total bandwidth to/from this memory (bytes/s) 379289Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.inst 468945 # Total bandwidth to/from this memory (bytes/s) 389289Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.data 36537571 # Total bandwidth to/from this memory (bytes/s) 399289Sandreas.hansson@arm.comsystem.physmem.bw_total::tsunami.ide 1449868 # Total bandwidth to/from this memory (bytes/s) 409289Sandreas.hansson@arm.comsystem.physmem.bw_total::total 42507667 # Total bandwidth to/from this memory (bytes/s) 418721SN/Asystem.iocache.replacements 41686 # number of replacements 429289Sandreas.hansson@arm.comsystem.iocache.tagsinuse 1.225558 # Cycle average of tags in use 438721SN/Asystem.iocache.total_refs 0 # Total number of references to valid blocks. 448721SN/Asystem.iocache.sampled_refs 41702 # Sample count of references to valid blocks. 458721SN/Asystem.iocache.avg_refs 0 # Average number of references to valid blocks. 469289Sandreas.hansson@arm.comsystem.iocache.warmup_cycle 1685780599067 # Cycle when the warmup percentage was hit. 479289Sandreas.hansson@arm.comsystem.iocache.occ_blocks::tsunami.ide 1.225558 # Average occupied blocks per requestor 489289Sandreas.hansson@arm.comsystem.iocache.occ_percent::tsunami.ide 0.076597 # Average percentage of cache occupancy 499289Sandreas.hansson@arm.comsystem.iocache.occ_percent::total 0.076597 # Average percentage of cache occupancy 508835SAli.Saidi@ARM.comsystem.iocache.ReadReq_misses::tsunami.ide 174 # number of ReadReq misses 518721SN/Asystem.iocache.ReadReq_misses::total 174 # number of ReadReq misses 528835SAli.Saidi@ARM.comsystem.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses 538721SN/Asystem.iocache.WriteReq_misses::total 41552 # number of WriteReq misses 548835SAli.Saidi@ARM.comsystem.iocache.demand_misses::tsunami.ide 41726 # number of demand (read+write) misses 558721SN/Asystem.iocache.demand_misses::total 41726 # number of demand (read+write) misses 568835SAli.Saidi@ARM.comsystem.iocache.overall_misses::tsunami.ide 41726 # number of overall misses 578721SN/Asystem.iocache.overall_misses::total 41726 # number of overall misses 588835SAli.Saidi@ARM.comsystem.iocache.ReadReq_accesses::tsunami.ide 174 # number of ReadReq accesses(hits+misses) 598721SN/Asystem.iocache.ReadReq_accesses::total 174 # number of ReadReq accesses(hits+misses) 608835SAli.Saidi@ARM.comsystem.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) 618721SN/Asystem.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) 628835SAli.Saidi@ARM.comsystem.iocache.demand_accesses::tsunami.ide 41726 # number of demand (read+write) accesses 638721SN/Asystem.iocache.demand_accesses::total 41726 # number of demand (read+write) accesses 648835SAli.Saidi@ARM.comsystem.iocache.overall_accesses::tsunami.ide 41726 # number of overall (read+write) accesses 658721SN/Asystem.iocache.overall_accesses::total 41726 # number of overall (read+write) accesses 668835SAli.Saidi@ARM.comsystem.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 679055Ssaidi@eecs.umich.edusystem.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 688835SAli.Saidi@ARM.comsystem.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses 699055Ssaidi@eecs.umich.edusystem.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 708835SAli.Saidi@ARM.comsystem.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 719055Ssaidi@eecs.umich.edusystem.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 728835SAli.Saidi@ARM.comsystem.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 739055Ssaidi@eecs.umich.edusystem.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 748721SN/Asystem.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 758721SN/Asystem.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 768721SN/Asystem.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 778721SN/Asystem.iocache.blocked::no_targets 0 # number of cycles access was blocked 788983Snate@binkert.orgsystem.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 798983Snate@binkert.orgsystem.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 808721SN/Asystem.iocache.fast_writes 0 # number of fast writes performed 818721SN/Asystem.iocache.cache_copies 0 # number of cache copies performed 828835SAli.Saidi@ARM.comsystem.iocache.writebacks::writebacks 41512 # number of writebacks 838835SAli.Saidi@ARM.comsystem.iocache.writebacks::total 41512 # number of writebacks 848721SN/Asystem.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 858721SN/Asystem.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 868721SN/Asystem.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 878721SN/Asystem.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 888721SN/Asystem.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 898721SN/Asystem.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 908721SN/Asystem.disk0.dma_write_txs 395 # Number of DMA write transactions. 918721SN/Asystem.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 928721SN/Asystem.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 938721SN/Asystem.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 948721SN/Asystem.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 958721SN/Asystem.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 968721SN/Asystem.disk2.dma_write_txs 1 # Number of DMA write transactions. 978721SN/Asystem.cpu.dtb.fetch_hits 0 # ITB hits 988721SN/Asystem.cpu.dtb.fetch_misses 0 # ITB misses 998721SN/Asystem.cpu.dtb.fetch_acv 0 # ITB acv 1008721SN/Asystem.cpu.dtb.fetch_accesses 0 # ITB accesses 1019289Sandreas.hansson@arm.comsystem.cpu.dtb.read_hits 9710417 # DTB read hits 1028721SN/Asystem.cpu.dtb.read_misses 10329 # DTB read misses 1038721SN/Asystem.cpu.dtb.read_acv 210 # DTB read access violations 1048721SN/Asystem.cpu.dtb.read_accesses 728856 # DTB read accesses 1059289Sandreas.hansson@arm.comsystem.cpu.dtb.write_hits 6352487 # DTB write hits 1068721SN/Asystem.cpu.dtb.write_misses 1142 # DTB write misses 1078721SN/Asystem.cpu.dtb.write_acv 157 # DTB write access violations 1088721SN/Asystem.cpu.dtb.write_accesses 291931 # DTB write accesses 1099289Sandreas.hansson@arm.comsystem.cpu.dtb.data_hits 16062904 # DTB hits 1106024SN/Asystem.cpu.dtb.data_misses 11471 # DTB misses 1118721SN/Asystem.cpu.dtb.data_acv 367 # DTB access violations 1128721SN/Asystem.cpu.dtb.data_accesses 1020787 # DTB accesses 1139289Sandreas.hansson@arm.comsystem.cpu.itb.fetch_hits 4974615 # ITB hits 1148721SN/Asystem.cpu.itb.fetch_misses 5006 # ITB misses 1158721SN/Asystem.cpu.itb.fetch_acv 184 # ITB acv 1169289Sandreas.hansson@arm.comsystem.cpu.itb.fetch_accesses 4979621 # ITB accesses 1178721SN/Asystem.cpu.itb.read_hits 0 # DTB read hits 1188721SN/Asystem.cpu.itb.read_misses 0 # DTB read misses 1198721SN/Asystem.cpu.itb.read_acv 0 # DTB read access violations 1208721SN/Asystem.cpu.itb.read_accesses 0 # DTB read accesses 1218721SN/Asystem.cpu.itb.write_hits 0 # DTB write hits 1228721SN/Asystem.cpu.itb.write_misses 0 # DTB write misses 1238721SN/Asystem.cpu.itb.write_acv 0 # DTB write access violations 1248721SN/Asystem.cpu.itb.write_accesses 0 # DTB write accesses 1256024SN/Asystem.cpu.itb.data_hits 0 # DTB hits 1266024SN/Asystem.cpu.itb.data_misses 0 # DTB misses 1278721SN/Asystem.cpu.itb.data_acv 0 # DTB access violations 1288721SN/Asystem.cpu.itb.data_accesses 0 # DTB accesses 1299289Sandreas.hansson@arm.comsystem.cpu.numCycles 3658661078 # number of cpu cycles simulated 1308721SN/Asystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 1318721SN/Asystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 1329289Sandreas.hansson@arm.comsystem.cpu.committedInsts 60037737 # Number of instructions committed 1339289Sandreas.hansson@arm.comsystem.cpu.committedOps 60037737 # Number of ops (including micro ops) committed 1349289Sandreas.hansson@arm.comsystem.cpu.num_int_alu_accesses 55912968 # Number of integer alu accesses 1358721SN/Asystem.cpu.num_fp_alu_accesses 324460 # Number of float alu accesses 1369289Sandreas.hansson@arm.comsystem.cpu.num_func_calls 1484174 # number of times a function call or return occured 1379289Sandreas.hansson@arm.comsystem.cpu.num_conditional_control_insts 7110641 # number of instructions that are conditional controls 1389289Sandreas.hansson@arm.comsystem.cpu.num_int_insts 55912968 # number of integer instructions 1398721SN/Asystem.cpu.num_fp_insts 324460 # number of float instructions 1409289Sandreas.hansson@arm.comsystem.cpu.num_int_register_reads 76953007 # number of times the integer registers were read 1419289Sandreas.hansson@arm.comsystem.cpu.num_int_register_writes 41739788 # number of times the integer registers were written 1428721SN/Asystem.cpu.num_fp_register_reads 163642 # number of times the floating registers were read 1438721SN/Asystem.cpu.num_fp_register_writes 166520 # number of times the floating registers were written 1449289Sandreas.hansson@arm.comsystem.cpu.num_mem_refs 16115688 # number of memory refs 1459289Sandreas.hansson@arm.comsystem.cpu.num_load_insts 9747503 # Number of load instructions 1469289Sandreas.hansson@arm.comsystem.cpu.num_store_insts 6368185 # Number of store instructions 1479289Sandreas.hansson@arm.comsystem.cpu.num_idle_cycles 3598606247.544791 # Number of idle cycles 1489289Sandreas.hansson@arm.comsystem.cpu.num_busy_cycles 60054830.455209 # Number of busy cycles 1499289Sandreas.hansson@arm.comsystem.cpu.not_idle_fraction 0.016414 # Percentage of non-idle cycles 1509289Sandreas.hansson@arm.comsystem.cpu.idle_fraction 0.983586 # Percentage of idle cycles 1512968SN/Asystem.cpu.kern.inst.arm 0 # number of arm instructions executed 1528721SN/Asystem.cpu.kern.inst.quiesce 6357 # number of quiesce instructions executed 1539289Sandreas.hansson@arm.comsystem.cpu.kern.inst.hwrei 211316 # number of hwrei instructions executed 1546291SN/Asystem.cpu.kern.ipl_count::0 74830 40.99% 40.99% # number of times we switched to this ipl 1556291SN/Asystem.cpu.kern.ipl_count::21 243 0.13% 41.12% # number of times we switched to this ipl 1566291SN/Asystem.cpu.kern.ipl_count::22 1866 1.02% 42.14% # number of times we switched to this ipl 1579289Sandreas.hansson@arm.comsystem.cpu.kern.ipl_count::31 105620 57.86% 100.00% # number of times we switched to this ipl 1589289Sandreas.hansson@arm.comsystem.cpu.kern.ipl_count::total 182559 # number of times we switched to this ipl 1596291SN/Asystem.cpu.kern.ipl_good::0 73463 49.29% 49.29% # number of times we switched to this ipl from a different ipl 1606291SN/Asystem.cpu.kern.ipl_good::21 243 0.16% 49.46% # number of times we switched to this ipl from a different ipl 1616291SN/Asystem.cpu.kern.ipl_good::22 1866 1.25% 50.71% # number of times we switched to this ipl from a different ipl 1626291SN/Asystem.cpu.kern.ipl_good::31 73463 49.29% 100.00% # number of times we switched to this ipl from a different ipl 1636127SN/Asystem.cpu.kern.ipl_good::total 149035 # number of times we switched to this ipl from a different ipl 1649289Sandreas.hansson@arm.comsystem.cpu.kern.ipl_ticks::0 1811925911500 99.05% 99.05% # number of cycles we spent at this ipl 1656291SN/Asystem.cpu.kern.ipl_ticks::21 20110000 0.00% 99.05% # number of cycles we spent at this ipl 1666291SN/Asystem.cpu.kern.ipl_ticks::22 80238000 0.00% 99.05% # number of cycles we spent at this ipl 1679289Sandreas.hansson@arm.comsystem.cpu.kern.ipl_ticks::31 17304126000 0.95% 100.00% # number of cycles we spent at this ipl 1689289Sandreas.hansson@arm.comsystem.cpu.kern.ipl_ticks::total 1829330385500 # number of cycles we spent at this ipl 1696127SN/Asystem.cpu.kern.ipl_used::0 0.981732 # fraction of swpipl calls that actually changed the ipl 1706127SN/Asystem.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 1716127SN/Asystem.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 1729289Sandreas.hansson@arm.comsystem.cpu.kern.ipl_used::31 0.695541 # fraction of swpipl calls that actually changed the ipl 1739289Sandreas.hansson@arm.comsystem.cpu.kern.ipl_used::total 0.816366 # fraction of swpipl calls that actually changed the ipl 1746291SN/Asystem.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed 1756291SN/Asystem.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed 1766291SN/Asystem.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed 1776291SN/Asystem.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed 1786291SN/Asystem.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed 1796291SN/Asystem.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed 1806291SN/Asystem.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed 1816291SN/Asystem.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed 1826291SN/Asystem.cpu.kern.syscall::20 6 1.84% 35.89% # number of syscalls executed 1836291SN/Asystem.cpu.kern.syscall::23 4 1.23% 37.12% # number of syscalls executed 1846291SN/Asystem.cpu.kern.syscall::24 6 1.84% 38.96% # number of syscalls executed 1856291SN/Asystem.cpu.kern.syscall::33 11 3.37% 42.33% # number of syscalls executed 1866291SN/Asystem.cpu.kern.syscall::41 2 0.61% 42.94% # number of syscalls executed 1876291SN/Asystem.cpu.kern.syscall::45 54 16.56% 59.51% # number of syscalls executed 1886291SN/Asystem.cpu.kern.syscall::47 6 1.84% 61.35% # number of syscalls executed 1896291SN/Asystem.cpu.kern.syscall::48 10 3.07% 64.42% # number of syscalls executed 1906291SN/Asystem.cpu.kern.syscall::54 10 3.07% 67.48% # number of syscalls executed 1916291SN/Asystem.cpu.kern.syscall::58 1 0.31% 67.79% # number of syscalls executed 1926291SN/Asystem.cpu.kern.syscall::59 7 2.15% 69.94% # number of syscalls executed 1936291SN/Asystem.cpu.kern.syscall::71 54 16.56% 86.50% # number of syscalls executed 1946291SN/Asystem.cpu.kern.syscall::73 3 0.92% 87.42% # number of syscalls executed 1956291SN/Asystem.cpu.kern.syscall::74 16 4.91% 92.33% # number of syscalls executed 1966291SN/Asystem.cpu.kern.syscall::87 1 0.31% 92.64% # number of syscalls executed 1976291SN/Asystem.cpu.kern.syscall::90 3 0.92% 93.56% # number of syscalls executed 1986291SN/Asystem.cpu.kern.syscall::92 9 2.76% 96.32% # number of syscalls executed 1996291SN/Asystem.cpu.kern.syscall::97 2 0.61% 96.93% # number of syscalls executed 2006291SN/Asystem.cpu.kern.syscall::98 2 0.61% 97.55% # number of syscalls executed 2016291SN/Asystem.cpu.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed 2026291SN/Asystem.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed 2036291SN/Asystem.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed 2046127SN/Asystem.cpu.kern.syscall::total 326 # number of syscalls executed 2058721SN/Asystem.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 2068721SN/Asystem.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed 2078721SN/Asystem.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed 2088721SN/Asystem.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed 2098721SN/Asystem.cpu.kern.callpal::swpctx 4177 2.17% 2.18% # number of callpals executed 2108721SN/Asystem.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed 2118721SN/Asystem.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed 2129289Sandreas.hansson@arm.comsystem.cpu.kern.callpal::swpipl 175246 91.19% 93.40% # number of callpals executed 2138721SN/Asystem.cpu.kern.callpal::rdps 6771 3.52% 96.92% # number of callpals executed 2148721SN/Asystem.cpu.kern.callpal::wrkgp 1 0.00% 96.92% # number of callpals executed 2158721SN/Asystem.cpu.kern.callpal::wrusp 7 0.00% 96.92% # number of callpals executed 2168721SN/Asystem.cpu.kern.callpal::rdusp 9 0.00% 96.93% # number of callpals executed 2178721SN/Asystem.cpu.kern.callpal::whami 2 0.00% 96.93% # number of callpals executed 2188721SN/Asystem.cpu.kern.callpal::rti 5203 2.71% 99.64% # number of callpals executed 2198721SN/Asystem.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed 2208721SN/Asystem.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed 2219289Sandreas.hansson@arm.comsystem.cpu.kern.callpal::total 192177 # number of callpals executed 2229289Sandreas.hansson@arm.comsystem.cpu.kern.mode_switch::kernel 5948 # number of protection mode switches 2239289Sandreas.hansson@arm.comsystem.cpu.kern.mode_switch::user 1735 # number of protection mode switches 2249289Sandreas.hansson@arm.comsystem.cpu.kern.mode_switch::idle 2098 # number of protection mode switches 2259289Sandreas.hansson@arm.comsystem.cpu.kern.mode_good::kernel 1906 2269289Sandreas.hansson@arm.comsystem.cpu.kern.mode_good::user 1735 2278721SN/Asystem.cpu.kern.mode_good::idle 171 2289289Sandreas.hansson@arm.comsystem.cpu.kern.mode_switch_good::kernel 0.320444 # fraction of useful protection mode switches 2298721SN/Asystem.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 2309289Sandreas.hansson@arm.comsystem.cpu.kern.mode_switch_good::idle 0.081506 # fraction of useful protection mode switches 2319289Sandreas.hansson@arm.comsystem.cpu.kern.mode_switch_good::total 0.389735 # fraction of useful protection mode switches 2329289Sandreas.hansson@arm.comsystem.cpu.kern.mode_ticks::kernel 26832734500 1.47% 1.47% # number of ticks spent at the given mode 2339289Sandreas.hansson@arm.comsystem.cpu.kern.mode_ticks::user 1465059000 0.08% 1.55% # number of ticks spent at the given mode 2349289Sandreas.hansson@arm.comsystem.cpu.kern.mode_ticks::idle 1801032591000 98.45% 100.00% # number of ticks spent at the given mode 2358721SN/Asystem.cpu.kern.swap_context 4178 # number of times the context was actually changed 2362968SN/Asystem.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 2372968SN/Asystem.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 2382968SN/Asystem.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 2392968SN/Asystem.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 2408721SN/Asystem.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 2418983Snate@binkert.orgsystem.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 2428721SN/Asystem.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 2438721SN/Asystem.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 2448983Snate@binkert.orgsystem.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 2458721SN/Asystem.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 2468721SN/Asystem.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 2478983Snate@binkert.orgsystem.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 2488721SN/Asystem.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR 2498721SN/Asystem.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 2508983Snate@binkert.orgsystem.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 2518721SN/Asystem.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 2528721SN/Asystem.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 2538983Snate@binkert.orgsystem.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 2548721SN/Asystem.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR 2558721SN/Asystem.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 2568983Snate@binkert.orgsystem.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 2578721SN/Asystem.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 2588721SN/Asystem.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 2598983Snate@binkert.orgsystem.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 2608721SN/Asystem.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 2618721SN/Asystem.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 2628983Snate@binkert.orgsystem.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 2638721SN/Asystem.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 2648983Snate@binkert.orgsystem.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 2658721SN/Asystem.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 2662968SN/Asystem.tsunami.ethernet.droppedPackets 0 # number of packets dropped 2679289Sandreas.hansson@arm.comsystem.cpu.icache.replacements 919577 # number of replacements 2689289Sandreas.hansson@arm.comsystem.cpu.icache.tagsinuse 511.215229 # Cycle average of tags in use 2699289Sandreas.hansson@arm.comsystem.cpu.icache.total_refs 59129371 # Total number of references to valid blocks. 2709289Sandreas.hansson@arm.comsystem.cpu.icache.sampled_refs 920089 # Sample count of references to valid blocks. 2719289Sandreas.hansson@arm.comsystem.cpu.icache.avg_refs 64.264839 # Average number of references to valid blocks. 2728721SN/Asystem.cpu.icache.warmup_cycle 9686972500 # Cycle when the warmup percentage was hit. 2739289Sandreas.hansson@arm.comsystem.cpu.icache.occ_blocks::cpu.inst 511.215229 # Average occupied blocks per requestor 2748835SAli.Saidi@ARM.comsystem.cpu.icache.occ_percent::cpu.inst 0.998467 # Average percentage of cache occupancy 2758835SAli.Saidi@ARM.comsystem.cpu.icache.occ_percent::total 0.998467 # Average percentage of cache occupancy 2769289Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::cpu.inst 59129371 # number of ReadReq hits 2779289Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::total 59129371 # number of ReadReq hits 2789289Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::cpu.inst 59129371 # number of demand (read+write) hits 2799289Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::total 59129371 # number of demand (read+write) hits 2809289Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::cpu.inst 59129371 # number of overall hits 2819289Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::total 59129371 # number of overall hits 2829289Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::cpu.inst 920204 # number of ReadReq misses 2839289Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::total 920204 # number of ReadReq misses 2849289Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::cpu.inst 920204 # number of demand (read+write) misses 2859289Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::total 920204 # number of demand (read+write) misses 2869289Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::cpu.inst 920204 # number of overall misses 2879289Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::total 920204 # number of overall misses 2889289Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::cpu.inst 60049575 # number of ReadReq accesses(hits+misses) 2899289Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::total 60049575 # number of ReadReq accesses(hits+misses) 2909289Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::cpu.inst 60049575 # number of demand (read+write) accesses 2919289Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::total 60049575 # number of demand (read+write) accesses 2929289Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::cpu.inst 60049575 # number of overall (read+write) accesses 2939289Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::total 60049575 # number of overall (read+write) accesses 2948835SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.015324 # miss rate for ReadReq accesses 2959055Ssaidi@eecs.umich.edusystem.cpu.icache.ReadReq_miss_rate::total 0.015324 # miss rate for ReadReq accesses 2968835SAli.Saidi@ARM.comsystem.cpu.icache.demand_miss_rate::cpu.inst 0.015324 # miss rate for demand accesses 2979055Ssaidi@eecs.umich.edusystem.cpu.icache.demand_miss_rate::total 0.015324 # miss rate for demand accesses 2988835SAli.Saidi@ARM.comsystem.cpu.icache.overall_miss_rate::cpu.inst 0.015324 # miss rate for overall accesses 2999055Ssaidi@eecs.umich.edusystem.cpu.icache.overall_miss_rate::total 0.015324 # miss rate for overall accesses 3008721SN/Asystem.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 3018721SN/Asystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 3028721SN/Asystem.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 3038721SN/Asystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 3048983Snate@binkert.orgsystem.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 3058983Snate@binkert.orgsystem.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 3068721SN/Asystem.cpu.icache.fast_writes 0 # number of fast writes performed 3078721SN/Asystem.cpu.icache.cache_copies 0 # number of cache copies performed 3088721SN/Asystem.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 3099289Sandreas.hansson@arm.comsystem.cpu.dcache.replacements 2042708 # number of replacements 3108721SN/Asystem.cpu.dcache.tagsinuse 511.997802 # Cycle average of tags in use 3119289Sandreas.hansson@arm.comsystem.cpu.dcache.total_refs 14038404 # Total number of references to valid blocks. 3129289Sandreas.hansson@arm.comsystem.cpu.dcache.sampled_refs 2043220 # Sample count of references to valid blocks. 3139289Sandreas.hansson@arm.comsystem.cpu.dcache.avg_refs 6.870726 # Average number of references to valid blocks. 3148721SN/Asystem.cpu.dcache.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. 3158835SAli.Saidi@ARM.comsystem.cpu.dcache.occ_blocks::cpu.data 511.997802 # Average occupied blocks per requestor 3168835SAli.Saidi@ARM.comsystem.cpu.dcache.occ_percent::cpu.data 0.999996 # Average percentage of cache occupancy 3178835SAli.Saidi@ARM.comsystem.cpu.dcache.occ_percent::total 0.999996 # Average percentage of cache occupancy 3189289Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::cpu.data 7807768 # number of ReadReq hits 3199289Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::total 7807768 # number of ReadReq hits 3209289Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_hits::cpu.data 5848199 # number of WriteReq hits 3219289Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_hits::total 5848199 # number of WriteReq hits 3229289Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_hits::cpu.data 183140 # number of LoadLockedReq hits 3239289Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_hits::total 183140 # number of LoadLockedReq hits 3249289Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_hits::cpu.data 199281 # number of StoreCondReq hits 3259289Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_hits::total 199281 # number of StoreCondReq hits 3269289Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::cpu.data 13655967 # number of demand (read+write) hits 3279289Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::total 13655967 # number of demand (read+write) hits 3289289Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::cpu.data 13655967 # number of overall hits 3299289Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::total 13655967 # number of overall hits 3309289Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::cpu.data 1721710 # number of ReadReq misses 3319289Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::total 1721710 # number of ReadReq misses 3329289Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::cpu.data 304365 # number of WriteReq misses 3339289Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::total 304365 # number of WriteReq misses 3348835SAli.Saidi@ARM.comsystem.cpu.dcache.LoadLockedReq_misses::cpu.data 17162 # number of LoadLockedReq misses 3358721SN/Asystem.cpu.dcache.LoadLockedReq_misses::total 17162 # number of LoadLockedReq misses 3369289Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::cpu.data 2026075 # number of demand (read+write) misses 3379289Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::total 2026075 # number of demand (read+write) misses 3389289Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::cpu.data 2026075 # number of overall misses 3399289Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::total 2026075 # number of overall misses 3409289Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::cpu.data 9529478 # number of ReadReq accesses(hits+misses) 3419289Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::total 9529478 # number of ReadReq accesses(hits+misses) 3429289Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_accesses::cpu.data 6152564 # number of WriteReq accesses(hits+misses) 3439289Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_accesses::total 6152564 # number of WriteReq accesses(hits+misses) 3449289Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::cpu.data 200302 # number of LoadLockedReq accesses(hits+misses) 3459289Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::total 200302 # number of LoadLockedReq accesses(hits+misses) 3469289Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_accesses::cpu.data 199281 # number of StoreCondReq accesses(hits+misses) 3479289Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_accesses::total 199281 # number of StoreCondReq accesses(hits+misses) 3489289Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::cpu.data 15682042 # number of demand (read+write) accesses 3499289Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::total 15682042 # number of demand (read+write) accesses 3509289Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::cpu.data 15682042 # number of overall (read+write) accesses 3519289Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::total 15682042 # number of overall (read+write) accesses 3529079SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.180672 # miss rate for ReadReq accesses 3539079SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_miss_rate::total 0.180672 # miss rate for ReadReq accesses 3549289Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049470 # miss rate for WriteReq accesses 3559289Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_rate::total 0.049470 # miss rate for WriteReq accesses 3569289Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085681 # miss rate for LoadLockedReq accesses 3579289Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_rate::total 0.085681 # miss rate for LoadLockedReq accesses 3589079SAli.Saidi@ARM.comsystem.cpu.dcache.demand_miss_rate::cpu.data 0.129197 # miss rate for demand accesses 3599079SAli.Saidi@ARM.comsystem.cpu.dcache.demand_miss_rate::total 0.129197 # miss rate for demand accesses 3609079SAli.Saidi@ARM.comsystem.cpu.dcache.overall_miss_rate::cpu.data 0.129197 # miss rate for overall accesses 3619079SAli.Saidi@ARM.comsystem.cpu.dcache.overall_miss_rate::total 0.129197 # miss rate for overall accesses 3628721SN/Asystem.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 3638721SN/Asystem.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 3648721SN/Asystem.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 3658721SN/Asystem.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 3668983Snate@binkert.orgsystem.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 3678983Snate@binkert.orgsystem.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 3688721SN/Asystem.cpu.dcache.fast_writes 0 # number of fast writes performed 3698721SN/Asystem.cpu.dcache.cache_copies 0 # number of cache copies performed 3709079SAli.Saidi@ARM.comsystem.cpu.dcache.writebacks::writebacks 833491 # number of writebacks 3719079SAli.Saidi@ARM.comsystem.cpu.dcache.writebacks::total 833491 # number of writebacks 3728721SN/Asystem.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 3739289Sandreas.hansson@arm.comsystem.cpu.l2cache.replacements 992297 # number of replacements 3749289Sandreas.hansson@arm.comsystem.cpu.l2cache.tagsinuse 65424.375500 # Cycle average of tags in use 3759289Sandreas.hansson@arm.comsystem.cpu.l2cache.total_refs 2433229 # Total number of references to valid blocks. 3769289Sandreas.hansson@arm.comsystem.cpu.l2cache.sampled_refs 1057460 # Sample count of references to valid blocks. 3779289Sandreas.hansson@arm.comsystem.cpu.l2cache.avg_refs 2.301013 # Average number of references to valid blocks. 3789289Sandreas.hansson@arm.comsystem.cpu.l2cache.warmup_cycle 614754000 # Cycle when the warmup percentage was hit. 3799289Sandreas.hansson@arm.comsystem.cpu.l2cache.occ_blocks::writebacks 56309.097195 # Average occupied blocks per requestor 3809289Sandreas.hansson@arm.comsystem.cpu.l2cache.occ_blocks::cpu.inst 4867.351144 # Average occupied blocks per requestor 3819289Sandreas.hansson@arm.comsystem.cpu.l2cache.occ_blocks::cpu.data 4247.927161 # Average occupied blocks per requestor 3829289Sandreas.hansson@arm.comsystem.cpu.l2cache.occ_percent::writebacks 0.859209 # Average percentage of cache occupancy 3839289Sandreas.hansson@arm.comsystem.cpu.l2cache.occ_percent::cpu.inst 0.074270 # Average percentage of cache occupancy 3849289Sandreas.hansson@arm.comsystem.cpu.l2cache.occ_percent::cpu.data 0.064818 # Average percentage of cache occupancy 3859289Sandreas.hansson@arm.comsystem.cpu.l2cache.occ_percent::total 0.998297 # Average percentage of cache occupancy 3869289Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_hits::cpu.inst 906782 # number of ReadReq hits 3879289Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_hits::cpu.data 811232 # number of ReadReq hits 3889289Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_hits::total 1718014 # number of ReadReq hits 3899289Sandreas.hansson@arm.comsystem.cpu.l2cache.Writeback_hits::writebacks 833491 # number of Writeback hits 3909289Sandreas.hansson@arm.comsystem.cpu.l2cache.Writeback_hits::total 833491 # number of Writeback hits 3919289Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits 3929289Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits 3939289Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_hits::cpu.data 187234 # number of ReadExReq hits 3949289Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_hits::total 187234 # number of ReadExReq hits 3959289Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.inst 906782 # number of demand (read+write) hits 3969289Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.data 998466 # number of demand (read+write) hits 3979289Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::total 1905248 # number of demand (read+write) hits 3989289Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.inst 906782 # number of overall hits 3999289Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.data 998466 # number of overall hits 4009289Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::total 1905248 # number of overall hits 4019289Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::cpu.inst 13404 # number of ReadReq misses 4029289Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::cpu.data 927640 # number of ReadReq misses 4039289Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::total 941044 # number of ReadReq misses 4049289Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_misses::cpu.data 12 # number of UpgradeReq misses 4059289Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_misses::total 12 # number of UpgradeReq misses 4069289Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_misses::cpu.data 117115 # number of ReadExReq misses 4079289Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_misses::total 117115 # number of ReadExReq misses 4089289Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.inst 13404 # number of demand (read+write) misses 4099289Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.data 1044755 # number of demand (read+write) misses 4109289Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::total 1058159 # number of demand (read+write) misses 4119289Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.inst 13404 # number of overall misses 4129289Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.data 1044755 # number of overall misses 4139289Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::total 1058159 # number of overall misses 4149289Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::cpu.inst 920186 # number of ReadReq accesses(hits+misses) 4159289Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::cpu.data 1738872 # number of ReadReq accesses(hits+misses) 4169289Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::total 2659058 # number of ReadReq accesses(hits+misses) 4179289Sandreas.hansson@arm.comsystem.cpu.l2cache.Writeback_accesses::writebacks 833491 # number of Writeback accesses(hits+misses) 4189289Sandreas.hansson@arm.comsystem.cpu.l2cache.Writeback_accesses::total 833491 # number of Writeback accesses(hits+misses) 4199289Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_accesses::cpu.data 16 # number of UpgradeReq accesses(hits+misses) 4209289Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_accesses::total 16 # number of UpgradeReq accesses(hits+misses) 4219289Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.data 304349 # number of ReadExReq accesses(hits+misses) 4229289Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_accesses::total 304349 # number of ReadExReq accesses(hits+misses) 4239289Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.inst 920186 # number of demand (read+write) accesses 4249289Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.data 2043221 # number of demand (read+write) accesses 4259289Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::total 2963407 # number of demand (read+write) accesses 4269289Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.inst 920186 # number of overall (read+write) accesses 4279289Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.data 2043221 # number of overall (read+write) accesses 4289289Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::total 2963407 # number of overall (read+write) accesses 4299289Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014567 # miss rate for ReadReq accesses 4309289Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.533472 # miss rate for ReadReq accesses 4319289Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::total 0.353901 # miss rate for ReadReq accesses 4329289Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.750000 # miss rate for UpgradeReq accesses 4339289Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_miss_rate::total 0.750000 # miss rate for UpgradeReq accesses 4349289Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.384805 # miss rate for ReadExReq accesses 4359289Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::total 0.384805 # miss rate for ReadExReq accesses 4369289Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.014567 # miss rate for demand accesses 4379289Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 0.511327 # miss rate for demand accesses 4389289Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::total 0.357075 # miss rate for demand accesses 4399289Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.014567 # miss rate for overall accesses 4409289Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 0.511327 # miss rate for overall accesses 4419289Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::total 0.357075 # miss rate for overall accesses 4429289Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 4439289Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 4449289Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 4459289Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 4469289Sandreas.hansson@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 4479289Sandreas.hansson@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 4489289Sandreas.hansson@arm.comsystem.cpu.l2cache.fast_writes 0 # number of fast writes performed 4499289Sandreas.hansson@arm.comsystem.cpu.l2cache.cache_copies 0 # number of cache copies performed 4509289Sandreas.hansson@arm.comsystem.cpu.l2cache.writebacks::writebacks 74287 # number of writebacks 4519289Sandreas.hansson@arm.comsystem.cpu.l2cache.writebacks::total 74287 # number of writebacks 4529289Sandreas.hansson@arm.comsystem.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 4532968SN/A 4542968SN/A---------- End Simulation Statistics ---------- 455