1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.829332 # Number of seconds simulated 4sim_ticks 1829332014500 # Number of ticks simulated 5final_tick 1829332014500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 3082632 # Simulator instruction rate (inst/s) 8host_op_rate 3082630 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 93925630949 # Simulator tick rate (ticks/s) 10host_mem_usage 334080 # Number of bytes of host memory used 11host_seconds 19.48 # Real time elapsed on the host 12sim_insts 60038469 # Number of instructions simulated 13sim_ops 60038469 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.inst 850496 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 66835072 # Number of bytes read from this memory 19system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory 20system.physmem.bytes_read::total 67686528 # Number of bytes read from this memory 21system.physmem.bytes_inst_read::cpu.inst 850496 # Number of instructions bytes read from this memory 22system.physmem.bytes_inst_read::total 850496 # Number of instructions bytes read from this memory 23system.physmem.bytes_written::writebacks 7415744 # Number of bytes written to this memory 24system.physmem.bytes_written::total 7415744 # Number of bytes written to this memory 25system.physmem.num_reads::cpu.inst 13289 # Number of read requests responded to by this memory 26system.physmem.num_reads::cpu.data 1044298 # Number of read requests responded to by this memory 27system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory 28system.physmem.num_reads::total 1057602 # Number of read requests responded to by this memory 29system.physmem.num_writes::writebacks 115871 # Number of write requests responded to by this memory 30system.physmem.num_writes::total 115871 # Number of write requests responded to by this memory 31system.physmem.bw_read::cpu.inst 464922 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_read::cpu.data 36535233 # Total read bandwidth from this memory (bytes/s) 33system.physmem.bw_read::tsunami.ide 525 # Total read bandwidth from this memory (bytes/s) 34system.physmem.bw_read::total 37000680 # Total read bandwidth from this memory (bytes/s) 35system.physmem.bw_inst_read::cpu.inst 464922 # Instruction read bandwidth from this memory (bytes/s) 36system.physmem.bw_inst_read::total 464922 # Instruction read bandwidth from this memory (bytes/s) 37system.physmem.bw_write::writebacks 4053799 # Write bandwidth from this memory (bytes/s) 38system.physmem.bw_write::total 4053799 # Write bandwidth from this memory (bytes/s) 39system.physmem.bw_total::writebacks 4053799 # Total bandwidth to/from this memory (bytes/s) 40system.physmem.bw_total::cpu.inst 464922 # Total bandwidth to/from this memory (bytes/s) 41system.physmem.bw_total::cpu.data 36535233 # Total bandwidth to/from this memory (bytes/s) 42system.physmem.bw_total::tsunami.ide 525 # Total bandwidth to/from this memory (bytes/s) 43system.physmem.bw_total::total 41054479 # Total bandwidth to/from this memory (bytes/s) 44system.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states 45system.bridge.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states 46system.cpu_clk_domain.clock 500 # Clock period in ticks 47system.cpu.dtb.fetch_hits 0 # ITB hits 48system.cpu.dtb.fetch_misses 0 # ITB misses 49system.cpu.dtb.fetch_acv 0 # ITB acv 50system.cpu.dtb.fetch_accesses 0 # ITB accesses 51system.cpu.dtb.read_hits 9710423 # DTB read hits 52system.cpu.dtb.read_misses 10329 # DTB read misses 53system.cpu.dtb.read_acv 210 # DTB read access violations 54system.cpu.dtb.read_accesses 728856 # DTB read accesses 55system.cpu.dtb.write_hits 6352496 # DTB write hits 56system.cpu.dtb.write_misses 1142 # DTB write misses 57system.cpu.dtb.write_acv 157 # DTB write access violations 58system.cpu.dtb.write_accesses 291931 # DTB write accesses 59system.cpu.dtb.data_hits 16062919 # DTB hits 60system.cpu.dtb.data_misses 11471 # DTB misses 61system.cpu.dtb.data_acv 367 # DTB access violations 62system.cpu.dtb.data_accesses 1020787 # DTB accesses 63system.cpu.itb.fetch_hits 4974637 # ITB hits 64system.cpu.itb.fetch_misses 5006 # ITB misses 65system.cpu.itb.fetch_acv 184 # ITB acv 66system.cpu.itb.fetch_accesses 4979643 # ITB accesses 67system.cpu.itb.read_hits 0 # DTB read hits 68system.cpu.itb.read_misses 0 # DTB read misses 69system.cpu.itb.read_acv 0 # DTB read access violations 70system.cpu.itb.read_accesses 0 # DTB read accesses 71system.cpu.itb.write_hits 0 # DTB write hits 72system.cpu.itb.write_misses 0 # DTB write misses 73system.cpu.itb.write_acv 0 # DTB write access violations 74system.cpu.itb.write_accesses 0 # DTB write accesses 75system.cpu.itb.data_hits 0 # DTB hits 76system.cpu.itb.data_misses 0 # DTB misses 77system.cpu.itb.data_acv 0 # DTB access violations 78system.cpu.itb.data_accesses 0 # DTB accesses 79system.cpu.numPwrStateTransitions 12714 # Number of power state transitions 80system.cpu.pwrStateClkGateDist::samples 6357 # Distribution of time spent in the clock gated state 81system.cpu.pwrStateClkGateDist::mean 283043478.877143 # Distribution of time spent in the clock gated state 82system.cpu.pwrStateClkGateDist::stdev 441371901.217911 # Distribution of time spent in the clock gated state 83system.cpu.pwrStateClkGateDist::1000-5e+10 6357 100.00% 100.00% # Distribution of time spent in the clock gated state 84system.cpu.pwrStateClkGateDist::min_value 386000 # Distribution of time spent in the clock gated state 85system.cpu.pwrStateClkGateDist::max_value 2000000000 # Distribution of time spent in the clock gated state 86system.cpu.pwrStateClkGateDist::total 6357 # Distribution of time spent in the clock gated state 87system.cpu.pwrStateResidencyTicks::ON 30024619278 # Cumulative time (in ticks) in various power states 88system.cpu.pwrStateResidencyTicks::CLK_GATED 1799307395222 # Cumulative time (in ticks) in various power states 89system.cpu.numCycles 3658670387 # number of cpu cycles simulated 90system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 91system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 92system.cpu.kern.inst.arm 0 # number of arm instructions executed 93system.cpu.kern.inst.quiesce 6357 # number of quiesce instructions executed 94system.cpu.kern.inst.hwrei 211318 # number of hwrei instructions executed 95system.cpu.kern.ipl_count::0 74830 40.99% 40.99% # number of times we switched to this ipl 96system.cpu.kern.ipl_count::21 243 0.13% 41.12% # number of times we switched to this ipl 97system.cpu.kern.ipl_count::22 1866 1.02% 42.14% # number of times we switched to this ipl 98system.cpu.kern.ipl_count::31 105622 57.86% 100.00% # number of times we switched to this ipl 99system.cpu.kern.ipl_count::total 182561 # number of times we switched to this ipl 100system.cpu.kern.ipl_good::0 73463 49.29% 49.29% # number of times we switched to this ipl from a different ipl 101system.cpu.kern.ipl_good::21 243 0.16% 49.46% # number of times we switched to this ipl from a different ipl 102system.cpu.kern.ipl_good::22 1866 1.25% 50.71% # number of times we switched to this ipl from a different ipl 103system.cpu.kern.ipl_good::31 73463 49.29% 100.00% # number of times we switched to this ipl from a different ipl 104system.cpu.kern.ipl_good::total 149035 # number of times we switched to this ipl from a different ipl 105system.cpu.kern.ipl_ticks::0 1811929148500 99.05% 99.05% # number of cycles we spent at this ipl 106system.cpu.kern.ipl_ticks::21 20110000 0.00% 99.05% # number of cycles we spent at this ipl 107system.cpu.kern.ipl_ticks::22 80238000 0.00% 99.05% # number of cycles we spent at this ipl 108system.cpu.kern.ipl_ticks::31 17302310500 0.95% 100.00% # number of cycles we spent at this ipl 109system.cpu.kern.ipl_ticks::total 1829331807000 # number of cycles we spent at this ipl 110system.cpu.kern.ipl_used::0 0.981732 # fraction of swpipl calls that actually changed the ipl 111system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 112system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 113system.cpu.kern.ipl_used::31 0.695527 # fraction of swpipl calls that actually changed the ipl 114system.cpu.kern.ipl_used::total 0.816357 # fraction of swpipl calls that actually changed the ipl 115system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 116system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed 117system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed 118system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed 119system.cpu.kern.callpal::swpctx 4177 2.17% 2.18% # number of callpals executed 120system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed 121system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed 122system.cpu.kern.callpal::swpipl 175248 91.19% 93.40% # number of callpals executed 123system.cpu.kern.callpal::rdps 6771 3.52% 96.92% # number of callpals executed 124system.cpu.kern.callpal::wrkgp 1 0.00% 96.92% # number of callpals executed 125system.cpu.kern.callpal::wrusp 7 0.00% 96.92% # number of callpals executed 126system.cpu.kern.callpal::rdusp 9 0.00% 96.93% # number of callpals executed 127system.cpu.kern.callpal::whami 2 0.00% 96.93% # number of callpals executed 128system.cpu.kern.callpal::rti 5203 2.71% 99.64% # number of callpals executed 129system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed 130system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed 131system.cpu.kern.callpal::total 192179 # number of callpals executed 132system.cpu.kern.mode_switch::kernel 5949 # number of protection mode switches 133system.cpu.kern.mode_switch::user 1737 # number of protection mode switches 134system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches 135system.cpu.kern.mode_good::kernel 1908 136system.cpu.kern.mode_good::user 1737 137system.cpu.kern.mode_good::idle 171 138system.cpu.kern.mode_switch_good::kernel 0.320726 # fraction of useful protection mode switches 139system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 140system.cpu.kern.mode_switch_good::idle 0.081545 # fraction of useful protection mode switches 141system.cpu.kern.mode_switch_good::total 0.390064 # fraction of useful protection mode switches 142system.cpu.kern.mode_ticks::kernel 26833316500 1.47% 1.47% # number of ticks spent at the given mode 143system.cpu.kern.mode_ticks::user 1465069000 0.08% 1.55% # number of ticks spent at the given mode 144system.cpu.kern.mode_ticks::idle 1801033420500 98.45% 100.00% # number of ticks spent at the given mode 145system.cpu.kern.swap_context 4178 # number of times the context was actually changed 146system.cpu.committedInsts 60038469 # Number of instructions committed 147system.cpu.committedOps 60038469 # Number of ops (including micro ops) committed 148system.cpu.num_int_alu_accesses 55913692 # Number of integer alu accesses 149system.cpu.num_fp_alu_accesses 324460 # Number of float alu accesses 150system.cpu.num_func_calls 1484182 # number of times a function call or return occured 151system.cpu.num_conditional_control_insts 7110791 # number of instructions that are conditional controls 152system.cpu.num_int_insts 55913692 # number of integer instructions 153system.cpu.num_fp_insts 324460 # number of float instructions 154system.cpu.num_int_register_reads 76954245 # number of times the integer registers were read 155system.cpu.num_int_register_writes 41740352 # number of times the integer registers were written 156system.cpu.num_fp_register_reads 163642 # number of times the floating registers were read 157system.cpu.num_fp_register_writes 166520 # number of times the floating registers were written 158system.cpu.num_mem_refs 16115703 # number of memory refs 159system.cpu.num_load_insts 9747509 # Number of load instructions 160system.cpu.num_store_insts 6368194 # Number of store instructions 161system.cpu.num_idle_cycles 3598621044.088899 # Number of idle cycles 162system.cpu.num_busy_cycles 60049342.911101 # Number of busy cycles 163system.cpu.not_idle_fraction 0.016413 # Percentage of non-idle cycles 164system.cpu.idle_fraction 0.983587 # Percentage of idle cycles 165system.cpu.Branches 9064428 # Number of branches fetched 166system.cpu.op_class::No_OpClass 3199100 5.33% 5.33% # Class of executed instruction 167system.cpu.op_class::IntAlu 39448406 65.69% 71.02% # Class of executed instruction 168system.cpu.op_class::IntMult 60677 0.10% 71.12% # Class of executed instruction 169system.cpu.op_class::IntDiv 0 0.00% 71.12% # Class of executed instruction 170system.cpu.op_class::FloatAdd 38087 0.06% 71.18% # Class of executed instruction 171system.cpu.op_class::FloatCmp 0 0.00% 71.18% # Class of executed instruction 172system.cpu.op_class::FloatCvt 0 0.00% 71.18% # Class of executed instruction 173system.cpu.op_class::FloatMult 0 0.00% 71.18% # Class of executed instruction 174system.cpu.op_class::FloatMultAcc 0 0.00% 71.18% # Class of executed instruction 175system.cpu.op_class::FloatDiv 3636 0.01% 71.19% # Class of executed instruction 176system.cpu.op_class::FloatMisc 0 0.00% 71.19% # Class of executed instruction 177system.cpu.op_class::FloatSqrt 0 0.00% 71.19% # Class of executed instruction 178system.cpu.op_class::SimdAdd 0 0.00% 71.19% # Class of executed instruction 179system.cpu.op_class::SimdAddAcc 0 0.00% 71.19% # Class of executed instruction 180system.cpu.op_class::SimdAlu 0 0.00% 71.19% # Class of executed instruction 181system.cpu.op_class::SimdCmp 0 0.00% 71.19% # Class of executed instruction 182system.cpu.op_class::SimdCvt 0 0.00% 71.19% # Class of executed instruction 183system.cpu.op_class::SimdMisc 0 0.00% 71.19% # Class of executed instruction 184system.cpu.op_class::SimdMult 0 0.00% 71.19% # Class of executed instruction 185system.cpu.op_class::SimdMultAcc 0 0.00% 71.19% # Class of executed instruction 186system.cpu.op_class::SimdShift 0 0.00% 71.19% # Class of executed instruction 187system.cpu.op_class::SimdShiftAcc 0 0.00% 71.19% # Class of executed instruction 188system.cpu.op_class::SimdSqrt 0 0.00% 71.19% # Class of executed instruction 189system.cpu.op_class::SimdFloatAdd 0 0.00% 71.19% # Class of executed instruction 190system.cpu.op_class::SimdFloatAlu 0 0.00% 71.19% # Class of executed instruction 191system.cpu.op_class::SimdFloatCmp 0 0.00% 71.19% # Class of executed instruction 192system.cpu.op_class::SimdFloatCvt 0 0.00% 71.19% # Class of executed instruction 193system.cpu.op_class::SimdFloatDiv 0 0.00% 71.19% # Class of executed instruction 194system.cpu.op_class::SimdFloatMisc 0 0.00% 71.19% # Class of executed instruction 195system.cpu.op_class::SimdFloatMult 0 0.00% 71.19% # Class of executed instruction 196system.cpu.op_class::SimdFloatMultAcc 0 0.00% 71.19% # Class of executed instruction 197system.cpu.op_class::SimdFloatSqrt 0 0.00% 71.19% # Class of executed instruction 198system.cpu.op_class::MemRead 9830448 16.37% 87.56% # Class of executed instruction 199system.cpu.op_class::MemWrite 6236007 10.38% 97.95% # Class of executed instruction 200system.cpu.op_class::FloatMemRead 144629 0.24% 98.19% # Class of executed instruction 201system.cpu.op_class::FloatMemWrite 138108 0.23% 98.42% # Class of executed instruction 202system.cpu.op_class::IprAccess 951209 1.58% 100.00% # Class of executed instruction 203system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 204system.cpu.op_class::total 60050307 # Class of executed instruction 205system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states 206system.cpu.dcache.tags.replacements 2042708 # number of replacements 207system.cpu.dcache.tags.tagsinuse 511.997802 # Cycle average of tags in use 208system.cpu.dcache.tags.total_refs 14038419 # Total number of references to valid blocks. 209system.cpu.dcache.tags.sampled_refs 2043220 # Sample count of references to valid blocks. 210system.cpu.dcache.tags.avg_refs 6.870733 # Average number of references to valid blocks. 211system.cpu.dcache.tags.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. 212system.cpu.dcache.tags.occ_blocks::cpu.data 511.997802 # Average occupied blocks per requestor 213system.cpu.dcache.tags.occ_percent::cpu.data 0.999996 # Average percentage of cache occupancy 214system.cpu.dcache.tags.occ_percent::total 0.999996 # Average percentage of cache occupancy 215system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 216system.cpu.dcache.tags.age_task_id_blocks_1024::0 443 # Occupied blocks per task id 217system.cpu.dcache.tags.age_task_id_blocks_1024::1 66 # Occupied blocks per task id 218system.cpu.dcache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id 219system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 220system.cpu.dcache.tags.tag_accesses 66369781 # Number of tag accesses 221system.cpu.dcache.tags.data_accesses 66369781 # Number of data accesses 222system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states 223system.cpu.dcache.ReadReq_hits::cpu.data 7807771 # number of ReadReq hits 224system.cpu.dcache.ReadReq_hits::total 7807771 # number of ReadReq hits 225system.cpu.dcache.WriteReq_hits::cpu.data 5848209 # number of WriteReq hits 226system.cpu.dcache.WriteReq_hits::total 5848209 # number of WriteReq hits 227system.cpu.dcache.LoadLockedReq_hits::cpu.data 183141 # number of LoadLockedReq hits 228system.cpu.dcache.LoadLockedReq_hits::total 183141 # number of LoadLockedReq hits 229system.cpu.dcache.StoreCondReq_hits::cpu.data 199282 # number of StoreCondReq hits 230system.cpu.dcache.StoreCondReq_hits::total 199282 # number of StoreCondReq hits 231system.cpu.dcache.demand_hits::cpu.data 13655980 # number of demand (read+write) hits 232system.cpu.dcache.demand_hits::total 13655980 # number of demand (read+write) hits 233system.cpu.dcache.overall_hits::cpu.data 13655980 # number of overall hits 234system.cpu.dcache.overall_hits::total 13655980 # number of overall hits 235system.cpu.dcache.ReadReq_misses::cpu.data 1721712 # number of ReadReq misses 236system.cpu.dcache.ReadReq_misses::total 1721712 # number of ReadReq misses 237system.cpu.dcache.WriteReq_misses::cpu.data 304363 # number of WriteReq misses 238system.cpu.dcache.WriteReq_misses::total 304363 # number of WriteReq misses 239system.cpu.dcache.LoadLockedReq_misses::cpu.data 17162 # number of LoadLockedReq misses 240system.cpu.dcache.LoadLockedReq_misses::total 17162 # number of LoadLockedReq misses 241system.cpu.dcache.demand_misses::cpu.data 2026075 # number of demand (read+write) misses 242system.cpu.dcache.demand_misses::total 2026075 # number of demand (read+write) misses 243system.cpu.dcache.overall_misses::cpu.data 2026075 # number of overall misses 244system.cpu.dcache.overall_misses::total 2026075 # number of overall misses 245system.cpu.dcache.ReadReq_accesses::cpu.data 9529483 # number of ReadReq accesses(hits+misses) 246system.cpu.dcache.ReadReq_accesses::total 9529483 # number of ReadReq accesses(hits+misses) 247system.cpu.dcache.WriteReq_accesses::cpu.data 6152572 # number of WriteReq accesses(hits+misses) 248system.cpu.dcache.WriteReq_accesses::total 6152572 # number of WriteReq accesses(hits+misses) 249system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200303 # number of LoadLockedReq accesses(hits+misses) 250system.cpu.dcache.LoadLockedReq_accesses::total 200303 # number of LoadLockedReq accesses(hits+misses) 251system.cpu.dcache.StoreCondReq_accesses::cpu.data 199282 # number of StoreCondReq accesses(hits+misses) 252system.cpu.dcache.StoreCondReq_accesses::total 199282 # number of StoreCondReq accesses(hits+misses) 253system.cpu.dcache.demand_accesses::cpu.data 15682055 # number of demand (read+write) accesses 254system.cpu.dcache.demand_accesses::total 15682055 # number of demand (read+write) accesses 255system.cpu.dcache.overall_accesses::cpu.data 15682055 # number of overall (read+write) accesses 256system.cpu.dcache.overall_accesses::total 15682055 # number of overall (read+write) accesses 257system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.180672 # miss rate for ReadReq accesses 258system.cpu.dcache.ReadReq_miss_rate::total 0.180672 # miss rate for ReadReq accesses 259system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049469 # miss rate for WriteReq accesses 260system.cpu.dcache.WriteReq_miss_rate::total 0.049469 # miss rate for WriteReq accesses 261system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085680 # miss rate for LoadLockedReq accesses 262system.cpu.dcache.LoadLockedReq_miss_rate::total 0.085680 # miss rate for LoadLockedReq accesses 263system.cpu.dcache.demand_miss_rate::cpu.data 0.129197 # miss rate for demand accesses 264system.cpu.dcache.demand_miss_rate::total 0.129197 # miss rate for demand accesses 265system.cpu.dcache.overall_miss_rate::cpu.data 0.129197 # miss rate for overall accesses 266system.cpu.dcache.overall_miss_rate::total 0.129197 # miss rate for overall accesses 267system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 268system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 269system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 270system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 271system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 272system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 273system.cpu.dcache.writebacks::writebacks 833476 # number of writebacks 274system.cpu.dcache.writebacks::total 833476 # number of writebacks 275system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states 276system.cpu.icache.tags.replacements 919605 # number of replacements 277system.cpu.icache.tags.tagsinuse 511.215257 # Cycle average of tags in use 278system.cpu.icache.tags.total_refs 59130075 # Total number of references to valid blocks. 279system.cpu.icache.tags.sampled_refs 920117 # Sample count of references to valid blocks. 280system.cpu.icache.tags.avg_refs 64.263648 # Average number of references to valid blocks. 281system.cpu.icache.tags.warmup_cycle 9686452000 # Cycle when the warmup percentage was hit. 282system.cpu.icache.tags.occ_blocks::cpu.inst 511.215257 # Average occupied blocks per requestor 283system.cpu.icache.tags.occ_percent::cpu.inst 0.998467 # Average percentage of cache occupancy 284system.cpu.icache.tags.occ_percent::total 0.998467 # Average percentage of cache occupancy 285system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 286system.cpu.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id 287system.cpu.icache.tags.age_task_id_blocks_1024::1 117 # Occupied blocks per task id 288system.cpu.icache.tags.age_task_id_blocks_1024::2 332 # Occupied blocks per task id 289system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 290system.cpu.icache.tags.tag_accesses 60970539 # Number of tag accesses 291system.cpu.icache.tags.data_accesses 60970539 # Number of data accesses 292system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states 293system.cpu.icache.ReadReq_hits::cpu.inst 59130075 # number of ReadReq hits 294system.cpu.icache.ReadReq_hits::total 59130075 # number of ReadReq hits 295system.cpu.icache.demand_hits::cpu.inst 59130075 # number of demand (read+write) hits 296system.cpu.icache.demand_hits::total 59130075 # number of demand (read+write) hits 297system.cpu.icache.overall_hits::cpu.inst 59130075 # number of overall hits 298system.cpu.icache.overall_hits::total 59130075 # number of overall hits 299system.cpu.icache.ReadReq_misses::cpu.inst 920232 # number of ReadReq misses 300system.cpu.icache.ReadReq_misses::total 920232 # number of ReadReq misses 301system.cpu.icache.demand_misses::cpu.inst 920232 # number of demand (read+write) misses 302system.cpu.icache.demand_misses::total 920232 # number of demand (read+write) misses 303system.cpu.icache.overall_misses::cpu.inst 920232 # number of overall misses 304system.cpu.icache.overall_misses::total 920232 # number of overall misses 305system.cpu.icache.ReadReq_accesses::cpu.inst 60050307 # number of ReadReq accesses(hits+misses) 306system.cpu.icache.ReadReq_accesses::total 60050307 # number of ReadReq accesses(hits+misses) 307system.cpu.icache.demand_accesses::cpu.inst 60050307 # number of demand (read+write) accesses 308system.cpu.icache.demand_accesses::total 60050307 # number of demand (read+write) accesses 309system.cpu.icache.overall_accesses::cpu.inst 60050307 # number of overall (read+write) accesses 310system.cpu.icache.overall_accesses::total 60050307 # number of overall (read+write) accesses 311system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.015324 # miss rate for ReadReq accesses 312system.cpu.icache.ReadReq_miss_rate::total 0.015324 # miss rate for ReadReq accesses 313system.cpu.icache.demand_miss_rate::cpu.inst 0.015324 # miss rate for demand accesses 314system.cpu.icache.demand_miss_rate::total 0.015324 # miss rate for demand accesses 315system.cpu.icache.overall_miss_rate::cpu.inst 0.015324 # miss rate for overall accesses 316system.cpu.icache.overall_miss_rate::total 0.015324 # miss rate for overall accesses 317system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 318system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 319system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 320system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 321system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 322system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 323system.cpu.icache.writebacks::writebacks 919605 # number of writebacks 324system.cpu.icache.writebacks::total 919605 # number of writebacks 325system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states 326system.cpu.l2cache.tags.replacements 992419 # number of replacements 327system.cpu.l2cache.tags.tagsinuse 65520.104764 # Cycle average of tags in use 328system.cpu.l2cache.tags.total_refs 4865571 # Total number of references to valid blocks. 329system.cpu.l2cache.tags.sampled_refs 1057941 # Sample count of references to valid blocks. 330system.cpu.l2cache.tags.avg_refs 4.599095 # Average number of references to valid blocks. 331system.cpu.l2cache.tags.warmup_cycle 614754000 # Cycle when the warmup percentage was hit. 332system.cpu.l2cache.tags.occ_blocks::writebacks 264.552906 # Average occupied blocks per requestor 333system.cpu.l2cache.tags.occ_blocks::cpu.inst 4852.732204 # Average occupied blocks per requestor 334system.cpu.l2cache.tags.occ_blocks::cpu.data 60402.819654 # Average occupied blocks per requestor 335system.cpu.l2cache.tags.occ_percent::writebacks 0.004037 # Average percentage of cache occupancy 336system.cpu.l2cache.tags.occ_percent::cpu.inst 0.074047 # Average percentage of cache occupancy 337system.cpu.l2cache.tags.occ_percent::cpu.data 0.921674 # Average percentage of cache occupancy 338system.cpu.l2cache.tags.occ_percent::total 0.999757 # Average percentage of cache occupancy 339system.cpu.l2cache.tags.occ_task_id_blocks::1024 65522 # Occupied blocks per task id 340system.cpu.l2cache.tags.age_task_id_blocks_1024::0 168 # Occupied blocks per task id 341system.cpu.l2cache.tags.age_task_id_blocks_1024::1 606 # Occupied blocks per task id 342system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3042 # Occupied blocks per task id 343system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6629 # Occupied blocks per task id 344system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55077 # Occupied blocks per task id 345system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999786 # Percentage of cache occupancy per task id 346system.cpu.l2cache.tags.tag_accesses 48449706 # Number of tag accesses 347system.cpu.l2cache.tags.data_accesses 48449706 # Number of data accesses 348system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states 349system.cpu.l2cache.WritebackDirty_hits::writebacks 833476 # number of WritebackDirty hits 350system.cpu.l2cache.WritebackDirty_hits::total 833476 # number of WritebackDirty hits 351system.cpu.l2cache.WritebackClean_hits::writebacks 919353 # number of WritebackClean hits 352system.cpu.l2cache.WritebackClean_hits::total 919353 # number of WritebackClean hits 353system.cpu.l2cache.UpgradeReq_hits::cpu.data 12 # number of UpgradeReq hits 354system.cpu.l2cache.UpgradeReq_hits::total 12 # number of UpgradeReq hits 355system.cpu.l2cache.ReadExReq_hits::cpu.data 187293 # number of ReadExReq hits 356system.cpu.l2cache.ReadExReq_hits::total 187293 # number of ReadExReq hits 357system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 906925 # number of ReadCleanReq hits 358system.cpu.l2cache.ReadCleanReq_hits::total 906925 # number of ReadCleanReq hits 359system.cpu.l2cache.ReadSharedReq_hits::cpu.data 811230 # number of ReadSharedReq hits 360system.cpu.l2cache.ReadSharedReq_hits::total 811230 # number of ReadSharedReq hits 361system.cpu.l2cache.demand_hits::cpu.inst 906925 # number of demand (read+write) hits 362system.cpu.l2cache.demand_hits::cpu.data 998523 # number of demand (read+write) hits 363system.cpu.l2cache.demand_hits::total 1905448 # number of demand (read+write) hits 364system.cpu.l2cache.overall_hits::cpu.inst 906925 # number of overall hits 365system.cpu.l2cache.overall_hits::cpu.data 998523 # number of overall hits 366system.cpu.l2cache.overall_hits::total 1905448 # number of overall hits 367system.cpu.l2cache.UpgradeReq_misses::cpu.data 4 # number of UpgradeReq misses 368system.cpu.l2cache.UpgradeReq_misses::total 4 # number of UpgradeReq misses 369system.cpu.l2cache.ReadExReq_misses::cpu.data 117054 # number of ReadExReq misses 370system.cpu.l2cache.ReadExReq_misses::total 117054 # number of ReadExReq misses 371system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 13289 # number of ReadCleanReq misses 372system.cpu.l2cache.ReadCleanReq_misses::total 13289 # number of ReadCleanReq misses 373system.cpu.l2cache.ReadSharedReq_misses::cpu.data 927644 # number of ReadSharedReq misses 374system.cpu.l2cache.ReadSharedReq_misses::total 927644 # number of ReadSharedReq misses 375system.cpu.l2cache.demand_misses::cpu.inst 13289 # number of demand (read+write) misses 376system.cpu.l2cache.demand_misses::cpu.data 1044698 # number of demand (read+write) misses 377system.cpu.l2cache.demand_misses::total 1057987 # number of demand (read+write) misses 378system.cpu.l2cache.overall_misses::cpu.inst 13289 # number of overall misses 379system.cpu.l2cache.overall_misses::cpu.data 1044698 # number of overall misses 380system.cpu.l2cache.overall_misses::total 1057987 # number of overall misses 381system.cpu.l2cache.WritebackDirty_accesses::writebacks 833476 # number of WritebackDirty accesses(hits+misses) 382system.cpu.l2cache.WritebackDirty_accesses::total 833476 # number of WritebackDirty accesses(hits+misses) 383system.cpu.l2cache.WritebackClean_accesses::writebacks 919353 # number of WritebackClean accesses(hits+misses) 384system.cpu.l2cache.WritebackClean_accesses::total 919353 # number of WritebackClean accesses(hits+misses) 385system.cpu.l2cache.UpgradeReq_accesses::cpu.data 16 # number of UpgradeReq accesses(hits+misses) 386system.cpu.l2cache.UpgradeReq_accesses::total 16 # number of UpgradeReq accesses(hits+misses) 387system.cpu.l2cache.ReadExReq_accesses::cpu.data 304347 # number of ReadExReq accesses(hits+misses) 388system.cpu.l2cache.ReadExReq_accesses::total 304347 # number of ReadExReq accesses(hits+misses) 389system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 920214 # number of ReadCleanReq accesses(hits+misses) 390system.cpu.l2cache.ReadCleanReq_accesses::total 920214 # number of ReadCleanReq accesses(hits+misses) 391system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1738874 # number of ReadSharedReq accesses(hits+misses) 392system.cpu.l2cache.ReadSharedReq_accesses::total 1738874 # number of ReadSharedReq accesses(hits+misses) 393system.cpu.l2cache.demand_accesses::cpu.inst 920214 # number of demand (read+write) accesses 394system.cpu.l2cache.demand_accesses::cpu.data 2043221 # number of demand (read+write) accesses 395system.cpu.l2cache.demand_accesses::total 2963435 # number of demand (read+write) accesses 396system.cpu.l2cache.overall_accesses::cpu.inst 920214 # number of overall (read+write) accesses 397system.cpu.l2cache.overall_accesses::cpu.data 2043221 # number of overall (read+write) accesses 398system.cpu.l2cache.overall_accesses::total 2963435 # number of overall (read+write) accesses 399system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.250000 # miss rate for UpgradeReq accesses 400system.cpu.l2cache.UpgradeReq_miss_rate::total 0.250000 # miss rate for UpgradeReq accesses 401system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.384607 # miss rate for ReadExReq accesses 402system.cpu.l2cache.ReadExReq_miss_rate::total 0.384607 # miss rate for ReadExReq accesses 403system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.014441 # miss rate for ReadCleanReq accesses 404system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.014441 # miss rate for ReadCleanReq accesses 405system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.533474 # miss rate for ReadSharedReq accesses 406system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.533474 # miss rate for ReadSharedReq accesses 407system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014441 # miss rate for demand accesses 408system.cpu.l2cache.demand_miss_rate::cpu.data 0.511300 # miss rate for demand accesses 409system.cpu.l2cache.demand_miss_rate::total 0.357014 # miss rate for demand accesses 410system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014441 # miss rate for overall accesses 411system.cpu.l2cache.overall_miss_rate::cpu.data 0.511300 # miss rate for overall accesses 412system.cpu.l2cache.overall_miss_rate::total 0.357014 # miss rate for overall accesses 413system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 414system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 415system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 416system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 417system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 418system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 419system.cpu.l2cache.writebacks::writebacks 74359 # number of writebacks 420system.cpu.l2cache.writebacks::total 74359 # number of writebacks 421system.cpu.toL2Bus.snoop_filter.tot_requests 5925782 # Total number of requests made to the snoop filter. 422system.cpu.toL2Bus.snoop_filter.hit_single_requests 2962349 # Number of requests hitting in the snoop filter with a single holder of the requested data. 423system.cpu.toL2Bus.snoop_filter.hit_multi_requests 2223 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 424system.cpu.toL2Bus.snoop_filter.tot_snoops 1449 # Total number of snoops made to the snoop filter. 425system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1449 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 426system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 427system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states 428system.cpu.toL2Bus.trans_dist::ReadReq 7184 # Transaction distribution 429system.cpu.toL2Bus.trans_dist::ReadResp 2666290 # Transaction distribution 430system.cpu.toL2Bus.trans_dist::WriteReq 9838 # Transaction distribution 431system.cpu.toL2Bus.trans_dist::WriteResp 9838 # Transaction distribution 432system.cpu.toL2Bus.trans_dist::WritebackDirty 833476 # Transaction distribution 433system.cpu.toL2Bus.trans_dist::WritebackClean 919605 # Transaction distribution 434system.cpu.toL2Bus.trans_dist::CleanEvict 1209232 # Transaction distribution 435system.cpu.toL2Bus.trans_dist::UpgradeReq 16 # Transaction distribution 436system.cpu.toL2Bus.trans_dist::UpgradeResp 16 # Transaction distribution 437system.cpu.toL2Bus.trans_dist::ReadExReq 304347 # Transaction distribution 438system.cpu.toL2Bus.trans_dist::ReadExResp 304347 # Transaction distribution 439system.cpu.toL2Bus.trans_dist::ReadCleanReq 920232 # Transaction distribution 440system.cpu.toL2Bus.trans_dist::ReadSharedReq 1738874 # Transaction distribution 441system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2760069 # Packet count per connected master and slave (bytes) 442system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6163226 # Packet count per connected master and slave (bytes) 443system.cpu.toL2Bus.pkt_count::total 8923295 # Packet count per connected master and slave (bytes) 444system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 117749568 # Cumulative packet size per connected master and slave (bytes) 445system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 184154734 # Cumulative packet size per connected master and slave (bytes) 446system.cpu.toL2Bus.pkt_size::total 301904302 # Cumulative packet size per connected master and slave (bytes) 447system.cpu.toL2Bus.snoops 993442 # Total snoops (count) 448system.cpu.toL2Bus.snoopTraffic 4779456 # Total snoop traffic (bytes) 449system.cpu.toL2Bus.snoop_fanout::samples 6936088 # Request fanout histogram 450system.cpu.toL2Bus.snoop_fanout::mean 0.000848 # Request fanout histogram 451system.cpu.toL2Bus.snoop_fanout::stdev 0.029106 # Request fanout histogram 452system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 453system.cpu.toL2Bus.snoop_fanout::0 6930207 99.92% 99.92% # Request fanout histogram 454system.cpu.toL2Bus.snoop_fanout::1 5881 0.08% 100.00% # Request fanout histogram 455system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 456system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 457system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 458system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 459system.cpu.toL2Bus.snoop_fanout::total 6936088 # Request fanout histogram 460system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 461system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 462system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 463system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 464system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 465system.disk0.dma_write_txs 395 # Number of DMA write transactions. 466system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 467system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 468system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 469system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 470system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 471system.disk2.dma_write_txs 1 # Number of DMA write transactions. 472system.iobus.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states 473system.iobus.trans_dist::ReadReq 7358 # Transaction distribution 474system.iobus.trans_dist::ReadResp 7358 # Transaction distribution 475system.iobus.trans_dist::WriteReq 51390 # Transaction distribution 476system.iobus.trans_dist::WriteResp 51390 # Transaction distribution 477system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5248 # Packet count per connected master and slave (bytes) 478system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1010 # Packet count per connected master and slave (bytes) 479system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) 480system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) 481system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 1076 # Packet count per connected master and slave (bytes) 482system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18012 # Packet count per connected master and slave (bytes) 483system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes) 484system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) 485system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) 486system.iobus.pkt_count_system.bridge.master::total 34044 # Packet count per connected master and slave (bytes) 487system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83452 # Packet count per connected master and slave (bytes) 488system.iobus.pkt_count_system.tsunami.ide.dma::total 83452 # Packet count per connected master and slave (bytes) 489system.iobus.pkt_count::total 117496 # Packet count per connected master and slave (bytes) 490system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20992 # Cumulative packet size per connected master and slave (bytes) 491system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 2733 # Cumulative packet size per connected master and slave (bytes) 492system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) 493system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) 494system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 1392 # Cumulative packet size per connected master and slave (bytes) 495system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9006 # Cumulative packet size per connected master and slave (bytes) 496system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes) 497system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) 498system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) 499system.iobus.pkt_size_system.bridge.master::total 46126 # Cumulative packet size per connected master and slave (bytes) 500system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661616 # Cumulative packet size per connected master and slave (bytes) 501system.iobus.pkt_size_system.tsunami.ide.dma::total 2661616 # Cumulative packet size per connected master and slave (bytes) 502system.iobus.pkt_size::total 2707742 # Cumulative packet size per connected master and slave (bytes) 503system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states 504system.iocache.tags.replacements 41686 # number of replacements 505system.iocache.tags.tagsinuse 1.225570 # Cycle average of tags in use 506system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 507system.iocache.tags.sampled_refs 41702 # Sample count of references to valid blocks. 508system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 509system.iocache.tags.warmup_cycle 1685780588017 # Cycle when the warmup percentage was hit. 510system.iocache.tags.occ_blocks::tsunami.ide 1.225570 # Average occupied blocks per requestor 511system.iocache.tags.occ_percent::tsunami.ide 0.076598 # Average percentage of cache occupancy 512system.iocache.tags.occ_percent::total 0.076598 # Average percentage of cache occupancy 513system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 514system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id 515system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 516system.iocache.tags.tag_accesses 375534 # Number of tag accesses 517system.iocache.tags.data_accesses 375534 # Number of data accesses 518system.iocache.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states 519system.iocache.ReadReq_misses::tsunami.ide 174 # number of ReadReq misses 520system.iocache.ReadReq_misses::total 174 # number of ReadReq misses 521system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses 522system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses 523system.iocache.demand_misses::tsunami.ide 41726 # number of demand (read+write) misses 524system.iocache.demand_misses::total 41726 # number of demand (read+write) misses 525system.iocache.overall_misses::tsunami.ide 41726 # number of overall misses 526system.iocache.overall_misses::total 41726 # number of overall misses 527system.iocache.ReadReq_accesses::tsunami.ide 174 # number of ReadReq accesses(hits+misses) 528system.iocache.ReadReq_accesses::total 174 # number of ReadReq accesses(hits+misses) 529system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) 530system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses) 531system.iocache.demand_accesses::tsunami.ide 41726 # number of demand (read+write) accesses 532system.iocache.demand_accesses::total 41726 # number of demand (read+write) accesses 533system.iocache.overall_accesses::tsunami.ide 41726 # number of overall (read+write) accesses 534system.iocache.overall_accesses::total 41726 # number of overall (read+write) accesses 535system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 536system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 537system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses 538system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 539system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 540system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 541system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 542system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 543system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 544system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 545system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 546system.iocache.blocked::no_targets 0 # number of cycles access was blocked 547system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 548system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 549system.iocache.writebacks::writebacks 41512 # number of writebacks 550system.iocache.writebacks::total 41512 # number of writebacks 551system.membus.snoop_filter.tot_requests 2132776 # Total number of requests made to the snoop filter. 552system.membus.snoop_filter.hit_single_requests 1034104 # Number of requests hitting in the snoop filter with a single holder of the requested data. 553system.membus.snoop_filter.hit_multi_requests 505 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 554system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 555system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 556system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 557system.membus.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states 558system.membus.trans_dist::ReadReq 7184 # Transaction distribution 559system.membus.trans_dist::ReadResp 948291 # Transaction distribution 560system.membus.trans_dist::WriteReq 9838 # Transaction distribution 561system.membus.trans_dist::WriteResp 9838 # Transaction distribution 562system.membus.trans_dist::WritebackDirty 115871 # Transaction distribution 563system.membus.trans_dist::CleanEvict 917188 # Transaction distribution 564system.membus.trans_dist::UpgradeReq 133 # Transaction distribution 565system.membus.trans_dist::UpgradeResp 133 # Transaction distribution 566system.membus.trans_dist::ReadExReq 116925 # Transaction distribution 567system.membus.trans_dist::ReadExResp 116925 # Transaction distribution 568system.membus.trans_dist::ReadSharedReq 941107 # Transaction distribution 569system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution 570system.membus.trans_dist::InvalidateResp 41552 # Transaction distribution 571system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 34044 # Packet count per connected master and slave (bytes) 572system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3107355 # Packet count per connected master and slave (bytes) 573system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3141399 # Packet count per connected master and slave (bytes) 574system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 125138 # Packet count per connected master and slave (bytes) 575system.membus.pkt_count_system.iocache.mem_side::total 125138 # Packet count per connected master and slave (bytes) 576system.membus.pkt_count::total 3266537 # Packet count per connected master and slave (bytes) 577system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 46126 # Cumulative packet size per connected master and slave (bytes) 578system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 72461888 # Cumulative packet size per connected master and slave (bytes) 579system.membus.pkt_size_system.cpu.l2cache.mem_side::total 72508014 # Cumulative packet size per connected master and slave (bytes) 580system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2667904 # Cumulative packet size per connected master and slave (bytes) 581system.membus.pkt_size_system.iocache.mem_side::total 2667904 # Cumulative packet size per connected master and slave (bytes) 582system.membus.pkt_size::total 75175918 # Cumulative packet size per connected master and slave (bytes) 583system.membus.snoops 0 # Total snoops (count) 584system.membus.snoopTraffic 0 # Total snoop traffic (bytes) 585system.membus.snoop_fanout::samples 2149798 # Request fanout histogram 586system.membus.snoop_fanout::mean 0.000529 # Request fanout histogram 587system.membus.snoop_fanout::stdev 0.023002 # Request fanout histogram 588system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 589system.membus.snoop_fanout::0 2148660 99.95% 99.95% # Request fanout histogram 590system.membus.snoop_fanout::1 1138 0.05% 100.00% # Request fanout histogram 591system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 592system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 593system.membus.snoop_fanout::min_value 0 # Request fanout histogram 594system.membus.snoop_fanout::max_value 1 # Request fanout histogram 595system.membus.snoop_fanout::total 2149798 # Request fanout histogram 596system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states 597system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states 598system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states 599system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states 600system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states 601system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 602system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 603system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 604system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 605system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 606system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 607system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 608system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 609system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 610system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 611system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 612system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 613system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR 614system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 615system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 616system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 617system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 618system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 619system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR 620system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 621system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 622system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 623system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 624system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 625system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 626system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 627system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 628system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 629system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 630system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 631system.tsunami.ethernet.droppedPackets 0 # number of packets dropped 632system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states 633system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states 634system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states 635system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states 636system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states 637system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states 638system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states 639system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states 640system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states 641system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states 642system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states 643system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states 644system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states 645system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states 646system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states 647system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states 648system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states 649system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states 650system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states 651system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states 652system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states 653system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states 654system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1829332014500 # Cumulative time (in ticks) in various power states 655 656---------- End Simulation Statistics ---------- 657