stats.txt revision 9289
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.829331 # Number of seconds simulated 4sim_ticks 1829330593000 # Number of ticks simulated 5final_tick 1829330593000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 2569577 # Simulator instruction rate (inst/s) 8host_op_rate 2569575 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 78294086451 # Simulator tick rate (ticks/s) 10host_mem_usage 295292 # Number of bytes of host memory used 11host_seconds 23.37 # Real time elapsed on the host 12sim_insts 60037737 # Number of instructions simulated 13sim_ops 60037737 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 857856 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 66839296 # Number of bytes read from this memory 16system.physmem.bytes_read::tsunami.ide 2652288 # Number of bytes read from this memory 17system.physmem.bytes_read::total 70349440 # Number of bytes read from this memory 18system.physmem.bytes_inst_read::cpu.inst 857856 # Number of instructions bytes read from this memory 19system.physmem.bytes_inst_read::total 857856 # Number of instructions bytes read from this memory 20system.physmem.bytes_written::writebacks 7411136 # Number of bytes written to this memory 21system.physmem.bytes_written::total 7411136 # Number of bytes written to this memory 22system.physmem.num_reads::cpu.inst 13404 # Number of read requests responded to by this memory 23system.physmem.num_reads::cpu.data 1044364 # Number of read requests responded to by this memory 24system.physmem.num_reads::tsunami.ide 41442 # Number of read requests responded to by this memory 25system.physmem.num_reads::total 1099210 # Number of read requests responded to by this memory 26system.physmem.num_writes::writebacks 115799 # Number of write requests responded to by this memory 27system.physmem.num_writes::total 115799 # Number of write requests responded to by this memory 28system.physmem.bw_read::cpu.inst 468945 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::cpu.data 36537571 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::tsunami.ide 1449868 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_read::total 38456384 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::cpu.inst 468945 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_inst_read::total 468945 # Instruction read bandwidth from this memory (bytes/s) 34system.physmem.bw_write::writebacks 4051283 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_write::total 4051283 # Write bandwidth from this memory (bytes/s) 36system.physmem.bw_total::writebacks 4051283 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.inst 468945 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::cpu.data 36537571 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.bw_total::tsunami.ide 1449868 # Total bandwidth to/from this memory (bytes/s) 40system.physmem.bw_total::total 42507667 # Total bandwidth to/from this memory (bytes/s) 41system.iocache.replacements 41686 # number of replacements 42system.iocache.tagsinuse 1.225558 # Cycle average of tags in use 43system.iocache.total_refs 0 # Total number of references to valid blocks. 44system.iocache.sampled_refs 41702 # Sample count of references to valid blocks. 45system.iocache.avg_refs 0 # Average number of references to valid blocks. 46system.iocache.warmup_cycle 1685780599067 # Cycle when the warmup percentage was hit. 47system.iocache.occ_blocks::tsunami.ide 1.225558 # Average occupied blocks per requestor 48system.iocache.occ_percent::tsunami.ide 0.076597 # Average percentage of cache occupancy 49system.iocache.occ_percent::total 0.076597 # Average percentage of cache occupancy 50system.iocache.ReadReq_misses::tsunami.ide 174 # number of ReadReq misses 51system.iocache.ReadReq_misses::total 174 # number of ReadReq misses 52system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses 53system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses 54system.iocache.demand_misses::tsunami.ide 41726 # number of demand (read+write) misses 55system.iocache.demand_misses::total 41726 # number of demand (read+write) misses 56system.iocache.overall_misses::tsunami.ide 41726 # number of overall misses 57system.iocache.overall_misses::total 41726 # number of overall misses 58system.iocache.ReadReq_accesses::tsunami.ide 174 # number of ReadReq accesses(hits+misses) 59system.iocache.ReadReq_accesses::total 174 # number of ReadReq accesses(hits+misses) 60system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) 61system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) 62system.iocache.demand_accesses::tsunami.ide 41726 # number of demand (read+write) accesses 63system.iocache.demand_accesses::total 41726 # number of demand (read+write) accesses 64system.iocache.overall_accesses::tsunami.ide 41726 # number of overall (read+write) accesses 65system.iocache.overall_accesses::total 41726 # number of overall (read+write) accesses 66system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 67system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 68system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses 69system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 70system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 71system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 72system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 73system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 74system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 75system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 76system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 77system.iocache.blocked::no_targets 0 # number of cycles access was blocked 78system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 79system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 80system.iocache.fast_writes 0 # number of fast writes performed 81system.iocache.cache_copies 0 # number of cache copies performed 82system.iocache.writebacks::writebacks 41512 # number of writebacks 83system.iocache.writebacks::total 41512 # number of writebacks 84system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 85system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 86system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 87system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 88system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 89system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 90system.disk0.dma_write_txs 395 # Number of DMA write transactions. 91system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 92system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 93system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 94system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 95system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 96system.disk2.dma_write_txs 1 # Number of DMA write transactions. 97system.cpu.dtb.fetch_hits 0 # ITB hits 98system.cpu.dtb.fetch_misses 0 # ITB misses 99system.cpu.dtb.fetch_acv 0 # ITB acv 100system.cpu.dtb.fetch_accesses 0 # ITB accesses 101system.cpu.dtb.read_hits 9710417 # DTB read hits 102system.cpu.dtb.read_misses 10329 # DTB read misses 103system.cpu.dtb.read_acv 210 # DTB read access violations 104system.cpu.dtb.read_accesses 728856 # DTB read accesses 105system.cpu.dtb.write_hits 6352487 # DTB write hits 106system.cpu.dtb.write_misses 1142 # DTB write misses 107system.cpu.dtb.write_acv 157 # DTB write access violations 108system.cpu.dtb.write_accesses 291931 # DTB write accesses 109system.cpu.dtb.data_hits 16062904 # DTB hits 110system.cpu.dtb.data_misses 11471 # DTB misses 111system.cpu.dtb.data_acv 367 # DTB access violations 112system.cpu.dtb.data_accesses 1020787 # DTB accesses 113system.cpu.itb.fetch_hits 4974615 # ITB hits 114system.cpu.itb.fetch_misses 5006 # ITB misses 115system.cpu.itb.fetch_acv 184 # ITB acv 116system.cpu.itb.fetch_accesses 4979621 # ITB accesses 117system.cpu.itb.read_hits 0 # DTB read hits 118system.cpu.itb.read_misses 0 # DTB read misses 119system.cpu.itb.read_acv 0 # DTB read access violations 120system.cpu.itb.read_accesses 0 # DTB read accesses 121system.cpu.itb.write_hits 0 # DTB write hits 122system.cpu.itb.write_misses 0 # DTB write misses 123system.cpu.itb.write_acv 0 # DTB write access violations 124system.cpu.itb.write_accesses 0 # DTB write accesses 125system.cpu.itb.data_hits 0 # DTB hits 126system.cpu.itb.data_misses 0 # DTB misses 127system.cpu.itb.data_acv 0 # DTB access violations 128system.cpu.itb.data_accesses 0 # DTB accesses 129system.cpu.numCycles 3658661078 # number of cpu cycles simulated 130system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 131system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 132system.cpu.committedInsts 60037737 # Number of instructions committed 133system.cpu.committedOps 60037737 # Number of ops (including micro ops) committed 134system.cpu.num_int_alu_accesses 55912968 # Number of integer alu accesses 135system.cpu.num_fp_alu_accesses 324460 # Number of float alu accesses 136system.cpu.num_func_calls 1484174 # number of times a function call or return occured 137system.cpu.num_conditional_control_insts 7110641 # number of instructions that are conditional controls 138system.cpu.num_int_insts 55912968 # number of integer instructions 139system.cpu.num_fp_insts 324460 # number of float instructions 140system.cpu.num_int_register_reads 76953007 # number of times the integer registers were read 141system.cpu.num_int_register_writes 41739788 # number of times the integer registers were written 142system.cpu.num_fp_register_reads 163642 # number of times the floating registers were read 143system.cpu.num_fp_register_writes 166520 # number of times the floating registers were written 144system.cpu.num_mem_refs 16115688 # number of memory refs 145system.cpu.num_load_insts 9747503 # Number of load instructions 146system.cpu.num_store_insts 6368185 # Number of store instructions 147system.cpu.num_idle_cycles 3598606247.544791 # Number of idle cycles 148system.cpu.num_busy_cycles 60054830.455209 # Number of busy cycles 149system.cpu.not_idle_fraction 0.016414 # Percentage of non-idle cycles 150system.cpu.idle_fraction 0.983586 # Percentage of idle cycles 151system.cpu.kern.inst.arm 0 # number of arm instructions executed 152system.cpu.kern.inst.quiesce 6357 # number of quiesce instructions executed 153system.cpu.kern.inst.hwrei 211316 # number of hwrei instructions executed 154system.cpu.kern.ipl_count::0 74830 40.99% 40.99% # number of times we switched to this ipl 155system.cpu.kern.ipl_count::21 243 0.13% 41.12% # number of times we switched to this ipl 156system.cpu.kern.ipl_count::22 1866 1.02% 42.14% # number of times we switched to this ipl 157system.cpu.kern.ipl_count::31 105620 57.86% 100.00% # number of times we switched to this ipl 158system.cpu.kern.ipl_count::total 182559 # number of times we switched to this ipl 159system.cpu.kern.ipl_good::0 73463 49.29% 49.29% # number of times we switched to this ipl from a different ipl 160system.cpu.kern.ipl_good::21 243 0.16% 49.46% # number of times we switched to this ipl from a different ipl 161system.cpu.kern.ipl_good::22 1866 1.25% 50.71% # number of times we switched to this ipl from a different ipl 162system.cpu.kern.ipl_good::31 73463 49.29% 100.00% # number of times we switched to this ipl from a different ipl 163system.cpu.kern.ipl_good::total 149035 # number of times we switched to this ipl from a different ipl 164system.cpu.kern.ipl_ticks::0 1811925911500 99.05% 99.05% # number of cycles we spent at this ipl 165system.cpu.kern.ipl_ticks::21 20110000 0.00% 99.05% # number of cycles we spent at this ipl 166system.cpu.kern.ipl_ticks::22 80238000 0.00% 99.05% # number of cycles we spent at this ipl 167system.cpu.kern.ipl_ticks::31 17304126000 0.95% 100.00% # number of cycles we spent at this ipl 168system.cpu.kern.ipl_ticks::total 1829330385500 # number of cycles we spent at this ipl 169system.cpu.kern.ipl_used::0 0.981732 # fraction of swpipl calls that actually changed the ipl 170system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 171system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 172system.cpu.kern.ipl_used::31 0.695541 # fraction of swpipl calls that actually changed the ipl 173system.cpu.kern.ipl_used::total 0.816366 # fraction of swpipl calls that actually changed the ipl 174system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed 175system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed 176system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed 177system.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed 178system.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed 179system.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed 180system.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed 181system.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed 182system.cpu.kern.syscall::20 6 1.84% 35.89% # number of syscalls executed 183system.cpu.kern.syscall::23 4 1.23% 37.12% # number of syscalls executed 184system.cpu.kern.syscall::24 6 1.84% 38.96% # number of syscalls executed 185system.cpu.kern.syscall::33 11 3.37% 42.33% # number of syscalls executed 186system.cpu.kern.syscall::41 2 0.61% 42.94% # number of syscalls executed 187system.cpu.kern.syscall::45 54 16.56% 59.51% # number of syscalls executed 188system.cpu.kern.syscall::47 6 1.84% 61.35% # number of syscalls executed 189system.cpu.kern.syscall::48 10 3.07% 64.42% # number of syscalls executed 190system.cpu.kern.syscall::54 10 3.07% 67.48% # number of syscalls executed 191system.cpu.kern.syscall::58 1 0.31% 67.79% # number of syscalls executed 192system.cpu.kern.syscall::59 7 2.15% 69.94% # number of syscalls executed 193system.cpu.kern.syscall::71 54 16.56% 86.50% # number of syscalls executed 194system.cpu.kern.syscall::73 3 0.92% 87.42% # number of syscalls executed 195system.cpu.kern.syscall::74 16 4.91% 92.33% # number of syscalls executed 196system.cpu.kern.syscall::87 1 0.31% 92.64% # number of syscalls executed 197system.cpu.kern.syscall::90 3 0.92% 93.56% # number of syscalls executed 198system.cpu.kern.syscall::92 9 2.76% 96.32% # number of syscalls executed 199system.cpu.kern.syscall::97 2 0.61% 96.93% # number of syscalls executed 200system.cpu.kern.syscall::98 2 0.61% 97.55% # number of syscalls executed 201system.cpu.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed 202system.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed 203system.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed 204system.cpu.kern.syscall::total 326 # number of syscalls executed 205system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 206system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed 207system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed 208system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed 209system.cpu.kern.callpal::swpctx 4177 2.17% 2.18% # number of callpals executed 210system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed 211system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed 212system.cpu.kern.callpal::swpipl 175246 91.19% 93.40% # number of callpals executed 213system.cpu.kern.callpal::rdps 6771 3.52% 96.92% # number of callpals executed 214system.cpu.kern.callpal::wrkgp 1 0.00% 96.92% # number of callpals executed 215system.cpu.kern.callpal::wrusp 7 0.00% 96.92% # number of callpals executed 216system.cpu.kern.callpal::rdusp 9 0.00% 96.93% # number of callpals executed 217system.cpu.kern.callpal::whami 2 0.00% 96.93% # number of callpals executed 218system.cpu.kern.callpal::rti 5203 2.71% 99.64% # number of callpals executed 219system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed 220system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed 221system.cpu.kern.callpal::total 192177 # number of callpals executed 222system.cpu.kern.mode_switch::kernel 5948 # number of protection mode switches 223system.cpu.kern.mode_switch::user 1735 # number of protection mode switches 224system.cpu.kern.mode_switch::idle 2098 # number of protection mode switches 225system.cpu.kern.mode_good::kernel 1906 226system.cpu.kern.mode_good::user 1735 227system.cpu.kern.mode_good::idle 171 228system.cpu.kern.mode_switch_good::kernel 0.320444 # fraction of useful protection mode switches 229system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 230system.cpu.kern.mode_switch_good::idle 0.081506 # fraction of useful protection mode switches 231system.cpu.kern.mode_switch_good::total 0.389735 # fraction of useful protection mode switches 232system.cpu.kern.mode_ticks::kernel 26832734500 1.47% 1.47% # number of ticks spent at the given mode 233system.cpu.kern.mode_ticks::user 1465059000 0.08% 1.55% # number of ticks spent at the given mode 234system.cpu.kern.mode_ticks::idle 1801032591000 98.45% 100.00% # number of ticks spent at the given mode 235system.cpu.kern.swap_context 4178 # number of times the context was actually changed 236system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 237system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 238system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 239system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 240system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 241system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 242system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 243system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 244system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 245system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 246system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 247system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 248system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR 249system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 250system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 251system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 252system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 253system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 254system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR 255system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 256system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 257system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 258system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 259system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 260system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 261system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 262system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 263system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 264system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 265system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 266system.tsunami.ethernet.droppedPackets 0 # number of packets dropped 267system.cpu.icache.replacements 919577 # number of replacements 268system.cpu.icache.tagsinuse 511.215229 # Cycle average of tags in use 269system.cpu.icache.total_refs 59129371 # Total number of references to valid blocks. 270system.cpu.icache.sampled_refs 920089 # Sample count of references to valid blocks. 271system.cpu.icache.avg_refs 64.264839 # Average number of references to valid blocks. 272system.cpu.icache.warmup_cycle 9686972500 # Cycle when the warmup percentage was hit. 273system.cpu.icache.occ_blocks::cpu.inst 511.215229 # Average occupied blocks per requestor 274system.cpu.icache.occ_percent::cpu.inst 0.998467 # Average percentage of cache occupancy 275system.cpu.icache.occ_percent::total 0.998467 # Average percentage of cache occupancy 276system.cpu.icache.ReadReq_hits::cpu.inst 59129371 # number of ReadReq hits 277system.cpu.icache.ReadReq_hits::total 59129371 # number of ReadReq hits 278system.cpu.icache.demand_hits::cpu.inst 59129371 # number of demand (read+write) hits 279system.cpu.icache.demand_hits::total 59129371 # number of demand (read+write) hits 280system.cpu.icache.overall_hits::cpu.inst 59129371 # number of overall hits 281system.cpu.icache.overall_hits::total 59129371 # number of overall hits 282system.cpu.icache.ReadReq_misses::cpu.inst 920204 # number of ReadReq misses 283system.cpu.icache.ReadReq_misses::total 920204 # number of ReadReq misses 284system.cpu.icache.demand_misses::cpu.inst 920204 # number of demand (read+write) misses 285system.cpu.icache.demand_misses::total 920204 # number of demand (read+write) misses 286system.cpu.icache.overall_misses::cpu.inst 920204 # number of overall misses 287system.cpu.icache.overall_misses::total 920204 # number of overall misses 288system.cpu.icache.ReadReq_accesses::cpu.inst 60049575 # number of ReadReq accesses(hits+misses) 289system.cpu.icache.ReadReq_accesses::total 60049575 # number of ReadReq accesses(hits+misses) 290system.cpu.icache.demand_accesses::cpu.inst 60049575 # number of demand (read+write) accesses 291system.cpu.icache.demand_accesses::total 60049575 # number of demand (read+write) accesses 292system.cpu.icache.overall_accesses::cpu.inst 60049575 # number of overall (read+write) accesses 293system.cpu.icache.overall_accesses::total 60049575 # number of overall (read+write) accesses 294system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.015324 # miss rate for ReadReq accesses 295system.cpu.icache.ReadReq_miss_rate::total 0.015324 # miss rate for ReadReq accesses 296system.cpu.icache.demand_miss_rate::cpu.inst 0.015324 # miss rate for demand accesses 297system.cpu.icache.demand_miss_rate::total 0.015324 # miss rate for demand accesses 298system.cpu.icache.overall_miss_rate::cpu.inst 0.015324 # miss rate for overall accesses 299system.cpu.icache.overall_miss_rate::total 0.015324 # miss rate for overall accesses 300system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 301system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 302system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 303system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 304system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 305system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 306system.cpu.icache.fast_writes 0 # number of fast writes performed 307system.cpu.icache.cache_copies 0 # number of cache copies performed 308system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 309system.cpu.dcache.replacements 2042708 # number of replacements 310system.cpu.dcache.tagsinuse 511.997802 # Cycle average of tags in use 311system.cpu.dcache.total_refs 14038404 # Total number of references to valid blocks. 312system.cpu.dcache.sampled_refs 2043220 # Sample count of references to valid blocks. 313system.cpu.dcache.avg_refs 6.870726 # Average number of references to valid blocks. 314system.cpu.dcache.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. 315system.cpu.dcache.occ_blocks::cpu.data 511.997802 # Average occupied blocks per requestor 316system.cpu.dcache.occ_percent::cpu.data 0.999996 # Average percentage of cache occupancy 317system.cpu.dcache.occ_percent::total 0.999996 # Average percentage of cache occupancy 318system.cpu.dcache.ReadReq_hits::cpu.data 7807768 # number of ReadReq hits 319system.cpu.dcache.ReadReq_hits::total 7807768 # number of ReadReq hits 320system.cpu.dcache.WriteReq_hits::cpu.data 5848199 # number of WriteReq hits 321system.cpu.dcache.WriteReq_hits::total 5848199 # number of WriteReq hits 322system.cpu.dcache.LoadLockedReq_hits::cpu.data 183140 # number of LoadLockedReq hits 323system.cpu.dcache.LoadLockedReq_hits::total 183140 # number of LoadLockedReq hits 324system.cpu.dcache.StoreCondReq_hits::cpu.data 199281 # number of StoreCondReq hits 325system.cpu.dcache.StoreCondReq_hits::total 199281 # number of StoreCondReq hits 326system.cpu.dcache.demand_hits::cpu.data 13655967 # number of demand (read+write) hits 327system.cpu.dcache.demand_hits::total 13655967 # number of demand (read+write) hits 328system.cpu.dcache.overall_hits::cpu.data 13655967 # number of overall hits 329system.cpu.dcache.overall_hits::total 13655967 # number of overall hits 330system.cpu.dcache.ReadReq_misses::cpu.data 1721710 # number of ReadReq misses 331system.cpu.dcache.ReadReq_misses::total 1721710 # number of ReadReq misses 332system.cpu.dcache.WriteReq_misses::cpu.data 304365 # number of WriteReq misses 333system.cpu.dcache.WriteReq_misses::total 304365 # number of WriteReq misses 334system.cpu.dcache.LoadLockedReq_misses::cpu.data 17162 # number of LoadLockedReq misses 335system.cpu.dcache.LoadLockedReq_misses::total 17162 # number of LoadLockedReq misses 336system.cpu.dcache.demand_misses::cpu.data 2026075 # number of demand (read+write) misses 337system.cpu.dcache.demand_misses::total 2026075 # number of demand (read+write) misses 338system.cpu.dcache.overall_misses::cpu.data 2026075 # number of overall misses 339system.cpu.dcache.overall_misses::total 2026075 # number of overall misses 340system.cpu.dcache.ReadReq_accesses::cpu.data 9529478 # number of ReadReq accesses(hits+misses) 341system.cpu.dcache.ReadReq_accesses::total 9529478 # number of ReadReq accesses(hits+misses) 342system.cpu.dcache.WriteReq_accesses::cpu.data 6152564 # number of WriteReq accesses(hits+misses) 343system.cpu.dcache.WriteReq_accesses::total 6152564 # number of WriteReq accesses(hits+misses) 344system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200302 # number of LoadLockedReq accesses(hits+misses) 345system.cpu.dcache.LoadLockedReq_accesses::total 200302 # number of LoadLockedReq accesses(hits+misses) 346system.cpu.dcache.StoreCondReq_accesses::cpu.data 199281 # number of StoreCondReq accesses(hits+misses) 347system.cpu.dcache.StoreCondReq_accesses::total 199281 # number of StoreCondReq accesses(hits+misses) 348system.cpu.dcache.demand_accesses::cpu.data 15682042 # number of demand (read+write) accesses 349system.cpu.dcache.demand_accesses::total 15682042 # number of demand (read+write) accesses 350system.cpu.dcache.overall_accesses::cpu.data 15682042 # number of overall (read+write) accesses 351system.cpu.dcache.overall_accesses::total 15682042 # number of overall (read+write) accesses 352system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.180672 # miss rate for ReadReq accesses 353system.cpu.dcache.ReadReq_miss_rate::total 0.180672 # miss rate for ReadReq accesses 354system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049470 # miss rate for WriteReq accesses 355system.cpu.dcache.WriteReq_miss_rate::total 0.049470 # miss rate for WriteReq accesses 356system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085681 # miss rate for LoadLockedReq accesses 357system.cpu.dcache.LoadLockedReq_miss_rate::total 0.085681 # miss rate for LoadLockedReq accesses 358system.cpu.dcache.demand_miss_rate::cpu.data 0.129197 # miss rate for demand accesses 359system.cpu.dcache.demand_miss_rate::total 0.129197 # miss rate for demand accesses 360system.cpu.dcache.overall_miss_rate::cpu.data 0.129197 # miss rate for overall accesses 361system.cpu.dcache.overall_miss_rate::total 0.129197 # miss rate for overall accesses 362system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 363system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 364system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 365system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 366system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 367system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 368system.cpu.dcache.fast_writes 0 # number of fast writes performed 369system.cpu.dcache.cache_copies 0 # number of cache copies performed 370system.cpu.dcache.writebacks::writebacks 833491 # number of writebacks 371system.cpu.dcache.writebacks::total 833491 # number of writebacks 372system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 373system.cpu.l2cache.replacements 992297 # number of replacements 374system.cpu.l2cache.tagsinuse 65424.375500 # Cycle average of tags in use 375system.cpu.l2cache.total_refs 2433229 # Total number of references to valid blocks. 376system.cpu.l2cache.sampled_refs 1057460 # Sample count of references to valid blocks. 377system.cpu.l2cache.avg_refs 2.301013 # Average number of references to valid blocks. 378system.cpu.l2cache.warmup_cycle 614754000 # Cycle when the warmup percentage was hit. 379system.cpu.l2cache.occ_blocks::writebacks 56309.097195 # Average occupied blocks per requestor 380system.cpu.l2cache.occ_blocks::cpu.inst 4867.351144 # Average occupied blocks per requestor 381system.cpu.l2cache.occ_blocks::cpu.data 4247.927161 # Average occupied blocks per requestor 382system.cpu.l2cache.occ_percent::writebacks 0.859209 # Average percentage of cache occupancy 383system.cpu.l2cache.occ_percent::cpu.inst 0.074270 # Average percentage of cache occupancy 384system.cpu.l2cache.occ_percent::cpu.data 0.064818 # Average percentage of cache occupancy 385system.cpu.l2cache.occ_percent::total 0.998297 # Average percentage of cache occupancy 386system.cpu.l2cache.ReadReq_hits::cpu.inst 906782 # number of ReadReq hits 387system.cpu.l2cache.ReadReq_hits::cpu.data 811232 # number of ReadReq hits 388system.cpu.l2cache.ReadReq_hits::total 1718014 # number of ReadReq hits 389system.cpu.l2cache.Writeback_hits::writebacks 833491 # number of Writeback hits 390system.cpu.l2cache.Writeback_hits::total 833491 # number of Writeback hits 391system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits 392system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits 393system.cpu.l2cache.ReadExReq_hits::cpu.data 187234 # number of ReadExReq hits 394system.cpu.l2cache.ReadExReq_hits::total 187234 # number of ReadExReq hits 395system.cpu.l2cache.demand_hits::cpu.inst 906782 # number of demand (read+write) hits 396system.cpu.l2cache.demand_hits::cpu.data 998466 # number of demand (read+write) hits 397system.cpu.l2cache.demand_hits::total 1905248 # number of demand (read+write) hits 398system.cpu.l2cache.overall_hits::cpu.inst 906782 # number of overall hits 399system.cpu.l2cache.overall_hits::cpu.data 998466 # number of overall hits 400system.cpu.l2cache.overall_hits::total 1905248 # number of overall hits 401system.cpu.l2cache.ReadReq_misses::cpu.inst 13404 # number of ReadReq misses 402system.cpu.l2cache.ReadReq_misses::cpu.data 927640 # number of ReadReq misses 403system.cpu.l2cache.ReadReq_misses::total 941044 # number of ReadReq misses 404system.cpu.l2cache.UpgradeReq_misses::cpu.data 12 # number of UpgradeReq misses 405system.cpu.l2cache.UpgradeReq_misses::total 12 # number of UpgradeReq misses 406system.cpu.l2cache.ReadExReq_misses::cpu.data 117115 # number of ReadExReq misses 407system.cpu.l2cache.ReadExReq_misses::total 117115 # number of ReadExReq misses 408system.cpu.l2cache.demand_misses::cpu.inst 13404 # number of demand (read+write) misses 409system.cpu.l2cache.demand_misses::cpu.data 1044755 # number of demand (read+write) misses 410system.cpu.l2cache.demand_misses::total 1058159 # number of demand (read+write) misses 411system.cpu.l2cache.overall_misses::cpu.inst 13404 # number of overall misses 412system.cpu.l2cache.overall_misses::cpu.data 1044755 # number of overall misses 413system.cpu.l2cache.overall_misses::total 1058159 # number of overall misses 414system.cpu.l2cache.ReadReq_accesses::cpu.inst 920186 # number of ReadReq accesses(hits+misses) 415system.cpu.l2cache.ReadReq_accesses::cpu.data 1738872 # number of ReadReq accesses(hits+misses) 416system.cpu.l2cache.ReadReq_accesses::total 2659058 # number of ReadReq accesses(hits+misses) 417system.cpu.l2cache.Writeback_accesses::writebacks 833491 # number of Writeback accesses(hits+misses) 418system.cpu.l2cache.Writeback_accesses::total 833491 # number of Writeback accesses(hits+misses) 419system.cpu.l2cache.UpgradeReq_accesses::cpu.data 16 # number of UpgradeReq accesses(hits+misses) 420system.cpu.l2cache.UpgradeReq_accesses::total 16 # number of UpgradeReq accesses(hits+misses) 421system.cpu.l2cache.ReadExReq_accesses::cpu.data 304349 # number of ReadExReq accesses(hits+misses) 422system.cpu.l2cache.ReadExReq_accesses::total 304349 # number of ReadExReq accesses(hits+misses) 423system.cpu.l2cache.demand_accesses::cpu.inst 920186 # number of demand (read+write) accesses 424system.cpu.l2cache.demand_accesses::cpu.data 2043221 # number of demand (read+write) accesses 425system.cpu.l2cache.demand_accesses::total 2963407 # number of demand (read+write) accesses 426system.cpu.l2cache.overall_accesses::cpu.inst 920186 # number of overall (read+write) accesses 427system.cpu.l2cache.overall_accesses::cpu.data 2043221 # number of overall (read+write) accesses 428system.cpu.l2cache.overall_accesses::total 2963407 # number of overall (read+write) accesses 429system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014567 # miss rate for ReadReq accesses 430system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.533472 # miss rate for ReadReq accesses 431system.cpu.l2cache.ReadReq_miss_rate::total 0.353901 # miss rate for ReadReq accesses 432system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.750000 # miss rate for UpgradeReq accesses 433system.cpu.l2cache.UpgradeReq_miss_rate::total 0.750000 # miss rate for UpgradeReq accesses 434system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.384805 # miss rate for ReadExReq accesses 435system.cpu.l2cache.ReadExReq_miss_rate::total 0.384805 # miss rate for ReadExReq accesses 436system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014567 # miss rate for demand accesses 437system.cpu.l2cache.demand_miss_rate::cpu.data 0.511327 # miss rate for demand accesses 438system.cpu.l2cache.demand_miss_rate::total 0.357075 # miss rate for demand accesses 439system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014567 # miss rate for overall accesses 440system.cpu.l2cache.overall_miss_rate::cpu.data 0.511327 # miss rate for overall accesses 441system.cpu.l2cache.overall_miss_rate::total 0.357075 # miss rate for overall accesses 442system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 443system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 444system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 445system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 446system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 447system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 448system.cpu.l2cache.fast_writes 0 # number of fast writes performed 449system.cpu.l2cache.cache_copies 0 # number of cache copies performed 450system.cpu.l2cache.writebacks::writebacks 74287 # number of writebacks 451system.cpu.l2cache.writebacks::total 74287 # number of writebacks 452system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 453 454---------- End Simulation Statistics ---------- 455