xref: /gem5/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.033333                       # Number of seconds simulated
sim_ticks                                 33333078000                       # Number of ticks simulated
final_tick                                33333078000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 125008                       # Simulator instruction rate (inst/s)
host_op_rate                                   159871                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                               58765299                       # Simulator tick rate (ticks/s)
host_mem_usage                                 325044                       # Number of bytes of host memory used
host_seconds                                   567.22                       # Real time elapsed on the host
sim_insts                                    70907630                       # Number of instructions simulated
sim_ops                                      90682585                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu.inst            591360                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data           2521216                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.l2cache.prefetcher      6195328                       # Number of bytes read from this memory
system.physmem.bytes_read::total              9307904                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       591360                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          591360                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      6264192                       # Number of bytes written to this memory
system.physmem.bytes_written::total           6264192                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst               9240                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data              39394                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.l2cache.prefetcher        96802                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                145436                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks           97878                       # Number of write requests responded to by this memory
system.physmem.num_writes::total                97878                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst             17740936                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data             75637059                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.l2cache.prefetcher    185861264                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total               279239259                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst        17740936                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total           17740936                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks         187927200                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total              187927200                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks         187927200                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst            17740936                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data            75637059                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.l2cache.prefetcher    185861264                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total              467166458                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        145436                       # Number of read requests accepted
system.physmem.writeReqs                        97878                       # Number of write requests accepted
system.physmem.readBursts                      145436                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                      97878                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                  9300544                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                      7360                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   6263104                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                   9307904                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                6264192                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      115                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              6                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0                9151                       # Per bank write bursts
system.physmem.perBankRdBursts::1                9416                       # Per bank write bursts
system.physmem.perBankRdBursts::2                9264                       # Per bank write bursts
system.physmem.perBankRdBursts::3                9524                       # Per bank write bursts
system.physmem.perBankRdBursts::4                9728                       # Per bank write bursts
system.physmem.perBankRdBursts::5                9774                       # Per bank write bursts
system.physmem.perBankRdBursts::6                9086                       # Per bank write bursts
system.physmem.perBankRdBursts::7                9016                       # Per bank write bursts
system.physmem.perBankRdBursts::8                9170                       # Per bank write bursts
system.physmem.perBankRdBursts::9                8620                       # Per bank write bursts
system.physmem.perBankRdBursts::10               8843                       # Per bank write bursts
system.physmem.perBankRdBursts::11               8715                       # Per bank write bursts
system.physmem.perBankRdBursts::12               8697                       # Per bank write bursts
system.physmem.perBankRdBursts::13               8672                       # Per bank write bursts
system.physmem.perBankRdBursts::14               8700                       # Per bank write bursts
system.physmem.perBankRdBursts::15               8945                       # Per bank write bursts
system.physmem.perBankWrBursts::0                6002                       # Per bank write bursts
system.physmem.perBankWrBursts::1                6227                       # Per bank write bursts
system.physmem.perBankWrBursts::2                6156                       # Per bank write bursts
system.physmem.perBankWrBursts::3                6165                       # Per bank write bursts
system.physmem.perBankWrBursts::4                6066                       # Per bank write bursts
system.physmem.perBankWrBursts::5                6338                       # Per bank write bursts
system.physmem.perBankWrBursts::6                6039                       # Per bank write bursts
system.physmem.perBankWrBursts::7                6021                       # Per bank write bursts
system.physmem.perBankWrBursts::8                6032                       # Per bank write bursts
system.physmem.perBankWrBursts::9                6183                       # Per bank write bursts
system.physmem.perBankWrBursts::10               6239                       # Per bank write bursts
system.physmem.perBankWrBursts::11               5928                       # Per bank write bursts
system.physmem.perBankWrBursts::12               6101                       # Per bank write bursts
system.physmem.perBankWrBursts::13               6124                       # Per bank write bursts
system.physmem.perBankWrBursts::14               6211                       # Per bank write bursts
system.physmem.perBankWrBursts::15               6029                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                     33332792500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  145436                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                  97878                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                     41531                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     55128                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                     14558                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                     10364                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                      5987                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                      5214                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                      4599                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                      4263                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                      3539                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                        86                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                       42                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        6                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        3                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     1148                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     1184                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     1918                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     2582                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     3353                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     4290                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     5332                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     5723                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     5988                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     6224                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     6557                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     7007                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     7623                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     8324                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     9140                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     7906                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     6877                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     6327                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                      206                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                       85                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                       44                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                       14                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                       11                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        88939                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      174.992388                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     110.439382                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     239.025071                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          52267     58.77%     58.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        22760     25.59%     84.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         4436      4.99%     89.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         1732      1.95%     91.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         1066      1.20%     92.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767          777      0.87%     93.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895          661      0.74%     94.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023          818      0.92%     95.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151         4422      4.97%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          88939                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          5911                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        24.584503                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::gmean       21.105941                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      187.238550                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-511            5910     99.98%     99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::14336-14847            1      0.02%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            5911                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          5911                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        16.555744                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       16.512900                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev        1.266741                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16               4704     79.58%     79.58% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::17                 36      0.61%     80.19% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18                781     13.21%     93.40% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::19                157      2.66%     96.06% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20                 88      1.49%     97.55% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::21                 64      1.08%     98.63% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::22                 47      0.80%     99.42% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::23                 14      0.24%     99.66% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24                 17      0.29%     99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::25                  2      0.03%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::26                  1      0.02%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            5911                       # Writes before turning the bus around for reads
system.physmem.totQLat                     7028707749                       # Total ticks spent queuing
system.physmem.totMemAccLat                9753476499                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                    726605000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       48366.77                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  67116.77                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                         279.02                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                         187.89                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                      279.24                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                      187.93                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           3.65                       # Data bus utilization in percentage
system.physmem.busUtilRead                       2.18                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      1.47                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.59                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        24.82                       # Average write queue length when enqueuing
system.physmem.readRowHits                     118079                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     36164                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   81.25                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  36.95                       # Row buffer hit rate for writes
system.physmem.avgGap                       136994.96                       # Average gap between requests
system.physmem.pageHitRate                      63.42                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                  343934640                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                  187662750                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                 584680200                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                317610720                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy             2177145360                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy            11782825965                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy             9664105500                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy              25057965135                       # Total energy per rank (pJ)
system.physmem_0.averagePower              751.742046                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE    15979863754                       # Time in different power states
system.physmem_0.memoryStateTime::REF      1112800000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT     16240286246                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                  328444200                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                  179210625                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                 548823600                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                316528560                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy             2177145360                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy            11298113640                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy            10089291750                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy              24937557735                       # Total energy per rank (pJ)
system.physmem_1.averagePower              748.129809                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE    16691408912                       # Time in different power states
system.physmem_1.memoryStateTime::REF      1112800000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT     15528741088                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.cpu.branchPred.lookups                17206633                       # Number of BP lookups
system.cpu.branchPred.condPredicted          11518078                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect            648316                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups              9346074                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                 7675410                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             82.124430                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                 1873047                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect             101552                       # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.dtb.walker.walks                         0                       # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                            0                       # DTB read hits
system.cpu.dtb.read_misses                          0                       # DTB read misses
system.cpu.dtb.write_hits                           0                       # DTB write hits
system.cpu.dtb.write_misses                         0                       # DTB write misses
system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                        0                       # DTB read accesses
system.cpu.dtb.write_accesses                       0                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                                 0                       # DTB hits
system.cpu.dtb.misses                               0                       # DTB misses
system.cpu.dtb.accesses                             0                       # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.itb.walker.walks                         0                       # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits                            0                       # ITB inst hits
system.cpu.itb.inst_misses                          0                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
system.cpu.itb.hits                                 0                       # DTB hits
system.cpu.itb.misses                               0                       # DTB misses
system.cpu.itb.accesses                             0                       # DTB accesses
system.cpu.workload.num_syscalls                 1946                       # Number of system calls
system.cpu.numCycles                         66666157                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles            5010938                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                       88191821                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                    17206633                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches            9548457                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                      60137734                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                 1322663                       # Number of cycles fetch has spent squashing
system.cpu.fetch.MiscStallCycles                 6978                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles            23                       # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles        13644                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                  22767110                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes                 69105                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples           65830648                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              1.695372                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             1.296604                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                 20050738     30.46%     30.46% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                  8265796     12.56%     43.01% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                  9200690     13.98%     56.99% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                 28313424     43.01%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                3                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total             65830648                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.258101                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        1.322887                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                  8588438                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles              19545167                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                  31574635                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles               5630215                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles                 492193                       # Number of cycles decode is squashing
system.cpu.decode.BranchResolved              3180012                       # Number of times decode resolved a branch
system.cpu.decode.BranchMispred                171001                       # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts              101409826                       # Number of instructions handled by decode
system.cpu.decode.SquashedInsts               3046686                       # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles                 492193                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                 13345278                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles                 5337889                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles         804170                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                  32233077                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles              13618041                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts               99203464                       # Number of instructions processed by rename
system.cpu.rename.SquashedInsts                983266                       # Number of squashed instructions processed by rename
system.cpu.rename.ROBFullEvents               3848076                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents                  66970                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents                4316860                       # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents                5302934                       # Number of times rename has blocked due to SQ full
system.cpu.rename.RenamedOperands           103925476                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups             457709098                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups        115412648                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups               550                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps              93629226                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                 10296250                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts              18661                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts          18653                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                  12703257                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads             24321959                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores            21992794                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads           1408685                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores          2344134                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                   98166936                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded               34525                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                  94895750                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued            693672                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined         7518876                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined     20249831                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved            739                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples      65830648                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         1.441513                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        1.149732                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0            17559708     26.67%     26.67% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1            17428340     26.47%     53.15% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2            17111473     25.99%     79.14% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3            11681013     17.74%     96.89% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4             2049145      3.11%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5                 969      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6                   0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7                   0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8                   0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total        65830648                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                 6713649     22.39%     22.39% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                     39      0.00%     22.39% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%     22.39% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%     22.39% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%     22.39% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%     22.39% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%     22.39% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%     22.39% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     22.39% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%     22.39% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     22.39% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%     22.39% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%     22.39% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%     22.39% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%     22.39% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%     22.39% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     22.39% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%     22.39% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     22.39% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     22.39% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     22.39% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     22.39% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     22.39% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     22.39% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     22.39% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     22.39% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     22.39% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     22.39% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     22.39% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead               11199453     37.36%     59.75% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite              12066123     40.25%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu              49496629     52.16%     52.16% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult                89874      0.09%     52.25% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     52.25% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                  31      0.00%     52.25% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     52.25% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     52.25% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     52.25% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     52.25% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     52.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     52.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     52.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     52.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     52.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     52.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     52.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     52.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     52.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     52.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     52.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     52.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     52.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     52.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     52.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     52.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     52.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc              7      0.00%     52.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     52.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     52.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     52.25% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead             24067515     25.36%     77.62% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite            21241694     22.38%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total               94895750                       # Type of FU issued
system.cpu.iq.rate                           1.423447                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                    29979264                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.315918                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads          286294877                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes         105731606                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses     93465380                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads                 207                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes                248                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses           57                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses              124874896                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                     118                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads          1362273                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads      1455697                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses         2068                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation        11776                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores      1437056                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads       140882                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked        184054                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles                 492193                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                  620956                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles                467696                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts            98211315                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts                 0                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts              24321959                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts             21992794                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts              18605                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                   1621                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents                463138                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents          11776                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect         302825                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect       221559                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts               524384                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts              93978064                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts              23759823                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts            917686                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                          9854                       # number of nop insts executed
system.cpu.iew.exec_refs                     44744798                       # number of memory reference insts executed
system.cpu.iew.exec_branches                 14251807                       # Number of branches executed
system.cpu.iew.exec_stores                   20984975                       # Number of stores executed
system.cpu.iew.exec_rate                     1.409682                       # Inst execution rate
system.cpu.iew.wb_sent                       93587077                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                      93465437                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                  44977935                       # num instructions producing a value
system.cpu.iew.wb_consumers                  76555853                       # num instructions consuming a value
system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate                       1.401992                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.587518                       # average fanout of values written-back
system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts         6538600                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls           33786                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts            479178                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples     64771963                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     1.400114                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     2.164673                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0     31176340     48.13%     48.13% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1     16804620     25.94%     74.08% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2      4339366      6.70%     80.78% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3      4157771      6.42%     87.20% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4      1944331      3.00%     90.20% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5      1263277      1.95%     92.15% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6       736800      1.14%     93.28% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7       578701      0.89%     94.18% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8      3770757      5.82%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total     64771963                       # Number of insts commited each cycle
system.cpu.commit.committedInsts             70913182                       # Number of instructions committed
system.cpu.commit.committedOps               90688137                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                       43422000                       # Number of memory references committed
system.cpu.commit.loads                      22866262                       # Number of loads committed
system.cpu.commit.membars                       15920                       # Number of memory barriers committed
system.cpu.commit.branches                   13741486                       # Number of branches committed
system.cpu.commit.fp_insts                         56                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                  81528487                       # Number of committed integer instructions.
system.cpu.commit.function_calls              1679850                       # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
system.cpu.commit.op_class_0::IntAlu         47186011     52.03%     52.03% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult           80119      0.09%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv                0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd              0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp              0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt              0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult             0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv              0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd               0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu               0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp               0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt               0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc              0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult              0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift             0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd            0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp            0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt            0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc            7      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead        22866262     25.21%     77.33% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite       20555738     22.67%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total          90688137                       # Class of committed instruction
system.cpu.commit.bw_lim_events               3770757                       # number cycles where commit BW limit reached
system.cpu.rob.rob_reads                    158202644                       # The number of ROB reads
system.cpu.rob.rob_writes                   195513856                       # The number of ROB writes
system.cpu.timesIdled                           23729                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                          835509                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts                    70907630                       # Number of Instructions Simulated
system.cpu.committedOps                      90682585                       # Number of Ops (including micro ops) Simulated
system.cpu.cpi                               0.940183                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         0.940183                       # CPI: Total CPI of All Threads
system.cpu.ipc                               1.063623                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         1.063623                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads                102275291                       # number of integer regfile reads
system.cpu.int_regfile_writes                56793629                       # number of integer regfile writes
system.cpu.fp_regfile_reads                        36                       # number of floating regfile reads
system.cpu.fp_regfile_writes                       21                       # number of floating regfile writes
system.cpu.cc_regfile_reads                 346102642                       # number of cc regfile reads
system.cpu.cc_regfile_writes                 38804681                       # number of cc regfile writes
system.cpu.misc_regfile_reads                44209969                       # number of misc regfile reads
system.cpu.misc_regfile_writes                  31840                       # number of misc regfile writes
system.cpu.dcache.tags.replacements            485047                       # number of replacements
system.cpu.dcache.tags.tagsinuse           510.741433                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs            40420740                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs            485559                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs             83.245785                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle         153056500                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data   510.741433                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.997542                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.997542                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0           58                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1          454                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses          84615723                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses         84615723                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data     21498446                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total        21498446                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data     18830779                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total       18830779                       # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data        60221                       # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total         60221                       # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data        15346                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total        15346                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data        15919                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total        15919                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data      40329225                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         40329225                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data     40389446                       # number of overall hits
system.cpu.dcache.overall_hits::total        40389446                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data       556041                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total        556041                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data      1019122                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total      1019122                       # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data        68628                       # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total        68628                       # number of SoftPFReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data          580                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total          580                       # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data      1575163                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        1575163                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      1643791                       # number of overall misses
system.cpu.dcache.overall_misses::total       1643791                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data   8960046000                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total   8960046000                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data  14598887903                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total  14598887903                       # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data      5237000                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total      5237000                       # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data  23558933903                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total  23558933903                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data  23558933903                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total  23558933903                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data     22054487                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total     22054487                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data     19849901                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total     19849901                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data       128849                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total       128849                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data        15926                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total        15926                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data        15919                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total        15919                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data     41904388                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     41904388                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data     42033237                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     42033237                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.025212                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.025212                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.051341                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.051341                       # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.532623                       # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total     0.532623                       # miss rate for SoftPFReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.036418                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.036418                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.037589                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.037589                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.039107                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.039107                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16114.002385                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 16114.002385                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 14324.965905                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 14324.965905                       # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data  9029.310345                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total  9029.310345                       # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 14956.505392                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 14956.505392                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 14332.073787                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 14332.073787                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs           55                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets      3099418                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 6                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets          130265                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs     9.166667                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets    23.793175                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks       261117                       # number of writebacks
system.cpu.dcache.writebacks::total            261117                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data       256598                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total       256598                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data       870592                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total       870592                       # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data          580                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total          580                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data      1127190                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total      1127190                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data      1127190                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total      1127190                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data       299443                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total       299443                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       148530                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       148530                       # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data        37597                       # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total        37597                       # number of SoftPFReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data       447973                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total       447973                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data       485570                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total       485570                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   3193306500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total   3193306500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   2352659965                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total   2352659965                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   2013580000                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   2013580000                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data   5545966465                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total   5545966465                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data   7559546465                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total   7559546465                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.013577                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.013577                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.007483                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.007483                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.291791                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.291791                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.010690                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.010690                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.011552                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.011552                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 10664.154781                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 10664.154781                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 15839.628122                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 15839.628122                       # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53556.932734                       # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53556.932734                       # average SoftPFReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12380.135555                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 12380.135555                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15568.396863                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 15568.396863                       # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.icache.tags.replacements            322838                       # number of replacements
system.cpu.icache.tags.tagsinuse           510.295109                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs            22432857                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs            323350                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs             69.376394                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle        1105263500                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   510.295109                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.996670                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.996670                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           89                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1           57                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2            6                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3          353                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4            7                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses          45857337                       # Number of tag accesses
system.cpu.icache.tags.data_accesses         45857337                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst     22432857                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total        22432857                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst      22432857                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total         22432857                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst     22432857                       # number of overall hits
system.cpu.icache.overall_hits::total        22432857                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst       334131                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total        334131                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst       334131                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total         334131                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst       334131                       # number of overall misses
system.cpu.icache.overall_misses::total        334131                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst   3372669901                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total   3372669901                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst   3372669901                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total   3372669901                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst   3372669901                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total   3372669901                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst     22766988                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total     22766988                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst     22766988                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total     22766988                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst     22766988                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total     22766988                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.014676                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.014676                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.014676                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.014676                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.014676                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.014676                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 10093.855108                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 10093.855108                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 10093.855108                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 10093.855108                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 10093.855108                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 10093.855108                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs       274760                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets          147                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs             16673                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               3                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs    16.479338                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets           49                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst        10770                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total        10770                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst        10770                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total        10770                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst        10770                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total        10770                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst       323361                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total       323361                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst       323361                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total       323361                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst       323361                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total       323361                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   3089767447                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total   3089767447                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst   3089767447                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total   3089767447                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst   3089767447                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total   3089767447                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.014203                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.014203                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.014203                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.014203                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.014203                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.014203                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst  9555.164188                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total  9555.164188                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst  9555.164188                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total  9555.164188                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst  9555.164188                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total  9555.164188                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.prefetcher.num_hwpf_issued       824514                       # number of hwpf issued
system.cpu.l2cache.prefetcher.pfIdentified       825954                       # number of prefetch candidates identified
system.cpu.l2cache.prefetcher.pfBufferHit         1262                       # number of redundant prefetches already in prefetch queue
system.cpu.l2cache.prefetcher.pfInCache             0                       # number of redundant prefetches already in cache/mshr dropped
system.cpu.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
system.cpu.l2cache.prefetcher.pfSpanPage        78678                       # number of prefetches not generated due to page crossing
system.cpu.l2cache.tags.replacements           129552                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        16077.997606                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs            1332384                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs           145834                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs             9.136306                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 12589.252408                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst  1431.737238                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data  1938.355630                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher   118.652331                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.768387                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.087386                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.118308                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher     0.007242                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.981323                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1022           37                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_blocks::1024        16245                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::1            8                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::2            3                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::3           22                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::4            4                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0          155                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1         2643                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2        12025                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3          539                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4          883                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1022     0.002258                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.991516                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses         24885703                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses        24885703                       # Number of data accesses
system.cpu.l2cache.Writeback_hits::writebacks       261117                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total       261117                       # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data            5                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total            5                       # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data       137140                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total       137140                       # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst       314068                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total       314068                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data       305844                       # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total       305844                       # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.inst       314068                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data       442984                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total          757052                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst       314068                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data       442984                       # number of overall hits
system.cpu.l2cache.overall_hits::total         757052                       # number of overall hits
system.cpu.l2cache.UpgradeReq_misses::cpu.data            6                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total            6                       # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data        11428                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total        11428                       # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         9278                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total         9278                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data        31147                       # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total        31147                       # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst         9278                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data        42575                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total         51853                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst         9278                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data        42575                       # number of overall misses
system.cpu.l2cache.overall_misses::total        51853                       # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   1235483500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total   1235483500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    721965000                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total    721965000                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data   2691191000                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total   2691191000                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst    721965000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data   3926674500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total   4648639500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst    721965000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data   3926674500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total   4648639500                       # number of overall miss cycles
system.cpu.l2cache.Writeback_accesses::writebacks       261117                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total       261117                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data           11                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total           11                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       148568                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       148568                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst       323346                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total       323346                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data       336991                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total       336991                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst       323346                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data       485559                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total       808905                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst       323346                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data       485559                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total       808905                       # number of overall (read+write) accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.545455                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.545455                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.076921                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.076921                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.028694                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.028694                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.092427                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.092427                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.028694                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.087682                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.064103                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.028694                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.087682                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.064103                       # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 108110.211761                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 108110.211761                       # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 77814.723001                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 77814.723001                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 86402.895945                       # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 86402.895945                       # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77814.723001                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 92229.583089                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 89650.348099                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77814.723001                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 92229.583089                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 89650.348099                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks        97878                       # number of writebacks
system.cpu.l2cache.writebacks::total            97878                       # number of writebacks
system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data         3042                       # number of ReadExReq MSHR hits
system.cpu.l2cache.ReadExReq_mshr_hits::total         3042                       # number of ReadExReq MSHR hits
system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst           38                       # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadCleanReq_mshr_hits::total           38                       # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data          139                       # number of ReadSharedReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::total          139                       # number of ReadSharedReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst           38                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data         3181                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total         3219                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst           38                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data         3181                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total         3219                       # number of overall MSHR hits
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks         3552                       # number of CleanEvict MSHR misses
system.cpu.l2cache.CleanEvict_mshr_misses::total         3552                       # number of CleanEvict MSHR misses
system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher       112510                       # number of HardPFReq MSHR misses
system.cpu.l2cache.HardPFReq_mshr_misses::total       112510                       # number of HardPFReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data            6                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total            6                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         8386                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total         8386                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         9240                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total         9240                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data        31008                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total        31008                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst         9240                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data        39394                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total        48634                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst         9240                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data        39394                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher       112510                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       161144                       # number of overall MSHR misses
system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher  10641572084                       # number of HardPFReq MSHR miss cycles
system.cpu.l2cache.HardPFReq_mshr_miss_latency::total  10641572084                       # number of HardPFReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data       100500                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total       100500                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    677751000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    677751000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    663843000                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    663843000                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   2494831000                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   2494831000                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    663843000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   3172582000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total   3836425000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    663843000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   3172582000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher  10641572084                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total  14477997084                       # number of overall MSHR miss cycles
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.545455                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.545455                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.056446                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.056446                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.028576                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.028576                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.092014                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.092014                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.028576                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.081131                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.060123                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.028576                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.081131                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.199213                       # mshr miss rate for overall accesses
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 94583.344449                       # average HardPFReq mshr miss latency
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 94583.344449                       # average HardPFReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data        16750                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total        16750                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80819.341760                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80819.341760                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 71844.480519                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 71844.480519                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 80457.656089                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 80457.656089                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71844.480519                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 80534.649947                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 78883.599951                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71844.480519                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 80534.649947                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 94583.344449                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 89845.089386                       # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadResp        660352                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback       358995                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict       498597                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::HardPFReq       141207                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq           11                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp           11                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq       148568                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp       148568                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq       323361                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq       336991                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       938997                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      1406890                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total           2345887                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     20694144                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     47787264                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total           68481408                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                      270774                       # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples      1887575                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean        1.143443                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev       0.350524                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1            1616816     85.66%     85.66% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2             270759     14.34%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total        1887575                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy     1069525000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          3.2                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy     485192198                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          1.5                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy     728416355                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          2.2                       # Layer utilization (%)
system.membus.trans_dist::ReadResp             137050                       # Transaction distribution
system.membus.trans_dist::Writeback             97878                       # Transaction distribution
system.membus.trans_dist::CleanEvict            30539                       # Transaction distribution
system.membus.trans_dist::UpgradeReq                6                       # Transaction distribution
system.membus.trans_dist::UpgradeResp               6                       # Transaction distribution
system.membus.trans_dist::ReadExReq              8386                       # Transaction distribution
system.membus.trans_dist::ReadExResp             8386                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq        137050                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       419301                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                 419301                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     15572096                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                15572096                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                                0                       # Total snoops (count)
system.membus.snoop_fanout::samples            273859                       # Request fanout histogram
system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                  273859    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
system.membus.snoop_fanout::total              273859                       # Request fanout histogram
system.membus.reqLayer0.occupancy           740935905                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               2.2                       # Layer utilization (%)
system.membus.respLayer1.occupancy          757820949                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              2.3                       # Layer utilization (%)

---------- End Simulation Statistics   ----------