stats: Update some stats after simulated program exit behavior was changed.

The following CL delayed program exit and changed the stats for many if not
most of the SE mode regressions.

commit 2c1286865fc2542a0586ca4ff40b00765d17b348
Author: Brandon Potter <Brandon.Potter@amd.com>
Date: Wed Mar 1 14:52:23 2017 -0600

syscall-emul: Rewrite system call exit code

Change-Id: Id241f2b7d5374947597c715ee44febe1acc5ea16
Reviewed-on: https://gem5-review.googlesource.com/2656
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

stats: Rename num_syscalls to numSyscalls in the reference stats.

The name of the stat was changed in the following change which broke all the
reference outputs.

commit 2367198921765848a4f5b3d020a7cc5776209f80
Author: Brandon Potter <brandon.potter@amd.com>
Date: Mon Feb 27 14:10:15 2017 -0500

syscall_emul: [PATCH 15/22] add clone/execve for threading and
multiprocess simulations

Change-Id: Id98b085ccae098c50c434ad81a72beee46084f40
Reviewed-on: https://gem5-review.googlesource.com/2651
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

stats: Get all stats updated to reflect current behaviour

Line everything up again.

stats: Update stats to reflect cache changes

stats: Update stats to reflect recent changes to floats

Mostly just splitting out the floats ops and corresponding
reads/writes.

stats: update references

stats: Update to match classic memory changes

stats: update references

stats: update references

stats: Add power stats to test references

Change-Id: Ic827213134b199446822f128b81d4a480e777fee

stats: Update to match ARM ISA changes

stats: update and fix e273e86a873d

stats: update for snoop filter tweak

stats: Update stats to reflect cache changes

Removed unused stats, now counting WriteLineReq, and changed how
uncacheable writes are handled while responses are outstanding.

stats: Match current behaviour

Small changes to the branch predictor and BTB caused stats changes
throughout.

stats: update stats for mmap changes

stats: update stats for mmap() change.

SE O3 runs see an additional reg read per mmap() call.

stats: Update stats to reflect changes to cache and crossbar

stats: remove wb_penalized and wb_penalized_rate

stats: Update stats to match cache changes

stats: Update stats to reflect snoop-filter changes

stats: Update stats for clean eviction addition

stats: Update stats for cache, crossbar and DRAM changes

This update includes the changes to whole-line writes, the refinement
of Read to ReadClean and ReadShared, the introduction of CleanEvict
for snoop-filter tracking, and updates to the DRAM command scheduler
for bank-group-aware scheduling.

Needless to say, almost every regression is affected.

stats: Update stats to reflect cache changes

stats: arm: updates

stats: update for previous changeset

Very small differences in IQ-specific O3 stats.

stats: changes to due to recent set of patches

stats: Update stats to reflect cache and interconnect changes

This is a bulk update of stats to match the changes to cache timing,
interconnect timing, and a few minor changes to the o3 CPU.

stats: Bump stats for decoder, TLB, prefetcher and DRAM changes

Changes due to speculative execution of an unaligned PC, introduction
of TLB stats, changes and re-work of the prefetcher, and the
introduction of rank-wise refresh in the DRAM controller.

stats: updates due to previous mmap and exit_group patches.

stats: Add DRAM power statistics to reference output

stats: Bump stats for filter, crossbar and config changes

This patch bumps the stats to reflect the addition of the snoop filter
and snoop stats, the change from bus to crossbar, and the updates to
the ARM regressions that are now using a different CPU and cache
configuration. Lastly, some minor changes are expected due to the
activation cleanup of the CPUs.

stats: Update stats for CPU and cache changes

This patch updates the stats to reflect the fixes and changes to the
CPU (mainly the o3), and the caches.

stats: update for O3 changes

Mostly small differences in total ticks, but O3 stall causes
shifted significantly.

30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex
by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8%
slower.

stats: changes due to o3 cpu and ruby message buffer patches

stats: Bump stats for the fixes, and mostly DRAM controller changes

stats: Update stats for DRAM changes

This patch updates the stats to reflect the changes to the DRAM
controller.

stats: update stats for ARMv8 changes

stats: update stats for cache occupancy and clock domain changes

stats: updates due to changes to ticksToCycles()

stats: Bump stats to match DRAM controller changes

This patch encompasses all the stats updates needed to reflect the
changes to the DRAM controller.

test: update stats

Update stats for recent changes. Mostly minor changes
in register access stats due to addition of new cc
register type and slightly different (and more accurate)
classification of int vs. fp register accesses.

stats: Cumulative stats update

This patch updates the stats to reflect the: 1) addition of the
internal queue in SimpleMemory, 2) moving of the memory class outside
FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying
burst size and interface width for the DRAM instead of relying on
cache-line size, 5) performing merging in the DRAM controller write
buffer, and 6) fixing how idle cycles are counted in the atomic and
timing CPU models.

The main reason for bundling them up is to minimise the changeset
size.

stats: Update stats for monitor, cache and bus changes

This patch removes the sparse histogram total from the CommMonitor
stats. It also bumps the stats after the unit fixes in the atomic
cache access. Lastly, it updates the stats to match the new port
ordering. All numbers are the same, and the only thing that changes is
which master corresponds to what port index.

stats: Update the stats to reflect bus and memory changes

This patch updates the stats to reflect the addition of the bus stats,
and changes to the bus layers. In addition it updates the stats to
match the addition of the static pipeline latency of the memory
conotroller and the addition of a stat tracking the bytes per
activate.

stats: Bump the vortex stats to match latest behaviour

This patch bumps the stats for the failing vortex o3 regression.

regressions: update due to cache latency fix

stats: Update stats to reflect bus retry changes

This patch updates the stats after splitting the bus retry into
waiting for the bus and waiting for the peer.

stats: update patches for branch predictor and fetch updates.

stats: Update stats to reflect SimpleDRAM changes

This patch bumps the stats to reflect the slight change in how the
retry is handled, and also the pruning of some redundant stats.

stats: Update stats for regressions using SimpleDDR3

This patch updates the regression stats to reflect that they are using
the SimpleDDR3 controller by default.

regressions: update stats due to branch predictor changes
The actual statistical values are being updated for only two tests belonging
to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others
the patch updates config.ini and name changes to statistical variables.

stats: update stats for previous six changes

stats: update stats for previous changes.

regressions: stats update due to decoder changes

update stats for preceeding changes

stats: Update stats for unified cache configuration

This patch updates the stats to reflect the changes in the L2 MSHRs,
as the latter are now uniform across the regressions.

stats: Update stats to reflect use of SimpleDRAM

This patch bumps the stats to match the use of SimpleDRAM instead of
SimpleMemory in all inorder and O3 regressions, and also all
full-system regressions. A number of performance-related stats change,
and a whole bunch of stats are added for the memory controller.

Stats: Update stats for cache timings in cycles

This patch updates the stats to reflect the change in how cache
latencies are expressed. In addition, the latencies are now rounded to
multiples of the clock period, thus also affecting other stats.

Stats: Update stats for new default L1-to-L2 bus clock and width

This patch updates the stats to reflect the changes in the clock speed
and width for the bus connecting the L1 and L2 caches.

ARM: update stats for bp and squash fixes.

Stats: Update stats to reflect SimpleMemory bandwidth

This patch simply bumps the stats to reflect the introduction of a
bandwidth limit of 12.8GB/s for SimpleMemory.

Stats: Remove the reference stats that are no longer present

This patch simply removes the commitCommittedInsts and
commitCommittedOps from the reference statistics, following their
removal from the CPU.

Stats: Updates due to bus changes

This patch bumps all the stats to reflect the bus changes, i.e. the
introduction of the state variable, the division into a request and
response layer, and the new default bus width of 8 bytes.

Stats: Update stats for RAS and LRU fixes.

all: Update stats for memory per master and total fix.

stats: update stats for no_value -> nan
Lots of accumulated older changes too.

ARM: Update stats for IT and conditional branch changes

ARM: Update stats for CBNZ fix.

bp: fix up stats for changes to branch predictor

stats: update stats for insts/ops and master id changes

Regressions: Update stats due to O3 CPU changes

SE/FS: Make both SE and FS tests available all the time.