stats.txt revision 9978:81d7551dd3be
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.026816 # Number of seconds simulated 4sim_ticks 26816405500 # Number of ticks simulated 5final_tick 26816405500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 109329 # Simulator instruction rate (inst/s) 8host_op_rate 155152 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 41346943 # Simulator tick rate (ticks/s) 10host_mem_usage 283460 # Number of bytes of host memory used 11host_seconds 648.57 # Real time elapsed on the host 12sim_insts 70907629 # Number of instructions simulated 13sim_ops 100626876 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 298432 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 7942848 # Number of bytes read from this memory 16system.physmem.bytes_read::total 8241280 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 298432 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 298432 # Number of instructions bytes read from this memory 19system.physmem.bytes_written::writebacks 5372096 # Number of bytes written to this memory 20system.physmem.bytes_written::total 5372096 # Number of bytes written to this memory 21system.physmem.num_reads::cpu.inst 4663 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 124107 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 128770 # Number of read requests responded to by this memory 24system.physmem.num_writes::writebacks 83939 # Number of write requests responded to by this memory 25system.physmem.num_writes::total 83939 # Number of write requests responded to by this memory 26system.physmem.bw_read::cpu.inst 11128710 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::cpu.data 296193612 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_read::total 307322322 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::cpu.inst 11128710 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_inst_read::total 11128710 # Instruction read bandwidth from this memory (bytes/s) 31system.physmem.bw_write::writebacks 200328713 # Write bandwidth from this memory (bytes/s) 32system.physmem.bw_write::total 200328713 # Write bandwidth from this memory (bytes/s) 33system.physmem.bw_total::writebacks 200328713 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bw_total::cpu.inst 11128710 # Total bandwidth to/from this memory (bytes/s) 35system.physmem.bw_total::cpu.data 296193612 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::total 507651035 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.readReqs 128770 # Number of read requests accepted 38system.physmem.writeReqs 83939 # Number of write requests accepted 39system.physmem.readBursts 128770 # Number of DRAM read bursts, including those serviced by the write queue 40system.physmem.writeBursts 83939 # Number of DRAM write bursts, including those merged in the write queue 41system.physmem.bytesReadDRAM 8241152 # Total number of bytes read from DRAM 42system.physmem.bytesReadWrQ 128 # Total number of bytes read from write queue 43system.physmem.bytesWritten 5371520 # Total number of bytes written to DRAM 44system.physmem.bytesReadSys 8241280 # Total read bytes from the system interface side 45system.physmem.bytesWrittenSys 5372096 # Total written bytes from the system interface side 46system.physmem.servicedByWrQ 2 # Number of DRAM read bursts serviced by the write queue 47system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 48system.physmem.neitherReadNorWriteReqs 318 # Number of requests that are neither read nor write 49system.physmem.perBankRdBursts::0 8144 # Per bank write bursts 50system.physmem.perBankRdBursts::1 8386 # Per bank write bursts 51system.physmem.perBankRdBursts::2 8247 # Per bank write bursts 52system.physmem.perBankRdBursts::3 8164 # Per bank write bursts 53system.physmem.perBankRdBursts::4 8296 # Per bank write bursts 54system.physmem.perBankRdBursts::5 8451 # Per bank write bursts 55system.physmem.perBankRdBursts::6 8094 # Per bank write bursts 56system.physmem.perBankRdBursts::7 7961 # Per bank write bursts 57system.physmem.perBankRdBursts::8 8061 # Per bank write bursts 58system.physmem.perBankRdBursts::9 7610 # Per bank write bursts 59system.physmem.perBankRdBursts::10 7787 # Per bank write bursts 60system.physmem.perBankRdBursts::11 7813 # Per bank write bursts 61system.physmem.perBankRdBursts::12 7882 # Per bank write bursts 62system.physmem.perBankRdBursts::13 7886 # Per bank write bursts 63system.physmem.perBankRdBursts::14 7979 # Per bank write bursts 64system.physmem.perBankRdBursts::15 8007 # Per bank write bursts 65system.physmem.perBankWrBursts::0 5180 # Per bank write bursts 66system.physmem.perBankWrBursts::1 5376 # Per bank write bursts 67system.physmem.perBankWrBursts::2 5287 # Per bank write bursts 68system.physmem.perBankWrBursts::3 5157 # Per bank write bursts 69system.physmem.perBankWrBursts::4 5265 # Per bank write bursts 70system.physmem.perBankWrBursts::5 5517 # Per bank write bursts 71system.physmem.perBankWrBursts::6 5205 # Per bank write bursts 72system.physmem.perBankWrBursts::7 5049 # Per bank write bursts 73system.physmem.perBankWrBursts::8 5030 # Per bank write bursts 74system.physmem.perBankWrBursts::9 5090 # Per bank write bursts 75system.physmem.perBankWrBursts::10 5251 # Per bank write bursts 76system.physmem.perBankWrBursts::11 5144 # Per bank write bursts 77system.physmem.perBankWrBursts::12 5342 # Per bank write bursts 78system.physmem.perBankWrBursts::13 5363 # Per bank write bursts 79system.physmem.perBankWrBursts::14 5451 # Per bank write bursts 80system.physmem.perBankWrBursts::15 5223 # Per bank write bursts 81system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 82system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 83system.physmem.totGap 26816294000 # Total gap between requests 84system.physmem.readPktSize::0 0 # Read request sizes (log2) 85system.physmem.readPktSize::1 0 # Read request sizes (log2) 86system.physmem.readPktSize::2 0 # Read request sizes (log2) 87system.physmem.readPktSize::3 0 # Read request sizes (log2) 88system.physmem.readPktSize::4 0 # Read request sizes (log2) 89system.physmem.readPktSize::5 0 # Read request sizes (log2) 90system.physmem.readPktSize::6 128770 # Read request sizes (log2) 91system.physmem.writePktSize::0 0 # Write request sizes (log2) 92system.physmem.writePktSize::1 0 # Write request sizes (log2) 93system.physmem.writePktSize::2 0 # Write request sizes (log2) 94system.physmem.writePktSize::3 0 # Write request sizes (log2) 95system.physmem.writePktSize::4 0 # Write request sizes (log2) 96system.physmem.writePktSize::5 0 # Write request sizes (log2) 97system.physmem.writePktSize::6 83939 # Write request sizes (log2) 98system.physmem.rdQLenPdf::0 72833 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::1 54568 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::2 1301 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::3 59 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 130system.physmem.wrQLenPdf::0 3673 # What write queue length does an incoming req see 131system.physmem.wrQLenPdf::1 3683 # What write queue length does an incoming req see 132system.physmem.wrQLenPdf::2 3685 # What write queue length does an incoming req see 133system.physmem.wrQLenPdf::3 3690 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::4 3686 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::5 3682 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::6 3680 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::7 3694 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::8 3679 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::9 3683 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::10 3685 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::11 3678 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::12 3681 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::13 3689 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::14 3707 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::15 3772 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::16 3727 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::17 3952 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::18 3874 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::19 3939 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::20 4329 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::21 5011 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::22 51 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::23 8 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::24 1 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 162system.physmem.bytesPerActivate::samples 37861 # Bytes accessed per row activation 163system.physmem.bytesPerActivate::mean 359.431816 # Bytes accessed per row activation 164system.physmem.bytesPerActivate::gmean 174.292002 # Bytes accessed per row activation 165system.physmem.bytesPerActivate::stdev 695.442994 # Bytes accessed per row activation 166system.physmem.bytesPerActivate::64-65 15095 39.87% 39.87% # Bytes accessed per row activation 167system.physmem.bytesPerActivate::128-129 5646 14.91% 54.78% # Bytes accessed per row activation 168system.physmem.bytesPerActivate::192-193 3407 9.00% 63.78% # Bytes accessed per row activation 169system.physmem.bytesPerActivate::256-257 2352 6.21% 69.99% # Bytes accessed per row activation 170system.physmem.bytesPerActivate::320-321 1734 4.58% 74.57% # Bytes accessed per row activation 171system.physmem.bytesPerActivate::384-385 1565 4.13% 78.71% # Bytes accessed per row activation 172system.physmem.bytesPerActivate::448-449 1073 2.83% 81.54% # Bytes accessed per row activation 173system.physmem.bytesPerActivate::512-513 929 2.45% 83.99% # Bytes accessed per row activation 174system.physmem.bytesPerActivate::576-577 665 1.76% 85.75% # Bytes accessed per row activation 175system.physmem.bytesPerActivate::640-641 565 1.49% 87.24% # Bytes accessed per row activation 176system.physmem.bytesPerActivate::704-705 384 1.01% 88.26% # Bytes accessed per row activation 177system.physmem.bytesPerActivate::768-769 558 1.47% 89.73% # Bytes accessed per row activation 178system.physmem.bytesPerActivate::832-833 286 0.76% 90.49% # Bytes accessed per row activation 179system.physmem.bytesPerActivate::896-897 361 0.95% 91.44% # Bytes accessed per row activation 180system.physmem.bytesPerActivate::960-961 176 0.46% 91.90% # Bytes accessed per row activation 181system.physmem.bytesPerActivate::1024-1025 218 0.58% 92.48% # Bytes accessed per row activation 182system.physmem.bytesPerActivate::1088-1089 133 0.35% 92.83% # Bytes accessed per row activation 183system.physmem.bytesPerActivate::1152-1153 247 0.65% 93.48% # Bytes accessed per row activation 184system.physmem.bytesPerActivate::1216-1217 117 0.31% 93.79% # Bytes accessed per row activation 185system.physmem.bytesPerActivate::1280-1281 270 0.71% 94.51% # Bytes accessed per row activation 186system.physmem.bytesPerActivate::1344-1345 104 0.27% 94.78% # Bytes accessed per row activation 187system.physmem.bytesPerActivate::1408-1409 418 1.10% 95.88% # Bytes accessed per row activation 188system.physmem.bytesPerActivate::1472-1473 100 0.26% 96.15% # Bytes accessed per row activation 189system.physmem.bytesPerActivate::1536-1537 243 0.64% 96.79% # Bytes accessed per row activation 190system.physmem.bytesPerActivate::1600-1601 38 0.10% 96.89% # Bytes accessed per row activation 191system.physmem.bytesPerActivate::1664-1665 144 0.38% 97.27% # Bytes accessed per row activation 192system.physmem.bytesPerActivate::1728-1729 38 0.10% 97.37% # Bytes accessed per row activation 193system.physmem.bytesPerActivate::1792-1793 86 0.23% 97.60% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::1856-1857 29 0.08% 97.68% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::1920-1921 54 0.14% 97.82% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::1984-1985 16 0.04% 97.86% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::2048-2049 43 0.11% 97.97% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::2112-2113 22 0.06% 98.03% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::2176-2177 34 0.09% 98.12% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::2240-2241 17 0.04% 98.17% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::2304-2305 32 0.08% 98.25% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::2368-2369 11 0.03% 98.28% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::2432-2433 29 0.08% 98.36% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::2496-2497 17 0.04% 98.40% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::2560-2561 31 0.08% 98.48% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::2624-2625 15 0.04% 98.52% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::2688-2689 15 0.04% 98.56% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::2752-2753 11 0.03% 98.59% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::2816-2817 16 0.04% 98.63% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::2880-2881 11 0.03% 98.66% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::2944-2945 9 0.02% 98.69% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::3008-3009 8 0.02% 98.71% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::3072-3073 21 0.06% 98.76% # Bytes accessed per row activation 214system.physmem.bytesPerActivate::3136-3137 4 0.01% 98.77% # Bytes accessed per row activation 215system.physmem.bytesPerActivate::3200-3201 10 0.03% 98.80% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::3264-3265 11 0.03% 98.83% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::3328-3329 21 0.06% 98.89% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::3392-3393 8 0.02% 98.91% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::3456-3457 7 0.02% 98.93% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::3520-3521 6 0.02% 98.94% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::3584-3585 11 0.03% 98.97% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::3648-3649 10 0.03% 99.00% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::3712-3713 5 0.01% 99.01% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::3776-3777 7 0.02% 99.03% # Bytes accessed per row activation 225system.physmem.bytesPerActivate::3840-3841 17 0.04% 99.07% # Bytes accessed per row activation 226system.physmem.bytesPerActivate::3904-3905 5 0.01% 99.09% # Bytes accessed per row activation 227system.physmem.bytesPerActivate::3968-3969 10 0.03% 99.11% # Bytes accessed per row activation 228system.physmem.bytesPerActivate::4032-4033 7 0.02% 99.13% # Bytes accessed per row activation 229system.physmem.bytesPerActivate::4096-4097 7 0.02% 99.15% # Bytes accessed per row activation 230system.physmem.bytesPerActivate::4160-4161 3 0.01% 99.16% # Bytes accessed per row activation 231system.physmem.bytesPerActivate::4224-4225 6 0.02% 99.17% # Bytes accessed per row activation 232system.physmem.bytesPerActivate::4288-4289 8 0.02% 99.19% # Bytes accessed per row activation 233system.physmem.bytesPerActivate::4352-4353 11 0.03% 99.22% # Bytes accessed per row activation 234system.physmem.bytesPerActivate::4416-4417 4 0.01% 99.23% # Bytes accessed per row activation 235system.physmem.bytesPerActivate::4480-4481 10 0.03% 99.26% # Bytes accessed per row activation 236system.physmem.bytesPerActivate::4544-4545 6 0.02% 99.28% # Bytes accessed per row activation 237system.physmem.bytesPerActivate::4608-4609 7 0.02% 99.29% # Bytes accessed per row activation 238system.physmem.bytesPerActivate::4672-4673 2 0.01% 99.30% # Bytes accessed per row activation 239system.physmem.bytesPerActivate::4736-4737 9 0.02% 99.32% # Bytes accessed per row activation 240system.physmem.bytesPerActivate::4800-4801 4 0.01% 99.33% # Bytes accessed per row activation 241system.physmem.bytesPerActivate::4864-4865 12 0.03% 99.37% # Bytes accessed per row activation 242system.physmem.bytesPerActivate::4928-4929 6 0.02% 99.38% # Bytes accessed per row activation 243system.physmem.bytesPerActivate::4992-4993 8 0.02% 99.40% # Bytes accessed per row activation 244system.physmem.bytesPerActivate::5056-5057 2 0.01% 99.41% # Bytes accessed per row activation 245system.physmem.bytesPerActivate::5120-5121 13 0.03% 99.44% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::5184-5185 5 0.01% 99.46% # Bytes accessed per row activation 247system.physmem.bytesPerActivate::5248-5249 11 0.03% 99.48% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::5312-5313 6 0.02% 99.50% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::5376-5377 8 0.02% 99.52% # Bytes accessed per row activation 250system.physmem.bytesPerActivate::5440-5441 5 0.01% 99.54% # Bytes accessed per row activation 251system.physmem.bytesPerActivate::5504-5505 10 0.03% 99.56% # Bytes accessed per row activation 252system.physmem.bytesPerActivate::5568-5569 6 0.02% 99.58% # Bytes accessed per row activation 253system.physmem.bytesPerActivate::5632-5633 10 0.03% 99.60% # Bytes accessed per row activation 254system.physmem.bytesPerActivate::5696-5697 7 0.02% 99.62% # Bytes accessed per row activation 255system.physmem.bytesPerActivate::5760-5761 3 0.01% 99.63% # Bytes accessed per row activation 256system.physmem.bytesPerActivate::5824-5825 4 0.01% 99.64% # Bytes accessed per row activation 257system.physmem.bytesPerActivate::5888-5889 3 0.01% 99.65% # Bytes accessed per row activation 258system.physmem.bytesPerActivate::5952-5953 4 0.01% 99.66% # Bytes accessed per row activation 259system.physmem.bytesPerActivate::6016-6017 1 0.00% 99.66% # Bytes accessed per row activation 260system.physmem.bytesPerActivate::6080-6081 5 0.01% 99.68% # Bytes accessed per row activation 261system.physmem.bytesPerActivate::6144-6145 8 0.02% 99.70% # Bytes accessed per row activation 262system.physmem.bytesPerActivate::6208-6209 2 0.01% 99.70% # Bytes accessed per row activation 263system.physmem.bytesPerActivate::6272-6273 1 0.00% 99.70% # Bytes accessed per row activation 264system.physmem.bytesPerActivate::6336-6337 4 0.01% 99.71% # Bytes accessed per row activation 265system.physmem.bytesPerActivate::6400-6401 2 0.01% 99.72% # Bytes accessed per row activation 266system.physmem.bytesPerActivate::6464-6465 6 0.02% 99.74% # Bytes accessed per row activation 267system.physmem.bytesPerActivate::6528-6529 1 0.00% 99.74% # Bytes accessed per row activation 268system.physmem.bytesPerActivate::6592-6593 4 0.01% 99.75% # Bytes accessed per row activation 269system.physmem.bytesPerActivate::6656-6657 1 0.00% 99.75% # Bytes accessed per row activation 270system.physmem.bytesPerActivate::6720-6721 5 0.01% 99.76% # Bytes accessed per row activation 271system.physmem.bytesPerActivate::6784-6785 3 0.01% 99.77% # Bytes accessed per row activation 272system.physmem.bytesPerActivate::6848-6849 1 0.00% 99.78% # Bytes accessed per row activation 273system.physmem.bytesPerActivate::6912-6913 5 0.01% 99.79% # Bytes accessed per row activation 274system.physmem.bytesPerActivate::6976-6977 3 0.01% 99.80% # Bytes accessed per row activation 275system.physmem.bytesPerActivate::7040-7041 5 0.01% 99.81% # Bytes accessed per row activation 276system.physmem.bytesPerActivate::7104-7105 1 0.00% 99.81% # Bytes accessed per row activation 277system.physmem.bytesPerActivate::7168-7169 1 0.00% 99.82% # Bytes accessed per row activation 278system.physmem.bytesPerActivate::7232-7233 2 0.01% 99.82% # Bytes accessed per row activation 279system.physmem.bytesPerActivate::7296-7297 4 0.01% 99.83% # Bytes accessed per row activation 280system.physmem.bytesPerActivate::7360-7361 1 0.00% 99.83% # Bytes accessed per row activation 281system.physmem.bytesPerActivate::7424-7425 4 0.01% 99.84% # Bytes accessed per row activation 282system.physmem.bytesPerActivate::7552-7553 3 0.01% 99.85% # Bytes accessed per row activation 283system.physmem.bytesPerActivate::7616-7617 1 0.00% 99.85% # Bytes accessed per row activation 284system.physmem.bytesPerActivate::7680-7681 3 0.01% 99.86% # Bytes accessed per row activation 285system.physmem.bytesPerActivate::7744-7745 1 0.00% 99.87% # Bytes accessed per row activation 286system.physmem.bytesPerActivate::7808-7809 2 0.01% 99.87% # Bytes accessed per row activation 287system.physmem.bytesPerActivate::7872-7873 2 0.01% 99.88% # Bytes accessed per row activation 288system.physmem.bytesPerActivate::7936-7937 3 0.01% 99.88% # Bytes accessed per row activation 289system.physmem.bytesPerActivate::8064-8065 3 0.01% 99.89% # Bytes accessed per row activation 290system.physmem.bytesPerActivate::8128-8129 5 0.01% 99.90% # Bytes accessed per row activation 291system.physmem.bytesPerActivate::8192-8193 36 0.10% 100.00% # Bytes accessed per row activation 292system.physmem.bytesPerActivate::total 37861 # Bytes accessed per row activation 293system.physmem.totQLat 3024623000 # Total ticks spent queuing 294system.physmem.totMemAccLat 4968016750 # Total ticks spent from burst creation until serviced by the DRAM 295system.physmem.totBusLat 643840000 # Total ticks spent in databus transfers 296system.physmem.totBankLat 1299553750 # Total ticks spent accessing banks 297system.physmem.avgQLat 23488.93 # Average queueing delay per DRAM burst 298system.physmem.avgBankLat 10092.21 # Average bank access latency per DRAM burst 299system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 300system.physmem.avgMemAccLat 38581.14 # Average memory access latency per DRAM burst 301system.physmem.avgRdBW 307.32 # Average DRAM read bandwidth in MiByte/s 302system.physmem.avgWrBW 200.31 # Average achieved write bandwidth in MiByte/s 303system.physmem.avgRdBWSys 307.32 # Average system read bandwidth in MiByte/s 304system.physmem.avgWrBWSys 200.33 # Average system write bandwidth in MiByte/s 305system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 306system.physmem.busUtil 3.97 # Data bus utilization in percentage 307system.physmem.busUtilRead 2.40 # Data bus utilization in percentage for reads 308system.physmem.busUtilWrite 1.56 # Data bus utilization in percentage for writes 309system.physmem.avgRdQLen 0.19 # Average read queue length when enqueuing 310system.physmem.avgWrQLen 9.76 # Average write queue length when enqueuing 311system.physmem.readRowHits 117866 # Number of row buffer hits during reads 312system.physmem.writeRowHits 56971 # Number of row buffer hits during writes 313system.physmem.readRowHitRate 91.53 # Row buffer hit rate for reads 314system.physmem.writeRowHitRate 67.87 # Row buffer hit rate for writes 315system.physmem.avgGap 126070.33 # Average gap between requests 316system.physmem.pageHitRate 82.20 # Row buffer hit rate, read and write combined 317system.physmem.prechargeAllPercent 11.88 # Percentage of time for which DRAM has all the banks in precharge state 318system.membus.throughput 507651035 # Throughput (bytes/s) 319system.membus.trans_dist::ReadReq 26514 # Transaction distribution 320system.membus.trans_dist::ReadResp 26514 # Transaction distribution 321system.membus.trans_dist::Writeback 83939 # Transaction distribution 322system.membus.trans_dist::UpgradeReq 318 # Transaction distribution 323system.membus.trans_dist::UpgradeResp 318 # Transaction distribution 324system.membus.trans_dist::ReadExReq 102256 # Transaction distribution 325system.membus.trans_dist::ReadExResp 102256 # Transaction distribution 326system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 342115 # Packet count per connected master and slave (bytes) 327system.membus.pkt_count::total 342115 # Packet count per connected master and slave (bytes) 328system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13613376 # Cumulative packet size per connected master and slave (bytes) 329system.membus.tot_pkt_size::total 13613376 # Cumulative packet size per connected master and slave (bytes) 330system.membus.data_through_bus 13613376 # Total data (bytes) 331system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 332system.membus.reqLayer0.occupancy 934803500 # Layer occupancy (ticks) 333system.membus.reqLayer0.utilization 3.5 # Layer utilization (%) 334system.membus.respLayer1.occupancy 1203423433 # Layer occupancy (ticks) 335system.membus.respLayer1.utilization 4.5 # Layer utilization (%) 336system.cpu.branchPred.lookups 16622919 # Number of BP lookups 337system.cpu.branchPred.condPredicted 12749857 # Number of conditional branches predicted 338system.cpu.branchPred.condIncorrect 605504 # Number of conditional branches incorrect 339system.cpu.branchPred.BTBLookups 10570940 # Number of BTB lookups 340system.cpu.branchPred.BTBHits 7775711 # Number of BTB hits 341system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 342system.cpu.branchPred.BTBHitPct 73.557423 # BTB Hit Percentage 343system.cpu.branchPred.usedRAS 1829148 # Number of times the RAS was used to get a target. 344system.cpu.branchPred.RASInCorrect 113993 # Number of incorrect RAS predictions. 345system.cpu.dtb.inst_hits 0 # ITB inst hits 346system.cpu.dtb.inst_misses 0 # ITB inst misses 347system.cpu.dtb.read_hits 0 # DTB read hits 348system.cpu.dtb.read_misses 0 # DTB read misses 349system.cpu.dtb.write_hits 0 # DTB write hits 350system.cpu.dtb.write_misses 0 # DTB write misses 351system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 352system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 353system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 354system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 355system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 356system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 357system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 358system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 359system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 360system.cpu.dtb.read_accesses 0 # DTB read accesses 361system.cpu.dtb.write_accesses 0 # DTB write accesses 362system.cpu.dtb.inst_accesses 0 # ITB inst accesses 363system.cpu.dtb.hits 0 # DTB hits 364system.cpu.dtb.misses 0 # DTB misses 365system.cpu.dtb.accesses 0 # DTB accesses 366system.cpu.itb.inst_hits 0 # ITB inst hits 367system.cpu.itb.inst_misses 0 # ITB inst misses 368system.cpu.itb.read_hits 0 # DTB read hits 369system.cpu.itb.read_misses 0 # DTB read misses 370system.cpu.itb.write_hits 0 # DTB write hits 371system.cpu.itb.write_misses 0 # DTB write misses 372system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 373system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 374system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 375system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 376system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 377system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 378system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 379system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 380system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 381system.cpu.itb.read_accesses 0 # DTB read accesses 382system.cpu.itb.write_accesses 0 # DTB write accesses 383system.cpu.itb.inst_accesses 0 # ITB inst accesses 384system.cpu.itb.hits 0 # DTB hits 385system.cpu.itb.misses 0 # DTB misses 386system.cpu.itb.accesses 0 # DTB accesses 387system.cpu.workload.num_syscalls 1946 # Number of system calls 388system.cpu.numCycles 53632812 # number of cpu cycles simulated 389system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 390system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 391system.cpu.fetch.icacheStallCycles 12575227 # Number of cycles fetch is stalled on an Icache miss 392system.cpu.fetch.Insts 85200235 # Number of instructions fetch has processed 393system.cpu.fetch.Branches 16622919 # Number of branches that fetch encountered 394system.cpu.fetch.predictedBranches 9604859 # Number of branches that fetch has predicted taken 395system.cpu.fetch.Cycles 21200799 # Number of cycles fetch has run and was not squashing or blocked 396system.cpu.fetch.SquashCycles 2368859 # Number of cycles fetch has spent squashing 397system.cpu.fetch.BlockedCycles 10684050 # Number of cycles fetch has spent blocked 398system.cpu.fetch.MiscStallCycles 61 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 399system.cpu.fetch.PendingTrapStallCycles 493 # Number of stall cycles due to pending traps 400system.cpu.fetch.IcacheWaitRetryStallCycles 31 # Number of stall cycles due to full MSHR 401system.cpu.fetch.CacheLines 11692200 # Number of cache lines fetched 402system.cpu.fetch.IcacheSquashes 184239 # Number of outstanding Icache misses that were squashed 403system.cpu.fetch.rateDist::samples 46197272 # Number of instructions fetched each cycle (Total) 404system.cpu.fetch.rateDist::mean 2.582993 # Number of instructions fetched each cycle (Total) 405system.cpu.fetch.rateDist::stdev 3.332808 # Number of instructions fetched each cycle (Total) 406system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 407system.cpu.fetch.rateDist::0 25016575 54.15% 54.15% # Number of instructions fetched each cycle (Total) 408system.cpu.fetch.rateDist::1 2138831 4.63% 58.78% # Number of instructions fetched each cycle (Total) 409system.cpu.fetch.rateDist::2 1968354 4.26% 63.04% # Number of instructions fetched each cycle (Total) 410system.cpu.fetch.rateDist::3 2045405 4.43% 67.47% # Number of instructions fetched each cycle (Total) 411system.cpu.fetch.rateDist::4 1466932 3.18% 70.65% # Number of instructions fetched each cycle (Total) 412system.cpu.fetch.rateDist::5 1376276 2.98% 73.62% # Number of instructions fetched each cycle (Total) 413system.cpu.fetch.rateDist::6 961294 2.08% 75.71% # Number of instructions fetched each cycle (Total) 414system.cpu.fetch.rateDist::7 1190217 2.58% 78.28% # Number of instructions fetched each cycle (Total) 415system.cpu.fetch.rateDist::8 10033388 21.72% 100.00% # Number of instructions fetched each cycle (Total) 416system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 417system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 418system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 419system.cpu.fetch.rateDist::total 46197272 # Number of instructions fetched each cycle (Total) 420system.cpu.fetch.branchRate 0.309939 # Number of branch fetches per cycle 421system.cpu.fetch.rate 1.588584 # Number of inst fetches per cycle 422system.cpu.decode.IdleCycles 14661485 # Number of cycles decode is idle 423system.cpu.decode.BlockedCycles 9032065 # Number of cycles decode is blocked 424system.cpu.decode.RunCycles 19500717 # Number of cycles decode is running 425system.cpu.decode.UnblockCycles 1369785 # Number of cycles decode is unblocking 426system.cpu.decode.SquashCycles 1633220 # Number of cycles decode is squashing 427system.cpu.decode.BranchResolved 3334387 # Number of times decode resolved a branch 428system.cpu.decode.BranchMispred 105402 # Number of times decode detected a branch misprediction 429system.cpu.decode.DecodedInsts 116870755 # Number of instructions handled by decode 430system.cpu.decode.SquashedInsts 365005 # Number of squashed instructions handled by decode 431system.cpu.rename.SquashCycles 1633220 # Number of cycles rename is squashing 432system.cpu.rename.IdleCycles 16370455 # Number of cycles rename is idle 433system.cpu.rename.BlockCycles 2587455 # Number of cycles rename is blocking 434system.cpu.rename.serializeStallCycles 1031873 # count of cycles rename stalled for serializing inst 435system.cpu.rename.RunCycles 19111398 # Number of cycles rename is running 436system.cpu.rename.UnblockCycles 5462871 # Number of cycles rename is unblocking 437system.cpu.rename.RenamedInsts 114984523 # Number of instructions processed by rename 438system.cpu.rename.ROBFullEvents 171 # Number of times rename has blocked due to ROB full 439system.cpu.rename.IQFullEvents 15960 # Number of times rename has blocked due to IQ full 440system.cpu.rename.LSQFullEvents 4602334 # Number of times rename has blocked due to LSQ full 441system.cpu.rename.FullRegisterEvents 241 # Number of times there has been no free registers 442system.cpu.rename.RenamedOperands 115277175 # Number of destination operands rename has renamed 443system.cpu.rename.RenameLookups 529754178 # Number of register rename lookups that rename has made 444system.cpu.rename.int_rename_lookups 476504412 # Number of integer rename lookups 445system.cpu.rename.fp_rename_lookups 2548 # Number of floating rename lookups 446system.cpu.rename.CommittedMaps 99132672 # Number of HB maps that are committed 447system.cpu.rename.UndoneMaps 16144503 # Number of HB maps that are undone due to squashing 448system.cpu.rename.serializingInsts 20627 # count of serializing insts renamed 449system.cpu.rename.tempSerializingInsts 20613 # count of temporary serializing insts renamed 450system.cpu.rename.skidInsts 12986013 # count of insts added to the skid buffer 451system.cpu.memDep0.insertedLoads 29603679 # Number of loads inserted to the mem dependence unit. 452system.cpu.memDep0.insertedStores 22442541 # Number of stores inserted to the mem dependence unit. 453system.cpu.memDep0.conflictingLoads 3905979 # Number of conflicting loads. 454system.cpu.memDep0.conflictingStores 4383979 # Number of conflicting stores. 455system.cpu.iq.iqInstsAdded 111534291 # Number of instructions added to the IQ (excludes non-spec) 456system.cpu.iq.iqNonSpecInstsAdded 36144 # Number of non-speculative instructions added to the IQ 457system.cpu.iq.iqInstsIssued 107247539 # Number of instructions issued 458system.cpu.iq.iqSquashedInstsIssued 279427 # Number of squashed instructions issued 459system.cpu.iq.iqSquashedInstsExamined 10792871 # Number of squashed instructions iterated over during squash; mainly for profiling 460system.cpu.iq.iqSquashedOperandsExamined 25872402 # Number of squashed operands that are examined and possibly removed from graph 461system.cpu.iq.iqSquashedNonSpecRemoved 2358 # Number of squashed non-spec instructions that were removed 462system.cpu.iq.issued_per_cycle::samples 46197272 # Number of insts issued each cycle 463system.cpu.iq.issued_per_cycle::mean 2.321512 # Number of insts issued each cycle 464system.cpu.iq.issued_per_cycle::stdev 1.989577 # Number of insts issued each cycle 465system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 466system.cpu.iq.issued_per_cycle::0 10946962 23.70% 23.70% # Number of insts issued each cycle 467system.cpu.iq.issued_per_cycle::1 8090791 17.51% 41.21% # Number of insts issued each cycle 468system.cpu.iq.issued_per_cycle::2 7422192 16.07% 57.28% # Number of insts issued each cycle 469system.cpu.iq.issued_per_cycle::3 7125519 15.42% 72.70% # Number of insts issued each cycle 470system.cpu.iq.issued_per_cycle::4 5414632 11.72% 84.42% # Number of insts issued each cycle 471system.cpu.iq.issued_per_cycle::5 3916527 8.48% 92.90% # Number of insts issued each cycle 472system.cpu.iq.issued_per_cycle::6 1842332 3.99% 96.89% # Number of insts issued each cycle 473system.cpu.iq.issued_per_cycle::7 865884 1.87% 98.76% # Number of insts issued each cycle 474system.cpu.iq.issued_per_cycle::8 572433 1.24% 100.00% # Number of insts issued each cycle 475system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 476system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 477system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 478system.cpu.iq.issued_per_cycle::total 46197272 # Number of insts issued each cycle 479system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 480system.cpu.iq.fu_full::IntAlu 111334 4.52% 4.52% # attempts to use FU when none available 481system.cpu.iq.fu_full::IntMult 0 0.00% 4.52% # attempts to use FU when none available 482system.cpu.iq.fu_full::IntDiv 0 0.00% 4.52% # attempts to use FU when none available 483system.cpu.iq.fu_full::FloatAdd 1 0.00% 4.52% # attempts to use FU when none available 484system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.52% # attempts to use FU when none available 485system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.52% # attempts to use FU when none available 486system.cpu.iq.fu_full::FloatMult 0 0.00% 4.52% # attempts to use FU when none available 487system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.52% # attempts to use FU when none available 488system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.52% # attempts to use FU when none available 489system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.52% # attempts to use FU when none available 490system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.52% # attempts to use FU when none available 491system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.52% # attempts to use FU when none available 492system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.52% # attempts to use FU when none available 493system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.52% # attempts to use FU when none available 494system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.52% # attempts to use FU when none available 495system.cpu.iq.fu_full::SimdMult 0 0.00% 4.52% # attempts to use FU when none available 496system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.52% # attempts to use FU when none available 497system.cpu.iq.fu_full::SimdShift 0 0.00% 4.52% # attempts to use FU when none available 498system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.52% # attempts to use FU when none available 499system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.52% # attempts to use FU when none available 500system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.52% # attempts to use FU when none available 501system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.52% # attempts to use FU when none available 502system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.52% # attempts to use FU when none available 503system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.52% # attempts to use FU when none available 504system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.52% # attempts to use FU when none available 505system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.52% # attempts to use FU when none available 506system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.52% # attempts to use FU when none available 507system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.52% # attempts to use FU when none available 508system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.52% # attempts to use FU when none available 509system.cpu.iq.fu_full::MemRead 1349070 54.73% 59.25% # attempts to use FU when none available 510system.cpu.iq.fu_full::MemWrite 1004381 40.75% 100.00% # attempts to use FU when none available 511system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 512system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 513system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 514system.cpu.iq.FU_type_0::IntAlu 56643981 52.82% 52.82% # Type of FU issued 515system.cpu.iq.FU_type_0::IntMult 91446 0.09% 52.90% # Type of FU issued 516system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.90% # Type of FU issued 517system.cpu.iq.FU_type_0::FloatAdd 176 0.00% 52.90% # Type of FU issued 518system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.90% # Type of FU issued 519system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.90% # Type of FU issued 520system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.90% # Type of FU issued 521system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 52.90% # Type of FU issued 522system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 52.90% # Type of FU issued 523system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 52.90% # Type of FU issued 524system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 52.90% # Type of FU issued 525system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 52.90% # Type of FU issued 526system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 52.90% # Type of FU issued 527system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 52.90% # Type of FU issued 528system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 52.90% # Type of FU issued 529system.cpu.iq.FU_type_0::SimdMult 0 0.00% 52.90% # Type of FU issued 530system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 52.90% # Type of FU issued 531system.cpu.iq.FU_type_0::SimdShift 0 0.00% 52.90% # Type of FU issued 532system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.90% # Type of FU issued 533system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 52.90% # Type of FU issued 534system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.90% # Type of FU issued 535system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.90% # Type of FU issued 536system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 52.90% # Type of FU issued 537system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.90% # Type of FU issued 538system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.90% # Type of FU issued 539system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 52.90% # Type of FU issued 540system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.90% # Type of FU issued 541system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.90% # Type of FU issued 542system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.90% # Type of FU issued 543system.cpu.iq.FU_type_0::MemRead 28888115 26.94% 79.84% # Type of FU issued 544system.cpu.iq.FU_type_0::MemWrite 21623814 20.16% 100.00% # Type of FU issued 545system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 546system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 547system.cpu.iq.FU_type_0::total 107247539 # Type of FU issued 548system.cpu.iq.rate 1.999663 # Inst issue rate 549system.cpu.iq.fu_busy_cnt 2464786 # FU busy when requested 550system.cpu.iq.fu_busy_rate 0.022982 # FU busy rate (busy events/executed inst) 551system.cpu.iq.int_inst_queue_reads 263436010 # Number of integer instruction queue reads 552system.cpu.iq.int_inst_queue_writes 122391385 # Number of integer instruction queue writes 553system.cpu.iq.int_inst_queue_wakeup_accesses 105557389 # Number of integer instruction queue wakeup accesses 554system.cpu.iq.fp_inst_queue_reads 553 # Number of floating instruction queue reads 555system.cpu.iq.fp_inst_queue_writes 926 # Number of floating instruction queue writes 556system.cpu.iq.fp_inst_queue_wakeup_accesses 158 # Number of floating instruction queue wakeup accesses 557system.cpu.iq.int_alu_accesses 109712054 # Number of integer alu accesses 558system.cpu.iq.fp_alu_accesses 271 # Number of floating point alu accesses 559system.cpu.iew.lsq.thread0.forwLoads 2181647 # Number of loads that had data forwarded from stores 560system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 561system.cpu.iew.lsq.thread0.squashedLoads 2296571 # Number of loads squashed 562system.cpu.iew.lsq.thread0.ignoredResponses 6409 # Number of memory responses ignored because the instruction is squashed 563system.cpu.iew.lsq.thread0.memOrderViolation 29938 # Number of memory ordering violations 564system.cpu.iew.lsq.thread0.squashedStores 1886803 # Number of stores squashed 565system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 566system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 567system.cpu.iew.lsq.thread0.rescheduledLoads 32 # Number of loads that were rescheduled 568system.cpu.iew.lsq.thread0.cacheBlocked 637 # Number of times an access to memory failed due to the cache being blocked 569system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 570system.cpu.iew.iewSquashCycles 1633220 # Number of cycles IEW is squashing 571system.cpu.iew.iewBlockCycles 1092915 # Number of cycles IEW is blocking 572system.cpu.iew.iewUnblockCycles 45139 # Number of cycles IEW is unblocking 573system.cpu.iew.iewDispatchedInsts 111580294 # Number of instructions dispatched to IQ 574system.cpu.iew.iewDispSquashedInsts 294739 # Number of squashed instructions skipped by dispatch 575system.cpu.iew.iewDispLoadInsts 29603679 # Number of dispatched load instructions 576system.cpu.iew.iewDispStoreInsts 22442541 # Number of dispatched store instructions 577system.cpu.iew.iewDispNonSpecInsts 20224 # Number of dispatched non-speculative instructions 578system.cpu.iew.iewIQFullEvents 6335 # Number of times the IQ has become full, causing a stall 579system.cpu.iew.iewLSQFullEvents 5295 # Number of times the LSQ has become full, causing a stall 580system.cpu.iew.memOrderViolationEvents 29938 # Number of memory order violations 581system.cpu.iew.predictedTakenIncorrect 394730 # Number of branches that were predicted taken incorrectly 582system.cpu.iew.predictedNotTakenIncorrect 181332 # Number of branches that were predicted not taken incorrectly 583system.cpu.iew.branchMispredicts 576062 # Number of branch mispredicts detected at execute 584system.cpu.iew.iewExecutedInsts 106214921 # Number of executed instructions 585system.cpu.iew.iewExecLoadInsts 28587238 # Number of load instructions executed 586system.cpu.iew.iewExecSquashedInsts 1032618 # Number of squashed instructions skipped in execute 587system.cpu.iew.exec_swp 0 # number of swp insts executed 588system.cpu.iew.exec_nop 9859 # number of nop insts executed 589system.cpu.iew.exec_refs 49925863 # number of memory reference insts executed 590system.cpu.iew.exec_branches 14600722 # Number of branches executed 591system.cpu.iew.exec_stores 21338625 # Number of stores executed 592system.cpu.iew.exec_rate 1.980409 # Inst execution rate 593system.cpu.iew.wb_sent 105779922 # cumulative count of insts sent to commit 594system.cpu.iew.wb_count 105557547 # cumulative count of insts written-back 595system.cpu.iew.wb_producers 53302648 # num instructions producing a value 596system.cpu.iew.wb_consumers 103946447 # num instructions consuming a value 597system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 598system.cpu.iew.wb_rate 1.968152 # insts written-back per cycle 599system.cpu.iew.wb_fanout 0.512790 # average fanout of values written-back 600system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 601system.cpu.commit.commitSquashedInsts 10948789 # The number of squashed insts skipped by commit 602system.cpu.commit.commitNonSpecStalls 33786 # The number of times commit has been forced to stall to communicate backwards 603system.cpu.commit.branchMispredicts 502113 # The number of times a branch was mispredicted 604system.cpu.commit.committed_per_cycle::samples 44564052 # Number of insts commited each cycle 605system.cpu.commit.committed_per_cycle::mean 2.258153 # Number of insts commited each cycle 606system.cpu.commit.committed_per_cycle::stdev 2.763889 # Number of insts commited each cycle 607system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 608system.cpu.commit.committed_per_cycle::0 15506218 34.80% 34.80% # Number of insts commited each cycle 609system.cpu.commit.committed_per_cycle::1 11644493 26.13% 60.93% # Number of insts commited each cycle 610system.cpu.commit.committed_per_cycle::2 3446423 7.73% 68.66% # Number of insts commited each cycle 611system.cpu.commit.committed_per_cycle::3 2869378 6.44% 75.10% # Number of insts commited each cycle 612system.cpu.commit.committed_per_cycle::4 1870309 4.20% 79.29% # Number of insts commited each cycle 613system.cpu.commit.committed_per_cycle::5 1959985 4.40% 83.69% # Number of insts commited each cycle 614system.cpu.commit.committed_per_cycle::6 685768 1.54% 85.23% # Number of insts commited each cycle 615system.cpu.commit.committed_per_cycle::7 560638 1.26% 86.49% # Number of insts commited each cycle 616system.cpu.commit.committed_per_cycle::8 6020840 13.51% 100.00% # Number of insts commited each cycle 617system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 618system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 619system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 620system.cpu.commit.committed_per_cycle::total 44564052 # Number of insts commited each cycle 621system.cpu.commit.committedInsts 70913181 # Number of instructions committed 622system.cpu.commit.committedOps 100632428 # Number of ops (including micro ops) committed 623system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 624system.cpu.commit.refs 47862846 # Number of memory references committed 625system.cpu.commit.loads 27307108 # Number of loads committed 626system.cpu.commit.membars 15920 # Number of memory barriers committed 627system.cpu.commit.branches 13741485 # Number of branches committed 628system.cpu.commit.fp_insts 56 # Number of committed floating point instructions. 629system.cpu.commit.int_insts 91472779 # Number of committed integer instructions. 630system.cpu.commit.function_calls 1679850 # Number of function calls committed. 631system.cpu.commit.bw_lim_events 6020840 # number cycles where commit BW limit reached 632system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 633system.cpu.rob.rob_reads 150099130 # The number of ROB reads 634system.cpu.rob.rob_writes 224804524 # The number of ROB writes 635system.cpu.timesIdled 76985 # Number of times that the entire CPU went into an idle state and unscheduled itself 636system.cpu.idleCycles 7435540 # Total number of cycles that the CPU has spent unscheduled due to idling 637system.cpu.committedInsts 70907629 # Number of Instructions Simulated 638system.cpu.committedOps 100626876 # Number of Ops (including micro ops) Simulated 639system.cpu.committedInsts_total 70907629 # Number of Instructions Simulated 640system.cpu.cpi 0.756376 # CPI: Cycles Per Instruction 641system.cpu.cpi_total 0.756376 # CPI: Total CPI of All Threads 642system.cpu.ipc 1.322094 # IPC: Instructions Per Cycle 643system.cpu.ipc_total 1.322094 # IPC: Total IPC of All Threads 644system.cpu.int_regfile_reads 511539854 # number of integer regfile reads 645system.cpu.int_regfile_writes 103334614 # number of integer regfile writes 646system.cpu.fp_regfile_reads 734 # number of floating regfile reads 647system.cpu.fp_regfile_writes 630 # number of floating regfile writes 648system.cpu.misc_regfile_reads 49164319 # number of misc regfile reads 649system.cpu.misc_regfile_writes 31840 # number of misc regfile writes 650system.cpu.toL2Bus.throughput 775188755 # Throughput (bytes/s) 651system.cpu.toL2Bus.trans_dist::ReadReq 88572 # Transaction distribution 652system.cpu.toL2Bus.trans_dist::ReadResp 88572 # Transaction distribution 653system.cpu.toL2Bus.trans_dist::Writeback 129187 # Transaction distribution 654system.cpu.toL2Bus.trans_dist::UpgradeReq 336 # Transaction distribution 655system.cpu.toL2Bus.trans_dist::UpgradeResp 336 # Transaction distribution 656system.cpu.toL2Bus.trans_dist::ReadExReq 107050 # Transaction distribution 657system.cpu.toL2Bus.trans_dist::ReadExResp 107050 # Transaction distribution 658system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 65806 # Packet count per connected master and slave (bytes) 659system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 454775 # Packet count per connected master and slave (bytes) 660system.cpu.toL2Bus.pkt_count::total 520581 # Packet count per connected master and slave (bytes) 661system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2089088 # Cumulative packet size per connected master and slave (bytes) 662system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18665280 # Cumulative packet size per connected master and slave (bytes) 663system.cpu.toL2Bus.tot_pkt_size::total 20754368 # Cumulative packet size per connected master and slave (bytes) 664system.cpu.toL2Bus.data_through_bus 20754368 # Total data (bytes) 665system.cpu.toL2Bus.snoop_data_through_bus 33408 # Total snoop data (bytes) 666system.cpu.toL2Bus.reqLayer0.occupancy 291762996 # Layer occupancy (ticks) 667system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) 668system.cpu.toL2Bus.respLayer0.occupancy 50495227 # Layer occupancy (ticks) 669system.cpu.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) 670system.cpu.toL2Bus.respLayer1.occupancy 260303004 # Layer occupancy (ticks) 671system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) 672system.cpu.icache.tags.replacements 30799 # number of replacements 673system.cpu.icache.tags.tagsinuse 1804.677341 # Cycle average of tags in use 674system.cpu.icache.tags.total_refs 11655246 # Total number of references to valid blocks. 675system.cpu.icache.tags.sampled_refs 32836 # Sample count of references to valid blocks. 676system.cpu.icache.tags.avg_refs 354.953283 # Average number of references to valid blocks. 677system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 678system.cpu.icache.tags.occ_blocks::cpu.inst 1804.677341 # Average occupied blocks per requestor 679system.cpu.icache.tags.occ_percent::cpu.inst 0.881190 # Average percentage of cache occupancy 680system.cpu.icache.tags.occ_percent::total 0.881190 # Average percentage of cache occupancy 681system.cpu.icache.ReadReq_hits::cpu.inst 11655255 # number of ReadReq hits 682system.cpu.icache.ReadReq_hits::total 11655255 # number of ReadReq hits 683system.cpu.icache.demand_hits::cpu.inst 11655255 # number of demand (read+write) hits 684system.cpu.icache.demand_hits::total 11655255 # number of demand (read+write) hits 685system.cpu.icache.overall_hits::cpu.inst 11655255 # number of overall hits 686system.cpu.icache.overall_hits::total 11655255 # number of overall hits 687system.cpu.icache.ReadReq_misses::cpu.inst 36945 # number of ReadReq misses 688system.cpu.icache.ReadReq_misses::total 36945 # number of ReadReq misses 689system.cpu.icache.demand_misses::cpu.inst 36945 # number of demand (read+write) misses 690system.cpu.icache.demand_misses::total 36945 # number of demand (read+write) misses 691system.cpu.icache.overall_misses::cpu.inst 36945 # number of overall misses 692system.cpu.icache.overall_misses::total 36945 # number of overall misses 693system.cpu.icache.ReadReq_miss_latency::cpu.inst 836533724 # number of ReadReq miss cycles 694system.cpu.icache.ReadReq_miss_latency::total 836533724 # number of ReadReq miss cycles 695system.cpu.icache.demand_miss_latency::cpu.inst 836533724 # number of demand (read+write) miss cycles 696system.cpu.icache.demand_miss_latency::total 836533724 # number of demand (read+write) miss cycles 697system.cpu.icache.overall_miss_latency::cpu.inst 836533724 # number of overall miss cycles 698system.cpu.icache.overall_miss_latency::total 836533724 # number of overall miss cycles 699system.cpu.icache.ReadReq_accesses::cpu.inst 11692200 # number of ReadReq accesses(hits+misses) 700system.cpu.icache.ReadReq_accesses::total 11692200 # number of ReadReq accesses(hits+misses) 701system.cpu.icache.demand_accesses::cpu.inst 11692200 # number of demand (read+write) accesses 702system.cpu.icache.demand_accesses::total 11692200 # number of demand (read+write) accesses 703system.cpu.icache.overall_accesses::cpu.inst 11692200 # number of overall (read+write) accesses 704system.cpu.icache.overall_accesses::total 11692200 # number of overall (read+write) accesses 705system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003160 # miss rate for ReadReq accesses 706system.cpu.icache.ReadReq_miss_rate::total 0.003160 # miss rate for ReadReq accesses 707system.cpu.icache.demand_miss_rate::cpu.inst 0.003160 # miss rate for demand accesses 708system.cpu.icache.demand_miss_rate::total 0.003160 # miss rate for demand accesses 709system.cpu.icache.overall_miss_rate::cpu.inst 0.003160 # miss rate for overall accesses 710system.cpu.icache.overall_miss_rate::total 0.003160 # miss rate for overall accesses 711system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22642.677602 # average ReadReq miss latency 712system.cpu.icache.ReadReq_avg_miss_latency::total 22642.677602 # average ReadReq miss latency 713system.cpu.icache.demand_avg_miss_latency::cpu.inst 22642.677602 # average overall miss latency 714system.cpu.icache.demand_avg_miss_latency::total 22642.677602 # average overall miss latency 715system.cpu.icache.overall_avg_miss_latency::cpu.inst 22642.677602 # average overall miss latency 716system.cpu.icache.overall_avg_miss_latency::total 22642.677602 # average overall miss latency 717system.cpu.icache.blocked_cycles::no_mshrs 965 # number of cycles access was blocked 718system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 719system.cpu.icache.blocked::no_mshrs 20 # number of cycles access was blocked 720system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 721system.cpu.icache.avg_blocked_cycles::no_mshrs 48.250000 # average number of cycles each access was blocked 722system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 723system.cpu.icache.fast_writes 0 # number of fast writes performed 724system.cpu.icache.cache_copies 0 # number of cache copies performed 725system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3781 # number of ReadReq MSHR hits 726system.cpu.icache.ReadReq_mshr_hits::total 3781 # number of ReadReq MSHR hits 727system.cpu.icache.demand_mshr_hits::cpu.inst 3781 # number of demand (read+write) MSHR hits 728system.cpu.icache.demand_mshr_hits::total 3781 # number of demand (read+write) MSHR hits 729system.cpu.icache.overall_mshr_hits::cpu.inst 3781 # number of overall MSHR hits 730system.cpu.icache.overall_mshr_hits::total 3781 # number of overall MSHR hits 731system.cpu.icache.ReadReq_mshr_misses::cpu.inst 33164 # number of ReadReq MSHR misses 732system.cpu.icache.ReadReq_mshr_misses::total 33164 # number of ReadReq MSHR misses 733system.cpu.icache.demand_mshr_misses::cpu.inst 33164 # number of demand (read+write) MSHR misses 734system.cpu.icache.demand_mshr_misses::total 33164 # number of demand (read+write) MSHR misses 735system.cpu.icache.overall_mshr_misses::cpu.inst 33164 # number of overall MSHR misses 736system.cpu.icache.overall_mshr_misses::total 33164 # number of overall MSHR misses 737system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 680570772 # number of ReadReq MSHR miss cycles 738system.cpu.icache.ReadReq_mshr_miss_latency::total 680570772 # number of ReadReq MSHR miss cycles 739system.cpu.icache.demand_mshr_miss_latency::cpu.inst 680570772 # number of demand (read+write) MSHR miss cycles 740system.cpu.icache.demand_mshr_miss_latency::total 680570772 # number of demand (read+write) MSHR miss cycles 741system.cpu.icache.overall_mshr_miss_latency::cpu.inst 680570772 # number of overall MSHR miss cycles 742system.cpu.icache.overall_mshr_miss_latency::total 680570772 # number of overall MSHR miss cycles 743system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.002836 # mshr miss rate for ReadReq accesses 744system.cpu.icache.ReadReq_mshr_miss_rate::total 0.002836 # mshr miss rate for ReadReq accesses 745system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.002836 # mshr miss rate for demand accesses 746system.cpu.icache.demand_mshr_miss_rate::total 0.002836 # mshr miss rate for demand accesses 747system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.002836 # mshr miss rate for overall accesses 748system.cpu.icache.overall_mshr_miss_rate::total 0.002836 # mshr miss rate for overall accesses 749system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20521.371728 # average ReadReq mshr miss latency 750system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20521.371728 # average ReadReq mshr miss latency 751system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20521.371728 # average overall mshr miss latency 752system.cpu.icache.demand_avg_mshr_miss_latency::total 20521.371728 # average overall mshr miss latency 753system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20521.371728 # average overall mshr miss latency 754system.cpu.icache.overall_avg_mshr_miss_latency::total 20521.371728 # average overall mshr miss latency 755system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 756system.cpu.l2cache.tags.replacements 95639 # number of replacements 757system.cpu.l2cache.tags.tagsinuse 29886.699201 # Cycle average of tags in use 758system.cpu.l2cache.tags.total_refs 90376 # Total number of references to valid blocks. 759system.cpu.l2cache.tags.sampled_refs 126754 # Sample count of references to valid blocks. 760system.cpu.l2cache.tags.avg_refs 0.713003 # Average number of references to valid blocks. 761system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 762system.cpu.l2cache.tags.occ_blocks::writebacks 26679.268686 # Average occupied blocks per requestor 763system.cpu.l2cache.tags.occ_blocks::cpu.inst 1365.813290 # Average occupied blocks per requestor 764system.cpu.l2cache.tags.occ_blocks::cpu.data 1841.617225 # Average occupied blocks per requestor 765system.cpu.l2cache.tags.occ_percent::writebacks 0.814187 # Average percentage of cache occupancy 766system.cpu.l2cache.tags.occ_percent::cpu.inst 0.041681 # Average percentage of cache occupancy 767system.cpu.l2cache.tags.occ_percent::cpu.data 0.056202 # Average percentage of cache occupancy 768system.cpu.l2cache.tags.occ_percent::total 0.912070 # Average percentage of cache occupancy 769system.cpu.l2cache.ReadReq_hits::cpu.inst 27962 # number of ReadReq hits 770system.cpu.l2cache.ReadReq_hits::cpu.data 33496 # number of ReadReq hits 771system.cpu.l2cache.ReadReq_hits::total 61458 # number of ReadReq hits 772system.cpu.l2cache.Writeback_hits::writebacks 129187 # number of Writeback hits 773system.cpu.l2cache.Writeback_hits::total 129187 # number of Writeback hits 774system.cpu.l2cache.UpgradeReq_hits::cpu.data 18 # number of UpgradeReq hits 775system.cpu.l2cache.UpgradeReq_hits::total 18 # number of UpgradeReq hits 776system.cpu.l2cache.ReadExReq_hits::cpu.data 4794 # number of ReadExReq hits 777system.cpu.l2cache.ReadExReq_hits::total 4794 # number of ReadExReq hits 778system.cpu.l2cache.demand_hits::cpu.inst 27962 # number of demand (read+write) hits 779system.cpu.l2cache.demand_hits::cpu.data 38290 # number of demand (read+write) hits 780system.cpu.l2cache.demand_hits::total 66252 # number of demand (read+write) hits 781system.cpu.l2cache.overall_hits::cpu.inst 27962 # number of overall hits 782system.cpu.l2cache.overall_hits::cpu.data 38290 # number of overall hits 783system.cpu.l2cache.overall_hits::total 66252 # number of overall hits 784system.cpu.l2cache.ReadReq_misses::cpu.inst 4680 # number of ReadReq misses 785system.cpu.l2cache.ReadReq_misses::cpu.data 21912 # number of ReadReq misses 786system.cpu.l2cache.ReadReq_misses::total 26592 # number of ReadReq misses 787system.cpu.l2cache.UpgradeReq_misses::cpu.data 318 # number of UpgradeReq misses 788system.cpu.l2cache.UpgradeReq_misses::total 318 # number of UpgradeReq misses 789system.cpu.l2cache.ReadExReq_misses::cpu.data 102256 # number of ReadExReq misses 790system.cpu.l2cache.ReadExReq_misses::total 102256 # number of ReadExReq misses 791system.cpu.l2cache.demand_misses::cpu.inst 4680 # number of demand (read+write) misses 792system.cpu.l2cache.demand_misses::cpu.data 124168 # number of demand (read+write) misses 793system.cpu.l2cache.demand_misses::total 128848 # number of demand (read+write) misses 794system.cpu.l2cache.overall_misses::cpu.inst 4680 # number of overall misses 795system.cpu.l2cache.overall_misses::cpu.data 124168 # number of overall misses 796system.cpu.l2cache.overall_misses::total 128848 # number of overall misses 797system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 367025250 # number of ReadReq miss cycles 798system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1881179499 # number of ReadReq miss cycles 799system.cpu.l2cache.ReadReq_miss_latency::total 2248204749 # number of ReadReq miss cycles 800system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 23499 # number of UpgradeReq miss cycles 801system.cpu.l2cache.UpgradeReq_miss_latency::total 23499 # number of UpgradeReq miss cycles 802system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8506522000 # number of ReadExReq miss cycles 803system.cpu.l2cache.ReadExReq_miss_latency::total 8506522000 # number of ReadExReq miss cycles 804system.cpu.l2cache.demand_miss_latency::cpu.inst 367025250 # number of demand (read+write) miss cycles 805system.cpu.l2cache.demand_miss_latency::cpu.data 10387701499 # number of demand (read+write) miss cycles 806system.cpu.l2cache.demand_miss_latency::total 10754726749 # number of demand (read+write) miss cycles 807system.cpu.l2cache.overall_miss_latency::cpu.inst 367025250 # number of overall miss cycles 808system.cpu.l2cache.overall_miss_latency::cpu.data 10387701499 # number of overall miss cycles 809system.cpu.l2cache.overall_miss_latency::total 10754726749 # number of overall miss cycles 810system.cpu.l2cache.ReadReq_accesses::cpu.inst 32642 # number of ReadReq accesses(hits+misses) 811system.cpu.l2cache.ReadReq_accesses::cpu.data 55408 # number of ReadReq accesses(hits+misses) 812system.cpu.l2cache.ReadReq_accesses::total 88050 # number of ReadReq accesses(hits+misses) 813system.cpu.l2cache.Writeback_accesses::writebacks 129187 # number of Writeback accesses(hits+misses) 814system.cpu.l2cache.Writeback_accesses::total 129187 # number of Writeback accesses(hits+misses) 815system.cpu.l2cache.UpgradeReq_accesses::cpu.data 336 # number of UpgradeReq accesses(hits+misses) 816system.cpu.l2cache.UpgradeReq_accesses::total 336 # number of UpgradeReq accesses(hits+misses) 817system.cpu.l2cache.ReadExReq_accesses::cpu.data 107050 # number of ReadExReq accesses(hits+misses) 818system.cpu.l2cache.ReadExReq_accesses::total 107050 # number of ReadExReq accesses(hits+misses) 819system.cpu.l2cache.demand_accesses::cpu.inst 32642 # number of demand (read+write) accesses 820system.cpu.l2cache.demand_accesses::cpu.data 162458 # number of demand (read+write) accesses 821system.cpu.l2cache.demand_accesses::total 195100 # number of demand (read+write) accesses 822system.cpu.l2cache.overall_accesses::cpu.inst 32642 # number of overall (read+write) accesses 823system.cpu.l2cache.overall_accesses::cpu.data 162458 # number of overall (read+write) accesses 824system.cpu.l2cache.overall_accesses::total 195100 # number of overall (read+write) accesses 825system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.143374 # miss rate for ReadReq accesses 826system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.395466 # miss rate for ReadReq accesses 827system.cpu.l2cache.ReadReq_miss_rate::total 0.302010 # miss rate for ReadReq accesses 828system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.946429 # miss rate for UpgradeReq accesses 829system.cpu.l2cache.UpgradeReq_miss_rate::total 0.946429 # miss rate for UpgradeReq accesses 830system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.955217 # miss rate for ReadExReq accesses 831system.cpu.l2cache.ReadExReq_miss_rate::total 0.955217 # miss rate for ReadExReq accesses 832system.cpu.l2cache.demand_miss_rate::cpu.inst 0.143374 # miss rate for demand accesses 833system.cpu.l2cache.demand_miss_rate::cpu.data 0.764308 # miss rate for demand accesses 834system.cpu.l2cache.demand_miss_rate::total 0.660420 # miss rate for demand accesses 835system.cpu.l2cache.overall_miss_rate::cpu.inst 0.143374 # miss rate for overall accesses 836system.cpu.l2cache.overall_miss_rate::cpu.data 0.764308 # miss rate for overall accesses 837system.cpu.l2cache.overall_miss_rate::total 0.660420 # miss rate for overall accesses 838system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 78424.198718 # average ReadReq miss latency 839system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 85851.565307 # average ReadReq miss latency 840system.cpu.l2cache.ReadReq_avg_miss_latency::total 84544.402414 # average ReadReq miss latency 841system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 73.896226 # average UpgradeReq miss latency 842system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 73.896226 # average UpgradeReq miss latency 843system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 83188.487717 # average ReadExReq miss latency 844system.cpu.l2cache.ReadExReq_avg_miss_latency::total 83188.487717 # average ReadExReq miss latency 845system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 78424.198718 # average overall miss latency 846system.cpu.l2cache.demand_avg_miss_latency::cpu.data 83658.442586 # average overall miss latency 847system.cpu.l2cache.demand_avg_miss_latency::total 83468.325073 # average overall miss latency 848system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 78424.198718 # average overall miss latency 849system.cpu.l2cache.overall_avg_miss_latency::cpu.data 83658.442586 # average overall miss latency 850system.cpu.l2cache.overall_avg_miss_latency::total 83468.325073 # average overall miss latency 851system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 852system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 853system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 854system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 855system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 856system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 857system.cpu.l2cache.fast_writes 0 # number of fast writes performed 858system.cpu.l2cache.cache_copies 0 # number of cache copies performed 859system.cpu.l2cache.writebacks::writebacks 83939 # number of writebacks 860system.cpu.l2cache.writebacks::total 83939 # number of writebacks 861system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 17 # number of ReadReq MSHR hits 862system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 61 # number of ReadReq MSHR hits 863system.cpu.l2cache.ReadReq_mshr_hits::total 78 # number of ReadReq MSHR hits 864system.cpu.l2cache.demand_mshr_hits::cpu.inst 17 # number of demand (read+write) MSHR hits 865system.cpu.l2cache.demand_mshr_hits::cpu.data 61 # number of demand (read+write) MSHR hits 866system.cpu.l2cache.demand_mshr_hits::total 78 # number of demand (read+write) MSHR hits 867system.cpu.l2cache.overall_mshr_hits::cpu.inst 17 # number of overall MSHR hits 868system.cpu.l2cache.overall_mshr_hits::cpu.data 61 # number of overall MSHR hits 869system.cpu.l2cache.overall_mshr_hits::total 78 # number of overall MSHR hits 870system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 4663 # number of ReadReq MSHR misses 871system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 21851 # number of ReadReq MSHR misses 872system.cpu.l2cache.ReadReq_mshr_misses::total 26514 # number of ReadReq MSHR misses 873system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 318 # number of UpgradeReq MSHR misses 874system.cpu.l2cache.UpgradeReq_mshr_misses::total 318 # number of UpgradeReq MSHR misses 875system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102256 # number of ReadExReq MSHR misses 876system.cpu.l2cache.ReadExReq_mshr_misses::total 102256 # number of ReadExReq MSHR misses 877system.cpu.l2cache.demand_mshr_misses::cpu.inst 4663 # number of demand (read+write) MSHR misses 878system.cpu.l2cache.demand_mshr_misses::cpu.data 124107 # number of demand (read+write) MSHR misses 879system.cpu.l2cache.demand_mshr_misses::total 128770 # number of demand (read+write) MSHR misses 880system.cpu.l2cache.overall_mshr_misses::cpu.inst 4663 # number of overall MSHR misses 881system.cpu.l2cache.overall_mshr_misses::cpu.data 124107 # number of overall MSHR misses 882system.cpu.l2cache.overall_mshr_misses::total 128770 # number of overall MSHR misses 883system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 307037750 # number of ReadReq MSHR miss cycles 884system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1604664499 # number of ReadReq MSHR miss cycles 885system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1911702249 # number of ReadReq MSHR miss cycles 886system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 3189317 # number of UpgradeReq MSHR miss cycles 887system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 3189317 # number of UpgradeReq MSHR miss cycles 888system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7230852500 # number of ReadExReq MSHR miss cycles 889system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7230852500 # number of ReadExReq MSHR miss cycles 890system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 307037750 # number of demand (read+write) MSHR miss cycles 891system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8835516999 # number of demand (read+write) MSHR miss cycles 892system.cpu.l2cache.demand_mshr_miss_latency::total 9142554749 # number of demand (read+write) MSHR miss cycles 893system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 307037750 # number of overall MSHR miss cycles 894system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8835516999 # number of overall MSHR miss cycles 895system.cpu.l2cache.overall_mshr_miss_latency::total 9142554749 # number of overall MSHR miss cycles 896system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.142853 # mshr miss rate for ReadReq accesses 897system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.394365 # mshr miss rate for ReadReq accesses 898system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.301124 # mshr miss rate for ReadReq accesses 899system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.946429 # mshr miss rate for UpgradeReq accesses 900system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.946429 # mshr miss rate for UpgradeReq accesses 901system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955217 # mshr miss rate for ReadExReq accesses 902system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955217 # mshr miss rate for ReadExReq accesses 903system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.142853 # mshr miss rate for demand accesses 904system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.763933 # mshr miss rate for demand accesses 905system.cpu.l2cache.demand_mshr_miss_rate::total 0.660021 # mshr miss rate for demand accesses 906system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.142853 # mshr miss rate for overall accesses 907system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.763933 # mshr miss rate for overall accesses 908system.cpu.l2cache.overall_mshr_miss_rate::total 0.660021 # mshr miss rate for overall accesses 909system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 65845.539352 # average ReadReq mshr miss latency 910system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 73436.661892 # average ReadReq mshr miss latency 911system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 72101.616090 # average ReadReq mshr miss latency 912system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10029.298742 # average UpgradeReq mshr miss latency 913system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10029.298742 # average UpgradeReq mshr miss latency 914system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70713.234431 # average ReadExReq mshr miss latency 915system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70713.234431 # average ReadExReq mshr miss latency 916system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65845.539352 # average overall mshr miss latency 917system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71192.736904 # average overall mshr miss latency 918system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70999.104986 # average overall mshr miss latency 919system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65845.539352 # average overall mshr miss latency 920system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71192.736904 # average overall mshr miss latency 921system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70999.104986 # average overall mshr miss latency 922system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 923system.cpu.dcache.tags.replacements 158362 # number of replacements 924system.cpu.dcache.tags.tagsinuse 4068.865935 # Cycle average of tags in use 925system.cpu.dcache.tags.total_refs 44347537 # Total number of references to valid blocks. 926system.cpu.dcache.tags.sampled_refs 162458 # Sample count of references to valid blocks. 927system.cpu.dcache.tags.avg_refs 272.978474 # Average number of references to valid blocks. 928system.cpu.dcache.tags.warmup_cycle 363282250 # Cycle when the warmup percentage was hit. 929system.cpu.dcache.tags.occ_blocks::cpu.data 4068.865935 # Average occupied blocks per requestor 930system.cpu.dcache.tags.occ_percent::cpu.data 0.993375 # Average percentage of cache occupancy 931system.cpu.dcache.tags.occ_percent::total 0.993375 # Average percentage of cache occupancy 932system.cpu.dcache.ReadReq_hits::cpu.data 26048299 # number of ReadReq hits 933system.cpu.dcache.ReadReq_hits::total 26048299 # number of ReadReq hits 934system.cpu.dcache.WriteReq_hits::cpu.data 18266707 # number of WriteReq hits 935system.cpu.dcache.WriteReq_hits::total 18266707 # number of WriteReq hits 936system.cpu.dcache.LoadLockedReq_hits::cpu.data 15986 # number of LoadLockedReq hits 937system.cpu.dcache.LoadLockedReq_hits::total 15986 # number of LoadLockedReq hits 938system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits 939system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits 940system.cpu.dcache.demand_hits::cpu.data 44315006 # number of demand (read+write) hits 941system.cpu.dcache.demand_hits::total 44315006 # number of demand (read+write) hits 942system.cpu.dcache.overall_hits::cpu.data 44315006 # number of overall hits 943system.cpu.dcache.overall_hits::total 44315006 # number of overall hits 944system.cpu.dcache.ReadReq_misses::cpu.data 125034 # number of ReadReq misses 945system.cpu.dcache.ReadReq_misses::total 125034 # number of ReadReq misses 946system.cpu.dcache.WriteReq_misses::cpu.data 1583194 # number of WriteReq misses 947system.cpu.dcache.WriteReq_misses::total 1583194 # number of WriteReq misses 948system.cpu.dcache.LoadLockedReq_misses::cpu.data 41 # number of LoadLockedReq misses 949system.cpu.dcache.LoadLockedReq_misses::total 41 # number of LoadLockedReq misses 950system.cpu.dcache.demand_misses::cpu.data 1708228 # number of demand (read+write) misses 951system.cpu.dcache.demand_misses::total 1708228 # number of demand (read+write) misses 952system.cpu.dcache.overall_misses::cpu.data 1708228 # number of overall misses 953system.cpu.dcache.overall_misses::total 1708228 # number of overall misses 954system.cpu.dcache.ReadReq_miss_latency::cpu.data 5241649212 # number of ReadReq miss cycles 955system.cpu.dcache.ReadReq_miss_latency::total 5241649212 # number of ReadReq miss cycles 956system.cpu.dcache.WriteReq_miss_latency::cpu.data 126812367989 # number of WriteReq miss cycles 957system.cpu.dcache.WriteReq_miss_latency::total 126812367989 # number of WriteReq miss cycles 958system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 914750 # number of LoadLockedReq miss cycles 959system.cpu.dcache.LoadLockedReq_miss_latency::total 914750 # number of LoadLockedReq miss cycles 960system.cpu.dcache.demand_miss_latency::cpu.data 132054017201 # number of demand (read+write) miss cycles 961system.cpu.dcache.demand_miss_latency::total 132054017201 # number of demand (read+write) miss cycles 962system.cpu.dcache.overall_miss_latency::cpu.data 132054017201 # number of overall miss cycles 963system.cpu.dcache.overall_miss_latency::total 132054017201 # number of overall miss cycles 964system.cpu.dcache.ReadReq_accesses::cpu.data 26173333 # number of ReadReq accesses(hits+misses) 965system.cpu.dcache.ReadReq_accesses::total 26173333 # number of ReadReq accesses(hits+misses) 966system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) 967system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) 968system.cpu.dcache.LoadLockedReq_accesses::cpu.data 16027 # number of LoadLockedReq accesses(hits+misses) 969system.cpu.dcache.LoadLockedReq_accesses::total 16027 # number of LoadLockedReq accesses(hits+misses) 970system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) 971system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) 972system.cpu.dcache.demand_accesses::cpu.data 46023234 # number of demand (read+write) accesses 973system.cpu.dcache.demand_accesses::total 46023234 # number of demand (read+write) accesses 974system.cpu.dcache.overall_accesses::cpu.data 46023234 # number of overall (read+write) accesses 975system.cpu.dcache.overall_accesses::total 46023234 # number of overall (read+write) accesses 976system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004777 # miss rate for ReadReq accesses 977system.cpu.dcache.ReadReq_miss_rate::total 0.004777 # miss rate for ReadReq accesses 978system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.079758 # miss rate for WriteReq accesses 979system.cpu.dcache.WriteReq_miss_rate::total 0.079758 # miss rate for WriteReq accesses 980system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002558 # miss rate for LoadLockedReq accesses 981system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002558 # miss rate for LoadLockedReq accesses 982system.cpu.dcache.demand_miss_rate::cpu.data 0.037117 # miss rate for demand accesses 983system.cpu.dcache.demand_miss_rate::total 0.037117 # miss rate for demand accesses 984system.cpu.dcache.overall_miss_rate::cpu.data 0.037117 # miss rate for overall accesses 985system.cpu.dcache.overall_miss_rate::total 0.037117 # miss rate for overall accesses 986system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 41921.790969 # average ReadReq miss latency 987system.cpu.dcache.ReadReq_avg_miss_latency::total 41921.790969 # average ReadReq miss latency 988system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 80099.070606 # average WriteReq miss latency 989system.cpu.dcache.WriteReq_avg_miss_latency::total 80099.070606 # average WriteReq miss latency 990system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 22310.975610 # average LoadLockedReq miss latency 991system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 22310.975610 # average LoadLockedReq miss latency 992system.cpu.dcache.demand_avg_miss_latency::cpu.data 77304.679001 # average overall miss latency 993system.cpu.dcache.demand_avg_miss_latency::total 77304.679001 # average overall miss latency 994system.cpu.dcache.overall_avg_miss_latency::cpu.data 77304.679001 # average overall miss latency 995system.cpu.dcache.overall_avg_miss_latency::total 77304.679001 # average overall miss latency 996system.cpu.dcache.blocked_cycles::no_mshrs 4730 # number of cycles access was blocked 997system.cpu.dcache.blocked_cycles::no_targets 1224 # number of cycles access was blocked 998system.cpu.dcache.blocked::no_mshrs 139 # number of cycles access was blocked 999system.cpu.dcache.blocked::no_targets 14 # number of cycles access was blocked 1000system.cpu.dcache.avg_blocked_cycles::no_mshrs 34.028777 # average number of cycles each access was blocked 1001system.cpu.dcache.avg_blocked_cycles::no_targets 87.428571 # average number of cycles each access was blocked 1002system.cpu.dcache.fast_writes 0 # number of fast writes performed 1003system.cpu.dcache.cache_copies 0 # number of cache copies performed 1004system.cpu.dcache.writebacks::writebacks 129187 # number of writebacks 1005system.cpu.dcache.writebacks::total 129187 # number of writebacks 1006system.cpu.dcache.ReadReq_mshr_hits::cpu.data 69592 # number of ReadReq MSHR hits 1007system.cpu.dcache.ReadReq_mshr_hits::total 69592 # number of ReadReq MSHR hits 1008system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1475842 # number of WriteReq MSHR hits 1009system.cpu.dcache.WriteReq_mshr_hits::total 1475842 # number of WriteReq MSHR hits 1010system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 41 # number of LoadLockedReq MSHR hits 1011system.cpu.dcache.LoadLockedReq_mshr_hits::total 41 # number of LoadLockedReq MSHR hits 1012system.cpu.dcache.demand_mshr_hits::cpu.data 1545434 # number of demand (read+write) MSHR hits 1013system.cpu.dcache.demand_mshr_hits::total 1545434 # number of demand (read+write) MSHR hits 1014system.cpu.dcache.overall_mshr_hits::cpu.data 1545434 # number of overall MSHR hits 1015system.cpu.dcache.overall_mshr_hits::total 1545434 # number of overall MSHR hits 1016system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55442 # number of ReadReq MSHR misses 1017system.cpu.dcache.ReadReq_mshr_misses::total 55442 # number of ReadReq MSHR misses 1018system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107352 # number of WriteReq MSHR misses 1019system.cpu.dcache.WriteReq_mshr_misses::total 107352 # number of WriteReq MSHR misses 1020system.cpu.dcache.demand_mshr_misses::cpu.data 162794 # number of demand (read+write) MSHR misses 1021system.cpu.dcache.demand_mshr_misses::total 162794 # number of demand (read+write) MSHR misses 1022system.cpu.dcache.overall_mshr_misses::cpu.data 162794 # number of overall MSHR misses 1023system.cpu.dcache.overall_mshr_misses::total 162794 # number of overall MSHR misses 1024system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2274282063 # number of ReadReq MSHR miss cycles 1025system.cpu.dcache.ReadReq_mshr_miss_latency::total 2274282063 # number of ReadReq MSHR miss cycles 1026system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8672803924 # number of WriteReq MSHR miss cycles 1027system.cpu.dcache.WriteReq_mshr_miss_latency::total 8672803924 # number of WriteReq MSHR miss cycles 1028system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10947085987 # number of demand (read+write) MSHR miss cycles 1029system.cpu.dcache.demand_mshr_miss_latency::total 10947085987 # number of demand (read+write) MSHR miss cycles 1030system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10947085987 # number of overall MSHR miss cycles 1031system.cpu.dcache.overall_mshr_miss_latency::total 10947085987 # number of overall MSHR miss cycles 1032system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002118 # mshr miss rate for ReadReq accesses 1033system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002118 # mshr miss rate for ReadReq accesses 1034system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005408 # mshr miss rate for WriteReq accesses 1035system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005408 # mshr miss rate for WriteReq accesses 1036system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003537 # mshr miss rate for demand accesses 1037system.cpu.dcache.demand_mshr_miss_rate::total 0.003537 # mshr miss rate for demand accesses 1038system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003537 # mshr miss rate for overall accesses 1039system.cpu.dcache.overall_mshr_miss_rate::total 0.003537 # mshr miss rate for overall accesses 1040system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 41020.923902 # average ReadReq mshr miss latency 1041system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 41020.923902 # average ReadReq mshr miss latency 1042system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80788.470862 # average WriteReq mshr miss latency 1043system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80788.470862 # average WriteReq mshr miss latency 1044system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 67245.021235 # average overall mshr miss latency 1045system.cpu.dcache.demand_avg_mshr_miss_latency::total 67245.021235 # average overall mshr miss latency 1046system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67245.021235 # average overall mshr miss latency 1047system.cpu.dcache.overall_avg_mshr_miss_latency::total 67245.021235 # average overall mshr miss latency 1048system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1049 1050---------- End Simulation Statistics ---------- 1051