stats.txt revision 11103
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.033333 # Number of seconds simulated 4sim_ticks 33333078000 # Number of ticks simulated 5final_tick 33333078000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 125008 # Simulator instruction rate (inst/s) 8host_op_rate 159871 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 58765299 # Simulator tick rate (ticks/s) 10host_mem_usage 325044 # Number of bytes of host memory used 11host_seconds 567.22 # Real time elapsed on the host 12sim_insts 70907630 # Number of instructions simulated 13sim_ops 90682585 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 591360 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 2521216 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.l2cache.prefetcher 6195328 # Number of bytes read from this memory 19system.physmem.bytes_read::total 9307904 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 591360 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 591360 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 6264192 # Number of bytes written to this memory 23system.physmem.bytes_written::total 6264192 # Number of bytes written to this memory 24system.physmem.num_reads::cpu.inst 9240 # Number of read requests responded to by this memory 25system.physmem.num_reads::cpu.data 39394 # Number of read requests responded to by this memory 26system.physmem.num_reads::cpu.l2cache.prefetcher 96802 # Number of read requests responded to by this memory 27system.physmem.num_reads::total 145436 # Number of read requests responded to by this memory 28system.physmem.num_writes::writebacks 97878 # Number of write requests responded to by this memory 29system.physmem.num_writes::total 97878 # Number of write requests responded to by this memory 30system.physmem.bw_read::cpu.inst 17740936 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_read::cpu.data 75637059 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_read::cpu.l2cache.prefetcher 185861264 # Total read bandwidth from this memory (bytes/s) 33system.physmem.bw_read::total 279239259 # Total read bandwidth from this memory (bytes/s) 34system.physmem.bw_inst_read::cpu.inst 17740936 # Instruction read bandwidth from this memory (bytes/s) 35system.physmem.bw_inst_read::total 17740936 # Instruction read bandwidth from this memory (bytes/s) 36system.physmem.bw_write::writebacks 187927200 # Write bandwidth from this memory (bytes/s) 37system.physmem.bw_write::total 187927200 # Write bandwidth from this memory (bytes/s) 38system.physmem.bw_total::writebacks 187927200 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.bw_total::cpu.inst 17740936 # Total bandwidth to/from this memory (bytes/s) 40system.physmem.bw_total::cpu.data 75637059 # Total bandwidth to/from this memory (bytes/s) 41system.physmem.bw_total::cpu.l2cache.prefetcher 185861264 # Total bandwidth to/from this memory (bytes/s) 42system.physmem.bw_total::total 467166458 # Total bandwidth to/from this memory (bytes/s) 43system.physmem.readReqs 145436 # Number of read requests accepted 44system.physmem.writeReqs 97878 # Number of write requests accepted 45system.physmem.readBursts 145436 # Number of DRAM read bursts, including those serviced by the write queue 46system.physmem.writeBursts 97878 # Number of DRAM write bursts, including those merged in the write queue 47system.physmem.bytesReadDRAM 9300544 # Total number of bytes read from DRAM 48system.physmem.bytesReadWrQ 7360 # Total number of bytes read from write queue 49system.physmem.bytesWritten 6263104 # Total number of bytes written to DRAM 50system.physmem.bytesReadSys 9307904 # Total read bytes from the system interface side 51system.physmem.bytesWrittenSys 6264192 # Total written bytes from the system interface side 52system.physmem.servicedByWrQ 115 # Number of DRAM read bursts serviced by the write queue 53system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 54system.physmem.neitherReadNorWriteReqs 6 # Number of requests that are neither read nor write 55system.physmem.perBankRdBursts::0 9151 # Per bank write bursts 56system.physmem.perBankRdBursts::1 9416 # Per bank write bursts 57system.physmem.perBankRdBursts::2 9264 # Per bank write bursts 58system.physmem.perBankRdBursts::3 9524 # Per bank write bursts 59system.physmem.perBankRdBursts::4 9728 # Per bank write bursts 60system.physmem.perBankRdBursts::5 9774 # Per bank write bursts 61system.physmem.perBankRdBursts::6 9086 # Per bank write bursts 62system.physmem.perBankRdBursts::7 9016 # Per bank write bursts 63system.physmem.perBankRdBursts::8 9170 # Per bank write bursts 64system.physmem.perBankRdBursts::9 8620 # Per bank write bursts 65system.physmem.perBankRdBursts::10 8843 # Per bank write bursts 66system.physmem.perBankRdBursts::11 8715 # Per bank write bursts 67system.physmem.perBankRdBursts::12 8697 # Per bank write bursts 68system.physmem.perBankRdBursts::13 8672 # Per bank write bursts 69system.physmem.perBankRdBursts::14 8700 # Per bank write bursts 70system.physmem.perBankRdBursts::15 8945 # Per bank write bursts 71system.physmem.perBankWrBursts::0 6002 # Per bank write bursts 72system.physmem.perBankWrBursts::1 6227 # Per bank write bursts 73system.physmem.perBankWrBursts::2 6156 # Per bank write bursts 74system.physmem.perBankWrBursts::3 6165 # Per bank write bursts 75system.physmem.perBankWrBursts::4 6066 # Per bank write bursts 76system.physmem.perBankWrBursts::5 6338 # Per bank write bursts 77system.physmem.perBankWrBursts::6 6039 # Per bank write bursts 78system.physmem.perBankWrBursts::7 6021 # Per bank write bursts 79system.physmem.perBankWrBursts::8 6032 # Per bank write bursts 80system.physmem.perBankWrBursts::9 6183 # Per bank write bursts 81system.physmem.perBankWrBursts::10 6239 # Per bank write bursts 82system.physmem.perBankWrBursts::11 5928 # Per bank write bursts 83system.physmem.perBankWrBursts::12 6101 # Per bank write bursts 84system.physmem.perBankWrBursts::13 6124 # Per bank write bursts 85system.physmem.perBankWrBursts::14 6211 # Per bank write bursts 86system.physmem.perBankWrBursts::15 6029 # Per bank write bursts 87system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 88system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 89system.physmem.totGap 33332792500 # Total gap between requests 90system.physmem.readPktSize::0 0 # Read request sizes (log2) 91system.physmem.readPktSize::1 0 # Read request sizes (log2) 92system.physmem.readPktSize::2 0 # Read request sizes (log2) 93system.physmem.readPktSize::3 0 # Read request sizes (log2) 94system.physmem.readPktSize::4 0 # Read request sizes (log2) 95system.physmem.readPktSize::5 0 # Read request sizes (log2) 96system.physmem.readPktSize::6 145436 # Read request sizes (log2) 97system.physmem.writePktSize::0 0 # Write request sizes (log2) 98system.physmem.writePktSize::1 0 # Write request sizes (log2) 99system.physmem.writePktSize::2 0 # Write request sizes (log2) 100system.physmem.writePktSize::3 0 # Write request sizes (log2) 101system.physmem.writePktSize::4 0 # Write request sizes (log2) 102system.physmem.writePktSize::5 0 # Write request sizes (log2) 103system.physmem.writePktSize::6 97878 # Write request sizes (log2) 104system.physmem.rdQLenPdf::0 41531 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::1 55128 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::2 14558 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::3 10364 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::4 5987 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::5 5214 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::6 4599 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::7 4263 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::8 3539 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::9 86 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::10 42 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::11 6 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::12 3 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 136system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::15 1148 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::16 1184 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::17 1918 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::18 2582 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::19 3353 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::20 4290 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::21 5332 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::22 5723 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::23 5988 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::24 6224 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::25 6557 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::26 7007 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::27 7623 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::28 8324 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::29 9140 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::30 7906 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::31 6877 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::32 6327 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::33 206 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::34 85 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::35 44 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::36 14 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::37 11 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 200system.physmem.bytesPerActivate::samples 88939 # Bytes accessed per row activation 201system.physmem.bytesPerActivate::mean 174.992388 # Bytes accessed per row activation 202system.physmem.bytesPerActivate::gmean 110.439382 # Bytes accessed per row activation 203system.physmem.bytesPerActivate::stdev 239.025071 # Bytes accessed per row activation 204system.physmem.bytesPerActivate::0-127 52267 58.77% 58.77% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::128-255 22760 25.59% 84.36% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::256-383 4436 4.99% 89.35% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::384-511 1732 1.95% 91.29% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::512-639 1066 1.20% 92.49% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::640-767 777 0.87% 93.37% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::768-895 661 0.74% 94.11% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::896-1023 818 0.92% 95.03% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::1024-1151 4422 4.97% 100.00% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::total 88939 # Bytes accessed per row activation 214system.physmem.rdPerTurnAround::samples 5911 # Reads before turning the bus around for writes 215system.physmem.rdPerTurnAround::mean 24.584503 # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::gmean 21.105941 # Reads before turning the bus around for writes 217system.physmem.rdPerTurnAround::stdev 187.238550 # Reads before turning the bus around for writes 218system.physmem.rdPerTurnAround::0-511 5910 99.98% 99.98% # Reads before turning the bus around for writes 219system.physmem.rdPerTurnAround::14336-14847 1 0.02% 100.00% # Reads before turning the bus around for writes 220system.physmem.rdPerTurnAround::total 5911 # Reads before turning the bus around for writes 221system.physmem.wrPerTurnAround::samples 5911 # Writes before turning the bus around for reads 222system.physmem.wrPerTurnAround::mean 16.555744 # Writes before turning the bus around for reads 223system.physmem.wrPerTurnAround::gmean 16.512900 # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::stdev 1.266741 # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::16 4704 79.58% 79.58% # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::17 36 0.61% 80.19% # Writes before turning the bus around for reads 227system.physmem.wrPerTurnAround::18 781 13.21% 93.40% # Writes before turning the bus around for reads 228system.physmem.wrPerTurnAround::19 157 2.66% 96.06% # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::20 88 1.49% 97.55% # Writes before turning the bus around for reads 230system.physmem.wrPerTurnAround::21 64 1.08% 98.63% # Writes before turning the bus around for reads 231system.physmem.wrPerTurnAround::22 47 0.80% 99.42% # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::23 14 0.24% 99.66% # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::24 17 0.29% 99.95% # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::25 2 0.03% 99.98% # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::26 1 0.02% 100.00% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::total 5911 # Writes before turning the bus around for reads 237system.physmem.totQLat 7028707749 # Total ticks spent queuing 238system.physmem.totMemAccLat 9753476499 # Total ticks spent from burst creation until serviced by the DRAM 239system.physmem.totBusLat 726605000 # Total ticks spent in databus transfers 240system.physmem.avgQLat 48366.77 # Average queueing delay per DRAM burst 241system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 242system.physmem.avgMemAccLat 67116.77 # Average memory access latency per DRAM burst 243system.physmem.avgRdBW 279.02 # Average DRAM read bandwidth in MiByte/s 244system.physmem.avgWrBW 187.89 # Average achieved write bandwidth in MiByte/s 245system.physmem.avgRdBWSys 279.24 # Average system read bandwidth in MiByte/s 246system.physmem.avgWrBWSys 187.93 # Average system write bandwidth in MiByte/s 247system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 248system.physmem.busUtil 3.65 # Data bus utilization in percentage 249system.physmem.busUtilRead 2.18 # Data bus utilization in percentage for reads 250system.physmem.busUtilWrite 1.47 # Data bus utilization in percentage for writes 251system.physmem.avgRdQLen 1.59 # Average read queue length when enqueuing 252system.physmem.avgWrQLen 24.82 # Average write queue length when enqueuing 253system.physmem.readRowHits 118079 # Number of row buffer hits during reads 254system.physmem.writeRowHits 36164 # Number of row buffer hits during writes 255system.physmem.readRowHitRate 81.25 # Row buffer hit rate for reads 256system.physmem.writeRowHitRate 36.95 # Row buffer hit rate for writes 257system.physmem.avgGap 136994.96 # Average gap between requests 258system.physmem.pageHitRate 63.42 # Row buffer hit rate, read and write combined 259system.physmem_0.actEnergy 343934640 # Energy for activate commands per rank (pJ) 260system.physmem_0.preEnergy 187662750 # Energy for precharge commands per rank (pJ) 261system.physmem_0.readEnergy 584680200 # Energy for read commands per rank (pJ) 262system.physmem_0.writeEnergy 317610720 # Energy for write commands per rank (pJ) 263system.physmem_0.refreshEnergy 2177145360 # Energy for refresh commands per rank (pJ) 264system.physmem_0.actBackEnergy 11782825965 # Energy for active background per rank (pJ) 265system.physmem_0.preBackEnergy 9664105500 # Energy for precharge background per rank (pJ) 266system.physmem_0.totalEnergy 25057965135 # Total energy per rank (pJ) 267system.physmem_0.averagePower 751.742046 # Core power per rank (mW) 268system.physmem_0.memoryStateTime::IDLE 15979863754 # Time in different power states 269system.physmem_0.memoryStateTime::REF 1112800000 # Time in different power states 270system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 271system.physmem_0.memoryStateTime::ACT 16240286246 # Time in different power states 272system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 273system.physmem_1.actEnergy 328444200 # Energy for activate commands per rank (pJ) 274system.physmem_1.preEnergy 179210625 # Energy for precharge commands per rank (pJ) 275system.physmem_1.readEnergy 548823600 # Energy for read commands per rank (pJ) 276system.physmem_1.writeEnergy 316528560 # Energy for write commands per rank (pJ) 277system.physmem_1.refreshEnergy 2177145360 # Energy for refresh commands per rank (pJ) 278system.physmem_1.actBackEnergy 11298113640 # Energy for active background per rank (pJ) 279system.physmem_1.preBackEnergy 10089291750 # Energy for precharge background per rank (pJ) 280system.physmem_1.totalEnergy 24937557735 # Total energy per rank (pJ) 281system.physmem_1.averagePower 748.129809 # Core power per rank (mW) 282system.physmem_1.memoryStateTime::IDLE 16691408912 # Time in different power states 283system.physmem_1.memoryStateTime::REF 1112800000 # Time in different power states 284system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 285system.physmem_1.memoryStateTime::ACT 15528741088 # Time in different power states 286system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 287system.cpu.branchPred.lookups 17206633 # Number of BP lookups 288system.cpu.branchPred.condPredicted 11518078 # Number of conditional branches predicted 289system.cpu.branchPred.condIncorrect 648316 # Number of conditional branches incorrect 290system.cpu.branchPred.BTBLookups 9346074 # Number of BTB lookups 291system.cpu.branchPred.BTBHits 7675410 # Number of BTB hits 292system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 293system.cpu.branchPred.BTBHitPct 82.124430 # BTB Hit Percentage 294system.cpu.branchPred.usedRAS 1873047 # Number of times the RAS was used to get a target. 295system.cpu.branchPred.RASInCorrect 101552 # Number of incorrect RAS predictions. 296system.cpu_clk_domain.clock 500 # Clock period in ticks 297system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 298system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 299system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 300system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 301system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 302system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 303system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 304system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 305system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 306system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 307system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 308system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 309system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 310system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 311system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 312system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 313system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 314system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 315system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 316system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 317system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 318system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 319system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 320system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 321system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 322system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 323system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 324system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 325system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 326system.cpu.dtb.walker.walks 0 # Table walker walks requested 327system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 328system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 329system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 330system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 331system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 332system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 333system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 334system.cpu.dtb.inst_hits 0 # ITB inst hits 335system.cpu.dtb.inst_misses 0 # ITB inst misses 336system.cpu.dtb.read_hits 0 # DTB read hits 337system.cpu.dtb.read_misses 0 # DTB read misses 338system.cpu.dtb.write_hits 0 # DTB write hits 339system.cpu.dtb.write_misses 0 # DTB write misses 340system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 341system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 342system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 343system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 344system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 345system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 346system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 347system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 348system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 349system.cpu.dtb.read_accesses 0 # DTB read accesses 350system.cpu.dtb.write_accesses 0 # DTB write accesses 351system.cpu.dtb.inst_accesses 0 # ITB inst accesses 352system.cpu.dtb.hits 0 # DTB hits 353system.cpu.dtb.misses 0 # DTB misses 354system.cpu.dtb.accesses 0 # DTB accesses 355system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 356system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 357system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 358system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 359system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 360system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 361system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 362system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 363system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 364system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 365system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 366system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 367system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 368system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 369system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 370system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 371system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 372system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 373system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 374system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 375system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 376system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 377system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 378system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 379system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 380system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 381system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 382system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 383system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 384system.cpu.itb.walker.walks 0 # Table walker walks requested 385system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 386system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 387system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 388system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 389system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 390system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 391system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 392system.cpu.itb.inst_hits 0 # ITB inst hits 393system.cpu.itb.inst_misses 0 # ITB inst misses 394system.cpu.itb.read_hits 0 # DTB read hits 395system.cpu.itb.read_misses 0 # DTB read misses 396system.cpu.itb.write_hits 0 # DTB write hits 397system.cpu.itb.write_misses 0 # DTB write misses 398system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 399system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 400system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 401system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 402system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 403system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 404system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 405system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 406system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 407system.cpu.itb.read_accesses 0 # DTB read accesses 408system.cpu.itb.write_accesses 0 # DTB write accesses 409system.cpu.itb.inst_accesses 0 # ITB inst accesses 410system.cpu.itb.hits 0 # DTB hits 411system.cpu.itb.misses 0 # DTB misses 412system.cpu.itb.accesses 0 # DTB accesses 413system.cpu.workload.num_syscalls 1946 # Number of system calls 414system.cpu.numCycles 66666157 # number of cpu cycles simulated 415system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 416system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 417system.cpu.fetch.icacheStallCycles 5010938 # Number of cycles fetch is stalled on an Icache miss 418system.cpu.fetch.Insts 88191821 # Number of instructions fetch has processed 419system.cpu.fetch.Branches 17206633 # Number of branches that fetch encountered 420system.cpu.fetch.predictedBranches 9548457 # Number of branches that fetch has predicted taken 421system.cpu.fetch.Cycles 60137734 # Number of cycles fetch has run and was not squashing or blocked 422system.cpu.fetch.SquashCycles 1322663 # Number of cycles fetch has spent squashing 423system.cpu.fetch.MiscStallCycles 6978 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 424system.cpu.fetch.PendingTrapStallCycles 23 # Number of stall cycles due to pending traps 425system.cpu.fetch.IcacheWaitRetryStallCycles 13644 # Number of stall cycles due to full MSHR 426system.cpu.fetch.CacheLines 22767110 # Number of cache lines fetched 427system.cpu.fetch.IcacheSquashes 69105 # Number of outstanding Icache misses that were squashed 428system.cpu.fetch.rateDist::samples 65830648 # Number of instructions fetched each cycle (Total) 429system.cpu.fetch.rateDist::mean 1.695372 # Number of instructions fetched each cycle (Total) 430system.cpu.fetch.rateDist::stdev 1.296604 # Number of instructions fetched each cycle (Total) 431system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 432system.cpu.fetch.rateDist::0 20050738 30.46% 30.46% # Number of instructions fetched each cycle (Total) 433system.cpu.fetch.rateDist::1 8265796 12.56% 43.01% # Number of instructions fetched each cycle (Total) 434system.cpu.fetch.rateDist::2 9200690 13.98% 56.99% # Number of instructions fetched each cycle (Total) 435system.cpu.fetch.rateDist::3 28313424 43.01% 100.00% # Number of instructions fetched each cycle (Total) 436system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 437system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 438system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) 439system.cpu.fetch.rateDist::total 65830648 # Number of instructions fetched each cycle (Total) 440system.cpu.fetch.branchRate 0.258101 # Number of branch fetches per cycle 441system.cpu.fetch.rate 1.322887 # Number of inst fetches per cycle 442system.cpu.decode.IdleCycles 8588438 # Number of cycles decode is idle 443system.cpu.decode.BlockedCycles 19545167 # Number of cycles decode is blocked 444system.cpu.decode.RunCycles 31574635 # Number of cycles decode is running 445system.cpu.decode.UnblockCycles 5630215 # Number of cycles decode is unblocking 446system.cpu.decode.SquashCycles 492193 # Number of cycles decode is squashing 447system.cpu.decode.BranchResolved 3180012 # Number of times decode resolved a branch 448system.cpu.decode.BranchMispred 171001 # Number of times decode detected a branch misprediction 449system.cpu.decode.DecodedInsts 101409826 # Number of instructions handled by decode 450system.cpu.decode.SquashedInsts 3046686 # Number of squashed instructions handled by decode 451system.cpu.rename.SquashCycles 492193 # Number of cycles rename is squashing 452system.cpu.rename.IdleCycles 13345278 # Number of cycles rename is idle 453system.cpu.rename.BlockCycles 5337889 # Number of cycles rename is blocking 454system.cpu.rename.serializeStallCycles 804170 # count of cycles rename stalled for serializing inst 455system.cpu.rename.RunCycles 32233077 # Number of cycles rename is running 456system.cpu.rename.UnblockCycles 13618041 # Number of cycles rename is unblocking 457system.cpu.rename.RenamedInsts 99203464 # Number of instructions processed by rename 458system.cpu.rename.SquashedInsts 983266 # Number of squashed instructions processed by rename 459system.cpu.rename.ROBFullEvents 3848076 # Number of times rename has blocked due to ROB full 460system.cpu.rename.IQFullEvents 66970 # Number of times rename has blocked due to IQ full 461system.cpu.rename.LQFullEvents 4316860 # Number of times rename has blocked due to LQ full 462system.cpu.rename.SQFullEvents 5302934 # Number of times rename has blocked due to SQ full 463system.cpu.rename.RenamedOperands 103925476 # Number of destination operands rename has renamed 464system.cpu.rename.RenameLookups 457709098 # Number of register rename lookups that rename has made 465system.cpu.rename.int_rename_lookups 115412648 # Number of integer rename lookups 466system.cpu.rename.fp_rename_lookups 550 # Number of floating rename lookups 467system.cpu.rename.CommittedMaps 93629226 # Number of HB maps that are committed 468system.cpu.rename.UndoneMaps 10296250 # Number of HB maps that are undone due to squashing 469system.cpu.rename.serializingInsts 18661 # count of serializing insts renamed 470system.cpu.rename.tempSerializingInsts 18653 # count of temporary serializing insts renamed 471system.cpu.rename.skidInsts 12703257 # count of insts added to the skid buffer 472system.cpu.memDep0.insertedLoads 24321959 # Number of loads inserted to the mem dependence unit. 473system.cpu.memDep0.insertedStores 21992794 # Number of stores inserted to the mem dependence unit. 474system.cpu.memDep0.conflictingLoads 1408685 # Number of conflicting loads. 475system.cpu.memDep0.conflictingStores 2344134 # Number of conflicting stores. 476system.cpu.iq.iqInstsAdded 98166936 # Number of instructions added to the IQ (excludes non-spec) 477system.cpu.iq.iqNonSpecInstsAdded 34525 # Number of non-speculative instructions added to the IQ 478system.cpu.iq.iqInstsIssued 94895750 # Number of instructions issued 479system.cpu.iq.iqSquashedInstsIssued 693672 # Number of squashed instructions issued 480system.cpu.iq.iqSquashedInstsExamined 7518876 # Number of squashed instructions iterated over during squash; mainly for profiling 481system.cpu.iq.iqSquashedOperandsExamined 20249831 # Number of squashed operands that are examined and possibly removed from graph 482system.cpu.iq.iqSquashedNonSpecRemoved 739 # Number of squashed non-spec instructions that were removed 483system.cpu.iq.issued_per_cycle::samples 65830648 # Number of insts issued each cycle 484system.cpu.iq.issued_per_cycle::mean 1.441513 # Number of insts issued each cycle 485system.cpu.iq.issued_per_cycle::stdev 1.149732 # Number of insts issued each cycle 486system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 487system.cpu.iq.issued_per_cycle::0 17559708 26.67% 26.67% # Number of insts issued each cycle 488system.cpu.iq.issued_per_cycle::1 17428340 26.47% 53.15% # Number of insts issued each cycle 489system.cpu.iq.issued_per_cycle::2 17111473 25.99% 79.14% # Number of insts issued each cycle 490system.cpu.iq.issued_per_cycle::3 11681013 17.74% 96.89% # Number of insts issued each cycle 491system.cpu.iq.issued_per_cycle::4 2049145 3.11% 100.00% # Number of insts issued each cycle 492system.cpu.iq.issued_per_cycle::5 969 0.00% 100.00% # Number of insts issued each cycle 493system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 494system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 495system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 496system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 497system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 498system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle 499system.cpu.iq.issued_per_cycle::total 65830648 # Number of insts issued each cycle 500system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 501system.cpu.iq.fu_full::IntAlu 6713649 22.39% 22.39% # attempts to use FU when none available 502system.cpu.iq.fu_full::IntMult 39 0.00% 22.39% # attempts to use FU when none available 503system.cpu.iq.fu_full::IntDiv 0 0.00% 22.39% # attempts to use FU when none available 504system.cpu.iq.fu_full::FloatAdd 0 0.00% 22.39% # attempts to use FU when none available 505system.cpu.iq.fu_full::FloatCmp 0 0.00% 22.39% # attempts to use FU when none available 506system.cpu.iq.fu_full::FloatCvt 0 0.00% 22.39% # attempts to use FU when none available 507system.cpu.iq.fu_full::FloatMult 0 0.00% 22.39% # attempts to use FU when none available 508system.cpu.iq.fu_full::FloatDiv 0 0.00% 22.39% # attempts to use FU when none available 509system.cpu.iq.fu_full::FloatSqrt 0 0.00% 22.39% # attempts to use FU when none available 510system.cpu.iq.fu_full::SimdAdd 0 0.00% 22.39% # attempts to use FU when none available 511system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 22.39% # attempts to use FU when none available 512system.cpu.iq.fu_full::SimdAlu 0 0.00% 22.39% # attempts to use FU when none available 513system.cpu.iq.fu_full::SimdCmp 0 0.00% 22.39% # attempts to use FU when none available 514system.cpu.iq.fu_full::SimdCvt 0 0.00% 22.39% # attempts to use FU when none available 515system.cpu.iq.fu_full::SimdMisc 0 0.00% 22.39% # attempts to use FU when none available 516system.cpu.iq.fu_full::SimdMult 0 0.00% 22.39% # attempts to use FU when none available 517system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 22.39% # attempts to use FU when none available 518system.cpu.iq.fu_full::SimdShift 0 0.00% 22.39% # attempts to use FU when none available 519system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 22.39% # attempts to use FU when none available 520system.cpu.iq.fu_full::SimdSqrt 0 0.00% 22.39% # attempts to use FU when none available 521system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 22.39% # attempts to use FU when none available 522system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 22.39% # attempts to use FU when none available 523system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 22.39% # attempts to use FU when none available 524system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 22.39% # attempts to use FU when none available 525system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 22.39% # attempts to use FU when none available 526system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 22.39% # attempts to use FU when none available 527system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 22.39% # attempts to use FU when none available 528system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 22.39% # attempts to use FU when none available 529system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 22.39% # attempts to use FU when none available 530system.cpu.iq.fu_full::MemRead 11199453 37.36% 59.75% # attempts to use FU when none available 531system.cpu.iq.fu_full::MemWrite 12066123 40.25% 100.00% # attempts to use FU when none available 532system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 533system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 534system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 535system.cpu.iq.FU_type_0::IntAlu 49496629 52.16% 52.16% # Type of FU issued 536system.cpu.iq.FU_type_0::IntMult 89874 0.09% 52.25% # Type of FU issued 537system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.25% # Type of FU issued 538system.cpu.iq.FU_type_0::FloatAdd 31 0.00% 52.25% # Type of FU issued 539system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.25% # Type of FU issued 540system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.25% # Type of FU issued 541system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.25% # Type of FU issued 542system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 52.25% # Type of FU issued 543system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 52.25% # Type of FU issued 544system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 52.25% # Type of FU issued 545system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 52.25% # Type of FU issued 546system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 52.25% # Type of FU issued 547system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 52.25% # Type of FU issued 548system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 52.25% # Type of FU issued 549system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 52.25% # Type of FU issued 550system.cpu.iq.FU_type_0::SimdMult 0 0.00% 52.25% # Type of FU issued 551system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 52.25% # Type of FU issued 552system.cpu.iq.FU_type_0::SimdShift 0 0.00% 52.25% # Type of FU issued 553system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.25% # Type of FU issued 554system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 52.25% # Type of FU issued 555system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.25% # Type of FU issued 556system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.25% # Type of FU issued 557system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 52.25% # Type of FU issued 558system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.25% # Type of FU issued 559system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.25% # Type of FU issued 560system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 52.25% # Type of FU issued 561system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.25% # Type of FU issued 562system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.25% # Type of FU issued 563system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.25% # Type of FU issued 564system.cpu.iq.FU_type_0::MemRead 24067515 25.36% 77.62% # Type of FU issued 565system.cpu.iq.FU_type_0::MemWrite 21241694 22.38% 100.00% # Type of FU issued 566system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 567system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 568system.cpu.iq.FU_type_0::total 94895750 # Type of FU issued 569system.cpu.iq.rate 1.423447 # Inst issue rate 570system.cpu.iq.fu_busy_cnt 29979264 # FU busy when requested 571system.cpu.iq.fu_busy_rate 0.315918 # FU busy rate (busy events/executed inst) 572system.cpu.iq.int_inst_queue_reads 286294877 # Number of integer instruction queue reads 573system.cpu.iq.int_inst_queue_writes 105731606 # Number of integer instruction queue writes 574system.cpu.iq.int_inst_queue_wakeup_accesses 93465380 # Number of integer instruction queue wakeup accesses 575system.cpu.iq.fp_inst_queue_reads 207 # Number of floating instruction queue reads 576system.cpu.iq.fp_inst_queue_writes 248 # Number of floating instruction queue writes 577system.cpu.iq.fp_inst_queue_wakeup_accesses 57 # Number of floating instruction queue wakeup accesses 578system.cpu.iq.int_alu_accesses 124874896 # Number of integer alu accesses 579system.cpu.iq.fp_alu_accesses 118 # Number of floating point alu accesses 580system.cpu.iew.lsq.thread0.forwLoads 1362273 # Number of loads that had data forwarded from stores 581system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 582system.cpu.iew.lsq.thread0.squashedLoads 1455697 # Number of loads squashed 583system.cpu.iew.lsq.thread0.ignoredResponses 2068 # Number of memory responses ignored because the instruction is squashed 584system.cpu.iew.lsq.thread0.memOrderViolation 11776 # Number of memory ordering violations 585system.cpu.iew.lsq.thread0.squashedStores 1437056 # Number of stores squashed 586system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 587system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 588system.cpu.iew.lsq.thread0.rescheduledLoads 140882 # Number of loads that were rescheduled 589system.cpu.iew.lsq.thread0.cacheBlocked 184054 # Number of times an access to memory failed due to the cache being blocked 590system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 591system.cpu.iew.iewSquashCycles 492193 # Number of cycles IEW is squashing 592system.cpu.iew.iewBlockCycles 620956 # Number of cycles IEW is blocking 593system.cpu.iew.iewUnblockCycles 467696 # Number of cycles IEW is unblocking 594system.cpu.iew.iewDispatchedInsts 98211315 # Number of instructions dispatched to IQ 595system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch 596system.cpu.iew.iewDispLoadInsts 24321959 # Number of dispatched load instructions 597system.cpu.iew.iewDispStoreInsts 21992794 # Number of dispatched store instructions 598system.cpu.iew.iewDispNonSpecInsts 18605 # Number of dispatched non-speculative instructions 599system.cpu.iew.iewIQFullEvents 1621 # Number of times the IQ has become full, causing a stall 600system.cpu.iew.iewLSQFullEvents 463138 # Number of times the LSQ has become full, causing a stall 601system.cpu.iew.memOrderViolationEvents 11776 # Number of memory order violations 602system.cpu.iew.predictedTakenIncorrect 302825 # Number of branches that were predicted taken incorrectly 603system.cpu.iew.predictedNotTakenIncorrect 221559 # Number of branches that were predicted not taken incorrectly 604system.cpu.iew.branchMispredicts 524384 # Number of branch mispredicts detected at execute 605system.cpu.iew.iewExecutedInsts 93978064 # Number of executed instructions 606system.cpu.iew.iewExecLoadInsts 23759823 # Number of load instructions executed 607system.cpu.iew.iewExecSquashedInsts 917686 # Number of squashed instructions skipped in execute 608system.cpu.iew.exec_swp 0 # number of swp insts executed 609system.cpu.iew.exec_nop 9854 # number of nop insts executed 610system.cpu.iew.exec_refs 44744798 # number of memory reference insts executed 611system.cpu.iew.exec_branches 14251807 # Number of branches executed 612system.cpu.iew.exec_stores 20984975 # Number of stores executed 613system.cpu.iew.exec_rate 1.409682 # Inst execution rate 614system.cpu.iew.wb_sent 93587077 # cumulative count of insts sent to commit 615system.cpu.iew.wb_count 93465437 # cumulative count of insts written-back 616system.cpu.iew.wb_producers 44977935 # num instructions producing a value 617system.cpu.iew.wb_consumers 76555853 # num instructions consuming a value 618system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 619system.cpu.iew.wb_rate 1.401992 # insts written-back per cycle 620system.cpu.iew.wb_fanout 0.587518 # average fanout of values written-back 621system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 622system.cpu.commit.commitSquashedInsts 6538600 # The number of squashed insts skipped by commit 623system.cpu.commit.commitNonSpecStalls 33786 # The number of times commit has been forced to stall to communicate backwards 624system.cpu.commit.branchMispredicts 479178 # The number of times a branch was mispredicted 625system.cpu.commit.committed_per_cycle::samples 64771963 # Number of insts commited each cycle 626system.cpu.commit.committed_per_cycle::mean 1.400114 # Number of insts commited each cycle 627system.cpu.commit.committed_per_cycle::stdev 2.164673 # Number of insts commited each cycle 628system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 629system.cpu.commit.committed_per_cycle::0 31176340 48.13% 48.13% # Number of insts commited each cycle 630system.cpu.commit.committed_per_cycle::1 16804620 25.94% 74.08% # Number of insts commited each cycle 631system.cpu.commit.committed_per_cycle::2 4339366 6.70% 80.78% # Number of insts commited each cycle 632system.cpu.commit.committed_per_cycle::3 4157771 6.42% 87.20% # Number of insts commited each cycle 633system.cpu.commit.committed_per_cycle::4 1944331 3.00% 90.20% # Number of insts commited each cycle 634system.cpu.commit.committed_per_cycle::5 1263277 1.95% 92.15% # Number of insts commited each cycle 635system.cpu.commit.committed_per_cycle::6 736800 1.14% 93.28% # Number of insts commited each cycle 636system.cpu.commit.committed_per_cycle::7 578701 0.89% 94.18% # Number of insts commited each cycle 637system.cpu.commit.committed_per_cycle::8 3770757 5.82% 100.00% # Number of insts commited each cycle 638system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 639system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 640system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 641system.cpu.commit.committed_per_cycle::total 64771963 # Number of insts commited each cycle 642system.cpu.commit.committedInsts 70913182 # Number of instructions committed 643system.cpu.commit.committedOps 90688137 # Number of ops (including micro ops) committed 644system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 645system.cpu.commit.refs 43422000 # Number of memory references committed 646system.cpu.commit.loads 22866262 # Number of loads committed 647system.cpu.commit.membars 15920 # Number of memory barriers committed 648system.cpu.commit.branches 13741486 # Number of branches committed 649system.cpu.commit.fp_insts 56 # Number of committed floating point instructions. 650system.cpu.commit.int_insts 81528487 # Number of committed integer instructions. 651system.cpu.commit.function_calls 1679850 # Number of function calls committed. 652system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 653system.cpu.commit.op_class_0::IntAlu 47186011 52.03% 52.03% # Class of committed instruction 654system.cpu.commit.op_class_0::IntMult 80119 0.09% 52.12% # Class of committed instruction 655system.cpu.commit.op_class_0::IntDiv 0 0.00% 52.12% # Class of committed instruction 656system.cpu.commit.op_class_0::FloatAdd 0 0.00% 52.12% # Class of committed instruction 657system.cpu.commit.op_class_0::FloatCmp 0 0.00% 52.12% # Class of committed instruction 658system.cpu.commit.op_class_0::FloatCvt 0 0.00% 52.12% # Class of committed instruction 659system.cpu.commit.op_class_0::FloatMult 0 0.00% 52.12% # Class of committed instruction 660system.cpu.commit.op_class_0::FloatDiv 0 0.00% 52.12% # Class of committed instruction 661system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 52.12% # Class of committed instruction 662system.cpu.commit.op_class_0::SimdAdd 0 0.00% 52.12% # Class of committed instruction 663system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 52.12% # Class of committed instruction 664system.cpu.commit.op_class_0::SimdAlu 0 0.00% 52.12% # Class of committed instruction 665system.cpu.commit.op_class_0::SimdCmp 0 0.00% 52.12% # Class of committed instruction 666system.cpu.commit.op_class_0::SimdCvt 0 0.00% 52.12% # Class of committed instruction 667system.cpu.commit.op_class_0::SimdMisc 0 0.00% 52.12% # Class of committed instruction 668system.cpu.commit.op_class_0::SimdMult 0 0.00% 52.12% # Class of committed instruction 669system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 52.12% # Class of committed instruction 670system.cpu.commit.op_class_0::SimdShift 0 0.00% 52.12% # Class of committed instruction 671system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 52.12% # Class of committed instruction 672system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 52.12% # Class of committed instruction 673system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 52.12% # Class of committed instruction 674system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 52.12% # Class of committed instruction 675system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 52.12% # Class of committed instruction 676system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 52.12% # Class of committed instruction 677system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 52.12% # Class of committed instruction 678system.cpu.commit.op_class_0::SimdFloatMisc 7 0.00% 52.12% # Class of committed instruction 679system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 52.12% # Class of committed instruction 680system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 52.12% # Class of committed instruction 681system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 52.12% # Class of committed instruction 682system.cpu.commit.op_class_0::MemRead 22866262 25.21% 77.33% # Class of committed instruction 683system.cpu.commit.op_class_0::MemWrite 20555738 22.67% 100.00% # Class of committed instruction 684system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 685system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 686system.cpu.commit.op_class_0::total 90688137 # Class of committed instruction 687system.cpu.commit.bw_lim_events 3770757 # number cycles where commit BW limit reached 688system.cpu.rob.rob_reads 158202644 # The number of ROB reads 689system.cpu.rob.rob_writes 195513856 # The number of ROB writes 690system.cpu.timesIdled 23729 # Number of times that the entire CPU went into an idle state and unscheduled itself 691system.cpu.idleCycles 835509 # Total number of cycles that the CPU has spent unscheduled due to idling 692system.cpu.committedInsts 70907630 # Number of Instructions Simulated 693system.cpu.committedOps 90682585 # Number of Ops (including micro ops) Simulated 694system.cpu.cpi 0.940183 # CPI: Cycles Per Instruction 695system.cpu.cpi_total 0.940183 # CPI: Total CPI of All Threads 696system.cpu.ipc 1.063623 # IPC: Instructions Per Cycle 697system.cpu.ipc_total 1.063623 # IPC: Total IPC of All Threads 698system.cpu.int_regfile_reads 102275291 # number of integer regfile reads 699system.cpu.int_regfile_writes 56793629 # number of integer regfile writes 700system.cpu.fp_regfile_reads 36 # number of floating regfile reads 701system.cpu.fp_regfile_writes 21 # number of floating regfile writes 702system.cpu.cc_regfile_reads 346102642 # number of cc regfile reads 703system.cpu.cc_regfile_writes 38804681 # number of cc regfile writes 704system.cpu.misc_regfile_reads 44209969 # number of misc regfile reads 705system.cpu.misc_regfile_writes 31840 # number of misc regfile writes 706system.cpu.dcache.tags.replacements 485047 # number of replacements 707system.cpu.dcache.tags.tagsinuse 510.741433 # Cycle average of tags in use 708system.cpu.dcache.tags.total_refs 40420740 # Total number of references to valid blocks. 709system.cpu.dcache.tags.sampled_refs 485559 # Sample count of references to valid blocks. 710system.cpu.dcache.tags.avg_refs 83.245785 # Average number of references to valid blocks. 711system.cpu.dcache.tags.warmup_cycle 153056500 # Cycle when the warmup percentage was hit. 712system.cpu.dcache.tags.occ_blocks::cpu.data 510.741433 # Average occupied blocks per requestor 713system.cpu.dcache.tags.occ_percent::cpu.data 0.997542 # Average percentage of cache occupancy 714system.cpu.dcache.tags.occ_percent::total 0.997542 # Average percentage of cache occupancy 715system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 716system.cpu.dcache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id 717system.cpu.dcache.tags.age_task_id_blocks_1024::1 454 # Occupied blocks per task id 718system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 719system.cpu.dcache.tags.tag_accesses 84615723 # Number of tag accesses 720system.cpu.dcache.tags.data_accesses 84615723 # Number of data accesses 721system.cpu.dcache.ReadReq_hits::cpu.data 21498446 # number of ReadReq hits 722system.cpu.dcache.ReadReq_hits::total 21498446 # number of ReadReq hits 723system.cpu.dcache.WriteReq_hits::cpu.data 18830779 # number of WriteReq hits 724system.cpu.dcache.WriteReq_hits::total 18830779 # number of WriteReq hits 725system.cpu.dcache.SoftPFReq_hits::cpu.data 60221 # number of SoftPFReq hits 726system.cpu.dcache.SoftPFReq_hits::total 60221 # number of SoftPFReq hits 727system.cpu.dcache.LoadLockedReq_hits::cpu.data 15346 # number of LoadLockedReq hits 728system.cpu.dcache.LoadLockedReq_hits::total 15346 # number of LoadLockedReq hits 729system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits 730system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits 731system.cpu.dcache.demand_hits::cpu.data 40329225 # number of demand (read+write) hits 732system.cpu.dcache.demand_hits::total 40329225 # number of demand (read+write) hits 733system.cpu.dcache.overall_hits::cpu.data 40389446 # number of overall hits 734system.cpu.dcache.overall_hits::total 40389446 # number of overall hits 735system.cpu.dcache.ReadReq_misses::cpu.data 556041 # number of ReadReq misses 736system.cpu.dcache.ReadReq_misses::total 556041 # number of ReadReq misses 737system.cpu.dcache.WriteReq_misses::cpu.data 1019122 # number of WriteReq misses 738system.cpu.dcache.WriteReq_misses::total 1019122 # number of WriteReq misses 739system.cpu.dcache.SoftPFReq_misses::cpu.data 68628 # number of SoftPFReq misses 740system.cpu.dcache.SoftPFReq_misses::total 68628 # number of SoftPFReq misses 741system.cpu.dcache.LoadLockedReq_misses::cpu.data 580 # number of LoadLockedReq misses 742system.cpu.dcache.LoadLockedReq_misses::total 580 # number of LoadLockedReq misses 743system.cpu.dcache.demand_misses::cpu.data 1575163 # number of demand (read+write) misses 744system.cpu.dcache.demand_misses::total 1575163 # number of demand (read+write) misses 745system.cpu.dcache.overall_misses::cpu.data 1643791 # number of overall misses 746system.cpu.dcache.overall_misses::total 1643791 # number of overall misses 747system.cpu.dcache.ReadReq_miss_latency::cpu.data 8960046000 # number of ReadReq miss cycles 748system.cpu.dcache.ReadReq_miss_latency::total 8960046000 # number of ReadReq miss cycles 749system.cpu.dcache.WriteReq_miss_latency::cpu.data 14598887903 # number of WriteReq miss cycles 750system.cpu.dcache.WriteReq_miss_latency::total 14598887903 # number of WriteReq miss cycles 751system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 5237000 # number of LoadLockedReq miss cycles 752system.cpu.dcache.LoadLockedReq_miss_latency::total 5237000 # number of LoadLockedReq miss cycles 753system.cpu.dcache.demand_miss_latency::cpu.data 23558933903 # number of demand (read+write) miss cycles 754system.cpu.dcache.demand_miss_latency::total 23558933903 # number of demand (read+write) miss cycles 755system.cpu.dcache.overall_miss_latency::cpu.data 23558933903 # number of overall miss cycles 756system.cpu.dcache.overall_miss_latency::total 23558933903 # number of overall miss cycles 757system.cpu.dcache.ReadReq_accesses::cpu.data 22054487 # number of ReadReq accesses(hits+misses) 758system.cpu.dcache.ReadReq_accesses::total 22054487 # number of ReadReq accesses(hits+misses) 759system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) 760system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) 761system.cpu.dcache.SoftPFReq_accesses::cpu.data 128849 # number of SoftPFReq accesses(hits+misses) 762system.cpu.dcache.SoftPFReq_accesses::total 128849 # number of SoftPFReq accesses(hits+misses) 763system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15926 # number of LoadLockedReq accesses(hits+misses) 764system.cpu.dcache.LoadLockedReq_accesses::total 15926 # number of LoadLockedReq accesses(hits+misses) 765system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) 766system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) 767system.cpu.dcache.demand_accesses::cpu.data 41904388 # number of demand (read+write) accesses 768system.cpu.dcache.demand_accesses::total 41904388 # number of demand (read+write) accesses 769system.cpu.dcache.overall_accesses::cpu.data 42033237 # number of overall (read+write) accesses 770system.cpu.dcache.overall_accesses::total 42033237 # number of overall (read+write) accesses 771system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.025212 # miss rate for ReadReq accesses 772system.cpu.dcache.ReadReq_miss_rate::total 0.025212 # miss rate for ReadReq accesses 773system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.051341 # miss rate for WriteReq accesses 774system.cpu.dcache.WriteReq_miss_rate::total 0.051341 # miss rate for WriteReq accesses 775system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.532623 # miss rate for SoftPFReq accesses 776system.cpu.dcache.SoftPFReq_miss_rate::total 0.532623 # miss rate for SoftPFReq accesses 777system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.036418 # miss rate for LoadLockedReq accesses 778system.cpu.dcache.LoadLockedReq_miss_rate::total 0.036418 # miss rate for LoadLockedReq accesses 779system.cpu.dcache.demand_miss_rate::cpu.data 0.037589 # miss rate for demand accesses 780system.cpu.dcache.demand_miss_rate::total 0.037589 # miss rate for demand accesses 781system.cpu.dcache.overall_miss_rate::cpu.data 0.039107 # miss rate for overall accesses 782system.cpu.dcache.overall_miss_rate::total 0.039107 # miss rate for overall accesses 783system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16114.002385 # average ReadReq miss latency 784system.cpu.dcache.ReadReq_avg_miss_latency::total 16114.002385 # average ReadReq miss latency 785system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 14324.965905 # average WriteReq miss latency 786system.cpu.dcache.WriteReq_avg_miss_latency::total 14324.965905 # average WriteReq miss latency 787system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 9029.310345 # average LoadLockedReq miss latency 788system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 9029.310345 # average LoadLockedReq miss latency 789system.cpu.dcache.demand_avg_miss_latency::cpu.data 14956.505392 # average overall miss latency 790system.cpu.dcache.demand_avg_miss_latency::total 14956.505392 # average overall miss latency 791system.cpu.dcache.overall_avg_miss_latency::cpu.data 14332.073787 # average overall miss latency 792system.cpu.dcache.overall_avg_miss_latency::total 14332.073787 # average overall miss latency 793system.cpu.dcache.blocked_cycles::no_mshrs 55 # number of cycles access was blocked 794system.cpu.dcache.blocked_cycles::no_targets 3099418 # number of cycles access was blocked 795system.cpu.dcache.blocked::no_mshrs 6 # number of cycles access was blocked 796system.cpu.dcache.blocked::no_targets 130265 # number of cycles access was blocked 797system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.166667 # average number of cycles each access was blocked 798system.cpu.dcache.avg_blocked_cycles::no_targets 23.793175 # average number of cycles each access was blocked 799system.cpu.dcache.fast_writes 0 # number of fast writes performed 800system.cpu.dcache.cache_copies 0 # number of cache copies performed 801system.cpu.dcache.writebacks::writebacks 261117 # number of writebacks 802system.cpu.dcache.writebacks::total 261117 # number of writebacks 803system.cpu.dcache.ReadReq_mshr_hits::cpu.data 256598 # number of ReadReq MSHR hits 804system.cpu.dcache.ReadReq_mshr_hits::total 256598 # number of ReadReq MSHR hits 805system.cpu.dcache.WriteReq_mshr_hits::cpu.data 870592 # number of WriteReq MSHR hits 806system.cpu.dcache.WriteReq_mshr_hits::total 870592 # number of WriteReq MSHR hits 807system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 580 # number of LoadLockedReq MSHR hits 808system.cpu.dcache.LoadLockedReq_mshr_hits::total 580 # number of LoadLockedReq MSHR hits 809system.cpu.dcache.demand_mshr_hits::cpu.data 1127190 # number of demand (read+write) MSHR hits 810system.cpu.dcache.demand_mshr_hits::total 1127190 # number of demand (read+write) MSHR hits 811system.cpu.dcache.overall_mshr_hits::cpu.data 1127190 # number of overall MSHR hits 812system.cpu.dcache.overall_mshr_hits::total 1127190 # number of overall MSHR hits 813system.cpu.dcache.ReadReq_mshr_misses::cpu.data 299443 # number of ReadReq MSHR misses 814system.cpu.dcache.ReadReq_mshr_misses::total 299443 # number of ReadReq MSHR misses 815system.cpu.dcache.WriteReq_mshr_misses::cpu.data 148530 # number of WriteReq MSHR misses 816system.cpu.dcache.WriteReq_mshr_misses::total 148530 # number of WriteReq MSHR misses 817system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 37597 # number of SoftPFReq MSHR misses 818system.cpu.dcache.SoftPFReq_mshr_misses::total 37597 # number of SoftPFReq MSHR misses 819system.cpu.dcache.demand_mshr_misses::cpu.data 447973 # number of demand (read+write) MSHR misses 820system.cpu.dcache.demand_mshr_misses::total 447973 # number of demand (read+write) MSHR misses 821system.cpu.dcache.overall_mshr_misses::cpu.data 485570 # number of overall MSHR misses 822system.cpu.dcache.overall_mshr_misses::total 485570 # number of overall MSHR misses 823system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3193306500 # number of ReadReq MSHR miss cycles 824system.cpu.dcache.ReadReq_mshr_miss_latency::total 3193306500 # number of ReadReq MSHR miss cycles 825system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2352659965 # number of WriteReq MSHR miss cycles 826system.cpu.dcache.WriteReq_mshr_miss_latency::total 2352659965 # number of WriteReq MSHR miss cycles 827system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 2013580000 # number of SoftPFReq MSHR miss cycles 828system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 2013580000 # number of SoftPFReq MSHR miss cycles 829system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5545966465 # number of demand (read+write) MSHR miss cycles 830system.cpu.dcache.demand_mshr_miss_latency::total 5545966465 # number of demand (read+write) MSHR miss cycles 831system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7559546465 # number of overall MSHR miss cycles 832system.cpu.dcache.overall_mshr_miss_latency::total 7559546465 # number of overall MSHR miss cycles 833system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013577 # mshr miss rate for ReadReq accesses 834system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013577 # mshr miss rate for ReadReq accesses 835system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.007483 # mshr miss rate for WriteReq accesses 836system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.007483 # mshr miss rate for WriteReq accesses 837system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.291791 # mshr miss rate for SoftPFReq accesses 838system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.291791 # mshr miss rate for SoftPFReq accesses 839system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.010690 # mshr miss rate for demand accesses 840system.cpu.dcache.demand_mshr_miss_rate::total 0.010690 # mshr miss rate for demand accesses 841system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.011552 # mshr miss rate for overall accesses 842system.cpu.dcache.overall_mshr_miss_rate::total 0.011552 # mshr miss rate for overall accesses 843system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 10664.154781 # average ReadReq mshr miss latency 844system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 10664.154781 # average ReadReq mshr miss latency 845system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 15839.628122 # average WriteReq mshr miss latency 846system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 15839.628122 # average WriteReq mshr miss latency 847system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53556.932734 # average SoftPFReq mshr miss latency 848system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53556.932734 # average SoftPFReq mshr miss latency 849system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12380.135555 # average overall mshr miss latency 850system.cpu.dcache.demand_avg_mshr_miss_latency::total 12380.135555 # average overall mshr miss latency 851system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15568.396863 # average overall mshr miss latency 852system.cpu.dcache.overall_avg_mshr_miss_latency::total 15568.396863 # average overall mshr miss latency 853system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 854system.cpu.icache.tags.replacements 322838 # number of replacements 855system.cpu.icache.tags.tagsinuse 510.295109 # Cycle average of tags in use 856system.cpu.icache.tags.total_refs 22432857 # Total number of references to valid blocks. 857system.cpu.icache.tags.sampled_refs 323350 # Sample count of references to valid blocks. 858system.cpu.icache.tags.avg_refs 69.376394 # Average number of references to valid blocks. 859system.cpu.icache.tags.warmup_cycle 1105263500 # Cycle when the warmup percentage was hit. 860system.cpu.icache.tags.occ_blocks::cpu.inst 510.295109 # Average occupied blocks per requestor 861system.cpu.icache.tags.occ_percent::cpu.inst 0.996670 # Average percentage of cache occupancy 862system.cpu.icache.tags.occ_percent::total 0.996670 # Average percentage of cache occupancy 863system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 864system.cpu.icache.tags.age_task_id_blocks_1024::0 89 # Occupied blocks per task id 865system.cpu.icache.tags.age_task_id_blocks_1024::1 57 # Occupied blocks per task id 866system.cpu.icache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id 867system.cpu.icache.tags.age_task_id_blocks_1024::3 353 # Occupied blocks per task id 868system.cpu.icache.tags.age_task_id_blocks_1024::4 7 # Occupied blocks per task id 869system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 870system.cpu.icache.tags.tag_accesses 45857337 # Number of tag accesses 871system.cpu.icache.tags.data_accesses 45857337 # Number of data accesses 872system.cpu.icache.ReadReq_hits::cpu.inst 22432857 # number of ReadReq hits 873system.cpu.icache.ReadReq_hits::total 22432857 # number of ReadReq hits 874system.cpu.icache.demand_hits::cpu.inst 22432857 # number of demand (read+write) hits 875system.cpu.icache.demand_hits::total 22432857 # number of demand (read+write) hits 876system.cpu.icache.overall_hits::cpu.inst 22432857 # number of overall hits 877system.cpu.icache.overall_hits::total 22432857 # number of overall hits 878system.cpu.icache.ReadReq_misses::cpu.inst 334131 # number of ReadReq misses 879system.cpu.icache.ReadReq_misses::total 334131 # number of ReadReq misses 880system.cpu.icache.demand_misses::cpu.inst 334131 # number of demand (read+write) misses 881system.cpu.icache.demand_misses::total 334131 # number of demand (read+write) misses 882system.cpu.icache.overall_misses::cpu.inst 334131 # number of overall misses 883system.cpu.icache.overall_misses::total 334131 # number of overall misses 884system.cpu.icache.ReadReq_miss_latency::cpu.inst 3372669901 # number of ReadReq miss cycles 885system.cpu.icache.ReadReq_miss_latency::total 3372669901 # number of ReadReq miss cycles 886system.cpu.icache.demand_miss_latency::cpu.inst 3372669901 # number of demand (read+write) miss cycles 887system.cpu.icache.demand_miss_latency::total 3372669901 # number of demand (read+write) miss cycles 888system.cpu.icache.overall_miss_latency::cpu.inst 3372669901 # number of overall miss cycles 889system.cpu.icache.overall_miss_latency::total 3372669901 # number of overall miss cycles 890system.cpu.icache.ReadReq_accesses::cpu.inst 22766988 # number of ReadReq accesses(hits+misses) 891system.cpu.icache.ReadReq_accesses::total 22766988 # number of ReadReq accesses(hits+misses) 892system.cpu.icache.demand_accesses::cpu.inst 22766988 # number of demand (read+write) accesses 893system.cpu.icache.demand_accesses::total 22766988 # number of demand (read+write) accesses 894system.cpu.icache.overall_accesses::cpu.inst 22766988 # number of overall (read+write) accesses 895system.cpu.icache.overall_accesses::total 22766988 # number of overall (read+write) accesses 896system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014676 # miss rate for ReadReq accesses 897system.cpu.icache.ReadReq_miss_rate::total 0.014676 # miss rate for ReadReq accesses 898system.cpu.icache.demand_miss_rate::cpu.inst 0.014676 # miss rate for demand accesses 899system.cpu.icache.demand_miss_rate::total 0.014676 # miss rate for demand accesses 900system.cpu.icache.overall_miss_rate::cpu.inst 0.014676 # miss rate for overall accesses 901system.cpu.icache.overall_miss_rate::total 0.014676 # miss rate for overall accesses 902system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 10093.855108 # average ReadReq miss latency 903system.cpu.icache.ReadReq_avg_miss_latency::total 10093.855108 # average ReadReq miss latency 904system.cpu.icache.demand_avg_miss_latency::cpu.inst 10093.855108 # average overall miss latency 905system.cpu.icache.demand_avg_miss_latency::total 10093.855108 # average overall miss latency 906system.cpu.icache.overall_avg_miss_latency::cpu.inst 10093.855108 # average overall miss latency 907system.cpu.icache.overall_avg_miss_latency::total 10093.855108 # average overall miss latency 908system.cpu.icache.blocked_cycles::no_mshrs 274760 # number of cycles access was blocked 909system.cpu.icache.blocked_cycles::no_targets 147 # number of cycles access was blocked 910system.cpu.icache.blocked::no_mshrs 16673 # number of cycles access was blocked 911system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked 912system.cpu.icache.avg_blocked_cycles::no_mshrs 16.479338 # average number of cycles each access was blocked 913system.cpu.icache.avg_blocked_cycles::no_targets 49 # average number of cycles each access was blocked 914system.cpu.icache.fast_writes 0 # number of fast writes performed 915system.cpu.icache.cache_copies 0 # number of cache copies performed 916system.cpu.icache.ReadReq_mshr_hits::cpu.inst 10770 # number of ReadReq MSHR hits 917system.cpu.icache.ReadReq_mshr_hits::total 10770 # number of ReadReq MSHR hits 918system.cpu.icache.demand_mshr_hits::cpu.inst 10770 # number of demand (read+write) MSHR hits 919system.cpu.icache.demand_mshr_hits::total 10770 # number of demand (read+write) MSHR hits 920system.cpu.icache.overall_mshr_hits::cpu.inst 10770 # number of overall MSHR hits 921system.cpu.icache.overall_mshr_hits::total 10770 # number of overall MSHR hits 922system.cpu.icache.ReadReq_mshr_misses::cpu.inst 323361 # number of ReadReq MSHR misses 923system.cpu.icache.ReadReq_mshr_misses::total 323361 # number of ReadReq MSHR misses 924system.cpu.icache.demand_mshr_misses::cpu.inst 323361 # number of demand (read+write) MSHR misses 925system.cpu.icache.demand_mshr_misses::total 323361 # number of demand (read+write) MSHR misses 926system.cpu.icache.overall_mshr_misses::cpu.inst 323361 # number of overall MSHR misses 927system.cpu.icache.overall_mshr_misses::total 323361 # number of overall MSHR misses 928system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 3089767447 # number of ReadReq MSHR miss cycles 929system.cpu.icache.ReadReq_mshr_miss_latency::total 3089767447 # number of ReadReq MSHR miss cycles 930system.cpu.icache.demand_mshr_miss_latency::cpu.inst 3089767447 # number of demand (read+write) MSHR miss cycles 931system.cpu.icache.demand_mshr_miss_latency::total 3089767447 # number of demand (read+write) MSHR miss cycles 932system.cpu.icache.overall_mshr_miss_latency::cpu.inst 3089767447 # number of overall MSHR miss cycles 933system.cpu.icache.overall_mshr_miss_latency::total 3089767447 # number of overall MSHR miss cycles 934system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014203 # mshr miss rate for ReadReq accesses 935system.cpu.icache.ReadReq_mshr_miss_rate::total 0.014203 # mshr miss rate for ReadReq accesses 936system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014203 # mshr miss rate for demand accesses 937system.cpu.icache.demand_mshr_miss_rate::total 0.014203 # mshr miss rate for demand accesses 938system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014203 # mshr miss rate for overall accesses 939system.cpu.icache.overall_mshr_miss_rate::total 0.014203 # mshr miss rate for overall accesses 940system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 9555.164188 # average ReadReq mshr miss latency 941system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 9555.164188 # average ReadReq mshr miss latency 942system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 9555.164188 # average overall mshr miss latency 943system.cpu.icache.demand_avg_mshr_miss_latency::total 9555.164188 # average overall mshr miss latency 944system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 9555.164188 # average overall mshr miss latency 945system.cpu.icache.overall_avg_mshr_miss_latency::total 9555.164188 # average overall mshr miss latency 946system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 947system.cpu.l2cache.prefetcher.num_hwpf_issued 824514 # number of hwpf issued 948system.cpu.l2cache.prefetcher.pfIdentified 825954 # number of prefetch candidates identified 949system.cpu.l2cache.prefetcher.pfBufferHit 1262 # number of redundant prefetches already in prefetch queue 950system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 951system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 952system.cpu.l2cache.prefetcher.pfSpanPage 78678 # number of prefetches not generated due to page crossing 953system.cpu.l2cache.tags.replacements 129552 # number of replacements 954system.cpu.l2cache.tags.tagsinuse 16077.997606 # Cycle average of tags in use 955system.cpu.l2cache.tags.total_refs 1332384 # Total number of references to valid blocks. 956system.cpu.l2cache.tags.sampled_refs 145834 # Sample count of references to valid blocks. 957system.cpu.l2cache.tags.avg_refs 9.136306 # Average number of references to valid blocks. 958system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 959system.cpu.l2cache.tags.occ_blocks::writebacks 12589.252408 # Average occupied blocks per requestor 960system.cpu.l2cache.tags.occ_blocks::cpu.inst 1431.737238 # Average occupied blocks per requestor 961system.cpu.l2cache.tags.occ_blocks::cpu.data 1938.355630 # Average occupied blocks per requestor 962system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 118.652331 # Average occupied blocks per requestor 963system.cpu.l2cache.tags.occ_percent::writebacks 0.768387 # Average percentage of cache occupancy 964system.cpu.l2cache.tags.occ_percent::cpu.inst 0.087386 # Average percentage of cache occupancy 965system.cpu.l2cache.tags.occ_percent::cpu.data 0.118308 # Average percentage of cache occupancy 966system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.007242 # Average percentage of cache occupancy 967system.cpu.l2cache.tags.occ_percent::total 0.981323 # Average percentage of cache occupancy 968system.cpu.l2cache.tags.occ_task_id_blocks::1022 37 # Occupied blocks per task id 969system.cpu.l2cache.tags.occ_task_id_blocks::1024 16245 # Occupied blocks per task id 970system.cpu.l2cache.tags.age_task_id_blocks_1022::1 8 # Occupied blocks per task id 971system.cpu.l2cache.tags.age_task_id_blocks_1022::2 3 # Occupied blocks per task id 972system.cpu.l2cache.tags.age_task_id_blocks_1022::3 22 # Occupied blocks per task id 973system.cpu.l2cache.tags.age_task_id_blocks_1022::4 4 # Occupied blocks per task id 974system.cpu.l2cache.tags.age_task_id_blocks_1024::0 155 # Occupied blocks per task id 975system.cpu.l2cache.tags.age_task_id_blocks_1024::1 2643 # Occupied blocks per task id 976system.cpu.l2cache.tags.age_task_id_blocks_1024::2 12025 # Occupied blocks per task id 977system.cpu.l2cache.tags.age_task_id_blocks_1024::3 539 # Occupied blocks per task id 978system.cpu.l2cache.tags.age_task_id_blocks_1024::4 883 # Occupied blocks per task id 979system.cpu.l2cache.tags.occ_task_id_percent::1022 0.002258 # Percentage of cache occupancy per task id 980system.cpu.l2cache.tags.occ_task_id_percent::1024 0.991516 # Percentage of cache occupancy per task id 981system.cpu.l2cache.tags.tag_accesses 24885703 # Number of tag accesses 982system.cpu.l2cache.tags.data_accesses 24885703 # Number of data accesses 983system.cpu.l2cache.Writeback_hits::writebacks 261117 # number of Writeback hits 984system.cpu.l2cache.Writeback_hits::total 261117 # number of Writeback hits 985system.cpu.l2cache.UpgradeReq_hits::cpu.data 5 # number of UpgradeReq hits 986system.cpu.l2cache.UpgradeReq_hits::total 5 # number of UpgradeReq hits 987system.cpu.l2cache.ReadExReq_hits::cpu.data 137140 # number of ReadExReq hits 988system.cpu.l2cache.ReadExReq_hits::total 137140 # number of ReadExReq hits 989system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 314068 # number of ReadCleanReq hits 990system.cpu.l2cache.ReadCleanReq_hits::total 314068 # number of ReadCleanReq hits 991system.cpu.l2cache.ReadSharedReq_hits::cpu.data 305844 # number of ReadSharedReq hits 992system.cpu.l2cache.ReadSharedReq_hits::total 305844 # number of ReadSharedReq hits 993system.cpu.l2cache.demand_hits::cpu.inst 314068 # number of demand (read+write) hits 994system.cpu.l2cache.demand_hits::cpu.data 442984 # number of demand (read+write) hits 995system.cpu.l2cache.demand_hits::total 757052 # number of demand (read+write) hits 996system.cpu.l2cache.overall_hits::cpu.inst 314068 # number of overall hits 997system.cpu.l2cache.overall_hits::cpu.data 442984 # number of overall hits 998system.cpu.l2cache.overall_hits::total 757052 # number of overall hits 999system.cpu.l2cache.UpgradeReq_misses::cpu.data 6 # number of UpgradeReq misses 1000system.cpu.l2cache.UpgradeReq_misses::total 6 # number of UpgradeReq misses 1001system.cpu.l2cache.ReadExReq_misses::cpu.data 11428 # number of ReadExReq misses 1002system.cpu.l2cache.ReadExReq_misses::total 11428 # number of ReadExReq misses 1003system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 9278 # number of ReadCleanReq misses 1004system.cpu.l2cache.ReadCleanReq_misses::total 9278 # number of ReadCleanReq misses 1005system.cpu.l2cache.ReadSharedReq_misses::cpu.data 31147 # number of ReadSharedReq misses 1006system.cpu.l2cache.ReadSharedReq_misses::total 31147 # number of ReadSharedReq misses 1007system.cpu.l2cache.demand_misses::cpu.inst 9278 # number of demand (read+write) misses 1008system.cpu.l2cache.demand_misses::cpu.data 42575 # number of demand (read+write) misses 1009system.cpu.l2cache.demand_misses::total 51853 # number of demand (read+write) misses 1010system.cpu.l2cache.overall_misses::cpu.inst 9278 # number of overall misses 1011system.cpu.l2cache.overall_misses::cpu.data 42575 # number of overall misses 1012system.cpu.l2cache.overall_misses::total 51853 # number of overall misses 1013system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1235483500 # number of ReadExReq miss cycles 1014system.cpu.l2cache.ReadExReq_miss_latency::total 1235483500 # number of ReadExReq miss cycles 1015system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 721965000 # number of ReadCleanReq miss cycles 1016system.cpu.l2cache.ReadCleanReq_miss_latency::total 721965000 # number of ReadCleanReq miss cycles 1017system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 2691191000 # number of ReadSharedReq miss cycles 1018system.cpu.l2cache.ReadSharedReq_miss_latency::total 2691191000 # number of ReadSharedReq miss cycles 1019system.cpu.l2cache.demand_miss_latency::cpu.inst 721965000 # number of demand (read+write) miss cycles 1020system.cpu.l2cache.demand_miss_latency::cpu.data 3926674500 # number of demand (read+write) miss cycles 1021system.cpu.l2cache.demand_miss_latency::total 4648639500 # number of demand (read+write) miss cycles 1022system.cpu.l2cache.overall_miss_latency::cpu.inst 721965000 # number of overall miss cycles 1023system.cpu.l2cache.overall_miss_latency::cpu.data 3926674500 # number of overall miss cycles 1024system.cpu.l2cache.overall_miss_latency::total 4648639500 # number of overall miss cycles 1025system.cpu.l2cache.Writeback_accesses::writebacks 261117 # number of Writeback accesses(hits+misses) 1026system.cpu.l2cache.Writeback_accesses::total 261117 # number of Writeback accesses(hits+misses) 1027system.cpu.l2cache.UpgradeReq_accesses::cpu.data 11 # number of UpgradeReq accesses(hits+misses) 1028system.cpu.l2cache.UpgradeReq_accesses::total 11 # number of UpgradeReq accesses(hits+misses) 1029system.cpu.l2cache.ReadExReq_accesses::cpu.data 148568 # number of ReadExReq accesses(hits+misses) 1030system.cpu.l2cache.ReadExReq_accesses::total 148568 # number of ReadExReq accesses(hits+misses) 1031system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 323346 # number of ReadCleanReq accesses(hits+misses) 1032system.cpu.l2cache.ReadCleanReq_accesses::total 323346 # number of ReadCleanReq accesses(hits+misses) 1033system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 336991 # number of ReadSharedReq accesses(hits+misses) 1034system.cpu.l2cache.ReadSharedReq_accesses::total 336991 # number of ReadSharedReq accesses(hits+misses) 1035system.cpu.l2cache.demand_accesses::cpu.inst 323346 # number of demand (read+write) accesses 1036system.cpu.l2cache.demand_accesses::cpu.data 485559 # number of demand (read+write) accesses 1037system.cpu.l2cache.demand_accesses::total 808905 # number of demand (read+write) accesses 1038system.cpu.l2cache.overall_accesses::cpu.inst 323346 # number of overall (read+write) accesses 1039system.cpu.l2cache.overall_accesses::cpu.data 485559 # number of overall (read+write) accesses 1040system.cpu.l2cache.overall_accesses::total 808905 # number of overall (read+write) accesses 1041system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.545455 # miss rate for UpgradeReq accesses 1042system.cpu.l2cache.UpgradeReq_miss_rate::total 0.545455 # miss rate for UpgradeReq accesses 1043system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.076921 # miss rate for ReadExReq accesses 1044system.cpu.l2cache.ReadExReq_miss_rate::total 0.076921 # miss rate for ReadExReq accesses 1045system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.028694 # miss rate for ReadCleanReq accesses 1046system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.028694 # miss rate for ReadCleanReq accesses 1047system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.092427 # miss rate for ReadSharedReq accesses 1048system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.092427 # miss rate for ReadSharedReq accesses 1049system.cpu.l2cache.demand_miss_rate::cpu.inst 0.028694 # miss rate for demand accesses 1050system.cpu.l2cache.demand_miss_rate::cpu.data 0.087682 # miss rate for demand accesses 1051system.cpu.l2cache.demand_miss_rate::total 0.064103 # miss rate for demand accesses 1052system.cpu.l2cache.overall_miss_rate::cpu.inst 0.028694 # miss rate for overall accesses 1053system.cpu.l2cache.overall_miss_rate::cpu.data 0.087682 # miss rate for overall accesses 1054system.cpu.l2cache.overall_miss_rate::total 0.064103 # miss rate for overall accesses 1055system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 108110.211761 # average ReadExReq miss latency 1056system.cpu.l2cache.ReadExReq_avg_miss_latency::total 108110.211761 # average ReadExReq miss latency 1057system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 77814.723001 # average ReadCleanReq miss latency 1058system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 77814.723001 # average ReadCleanReq miss latency 1059system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 86402.895945 # average ReadSharedReq miss latency 1060system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 86402.895945 # average ReadSharedReq miss latency 1061system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77814.723001 # average overall miss latency 1062system.cpu.l2cache.demand_avg_miss_latency::cpu.data 92229.583089 # average overall miss latency 1063system.cpu.l2cache.demand_avg_miss_latency::total 89650.348099 # average overall miss latency 1064system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77814.723001 # average overall miss latency 1065system.cpu.l2cache.overall_avg_miss_latency::cpu.data 92229.583089 # average overall miss latency 1066system.cpu.l2cache.overall_avg_miss_latency::total 89650.348099 # average overall miss latency 1067system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1068system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1069system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1070system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1071system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1072system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1073system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1074system.cpu.l2cache.cache_copies 0 # number of cache copies performed 1075system.cpu.l2cache.writebacks::writebacks 97878 # number of writebacks 1076system.cpu.l2cache.writebacks::total 97878 # number of writebacks 1077system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 3042 # number of ReadExReq MSHR hits 1078system.cpu.l2cache.ReadExReq_mshr_hits::total 3042 # number of ReadExReq MSHR hits 1079system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 38 # number of ReadCleanReq MSHR hits 1080system.cpu.l2cache.ReadCleanReq_mshr_hits::total 38 # number of ReadCleanReq MSHR hits 1081system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 139 # number of ReadSharedReq MSHR hits 1082system.cpu.l2cache.ReadSharedReq_mshr_hits::total 139 # number of ReadSharedReq MSHR hits 1083system.cpu.l2cache.demand_mshr_hits::cpu.inst 38 # number of demand (read+write) MSHR hits 1084system.cpu.l2cache.demand_mshr_hits::cpu.data 3181 # number of demand (read+write) MSHR hits 1085system.cpu.l2cache.demand_mshr_hits::total 3219 # number of demand (read+write) MSHR hits 1086system.cpu.l2cache.overall_mshr_hits::cpu.inst 38 # number of overall MSHR hits 1087system.cpu.l2cache.overall_mshr_hits::cpu.data 3181 # number of overall MSHR hits 1088system.cpu.l2cache.overall_mshr_hits::total 3219 # number of overall MSHR hits 1089system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 3552 # number of CleanEvict MSHR misses 1090system.cpu.l2cache.CleanEvict_mshr_misses::total 3552 # number of CleanEvict MSHR misses 1091system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 112510 # number of HardPFReq MSHR misses 1092system.cpu.l2cache.HardPFReq_mshr_misses::total 112510 # number of HardPFReq MSHR misses 1093system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 6 # number of UpgradeReq MSHR misses 1094system.cpu.l2cache.UpgradeReq_mshr_misses::total 6 # number of UpgradeReq MSHR misses 1095system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 8386 # number of ReadExReq MSHR misses 1096system.cpu.l2cache.ReadExReq_mshr_misses::total 8386 # number of ReadExReq MSHR misses 1097system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 9240 # number of ReadCleanReq MSHR misses 1098system.cpu.l2cache.ReadCleanReq_mshr_misses::total 9240 # number of ReadCleanReq MSHR misses 1099system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 31008 # number of ReadSharedReq MSHR misses 1100system.cpu.l2cache.ReadSharedReq_mshr_misses::total 31008 # number of ReadSharedReq MSHR misses 1101system.cpu.l2cache.demand_mshr_misses::cpu.inst 9240 # number of demand (read+write) MSHR misses 1102system.cpu.l2cache.demand_mshr_misses::cpu.data 39394 # number of demand (read+write) MSHR misses 1103system.cpu.l2cache.demand_mshr_misses::total 48634 # number of demand (read+write) MSHR misses 1104system.cpu.l2cache.overall_mshr_misses::cpu.inst 9240 # number of overall MSHR misses 1105system.cpu.l2cache.overall_mshr_misses::cpu.data 39394 # number of overall MSHR misses 1106system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 112510 # number of overall MSHR misses 1107system.cpu.l2cache.overall_mshr_misses::total 161144 # number of overall MSHR misses 1108system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 10641572084 # number of HardPFReq MSHR miss cycles 1109system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 10641572084 # number of HardPFReq MSHR miss cycles 1110system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 100500 # number of UpgradeReq MSHR miss cycles 1111system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 100500 # number of UpgradeReq MSHR miss cycles 1112system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 677751000 # number of ReadExReq MSHR miss cycles 1113system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 677751000 # number of ReadExReq MSHR miss cycles 1114system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 663843000 # number of ReadCleanReq MSHR miss cycles 1115system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 663843000 # number of ReadCleanReq MSHR miss cycles 1116system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2494831000 # number of ReadSharedReq MSHR miss cycles 1117system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2494831000 # number of ReadSharedReq MSHR miss cycles 1118system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 663843000 # number of demand (read+write) MSHR miss cycles 1119system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3172582000 # number of demand (read+write) MSHR miss cycles 1120system.cpu.l2cache.demand_mshr_miss_latency::total 3836425000 # number of demand (read+write) MSHR miss cycles 1121system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 663843000 # number of overall MSHR miss cycles 1122system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3172582000 # number of overall MSHR miss cycles 1123system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 10641572084 # number of overall MSHR miss cycles 1124system.cpu.l2cache.overall_mshr_miss_latency::total 14477997084 # number of overall MSHR miss cycles 1125system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 1126system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 1127system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1128system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 1129system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.545455 # mshr miss rate for UpgradeReq accesses 1130system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.545455 # mshr miss rate for UpgradeReq accesses 1131system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.056446 # mshr miss rate for ReadExReq accesses 1132system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.056446 # mshr miss rate for ReadExReq accesses 1133system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.028576 # mshr miss rate for ReadCleanReq accesses 1134system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.028576 # mshr miss rate for ReadCleanReq accesses 1135system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.092014 # mshr miss rate for ReadSharedReq accesses 1136system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.092014 # mshr miss rate for ReadSharedReq accesses 1137system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.028576 # mshr miss rate for demand accesses 1138system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.081131 # mshr miss rate for demand accesses 1139system.cpu.l2cache.demand_mshr_miss_rate::total 0.060123 # mshr miss rate for demand accesses 1140system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.028576 # mshr miss rate for overall accesses 1141system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.081131 # mshr miss rate for overall accesses 1142system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses 1143system.cpu.l2cache.overall_mshr_miss_rate::total 0.199213 # mshr miss rate for overall accesses 1144system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 94583.344449 # average HardPFReq mshr miss latency 1145system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 94583.344449 # average HardPFReq mshr miss latency 1146system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 16750 # average UpgradeReq mshr miss latency 1147system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16750 # average UpgradeReq mshr miss latency 1148system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80819.341760 # average ReadExReq mshr miss latency 1149system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80819.341760 # average ReadExReq mshr miss latency 1150system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 71844.480519 # average ReadCleanReq mshr miss latency 1151system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 71844.480519 # average ReadCleanReq mshr miss latency 1152system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 80457.656089 # average ReadSharedReq mshr miss latency 1153system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 80457.656089 # average ReadSharedReq mshr miss latency 1154system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71844.480519 # average overall mshr miss latency 1155system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 80534.649947 # average overall mshr miss latency 1156system.cpu.l2cache.demand_avg_mshr_miss_latency::total 78883.599951 # average overall mshr miss latency 1157system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71844.480519 # average overall mshr miss latency 1158system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 80534.649947 # average overall mshr miss latency 1159system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 94583.344449 # average overall mshr miss latency 1160system.cpu.l2cache.overall_avg_mshr_miss_latency::total 89845.089386 # average overall mshr miss latency 1161system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1162system.cpu.toL2Bus.trans_dist::ReadResp 660352 # Transaction distribution 1163system.cpu.toL2Bus.trans_dist::Writeback 358995 # Transaction distribution 1164system.cpu.toL2Bus.trans_dist::CleanEvict 498597 # Transaction distribution 1165system.cpu.toL2Bus.trans_dist::HardPFReq 141207 # Transaction distribution 1166system.cpu.toL2Bus.trans_dist::UpgradeReq 11 # Transaction distribution 1167system.cpu.toL2Bus.trans_dist::UpgradeResp 11 # Transaction distribution 1168system.cpu.toL2Bus.trans_dist::ReadExReq 148568 # Transaction distribution 1169system.cpu.toL2Bus.trans_dist::ReadExResp 148568 # Transaction distribution 1170system.cpu.toL2Bus.trans_dist::ReadCleanReq 323361 # Transaction distribution 1171system.cpu.toL2Bus.trans_dist::ReadSharedReq 336991 # Transaction distribution 1172system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 938997 # Packet count per connected master and slave (bytes) 1173system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1406890 # Packet count per connected master and slave (bytes) 1174system.cpu.toL2Bus.pkt_count::total 2345887 # Packet count per connected master and slave (bytes) 1175system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20694144 # Cumulative packet size per connected master and slave (bytes) 1176system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 47787264 # Cumulative packet size per connected master and slave (bytes) 1177system.cpu.toL2Bus.pkt_size::total 68481408 # Cumulative packet size per connected master and slave (bytes) 1178system.cpu.toL2Bus.snoops 270774 # Total snoops (count) 1179system.cpu.toL2Bus.snoop_fanout::samples 1887575 # Request fanout histogram 1180system.cpu.toL2Bus.snoop_fanout::mean 1.143443 # Request fanout histogram 1181system.cpu.toL2Bus.snoop_fanout::stdev 0.350524 # Request fanout histogram 1182system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1183system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1184system.cpu.toL2Bus.snoop_fanout::1 1616816 85.66% 85.66% # Request fanout histogram 1185system.cpu.toL2Bus.snoop_fanout::2 270759 14.34% 100.00% # Request fanout histogram 1186system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1187system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 1188system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 1189system.cpu.toL2Bus.snoop_fanout::total 1887575 # Request fanout histogram 1190system.cpu.toL2Bus.reqLayer0.occupancy 1069525000 # Layer occupancy (ticks) 1191system.cpu.toL2Bus.reqLayer0.utilization 3.2 # Layer utilization (%) 1192system.cpu.toL2Bus.respLayer0.occupancy 485192198 # Layer occupancy (ticks) 1193system.cpu.toL2Bus.respLayer0.utilization 1.5 # Layer utilization (%) 1194system.cpu.toL2Bus.respLayer1.occupancy 728416355 # Layer occupancy (ticks) 1195system.cpu.toL2Bus.respLayer1.utilization 2.2 # Layer utilization (%) 1196system.membus.trans_dist::ReadResp 137050 # Transaction distribution 1197system.membus.trans_dist::Writeback 97878 # Transaction distribution 1198system.membus.trans_dist::CleanEvict 30539 # Transaction distribution 1199system.membus.trans_dist::UpgradeReq 6 # Transaction distribution 1200system.membus.trans_dist::UpgradeResp 6 # Transaction distribution 1201system.membus.trans_dist::ReadExReq 8386 # Transaction distribution 1202system.membus.trans_dist::ReadExResp 8386 # Transaction distribution 1203system.membus.trans_dist::ReadSharedReq 137050 # Transaction distribution 1204system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 419301 # Packet count per connected master and slave (bytes) 1205system.membus.pkt_count::total 419301 # Packet count per connected master and slave (bytes) 1206system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15572096 # Cumulative packet size per connected master and slave (bytes) 1207system.membus.pkt_size::total 15572096 # Cumulative packet size per connected master and slave (bytes) 1208system.membus.snoops 0 # Total snoops (count) 1209system.membus.snoop_fanout::samples 273859 # Request fanout histogram 1210system.membus.snoop_fanout::mean 0 # Request fanout histogram 1211system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1212system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1213system.membus.snoop_fanout::0 273859 100.00% 100.00% # Request fanout histogram 1214system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 1215system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1216system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1217system.membus.snoop_fanout::max_value 0 # Request fanout histogram 1218system.membus.snoop_fanout::total 273859 # Request fanout histogram 1219system.membus.reqLayer0.occupancy 740935905 # Layer occupancy (ticks) 1220system.membus.reqLayer0.utilization 2.2 # Layer utilization (%) 1221system.membus.respLayer1.occupancy 757820949 # Layer occupancy (ticks) 1222system.membus.respLayer1.utilization 2.3 # Layer utilization (%) 1223 1224---------- End Simulation Statistics ---------- 1225