stats.txt revision 11103
110515SAli.Saidi@ARM.com 210515SAli.Saidi@ARM.com---------- Begin Simulation Statistics ---------- 311103Snilay@cs.wisc.edusim_seconds 51.694125 # Number of seconds simulated 411103Snilay@cs.wisc.edusim_ticks 51694125219000 # Number of ticks simulated 511103Snilay@cs.wisc.edufinal_tick 51694125219000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 610515SAli.Saidi@ARM.comsim_freq 1000000000000 # Frequency of simulated ticks 711103Snilay@cs.wisc.eduhost_inst_rate 131034 # Simulator instruction rate (inst/s) 811103Snilay@cs.wisc.eduhost_op_rate 153967 # Simulator op (including micro ops) rate (op/s) 911103Snilay@cs.wisc.eduhost_tick_rate 7136466436 # Simulator tick rate (ticks/s) 1011103Snilay@cs.wisc.eduhost_mem_usage 718208 # Number of bytes of host memory used 1111103Snilay@cs.wisc.eduhost_seconds 7243.66 # Real time elapsed on the host 1211103Snilay@cs.wisc.edusim_insts 949163000 # Number of instructions simulated 1311103Snilay@cs.wisc.edusim_ops 1115282140 # Number of ops (including micro ops) simulated 1410515SAli.Saidi@ARM.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1510515SAli.Saidi@ARM.comsystem.clk_domain.clock 1000 # Clock period in ticks 1611103Snilay@cs.wisc.edusystem.physmem.bytes_read::cpu.dtb.walker 407680 # Number of bytes read from this memory 1711103Snilay@cs.wisc.edusystem.physmem.bytes_read::cpu.itb.walker 346624 # Number of bytes read from this memory 1811103Snilay@cs.wisc.edusystem.physmem.bytes_read::cpu.inst 10124864 # Number of bytes read from this memory 1911103Snilay@cs.wisc.edusystem.physmem.bytes_read::cpu.data 101217736 # Number of bytes read from this memory 2011103Snilay@cs.wisc.edusystem.physmem.bytes_read::realview.ide 409088 # Number of bytes read from this memory 2111103Snilay@cs.wisc.edusystem.physmem.bytes_read::total 112505992 # Number of bytes read from this memory 2211103Snilay@cs.wisc.edusystem.physmem.bytes_inst_read::cpu.inst 10124864 # Number of instructions bytes read from this memory 2311103Snilay@cs.wisc.edusystem.physmem.bytes_inst_read::total 10124864 # Number of instructions bytes read from this memory 2411103Snilay@cs.wisc.edusystem.physmem.bytes_written::writebacks 94737216 # Number of bytes written to this memory 2510636Snilay@cs.wisc.edusystem.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory 2611103Snilay@cs.wisc.edusystem.physmem.bytes_written::total 94757796 # Number of bytes written to this memory 2711103Snilay@cs.wisc.edusystem.physmem.num_reads::cpu.dtb.walker 6370 # Number of read requests responded to by this memory 2811103Snilay@cs.wisc.edusystem.physmem.num_reads::cpu.itb.walker 5416 # Number of read requests responded to by this memory 2911103Snilay@cs.wisc.edusystem.physmem.num_reads::cpu.inst 158201 # Number of read requests responded to by this memory 3011103Snilay@cs.wisc.edusystem.physmem.num_reads::cpu.data 1581540 # Number of read requests responded to by this memory 3111103Snilay@cs.wisc.edusystem.physmem.num_reads::realview.ide 6392 # Number of read requests responded to by this memory 3211103Snilay@cs.wisc.edusystem.physmem.num_reads::total 1757919 # Number of read requests responded to by this memory 3311103Snilay@cs.wisc.edusystem.physmem.num_writes::writebacks 1480269 # Number of write requests responded to by this memory 3410636Snilay@cs.wisc.edusystem.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory 3511103Snilay@cs.wisc.edusystem.physmem.num_writes::total 1482842 # Number of write requests responded to by this memory 3611103Snilay@cs.wisc.edusystem.physmem.bw_read::cpu.dtb.walker 7886 # Total read bandwidth from this memory (bytes/s) 3711103Snilay@cs.wisc.edusystem.physmem.bw_read::cpu.itb.walker 6705 # Total read bandwidth from this memory (bytes/s) 3811103Snilay@cs.wisc.edusystem.physmem.bw_read::cpu.inst 195861 # Total read bandwidth from this memory (bytes/s) 3911103Snilay@cs.wisc.edusystem.physmem.bw_read::cpu.data 1958012 # Total read bandwidth from this memory (bytes/s) 4011103Snilay@cs.wisc.edusystem.physmem.bw_read::realview.ide 7914 # Total read bandwidth from this memory (bytes/s) 4111103Snilay@cs.wisc.edusystem.physmem.bw_read::total 2176379 # Total read bandwidth from this memory (bytes/s) 4211103Snilay@cs.wisc.edusystem.physmem.bw_inst_read::cpu.inst 195861 # Instruction read bandwidth from this memory (bytes/s) 4311103Snilay@cs.wisc.edusystem.physmem.bw_inst_read::total 195861 # Instruction read bandwidth from this memory (bytes/s) 4411103Snilay@cs.wisc.edusystem.physmem.bw_write::writebacks 1832650 # Write bandwidth from this memory (bytes/s) 4510892Sandreas.hansson@arm.comsystem.physmem.bw_write::cpu.data 398 # Write bandwidth from this memory (bytes/s) 4611103Snilay@cs.wisc.edusystem.physmem.bw_write::total 1833048 # Write bandwidth from this memory (bytes/s) 4711103Snilay@cs.wisc.edusystem.physmem.bw_total::writebacks 1832650 # Total bandwidth to/from this memory (bytes/s) 4811103Snilay@cs.wisc.edusystem.physmem.bw_total::cpu.dtb.walker 7886 # Total bandwidth to/from this memory (bytes/s) 4911103Snilay@cs.wisc.edusystem.physmem.bw_total::cpu.itb.walker 6705 # Total bandwidth to/from this memory (bytes/s) 5011103Snilay@cs.wisc.edusystem.physmem.bw_total::cpu.inst 195861 # Total bandwidth to/from this memory (bytes/s) 5111103Snilay@cs.wisc.edusystem.physmem.bw_total::cpu.data 1958410 # Total bandwidth to/from this memory (bytes/s) 5211103Snilay@cs.wisc.edusystem.physmem.bw_total::realview.ide 7914 # Total bandwidth to/from this memory (bytes/s) 5311103Snilay@cs.wisc.edusystem.physmem.bw_total::total 4009426 # Total bandwidth to/from this memory (bytes/s) 5411103Snilay@cs.wisc.edusystem.physmem.readReqs 1757919 # Number of read requests accepted 5511103Snilay@cs.wisc.edusystem.physmem.writeReqs 1482842 # Number of write requests accepted 5611103Snilay@cs.wisc.edusystem.physmem.readBursts 1757919 # Number of DRAM read bursts, including those serviced by the write queue 5711103Snilay@cs.wisc.edusystem.physmem.writeBursts 1482842 # Number of DRAM write bursts, including those merged in the write queue 5811103Snilay@cs.wisc.edusystem.physmem.bytesReadDRAM 112457536 # Total number of bytes read from DRAM 5911103Snilay@cs.wisc.edusystem.physmem.bytesReadWrQ 49280 # Total number of bytes read from write queue 6011103Snilay@cs.wisc.edusystem.physmem.bytesWritten 94756288 # Total number of bytes written to DRAM 6111103Snilay@cs.wisc.edusystem.physmem.bytesReadSys 112505992 # Total read bytes from the system interface side 6211103Snilay@cs.wisc.edusystem.physmem.bytesWrittenSys 94757796 # Total written bytes from the system interface side 6311103Snilay@cs.wisc.edusystem.physmem.servicedByWrQ 770 # Number of DRAM read bursts serviced by the write queue 6411103Snilay@cs.wisc.edusystem.physmem.mergedWrBursts 2248 # Number of DRAM write bursts merged with an existing one 6511103Snilay@cs.wisc.edusystem.physmem.neitherReadNorWriteReqs 146200 # Number of requests that are neither read nor write 6611103Snilay@cs.wisc.edusystem.physmem.perBankRdBursts::0 105973 # Per bank write bursts 6711103Snilay@cs.wisc.edusystem.physmem.perBankRdBursts::1 111407 # Per bank write bursts 6811103Snilay@cs.wisc.edusystem.physmem.perBankRdBursts::2 105002 # Per bank write bursts 6911103Snilay@cs.wisc.edusystem.physmem.perBankRdBursts::3 101812 # Per bank write bursts 7011103Snilay@cs.wisc.edusystem.physmem.perBankRdBursts::4 108332 # Per bank write bursts 7111103Snilay@cs.wisc.edusystem.physmem.perBankRdBursts::5 117578 # Per bank write bursts 7211103Snilay@cs.wisc.edusystem.physmem.perBankRdBursts::6 104534 # Per bank write bursts 7311103Snilay@cs.wisc.edusystem.physmem.perBankRdBursts::7 108687 # Per bank write bursts 7411103Snilay@cs.wisc.edusystem.physmem.perBankRdBursts::8 103848 # Per bank write bursts 7511103Snilay@cs.wisc.edusystem.physmem.perBankRdBursts::9 161007 # Per bank write bursts 7611103Snilay@cs.wisc.edusystem.physmem.perBankRdBursts::10 107405 # Per bank write bursts 7711103Snilay@cs.wisc.edusystem.physmem.perBankRdBursts::11 110838 # Per bank write bursts 7811103Snilay@cs.wisc.edusystem.physmem.perBankRdBursts::12 104563 # Per bank write bursts 7911103Snilay@cs.wisc.edusystem.physmem.perBankRdBursts::13 103815 # Per bank write bursts 8011103Snilay@cs.wisc.edusystem.physmem.perBankRdBursts::14 100822 # Per bank write bursts 8111103Snilay@cs.wisc.edusystem.physmem.perBankRdBursts::15 101526 # Per bank write bursts 8211103Snilay@cs.wisc.edusystem.physmem.perBankWrBursts::0 90430 # Per bank write bursts 8311103Snilay@cs.wisc.edusystem.physmem.perBankWrBursts::1 94995 # Per bank write bursts 8411103Snilay@cs.wisc.edusystem.physmem.perBankWrBursts::2 91678 # Per bank write bursts 8511103Snilay@cs.wisc.edusystem.physmem.perBankWrBursts::3 90022 # Per bank write bursts 8611103Snilay@cs.wisc.edusystem.physmem.perBankWrBursts::4 94229 # Per bank write bursts 8711103Snilay@cs.wisc.edusystem.physmem.perBankWrBursts::5 99888 # Per bank write bursts 8811103Snilay@cs.wisc.edusystem.physmem.perBankWrBursts::6 89385 # Per bank write bursts 8911103Snilay@cs.wisc.edusystem.physmem.perBankWrBursts::7 93994 # Per bank write bursts 9011103Snilay@cs.wisc.edusystem.physmem.perBankWrBursts::8 90076 # Per bank write bursts 9111103Snilay@cs.wisc.edusystem.physmem.perBankWrBursts::9 95745 # Per bank write bursts 9211103Snilay@cs.wisc.edusystem.physmem.perBankWrBursts::10 91874 # Per bank write bursts 9311103Snilay@cs.wisc.edusystem.physmem.perBankWrBursts::11 95898 # Per bank write bursts 9411103Snilay@cs.wisc.edusystem.physmem.perBankWrBursts::12 91438 # Per bank write bursts 9511103Snilay@cs.wisc.edusystem.physmem.perBankWrBursts::13 92023 # Per bank write bursts 9611103Snilay@cs.wisc.edusystem.physmem.perBankWrBursts::14 89075 # Per bank write bursts 9711103Snilay@cs.wisc.edusystem.physmem.perBankWrBursts::15 89817 # Per bank write bursts 9810515SAli.Saidi@ARM.comsystem.physmem.numRdRetry 0 # Number of times read queue was full causing retry 9911103Snilay@cs.wisc.edusystem.physmem.numWrRetry 27 # Number of times write queue was full causing retry 10011103Snilay@cs.wisc.edusystem.physmem.totGap 51694123514000 # Total gap between requests 10110515SAli.Saidi@ARM.comsystem.physmem.readPktSize::0 0 # Read request sizes (log2) 10210515SAli.Saidi@ARM.comsystem.physmem.readPktSize::1 0 # Read request sizes (log2) 10310515SAli.Saidi@ARM.comsystem.physmem.readPktSize::2 0 # Read request sizes (log2) 10410515SAli.Saidi@ARM.comsystem.physmem.readPktSize::3 13 # Read request sizes (log2) 10510515SAli.Saidi@ARM.comsystem.physmem.readPktSize::4 2 # Read request sizes (log2) 10610515SAli.Saidi@ARM.comsystem.physmem.readPktSize::5 0 # Read request sizes (log2) 10711103Snilay@cs.wisc.edusystem.physmem.readPktSize::6 1757904 # Read request sizes (log2) 10810515SAli.Saidi@ARM.comsystem.physmem.writePktSize::0 0 # Write request sizes (log2) 10910515SAli.Saidi@ARM.comsystem.physmem.writePktSize::1 0 # Write request sizes (log2) 11010515SAli.Saidi@ARM.comsystem.physmem.writePktSize::2 1 # Write request sizes (log2) 11110515SAli.Saidi@ARM.comsystem.physmem.writePktSize::3 2572 # Write request sizes (log2) 11210515SAli.Saidi@ARM.comsystem.physmem.writePktSize::4 0 # Write request sizes (log2) 11310515SAli.Saidi@ARM.comsystem.physmem.writePktSize::5 0 # Write request sizes (log2) 11411103Snilay@cs.wisc.edusystem.physmem.writePktSize::6 1480269 # Write request sizes (log2) 11511103Snilay@cs.wisc.edusystem.physmem.rdQLenPdf::0 1422025 # What read queue length does an incoming req see 11611103Snilay@cs.wisc.edusystem.physmem.rdQLenPdf::1 328688 # What read queue length does an incoming req see 11711103Snilay@cs.wisc.edusystem.physmem.rdQLenPdf::2 1048 # What read queue length does an incoming req see 11811103Snilay@cs.wisc.edusystem.physmem.rdQLenPdf::3 351 # What read queue length does an incoming req see 11911103Snilay@cs.wisc.edusystem.physmem.rdQLenPdf::4 481 # What read queue length does an incoming req see 12011103Snilay@cs.wisc.edusystem.physmem.rdQLenPdf::5 469 # What read queue length does an incoming req see 12111103Snilay@cs.wisc.edusystem.physmem.rdQLenPdf::6 492 # What read queue length does an incoming req see 12211103Snilay@cs.wisc.edusystem.physmem.rdQLenPdf::7 522 # What read queue length does an incoming req see 12311103Snilay@cs.wisc.edusystem.physmem.rdQLenPdf::8 773 # What read queue length does an incoming req see 12411103Snilay@cs.wisc.edusystem.physmem.rdQLenPdf::9 906 # What read queue length does an incoming req see 12511103Snilay@cs.wisc.edusystem.physmem.rdQLenPdf::10 358 # What read queue length does an incoming req see 12611103Snilay@cs.wisc.edusystem.physmem.rdQLenPdf::11 190 # What read queue length does an incoming req see 12711103Snilay@cs.wisc.edusystem.physmem.rdQLenPdf::12 168 # What read queue length does an incoming req see 12811103Snilay@cs.wisc.edusystem.physmem.rdQLenPdf::13 130 # What read queue length does an incoming req see 12911103Snilay@cs.wisc.edusystem.physmem.rdQLenPdf::14 117 # What read queue length does an incoming req see 13011103Snilay@cs.wisc.edusystem.physmem.rdQLenPdf::15 106 # What read queue length does an incoming req see 13111103Snilay@cs.wisc.edusystem.physmem.rdQLenPdf::16 93 # What read queue length does an incoming req see 13211103Snilay@cs.wisc.edusystem.physmem.rdQLenPdf::17 92 # What read queue length does an incoming req see 13311103Snilay@cs.wisc.edusystem.physmem.rdQLenPdf::18 77 # What read queue length does an incoming req see 13411103Snilay@cs.wisc.edusystem.physmem.rdQLenPdf::19 57 # What read queue length does an incoming req see 13511103Snilay@cs.wisc.edusystem.physmem.rdQLenPdf::20 4 # What read queue length does an incoming req see 13611103Snilay@cs.wisc.edusystem.physmem.rdQLenPdf::21 2 # What read queue length does an incoming req see 13710515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 13810515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 13910515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 14010515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 14110515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 14210515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 14310515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 14410515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 14510515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 14610515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 14710515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 14810515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 14910515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 15010515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 15110515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 15210515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 15310515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 15410515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 15510515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 15610515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 15710515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 15810515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 15910515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 16010515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 16110515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 16211103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::15 15568 # What write queue length does an incoming req see 16311103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::16 18151 # What write queue length does an incoming req see 16411103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::17 71947 # What write queue length does an incoming req see 16511103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::18 88213 # What write queue length does an incoming req see 16611103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::19 88480 # What write queue length does an incoming req see 16711103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::20 88386 # What write queue length does an incoming req see 16811103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::21 88377 # What write queue length does an incoming req see 16911103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::22 91264 # What write queue length does an incoming req see 17011103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::23 92065 # What write queue length does an incoming req see 17111103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::24 94405 # What write queue length does an incoming req see 17211103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::25 93246 # What write queue length does an incoming req see 17311103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::26 93724 # What write queue length does an incoming req see 17411103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::27 90170 # What write queue length does an incoming req see 17511103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::28 90391 # What write queue length does an incoming req see 17611103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::29 100271 # What write queue length does an incoming req see 17711103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::30 88772 # What write queue length does an incoming req see 17811103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::31 90332 # What write queue length does an incoming req see 17911103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::32 87233 # What write queue length does an incoming req see 18011103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::33 738 # What write queue length does an incoming req see 18111103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::34 612 # What write queue length does an incoming req see 18211103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::35 700 # What write queue length does an incoming req see 18311103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::36 613 # What write queue length does an incoming req see 18411103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::37 492 # What write queue length does an incoming req see 18511103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::38 421 # What write queue length does an incoming req see 18611103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::39 484 # What write queue length does an incoming req see 18711103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::40 399 # What write queue length does an incoming req see 18811103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::41 400 # What write queue length does an incoming req see 18911103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::42 350 # What write queue length does an incoming req see 19011103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::43 281 # What write queue length does an incoming req see 19111103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::44 352 # What write queue length does an incoming req see 19211103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::45 261 # What write queue length does an incoming req see 19311103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::46 306 # What write queue length does an incoming req see 19411103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::47 263 # What write queue length does an incoming req see 19511103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::48 275 # What write queue length does an incoming req see 19611103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::49 253 # What write queue length does an incoming req see 19711103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::50 240 # What write queue length does an incoming req see 19811103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::51 271 # What write queue length does an incoming req see 19911103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::52 253 # What write queue length does an incoming req see 20011103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::53 203 # What write queue length does an incoming req see 20111103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::54 244 # What write queue length does an incoming req see 20211103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::55 219 # What write queue length does an incoming req see 20311103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::56 182 # What write queue length does an incoming req see 20411103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::57 159 # What write queue length does an incoming req see 20511103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::58 123 # What write queue length does an incoming req see 20611103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::59 105 # What write queue length does an incoming req see 20711103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::60 110 # What write queue length does an incoming req see 20811103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::61 129 # What write queue length does an incoming req see 20911103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::62 63 # What write queue length does an incoming req see 21011103Snilay@cs.wisc.edusystem.physmem.wrQLenPdf::63 83 # What write queue length does an incoming req see 21111103Snilay@cs.wisc.edusystem.physmem.bytesPerActivate::samples 690739 # Bytes accessed per row activation 21211103Snilay@cs.wisc.edusystem.physmem.bytesPerActivate::mean 299.988042 # Bytes accessed per row activation 21311103Snilay@cs.wisc.edusystem.physmem.bytesPerActivate::gmean 174.369601 # Bytes accessed per row activation 21411103Snilay@cs.wisc.edusystem.physmem.bytesPerActivate::stdev 327.443819 # Bytes accessed per row activation 21511103Snilay@cs.wisc.edusystem.physmem.bytesPerActivate::0-127 271817 39.35% 39.35% # Bytes accessed per row activation 21611103Snilay@cs.wisc.edusystem.physmem.bytesPerActivate::128-255 165800 24.00% 63.35% # Bytes accessed per row activation 21711103Snilay@cs.wisc.edusystem.physmem.bytesPerActivate::256-383 63380 9.18% 72.53% # Bytes accessed per row activation 21811103Snilay@cs.wisc.edusystem.physmem.bytesPerActivate::384-511 36796 5.33% 77.86% # Bytes accessed per row activation 21911103Snilay@cs.wisc.edusystem.physmem.bytesPerActivate::512-639 26984 3.91% 81.76% # Bytes accessed per row activation 22011103Snilay@cs.wisc.edusystem.physmem.bytesPerActivate::640-767 18833 2.73% 84.49% # Bytes accessed per row activation 22111103Snilay@cs.wisc.edusystem.physmem.bytesPerActivate::768-895 14857 2.15% 86.64% # Bytes accessed per row activation 22211103Snilay@cs.wisc.edusystem.physmem.bytesPerActivate::896-1023 13605 1.97% 88.61% # Bytes accessed per row activation 22311103Snilay@cs.wisc.edusystem.physmem.bytesPerActivate::1024-1151 78667 11.39% 100.00% # Bytes accessed per row activation 22411103Snilay@cs.wisc.edusystem.physmem.bytesPerActivate::total 690739 # Bytes accessed per row activation 22511103Snilay@cs.wisc.edusystem.physmem.rdPerTurnAround::samples 86593 # Reads before turning the bus around for writes 22611103Snilay@cs.wisc.edusystem.physmem.rdPerTurnAround::mean 20.291686 # Reads before turning the bus around for writes 22711103Snilay@cs.wisc.edusystem.physmem.rdPerTurnAround::stdev 270.345126 # Reads before turning the bus around for writes 22811103Snilay@cs.wisc.edusystem.physmem.rdPerTurnAround::0-4095 86590 100.00% 100.00% # Reads before turning the bus around for writes 22910892Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::4096-8191 1 0.00% 100.00% # Reads before turning the bus around for writes 23010892Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::24576-28671 1 0.00% 100.00% # Reads before turning the bus around for writes 23110892Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::73728-77823 1 0.00% 100.00% # Reads before turning the bus around for writes 23211103Snilay@cs.wisc.edusystem.physmem.rdPerTurnAround::total 86593 # Reads before turning the bus around for writes 23311103Snilay@cs.wisc.edusystem.physmem.wrPerTurnAround::samples 86593 # Writes before turning the bus around for reads 23411103Snilay@cs.wisc.edusystem.physmem.wrPerTurnAround::mean 17.097999 # Writes before turning the bus around for reads 23511103Snilay@cs.wisc.edusystem.physmem.wrPerTurnAround::gmean 16.728630 # Writes before turning the bus around for reads 23611103Snilay@cs.wisc.edusystem.physmem.wrPerTurnAround::stdev 5.809360 # Writes before turning the bus around for reads 23711103Snilay@cs.wisc.edusystem.physmem.wrPerTurnAround::16-19 84121 97.15% 97.15% # Writes before turning the bus around for reads 23811103Snilay@cs.wisc.edusystem.physmem.wrPerTurnAround::20-23 149 0.17% 97.32% # Writes before turning the bus around for reads 23911103Snilay@cs.wisc.edusystem.physmem.wrPerTurnAround::24-27 413 0.48% 97.79% # Writes before turning the bus around for reads 24011103Snilay@cs.wisc.edusystem.physmem.wrPerTurnAround::28-31 198 0.23% 98.02% # Writes before turning the bus around for reads 24111103Snilay@cs.wisc.edusystem.physmem.wrPerTurnAround::32-35 310 0.36% 98.38% # Writes before turning the bus around for reads 24211103Snilay@cs.wisc.edusystem.physmem.wrPerTurnAround::36-39 507 0.59% 98.97% # Writes before turning the bus around for reads 24311103Snilay@cs.wisc.edusystem.physmem.wrPerTurnAround::40-43 123 0.14% 99.11% # Writes before turning the bus around for reads 24410892Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::44-47 35 0.04% 99.15% # Writes before turning the bus around for reads 24511103Snilay@cs.wisc.edusystem.physmem.wrPerTurnAround::48-51 41 0.05% 99.20% # Writes before turning the bus around for reads 24611103Snilay@cs.wisc.edusystem.physmem.wrPerTurnAround::52-55 24 0.03% 99.22% # Writes before turning the bus around for reads 24711103Snilay@cs.wisc.edusystem.physmem.wrPerTurnAround::56-59 40 0.05% 99.27% # Writes before turning the bus around for reads 24811103Snilay@cs.wisc.edusystem.physmem.wrPerTurnAround::60-63 29 0.03% 99.30% # Writes before turning the bus around for reads 24911103Snilay@cs.wisc.edusystem.physmem.wrPerTurnAround::64-67 413 0.48% 99.78% # Writes before turning the bus around for reads 25011103Snilay@cs.wisc.edusystem.physmem.wrPerTurnAround::68-71 31 0.04% 99.82% # Writes before turning the bus around for reads 25111103Snilay@cs.wisc.edusystem.physmem.wrPerTurnAround::72-75 42 0.05% 99.86% # Writes before turning the bus around for reads 25211103Snilay@cs.wisc.edusystem.physmem.wrPerTurnAround::76-79 40 0.05% 99.91% # Writes before turning the bus around for reads 25311103Snilay@cs.wisc.edusystem.physmem.wrPerTurnAround::80-83 8 0.01% 99.92% # Writes before turning the bus around for reads 25411103Snilay@cs.wisc.edusystem.physmem.wrPerTurnAround::84-87 3 0.00% 99.92% # Writes before turning the bus around for reads 25511103Snilay@cs.wisc.edusystem.physmem.wrPerTurnAround::88-91 4 0.00% 99.93% # Writes before turning the bus around for reads 25611103Snilay@cs.wisc.edusystem.physmem.wrPerTurnAround::92-95 4 0.00% 99.93% # Writes before turning the bus around for reads 25711103Snilay@cs.wisc.edusystem.physmem.wrPerTurnAround::96-99 1 0.00% 99.93% # Writes before turning the bus around for reads 25811103Snilay@cs.wisc.edusystem.physmem.wrPerTurnAround::100-103 4 0.00% 99.94% # Writes before turning the bus around for reads 25911103Snilay@cs.wisc.edusystem.physmem.wrPerTurnAround::112-115 2 0.00% 99.94% # Writes before turning the bus around for reads 26011103Snilay@cs.wisc.edusystem.physmem.wrPerTurnAround::120-123 1 0.00% 99.94% # Writes before turning the bus around for reads 26111103Snilay@cs.wisc.edusystem.physmem.wrPerTurnAround::124-127 3 0.00% 99.95% # Writes before turning the bus around for reads 26211103Snilay@cs.wisc.edusystem.physmem.wrPerTurnAround::128-131 31 0.04% 99.98% # Writes before turning the bus around for reads 26311103Snilay@cs.wisc.edusystem.physmem.wrPerTurnAround::136-139 2 0.00% 99.98% # Writes before turning the bus around for reads 26411103Snilay@cs.wisc.edusystem.physmem.wrPerTurnAround::140-143 2 0.00% 99.99% # Writes before turning the bus around for reads 26511103Snilay@cs.wisc.edusystem.physmem.wrPerTurnAround::144-147 1 0.00% 99.99% # Writes before turning the bus around for reads 26611103Snilay@cs.wisc.edusystem.physmem.wrPerTurnAround::148-151 3 0.00% 99.99% # Writes before turning the bus around for reads 26711103Snilay@cs.wisc.edusystem.physmem.wrPerTurnAround::160-163 1 0.00% 99.99% # Writes before turning the bus around for reads 26811103Snilay@cs.wisc.edusystem.physmem.wrPerTurnAround::164-167 2 0.00% 99.99% # Writes before turning the bus around for reads 26911103Snilay@cs.wisc.edusystem.physmem.wrPerTurnAround::172-175 1 0.00% 100.00% # Writes before turning the bus around for reads 27011103Snilay@cs.wisc.edusystem.physmem.wrPerTurnAround::176-179 4 0.00% 100.00% # Writes before turning the bus around for reads 27111103Snilay@cs.wisc.edusystem.physmem.wrPerTurnAround::total 86593 # Writes before turning the bus around for reads 27211103Snilay@cs.wisc.edusystem.physmem.totQLat 26847024830 # Total ticks spent queuing 27311103Snilay@cs.wisc.edusystem.physmem.totMemAccLat 59793568580 # Total ticks spent from burst creation until serviced by the DRAM 27411103Snilay@cs.wisc.edusystem.physmem.totBusLat 8785745000 # Total ticks spent in databus transfers 27511103Snilay@cs.wisc.edusystem.physmem.avgQLat 15278.74 # Average queueing delay per DRAM burst 27610515SAli.Saidi@ARM.comsystem.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 27711103Snilay@cs.wisc.edusystem.physmem.avgMemAccLat 34028.74 # Average memory access latency per DRAM burst 27811103Snilay@cs.wisc.edusystem.physmem.avgRdBW 2.18 # Average DRAM read bandwidth in MiByte/s 27910892Sandreas.hansson@arm.comsystem.physmem.avgWrBW 1.83 # Average achieved write bandwidth in MiByte/s 28011103Snilay@cs.wisc.edusystem.physmem.avgRdBWSys 2.18 # Average system read bandwidth in MiByte/s 28110892Sandreas.hansson@arm.comsystem.physmem.avgWrBWSys 1.83 # Average system write bandwidth in MiByte/s 28210515SAli.Saidi@ARM.comsystem.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 28310585Sandreas.hansson@arm.comsystem.physmem.busUtil 0.03 # Data bus utilization in percentage 28410892Sandreas.hansson@arm.comsystem.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads 28510892Sandreas.hansson@arm.comsystem.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes 28611103Snilay@cs.wisc.edusystem.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing 28711103Snilay@cs.wisc.edusystem.physmem.avgWrQLen 23.96 # Average write queue length when enqueuing 28811103Snilay@cs.wisc.edusystem.physmem.readRowHits 1436721 # Number of row buffer hits during reads 28911103Snilay@cs.wisc.edusystem.physmem.writeRowHits 1110255 # Number of row buffer hits during writes 29011103Snilay@cs.wisc.edusystem.physmem.readRowHitRate 81.76 # Row buffer hit rate for reads 29111103Snilay@cs.wisc.edusystem.physmem.writeRowHitRate 74.99 # Row buffer hit rate for writes 29211103Snilay@cs.wisc.edusystem.physmem.avgGap 15951229.82 # Average gap between requests 29311103Snilay@cs.wisc.edusystem.physmem.pageHitRate 78.67 # Row buffer hit rate, read and write combined 29411103Snilay@cs.wisc.edusystem.physmem_0.actEnergy 2651919480 # Energy for activate commands per rank (pJ) 29511103Snilay@cs.wisc.edusystem.physmem_0.preEnergy 1446979875 # Energy for precharge commands per rank (pJ) 29611103Snilay@cs.wisc.edusystem.physmem_0.readEnergy 6733888200 # Energy for read commands per rank (pJ) 29711103Snilay@cs.wisc.edusystem.physmem_0.writeEnergy 4825144080 # Energy for write commands per rank (pJ) 29811103Snilay@cs.wisc.edusystem.physmem_0.refreshEnergy 3376408666800 # Energy for refresh commands per rank (pJ) 29911103Snilay@cs.wisc.edusystem.physmem_0.actBackEnergy 1308234674070 # Energy for active background per rank (pJ) 30011103Snilay@cs.wisc.edusystem.physmem_0.preBackEnergy 29868898243500 # Energy for precharge background per rank (pJ) 30111103Snilay@cs.wisc.edusystem.physmem_0.totalEnergy 34569199516005 # Total energy per rank (pJ) 30211103Snilay@cs.wisc.edusystem.physmem_0.averagePower 668.725939 # Core power per rank (mW) 30311103Snilay@cs.wisc.edusystem.physmem_0.memoryStateTime::IDLE 49688706621634 # Time in different power states 30411103Snilay@cs.wisc.edusystem.physmem_0.memoryStateTime::REF 1726180300000 # Time in different power states 30510628Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 30611103Snilay@cs.wisc.edusystem.physmem_0.memoryStateTime::ACT 279237825366 # Time in different power states 30710628Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 30811103Snilay@cs.wisc.edusystem.physmem_1.actEnergy 2570067360 # Energy for activate commands per rank (pJ) 30911103Snilay@cs.wisc.edusystem.physmem_1.preEnergy 1402318500 # Energy for precharge commands per rank (pJ) 31011103Snilay@cs.wisc.edusystem.physmem_1.readEnergy 6971827200 # Energy for read commands per rank (pJ) 31111103Snilay@cs.wisc.edusystem.physmem_1.writeEnergy 4768930080 # Energy for write commands per rank (pJ) 31211103Snilay@cs.wisc.edusystem.physmem_1.refreshEnergy 3376408666800 # Energy for refresh commands per rank (pJ) 31311103Snilay@cs.wisc.edusystem.physmem_1.actBackEnergy 1306063695690 # Energy for active background per rank (pJ) 31411103Snilay@cs.wisc.edusystem.physmem_1.preBackEnergy 29870802610500 # Energy for precharge background per rank (pJ) 31511103Snilay@cs.wisc.edusystem.physmem_1.totalEnergy 34568988116130 # Total energy per rank (pJ) 31611103Snilay@cs.wisc.edusystem.physmem_1.averagePower 668.721850 # Core power per rank (mW) 31711103Snilay@cs.wisc.edusystem.physmem_1.memoryStateTime::IDLE 49691848230640 # Time in different power states 31811103Snilay@cs.wisc.edusystem.physmem_1.memoryStateTime::REF 1726180300000 # Time in different power states 31910628Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 32011103Snilay@cs.wisc.edusystem.physmem_1.memoryStateTime::ACT 276092348110 # Time in different power states 32110628Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 32210636Snilay@cs.wisc.edusystem.realview.nvmem.bytes_read::cpu.inst 704 # Number of bytes read from this memory 32310636Snilay@cs.wisc.edusystem.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory 32410515SAli.Saidi@ARM.comsystem.realview.nvmem.bytes_read::total 740 # Number of bytes read from this memory 32510515SAli.Saidi@ARM.comsystem.realview.nvmem.bytes_inst_read::cpu.inst 704 # Number of instructions bytes read from this memory 32610515SAli.Saidi@ARM.comsystem.realview.nvmem.bytes_inst_read::total 704 # Number of instructions bytes read from this memory 32710636Snilay@cs.wisc.edusystem.realview.nvmem.num_reads::cpu.inst 11 # Number of read requests responded to by this memory 32810636Snilay@cs.wisc.edusystem.realview.nvmem.num_reads::cpu.data 5 # Number of read requests responded to by this memory 32910515SAli.Saidi@ARM.comsystem.realview.nvmem.num_reads::total 16 # Number of read requests responded to by this memory 33010515SAli.Saidi@ARM.comsystem.realview.nvmem.bw_read::cpu.inst 14 # Total read bandwidth from this memory (bytes/s) 33110636Snilay@cs.wisc.edusystem.realview.nvmem.bw_read::cpu.data 1 # Total read bandwidth from this memory (bytes/s) 33210515SAli.Saidi@ARM.comsystem.realview.nvmem.bw_read::total 14 # Total read bandwidth from this memory (bytes/s) 33310515SAli.Saidi@ARM.comsystem.realview.nvmem.bw_inst_read::cpu.inst 14 # Instruction read bandwidth from this memory (bytes/s) 33410515SAli.Saidi@ARM.comsystem.realview.nvmem.bw_inst_read::total 14 # Instruction read bandwidth from this memory (bytes/s) 33510515SAli.Saidi@ARM.comsystem.realview.nvmem.bw_total::cpu.inst 14 # Total bandwidth to/from this memory (bytes/s) 33610636Snilay@cs.wisc.edusystem.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s) 33710515SAli.Saidi@ARM.comsystem.realview.nvmem.bw_total::total 14 # Total bandwidth to/from this memory (bytes/s) 33810585Sandreas.hansson@arm.comsystem.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 33910585Sandreas.hansson@arm.comsystem.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 34010585Sandreas.hansson@arm.comsystem.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 34110585Sandreas.hansson@arm.comsystem.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. 34210585Sandreas.hansson@arm.comsystem.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. 34310585Sandreas.hansson@arm.comsystem.cf0.dma_write_txs 1669 # Number of DMA write transactions. 34411103Snilay@cs.wisc.edusystem.cpu.branchPred.lookups 260286663 # Number of BP lookups 34511103Snilay@cs.wisc.edusystem.cpu.branchPred.condPredicted 182589592 # Number of conditional branches predicted 34611103Snilay@cs.wisc.edusystem.cpu.branchPred.condIncorrect 12077009 # Number of conditional branches incorrect 34711103Snilay@cs.wisc.edusystem.cpu.branchPred.BTBLookups 191806323 # Number of BTB lookups 34811103Snilay@cs.wisc.edusystem.cpu.branchPred.BTBHits 136128585 # Number of BTB hits 34910585Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 35011103Snilay@cs.wisc.edusystem.cpu.branchPred.BTBHitPct 70.971896 # BTB Hit Percentage 35111103Snilay@cs.wisc.edusystem.cpu.branchPred.usedRAS 31602025 # Number of times the RAS was used to get a target. 35211103Snilay@cs.wisc.edusystem.cpu.branchPred.RASInCorrect 2167880 # Number of incorrect RAS predictions. 35310585Sandreas.hansson@arm.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 35410628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 35510628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 35610628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 35710628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 35810628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 35910628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 36010628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 36110628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 36210585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 36310585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 36410585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 36510585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 36610585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 36710585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 36810585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 36910585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 37010585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 37110585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 37210585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 37310585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 37410585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 37510585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 37610585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 37710585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 37810585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 37910585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 38010585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 38110585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 38210585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 38311103Snilay@cs.wisc.edusystem.cpu.dtb.walker.walks 582770 # Table walker walks requested 38411103Snilay@cs.wisc.edusystem.cpu.dtb.walker.walksLong 582770 # Table walker walks initiated with long descriptors 38511103Snilay@cs.wisc.edusystem.cpu.dtb.walker.walksLongTerminationLevel::Level2 22376 # Level at which table walker walks with long descriptors terminate 38611103Snilay@cs.wisc.edusystem.cpu.dtb.walker.walksLongTerminationLevel::Level3 191329 # Level at which table walker walks with long descriptors terminate 38711103Snilay@cs.wisc.edusystem.cpu.dtb.walker.walkWaitTime::samples 582770 # Table walker wait (enqueue to first request) latency 38811103Snilay@cs.wisc.edusystem.cpu.dtb.walker.walkWaitTime::0 582770 100.00% 100.00% # Table walker wait (enqueue to first request) latency 38911103Snilay@cs.wisc.edusystem.cpu.dtb.walker.walkWaitTime::total 582770 # Table walker wait (enqueue to first request) latency 39011103Snilay@cs.wisc.edusystem.cpu.dtb.walker.walkCompletionTime::samples 213705 # Table walker service (enqueue to completion) latency 39111103Snilay@cs.wisc.edusystem.cpu.dtb.walker.walkCompletionTime::mean 26351.678716 # Table walker service (enqueue to completion) latency 39211103Snilay@cs.wisc.edusystem.cpu.dtb.walker.walkCompletionTime::gmean 22931.447770 # Table walker service (enqueue to completion) latency 39311103Snilay@cs.wisc.edusystem.cpu.dtb.walker.walkCompletionTime::stdev 15578.711548 # Table walker service (enqueue to completion) latency 39411103Snilay@cs.wisc.edusystem.cpu.dtb.walker.walkCompletionTime::0-65535 211142 98.80% 98.80% # Table walker service (enqueue to completion) latency 39511103Snilay@cs.wisc.edusystem.cpu.dtb.walker.walkCompletionTime::65536-131071 2168 1.01% 99.82% # Table walker service (enqueue to completion) latency 39611103Snilay@cs.wisc.edusystem.cpu.dtb.walker.walkCompletionTime::131072-196607 149 0.07% 99.88% # Table walker service (enqueue to completion) latency 39711103Snilay@cs.wisc.edusystem.cpu.dtb.walker.walkCompletionTime::196608-262143 124 0.06% 99.94% # Table walker service (enqueue to completion) latency 39811103Snilay@cs.wisc.edusystem.cpu.dtb.walker.walkCompletionTime::262144-327679 84 0.04% 99.98% # Table walker service (enqueue to completion) latency 39911103Snilay@cs.wisc.edusystem.cpu.dtb.walker.walkCompletionTime::327680-393215 25 0.01% 99.99% # Table walker service (enqueue to completion) latency 40011103Snilay@cs.wisc.edusystem.cpu.dtb.walker.walkCompletionTime::393216-458751 6 0.00% 100.00% # Table walker service (enqueue to completion) latency 40111103Snilay@cs.wisc.edusystem.cpu.dtb.walker.walkCompletionTime::458752-524287 6 0.00% 100.00% # Table walker service (enqueue to completion) latency 40211103Snilay@cs.wisc.edusystem.cpu.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 40311103Snilay@cs.wisc.edusystem.cpu.dtb.walker.walkCompletionTime::total 213705 # Table walker service (enqueue to completion) latency 40410892Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walksPending::samples -58656296 # Table walker pending requests distribution 40510892Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walksPending::0 -58656296 100.00% 100.00% # Table walker pending requests distribution 40610892Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walksPending::total -58656296 # Table walker pending requests distribution 40711103Snilay@cs.wisc.edusystem.cpu.dtb.walker.walkPageSizes::4K 191330 89.53% 89.53% # Table walker page sizes translated 40811103Snilay@cs.wisc.edusystem.cpu.dtb.walker.walkPageSizes::2M 22376 10.47% 100.00% # Table walker page sizes translated 40911103Snilay@cs.wisc.edusystem.cpu.dtb.walker.walkPageSizes::total 213706 # Table walker page sizes translated 41011103Snilay@cs.wisc.edusystem.cpu.dtb.walker.walkRequestOrigin_Requested::Data 582770 # Table walker requests started/completed, data/inst 41110628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 41211103Snilay@cs.wisc.edusystem.cpu.dtb.walker.walkRequestOrigin_Requested::total 582770 # Table walker requests started/completed, data/inst 41311103Snilay@cs.wisc.edusystem.cpu.dtb.walker.walkRequestOrigin_Completed::Data 213706 # Table walker requests started/completed, data/inst 41410628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 41511103Snilay@cs.wisc.edusystem.cpu.dtb.walker.walkRequestOrigin_Completed::total 213706 # Table walker requests started/completed, data/inst 41611103Snilay@cs.wisc.edusystem.cpu.dtb.walker.walkRequestOrigin::total 796476 # Table walker requests started/completed, data/inst 41710585Sandreas.hansson@arm.comsystem.cpu.dtb.inst_hits 0 # ITB inst hits 41810585Sandreas.hansson@arm.comsystem.cpu.dtb.inst_misses 0 # ITB inst misses 41911103Snilay@cs.wisc.edusystem.cpu.dtb.read_hits 183257458 # DTB read hits 42011103Snilay@cs.wisc.edusystem.cpu.dtb.read_misses 481031 # DTB read misses 42111103Snilay@cs.wisc.edusystem.cpu.dtb.write_hits 162586595 # DTB write hits 42211103Snilay@cs.wisc.edusystem.cpu.dtb.write_misses 101739 # DTB write misses 42310585Sandreas.hansson@arm.comsystem.cpu.dtb.flush_tlb 11 # Number of times complete TLB was flushed 42410585Sandreas.hansson@arm.comsystem.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 42510892Sandreas.hansson@arm.comsystem.cpu.dtb.flush_tlb_mva_asid 47231 # Number of times TLB was flushed by MVA & ASID 42610852Sandreas.hansson@arm.comsystem.cpu.dtb.flush_tlb_asid 1111 # Number of times TLB was flushed by ASID 42711103Snilay@cs.wisc.edusystem.cpu.dtb.flush_entries 80339 # Number of entries that have been flushed from TLB 42811103Snilay@cs.wisc.edusystem.cpu.dtb.align_faults 1450 # Number of TLB faults due to alignment restrictions 42911103Snilay@cs.wisc.edusystem.cpu.dtb.prefetch_faults 15121 # Number of TLB faults due to prefetch 43010585Sandreas.hansson@arm.comsystem.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 43111103Snilay@cs.wisc.edusystem.cpu.dtb.perms_faults 23575 # Number of TLB faults due to permissions restrictions 43211103Snilay@cs.wisc.edusystem.cpu.dtb.read_accesses 183738489 # DTB read accesses 43311103Snilay@cs.wisc.edusystem.cpu.dtb.write_accesses 162688334 # DTB write accesses 43410585Sandreas.hansson@arm.comsystem.cpu.dtb.inst_accesses 0 # ITB inst accesses 43511103Snilay@cs.wisc.edusystem.cpu.dtb.hits 345844053 # DTB hits 43611103Snilay@cs.wisc.edusystem.cpu.dtb.misses 582770 # DTB misses 43711103Snilay@cs.wisc.edusystem.cpu.dtb.accesses 346426823 # DTB accesses 43810628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 43910628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 44010628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 44110628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 44210628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 44310628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 44410628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 44510628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 44610585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 44710585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 44810585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 44910585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 45010585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 45110585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 45210585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 45310585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 45410585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 45510585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 45610585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 45710585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 45810585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 45910585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 46010585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 46110585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 46210585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 46310585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 46410585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 46510585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 46610585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 46711103Snilay@cs.wisc.edusystem.cpu.itb.walker.walks 136614 # Table walker walks requested 46811103Snilay@cs.wisc.edusystem.cpu.itb.walker.walksLong 136614 # Table walker walks initiated with long descriptors 46911103Snilay@cs.wisc.edusystem.cpu.itb.walker.walksLongTerminationLevel::Level2 1073 # Level at which table walker walks with long descriptors terminate 47011103Snilay@cs.wisc.edusystem.cpu.itb.walker.walksLongTerminationLevel::Level3 118911 # Level at which table walker walks with long descriptors terminate 47111103Snilay@cs.wisc.edusystem.cpu.itb.walker.walkWaitTime::samples 136614 # Table walker wait (enqueue to first request) latency 47211103Snilay@cs.wisc.edusystem.cpu.itb.walker.walkWaitTime::0 136614 100.00% 100.00% # Table walker wait (enqueue to first request) latency 47311103Snilay@cs.wisc.edusystem.cpu.itb.walker.walkWaitTime::total 136614 # Table walker wait (enqueue to first request) latency 47411103Snilay@cs.wisc.edusystem.cpu.itb.walker.walkCompletionTime::samples 119984 # Table walker service (enqueue to completion) latency 47511103Snilay@cs.wisc.edusystem.cpu.itb.walker.walkCompletionTime::mean 28837.324143 # Table walker service (enqueue to completion) latency 47611103Snilay@cs.wisc.edusystem.cpu.itb.walker.walkCompletionTime::gmean 25253.165818 # Table walker service (enqueue to completion) latency 47711103Snilay@cs.wisc.edusystem.cpu.itb.walker.walkCompletionTime::stdev 17670.490053 # Table walker service (enqueue to completion) latency 47811103Snilay@cs.wisc.edusystem.cpu.itb.walker.walkCompletionTime::0-65535 116985 97.50% 97.50% # Table walker service (enqueue to completion) latency 47911103Snilay@cs.wisc.edusystem.cpu.itb.walker.walkCompletionTime::65536-131071 2707 2.26% 99.76% # Table walker service (enqueue to completion) latency 48011103Snilay@cs.wisc.edusystem.cpu.itb.walker.walkCompletionTime::131072-196607 180 0.15% 99.91% # Table walker service (enqueue to completion) latency 48111103Snilay@cs.wisc.edusystem.cpu.itb.walker.walkCompletionTime::196608-262143 56 0.05% 99.95% # Table walker service (enqueue to completion) latency 48211103Snilay@cs.wisc.edusystem.cpu.itb.walker.walkCompletionTime::262144-327679 24 0.02% 99.97% # Table walker service (enqueue to completion) latency 48311103Snilay@cs.wisc.edusystem.cpu.itb.walker.walkCompletionTime::327680-393215 27 0.02% 100.00% # Table walker service (enqueue to completion) latency 48411103Snilay@cs.wisc.edusystem.cpu.itb.walker.walkCompletionTime::393216-458751 3 0.00% 100.00% # Table walker service (enqueue to completion) latency 48511103Snilay@cs.wisc.edusystem.cpu.itb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 48611103Snilay@cs.wisc.edusystem.cpu.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 48711103Snilay@cs.wisc.edusystem.cpu.itb.walker.walkCompletionTime::total 119984 # Table walker service (enqueue to completion) latency 48810892Sandreas.hansson@arm.comsystem.cpu.itb.walker.walksPending::samples -59528796 # Table walker pending requests distribution 48910892Sandreas.hansson@arm.comsystem.cpu.itb.walker.walksPending::0 -59528796 100.00% 100.00% # Table walker pending requests distribution 49010892Sandreas.hansson@arm.comsystem.cpu.itb.walker.walksPending::total -59528796 # Table walker pending requests distribution 49111103Snilay@cs.wisc.edusystem.cpu.itb.walker.walkPageSizes::4K 118911 99.11% 99.11% # Table walker page sizes translated 49211103Snilay@cs.wisc.edusystem.cpu.itb.walker.walkPageSizes::2M 1073 0.89% 100.00% # Table walker page sizes translated 49311103Snilay@cs.wisc.edusystem.cpu.itb.walker.walkPageSizes::total 119984 # Table walker page sizes translated 49410628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 49511103Snilay@cs.wisc.edusystem.cpu.itb.walker.walkRequestOrigin_Requested::Inst 136614 # Table walker requests started/completed, data/inst 49611103Snilay@cs.wisc.edusystem.cpu.itb.walker.walkRequestOrigin_Requested::total 136614 # Table walker requests started/completed, data/inst 49710628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 49811103Snilay@cs.wisc.edusystem.cpu.itb.walker.walkRequestOrigin_Completed::Inst 119984 # Table walker requests started/completed, data/inst 49911103Snilay@cs.wisc.edusystem.cpu.itb.walker.walkRequestOrigin_Completed::total 119984 # Table walker requests started/completed, data/inst 50011103Snilay@cs.wisc.edusystem.cpu.itb.walker.walkRequestOrigin::total 256598 # Table walker requests started/completed, data/inst 50111103Snilay@cs.wisc.edusystem.cpu.itb.inst_hits 452975639 # ITB inst hits 50211103Snilay@cs.wisc.edusystem.cpu.itb.inst_misses 136614 # ITB inst misses 50310585Sandreas.hansson@arm.comsystem.cpu.itb.read_hits 0 # DTB read hits 50410585Sandreas.hansson@arm.comsystem.cpu.itb.read_misses 0 # DTB read misses 50510585Sandreas.hansson@arm.comsystem.cpu.itb.write_hits 0 # DTB write hits 50610585Sandreas.hansson@arm.comsystem.cpu.itb.write_misses 0 # DTB write misses 50710585Sandreas.hansson@arm.comsystem.cpu.itb.flush_tlb 11 # Number of times complete TLB was flushed 50810585Sandreas.hansson@arm.comsystem.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 50910892Sandreas.hansson@arm.comsystem.cpu.itb.flush_tlb_mva_asid 47231 # Number of times TLB was flushed by MVA & ASID 51010852Sandreas.hansson@arm.comsystem.cpu.itb.flush_tlb_asid 1111 # Number of times TLB was flushed by ASID 51111103Snilay@cs.wisc.edusystem.cpu.itb.flush_entries 57698 # Number of entries that have been flushed from TLB 51210585Sandreas.hansson@arm.comsystem.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 51310585Sandreas.hansson@arm.comsystem.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 51410585Sandreas.hansson@arm.comsystem.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 51511103Snilay@cs.wisc.edusystem.cpu.itb.perms_faults 370160 # Number of TLB faults due to permissions restrictions 51610585Sandreas.hansson@arm.comsystem.cpu.itb.read_accesses 0 # DTB read accesses 51710585Sandreas.hansson@arm.comsystem.cpu.itb.write_accesses 0 # DTB write accesses 51811103Snilay@cs.wisc.edusystem.cpu.itb.inst_accesses 453112253 # ITB inst accesses 51911103Snilay@cs.wisc.edusystem.cpu.itb.hits 452975639 # DTB hits 52011103Snilay@cs.wisc.edusystem.cpu.itb.misses 136614 # DTB misses 52111103Snilay@cs.wisc.edusystem.cpu.itb.accesses 453112253 # DTB accesses 52211103Snilay@cs.wisc.edusystem.cpu.numCycles 2511767999 # number of cpu cycles simulated 52310585Sandreas.hansson@arm.comsystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 52410585Sandreas.hansson@arm.comsystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 52511103Snilay@cs.wisc.edusystem.cpu.committedInsts 949163000 # Number of instructions committed 52611103Snilay@cs.wisc.edusystem.cpu.committedOps 1115282140 # Number of ops (including micro ops) committed 52711103Snilay@cs.wisc.edusystem.cpu.discardedOps 97160712 # Number of ops (including micro ops) which were discarded before commit 52811103Snilay@cs.wisc.edusystem.cpu.numFetchSuspends 7743 # Number of times Execute suspended instruction fetching 52911103Snilay@cs.wisc.edusystem.cpu.quiesceCycles 100877722288 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 53011103Snilay@cs.wisc.edusystem.cpu.cpi 2.646298 # CPI: cycles per instruction 53111103Snilay@cs.wisc.edusystem.cpu.ipc 0.377886 # IPC: instructions per cycle 53210585Sandreas.hansson@arm.comsystem.cpu.kern.inst.arm 0 # number of arm instructions executed 53311103Snilay@cs.wisc.edusystem.cpu.kern.inst.quiesce 19481 # number of quiesce instructions executed 53411103Snilay@cs.wisc.edusystem.cpu.tickCycles 1790897935 # Number of cycles that the object actually ticked 53511103Snilay@cs.wisc.edusystem.cpu.idleCycles 720870064 # Total number of cycles that the object has spent stopped 53611103Snilay@cs.wisc.edusystem.cpu.dcache.tags.replacements 11142195 # number of replacements 53711103Snilay@cs.wisc.edusystem.cpu.dcache.tags.tagsinuse 511.957822 # Cycle average of tags in use 53811103Snilay@cs.wisc.edusystem.cpu.dcache.tags.total_refs 329410408 # Total number of references to valid blocks. 53911103Snilay@cs.wisc.edusystem.cpu.dcache.tags.sampled_refs 11142707 # Sample count of references to valid blocks. 54011103Snilay@cs.wisc.edusystem.cpu.dcache.tags.avg_refs 29.562871 # Average number of references to valid blocks. 54110892Sandreas.hansson@arm.comsystem.cpu.dcache.tags.warmup_cycle 4277412500 # Cycle when the warmup percentage was hit. 54211103Snilay@cs.wisc.edusystem.cpu.dcache.tags.occ_blocks::cpu.data 511.957822 # Average occupied blocks per requestor 54310892Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_percent::cpu.data 0.999918 # Average percentage of cache occupancy 54410892Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_percent::total 0.999918 # Average percentage of cache occupancy 54510585Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 54611103Snilay@cs.wisc.edusystem.cpu.dcache.tags.age_task_id_blocks_1024::0 70 # Occupied blocks per task id 54711103Snilay@cs.wisc.edusystem.cpu.dcache.tags.age_task_id_blocks_1024::1 385 # Occupied blocks per task id 54811103Snilay@cs.wisc.edusystem.cpu.dcache.tags.age_task_id_blocks_1024::2 57 # Occupied blocks per task id 54910585Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 55011103Snilay@cs.wisc.edusystem.cpu.dcache.tags.tag_accesses 1384553632 # Number of tag accesses 55111103Snilay@cs.wisc.edusystem.cpu.dcache.tags.data_accesses 1384553632 # Number of data accesses 55211103Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_hits::cpu.data 168394927 # number of ReadReq hits 55311103Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_hits::total 168394927 # number of ReadReq hits 55411103Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_hits::cpu.data 151754199 # number of WriteReq hits 55511103Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_hits::total 151754199 # number of WriteReq hits 55611103Snilay@cs.wisc.edusystem.cpu.dcache.SoftPFReq_hits::cpu.data 523439 # number of SoftPFReq hits 55711103Snilay@cs.wisc.edusystem.cpu.dcache.SoftPFReq_hits::total 523439 # number of SoftPFReq hits 55811103Snilay@cs.wisc.edusystem.cpu.dcache.WriteLineReq_hits::cpu.data 336679 # number of WriteLineReq hits 55911103Snilay@cs.wisc.edusystem.cpu.dcache.WriteLineReq_hits::total 336679 # number of WriteLineReq hits 56011103Snilay@cs.wisc.edusystem.cpu.dcache.LoadLockedReq_hits::cpu.data 4017108 # number of LoadLockedReq hits 56111103Snilay@cs.wisc.edusystem.cpu.dcache.LoadLockedReq_hits::total 4017108 # number of LoadLockedReq hits 56211103Snilay@cs.wisc.edusystem.cpu.dcache.StoreCondReq_hits::cpu.data 4334477 # number of StoreCondReq hits 56311103Snilay@cs.wisc.edusystem.cpu.dcache.StoreCondReq_hits::total 4334477 # number of StoreCondReq hits 56411103Snilay@cs.wisc.edusystem.cpu.dcache.demand_hits::cpu.data 320149126 # number of demand (read+write) hits 56511103Snilay@cs.wisc.edusystem.cpu.dcache.demand_hits::total 320149126 # number of demand (read+write) hits 56611103Snilay@cs.wisc.edusystem.cpu.dcache.overall_hits::cpu.data 320672565 # number of overall hits 56711103Snilay@cs.wisc.edusystem.cpu.dcache.overall_hits::total 320672565 # number of overall hits 56811103Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_misses::cpu.data 6628843 # number of ReadReq misses 56911103Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_misses::total 6628843 # number of ReadReq misses 57011103Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_misses::cpu.data 4317749 # number of WriteReq misses 57111103Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_misses::total 4317749 # number of WriteReq misses 57211103Snilay@cs.wisc.edusystem.cpu.dcache.SoftPFReq_misses::cpu.data 1481094 # number of SoftPFReq misses 57311103Snilay@cs.wisc.edusystem.cpu.dcache.SoftPFReq_misses::total 1481094 # number of SoftPFReq misses 57411103Snilay@cs.wisc.edusystem.cpu.dcache.WriteLineReq_misses::cpu.data 1245106 # number of WriteLineReq misses 57511103Snilay@cs.wisc.edusystem.cpu.dcache.WriteLineReq_misses::total 1245106 # number of WriteLineReq misses 57611103Snilay@cs.wisc.edusystem.cpu.dcache.LoadLockedReq_misses::cpu.data 319103 # number of LoadLockedReq misses 57711103Snilay@cs.wisc.edusystem.cpu.dcache.LoadLockedReq_misses::total 319103 # number of LoadLockedReq misses 57810892Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses 57910892Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses 58011103Snilay@cs.wisc.edusystem.cpu.dcache.demand_misses::cpu.data 10946592 # number of demand (read+write) misses 58111103Snilay@cs.wisc.edusystem.cpu.dcache.demand_misses::total 10946592 # number of demand (read+write) misses 58211103Snilay@cs.wisc.edusystem.cpu.dcache.overall_misses::cpu.data 12427686 # number of overall misses 58311103Snilay@cs.wisc.edusystem.cpu.dcache.overall_misses::total 12427686 # number of overall misses 58411103Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_miss_latency::cpu.data 107264639000 # number of ReadReq miss cycles 58511103Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_miss_latency::total 107264639000 # number of ReadReq miss cycles 58611103Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_miss_latency::cpu.data 153170066000 # number of WriteReq miss cycles 58711103Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_miss_latency::total 153170066000 # number of WriteReq miss cycles 58811103Snilay@cs.wisc.edusystem.cpu.dcache.WriteLineReq_miss_latency::cpu.data 58641269000 # number of WriteLineReq miss cycles 58911103Snilay@cs.wisc.edusystem.cpu.dcache.WriteLineReq_miss_latency::total 58641269000 # number of WriteLineReq miss cycles 59011103Snilay@cs.wisc.edusystem.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 4837420500 # number of LoadLockedReq miss cycles 59111103Snilay@cs.wisc.edusystem.cpu.dcache.LoadLockedReq_miss_latency::total 4837420500 # number of LoadLockedReq miss cycles 59210892Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_miss_latency::cpu.data 115500 # number of StoreCondReq miss cycles 59310892Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_miss_latency::total 115500 # number of StoreCondReq miss cycles 59411103Snilay@cs.wisc.edusystem.cpu.dcache.demand_miss_latency::cpu.data 260434705000 # number of demand (read+write) miss cycles 59511103Snilay@cs.wisc.edusystem.cpu.dcache.demand_miss_latency::total 260434705000 # number of demand (read+write) miss cycles 59611103Snilay@cs.wisc.edusystem.cpu.dcache.overall_miss_latency::cpu.data 260434705000 # number of overall miss cycles 59711103Snilay@cs.wisc.edusystem.cpu.dcache.overall_miss_latency::total 260434705000 # number of overall miss cycles 59811103Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_accesses::cpu.data 175023770 # number of ReadReq accesses(hits+misses) 59911103Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_accesses::total 175023770 # number of ReadReq accesses(hits+misses) 60011103Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_accesses::cpu.data 156071948 # number of WriteReq accesses(hits+misses) 60111103Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_accesses::total 156071948 # number of WriteReq accesses(hits+misses) 60211103Snilay@cs.wisc.edusystem.cpu.dcache.SoftPFReq_accesses::cpu.data 2004533 # number of SoftPFReq accesses(hits+misses) 60311103Snilay@cs.wisc.edusystem.cpu.dcache.SoftPFReq_accesses::total 2004533 # number of SoftPFReq accesses(hits+misses) 60411103Snilay@cs.wisc.edusystem.cpu.dcache.WriteLineReq_accesses::cpu.data 1581785 # number of WriteLineReq accesses(hits+misses) 60511103Snilay@cs.wisc.edusystem.cpu.dcache.WriteLineReq_accesses::total 1581785 # number of WriteLineReq accesses(hits+misses) 60611103Snilay@cs.wisc.edusystem.cpu.dcache.LoadLockedReq_accesses::cpu.data 4336211 # number of LoadLockedReq accesses(hits+misses) 60711103Snilay@cs.wisc.edusystem.cpu.dcache.LoadLockedReq_accesses::total 4336211 # number of LoadLockedReq accesses(hits+misses) 60811103Snilay@cs.wisc.edusystem.cpu.dcache.StoreCondReq_accesses::cpu.data 4334479 # number of StoreCondReq accesses(hits+misses) 60911103Snilay@cs.wisc.edusystem.cpu.dcache.StoreCondReq_accesses::total 4334479 # number of StoreCondReq accesses(hits+misses) 61011103Snilay@cs.wisc.edusystem.cpu.dcache.demand_accesses::cpu.data 331095718 # number of demand (read+write) accesses 61111103Snilay@cs.wisc.edusystem.cpu.dcache.demand_accesses::total 331095718 # number of demand (read+write) accesses 61211103Snilay@cs.wisc.edusystem.cpu.dcache.overall_accesses::cpu.data 333100251 # number of overall (read+write) accesses 61311103Snilay@cs.wisc.edusystem.cpu.dcache.overall_accesses::total 333100251 # number of overall (read+write) accesses 61411103Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.037874 # miss rate for ReadReq accesses 61511103Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_miss_rate::total 0.037874 # miss rate for ReadReq accesses 61611103Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.027665 # miss rate for WriteReq accesses 61711103Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_miss_rate::total 0.027665 # miss rate for WriteReq accesses 61811103Snilay@cs.wisc.edusystem.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.738872 # miss rate for SoftPFReq accesses 61911103Snilay@cs.wisc.edusystem.cpu.dcache.SoftPFReq_miss_rate::total 0.738872 # miss rate for SoftPFReq accesses 62011103Snilay@cs.wisc.edusystem.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.787152 # miss rate for WriteLineReq accesses 62111103Snilay@cs.wisc.edusystem.cpu.dcache.WriteLineReq_miss_rate::total 0.787152 # miss rate for WriteLineReq accesses 62211103Snilay@cs.wisc.edusystem.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.073590 # miss rate for LoadLockedReq accesses 62311103Snilay@cs.wisc.edusystem.cpu.dcache.LoadLockedReq_miss_rate::total 0.073590 # miss rate for LoadLockedReq accesses 62410636Snilay@cs.wisc.edusystem.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000000 # miss rate for StoreCondReq accesses 62510585Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_miss_rate::total 0.000000 # miss rate for StoreCondReq accesses 62611103Snilay@cs.wisc.edusystem.cpu.dcache.demand_miss_rate::cpu.data 0.033062 # miss rate for demand accesses 62711103Snilay@cs.wisc.edusystem.cpu.dcache.demand_miss_rate::total 0.033062 # miss rate for demand accesses 62811103Snilay@cs.wisc.edusystem.cpu.dcache.overall_miss_rate::cpu.data 0.037309 # miss rate for overall accesses 62911103Snilay@cs.wisc.edusystem.cpu.dcache.overall_miss_rate::total 0.037309 # miss rate for overall accesses 63011103Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16181.502413 # average ReadReq miss latency 63111103Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_avg_miss_latency::total 16181.502413 # average ReadReq miss latency 63211103Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35474.518320 # average WriteReq miss latency 63311103Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_avg_miss_latency::total 35474.518320 # average WriteReq miss latency 63411103Snilay@cs.wisc.edusystem.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 47097.410983 # average WriteLineReq miss latency 63511103Snilay@cs.wisc.edusystem.cpu.dcache.WriteLineReq_avg_miss_latency::total 47097.410983 # average WriteLineReq miss latency 63611103Snilay@cs.wisc.edusystem.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15159.432848 # average LoadLockedReq miss latency 63711103Snilay@cs.wisc.edusystem.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15159.432848 # average LoadLockedReq miss latency 63810892Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 57750 # average StoreCondReq miss latency 63910892Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_avg_miss_latency::total 57750 # average StoreCondReq miss latency 64011103Snilay@cs.wisc.edusystem.cpu.dcache.demand_avg_miss_latency::cpu.data 23791.395989 # average overall miss latency 64111103Snilay@cs.wisc.edusystem.cpu.dcache.demand_avg_miss_latency::total 23791.395989 # average overall miss latency 64211103Snilay@cs.wisc.edusystem.cpu.dcache.overall_avg_miss_latency::cpu.data 20956.009429 # average overall miss latency 64311103Snilay@cs.wisc.edusystem.cpu.dcache.overall_avg_miss_latency::total 20956.009429 # average overall miss latency 64410892Sandreas.hansson@arm.comsystem.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 64510585Sandreas.hansson@arm.comsystem.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 64610892Sandreas.hansson@arm.comsystem.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 64710585Sandreas.hansson@arm.comsystem.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 64810892Sandreas.hansson@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 64910585Sandreas.hansson@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 65010585Sandreas.hansson@arm.comsystem.cpu.dcache.fast_writes 0 # number of fast writes performed 65110585Sandreas.hansson@arm.comsystem.cpu.dcache.cache_copies 0 # number of cache copies performed 65211103Snilay@cs.wisc.edusystem.cpu.dcache.writebacks::writebacks 8554549 # number of writebacks 65311103Snilay@cs.wisc.edusystem.cpu.dcache.writebacks::total 8554549 # number of writebacks 65411103Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_mshr_hits::cpu.data 817761 # number of ReadReq MSHR hits 65511103Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_mshr_hits::total 817761 # number of ReadReq MSHR hits 65611103Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_mshr_hits::cpu.data 1903794 # number of WriteReq MSHR hits 65711103Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_mshr_hits::total 1903794 # number of WriteReq MSHR hits 65811103Snilay@cs.wisc.edusystem.cpu.dcache.WriteLineReq_mshr_hits::cpu.data 151 # number of WriteLineReq MSHR hits 65911103Snilay@cs.wisc.edusystem.cpu.dcache.WriteLineReq_mshr_hits::total 151 # number of WriteLineReq MSHR hits 66011103Snilay@cs.wisc.edusystem.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 70489 # number of LoadLockedReq MSHR hits 66111103Snilay@cs.wisc.edusystem.cpu.dcache.LoadLockedReq_mshr_hits::total 70489 # number of LoadLockedReq MSHR hits 66211103Snilay@cs.wisc.edusystem.cpu.dcache.demand_mshr_hits::cpu.data 2721555 # number of demand (read+write) MSHR hits 66311103Snilay@cs.wisc.edusystem.cpu.dcache.demand_mshr_hits::total 2721555 # number of demand (read+write) MSHR hits 66411103Snilay@cs.wisc.edusystem.cpu.dcache.overall_mshr_hits::cpu.data 2721555 # number of overall MSHR hits 66511103Snilay@cs.wisc.edusystem.cpu.dcache.overall_mshr_hits::total 2721555 # number of overall MSHR hits 66611103Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_mshr_misses::cpu.data 5811082 # number of ReadReq MSHR misses 66711103Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_mshr_misses::total 5811082 # number of ReadReq MSHR misses 66811103Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_mshr_misses::cpu.data 2413955 # number of WriteReq MSHR misses 66911103Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_mshr_misses::total 2413955 # number of WriteReq MSHR misses 67011103Snilay@cs.wisc.edusystem.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1473693 # number of SoftPFReq MSHR misses 67111103Snilay@cs.wisc.edusystem.cpu.dcache.SoftPFReq_mshr_misses::total 1473693 # number of SoftPFReq MSHR misses 67211103Snilay@cs.wisc.edusystem.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1244955 # number of WriteLineReq MSHR misses 67311103Snilay@cs.wisc.edusystem.cpu.dcache.WriteLineReq_mshr_misses::total 1244955 # number of WriteLineReq MSHR misses 67411103Snilay@cs.wisc.edusystem.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 248614 # number of LoadLockedReq MSHR misses 67511103Snilay@cs.wisc.edusystem.cpu.dcache.LoadLockedReq_mshr_misses::total 248614 # number of LoadLockedReq MSHR misses 67610892Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses 67710892Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses 67811103Snilay@cs.wisc.edusystem.cpu.dcache.demand_mshr_misses::cpu.data 8225037 # number of demand (read+write) MSHR misses 67911103Snilay@cs.wisc.edusystem.cpu.dcache.demand_mshr_misses::total 8225037 # number of demand (read+write) MSHR misses 68011103Snilay@cs.wisc.edusystem.cpu.dcache.overall_mshr_misses::cpu.data 9698730 # number of overall MSHR misses 68111103Snilay@cs.wisc.edusystem.cpu.dcache.overall_mshr_misses::total 9698730 # number of overall MSHR misses 68210892Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33699 # number of ReadReq MSHR uncacheable 68310892Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_uncacheable::total 33699 # number of ReadReq MSHR uncacheable 68410892Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33707 # number of WriteReq MSHR uncacheable 68510892Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_uncacheable::total 33707 # number of WriteReq MSHR uncacheable 68610892Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67406 # number of overall MSHR uncacheable misses 68710892Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_uncacheable_misses::total 67406 # number of overall MSHR uncacheable misses 68811103Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 87944699500 # number of ReadReq MSHR miss cycles 68911103Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_mshr_miss_latency::total 87944699500 # number of ReadReq MSHR miss cycles 69011103Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 80337194000 # number of WriteReq MSHR miss cycles 69111103Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_mshr_miss_latency::total 80337194000 # number of WriteReq MSHR miss cycles 69211103Snilay@cs.wisc.edusystem.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 23656791000 # number of SoftPFReq MSHR miss cycles 69311103Snilay@cs.wisc.edusystem.cpu.dcache.SoftPFReq_mshr_miss_latency::total 23656791000 # number of SoftPFReq MSHR miss cycles 69411103Snilay@cs.wisc.edusystem.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 57392051500 # number of WriteLineReq MSHR miss cycles 69511103Snilay@cs.wisc.edusystem.cpu.dcache.WriteLineReq_mshr_miss_latency::total 57392051500 # number of WriteLineReq MSHR miss cycles 69611103Snilay@cs.wisc.edusystem.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3386354500 # number of LoadLockedReq MSHR miss cycles 69711103Snilay@cs.wisc.edusystem.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3386354500 # number of LoadLockedReq MSHR miss cycles 69810892Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 113500 # number of StoreCondReq MSHR miss cycles 69910892Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_mshr_miss_latency::total 113500 # number of StoreCondReq MSHR miss cycles 70011103Snilay@cs.wisc.edusystem.cpu.dcache.demand_mshr_miss_latency::cpu.data 168281893500 # number of demand (read+write) MSHR miss cycles 70111103Snilay@cs.wisc.edusystem.cpu.dcache.demand_mshr_miss_latency::total 168281893500 # number of demand (read+write) MSHR miss cycles 70211103Snilay@cs.wisc.edusystem.cpu.dcache.overall_mshr_miss_latency::cpu.data 191938684500 # number of overall MSHR miss cycles 70311103Snilay@cs.wisc.edusystem.cpu.dcache.overall_mshr_miss_latency::total 191938684500 # number of overall MSHR miss cycles 70411103Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5830552000 # number of ReadReq MSHR uncacheable cycles 70511103Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5830552000 # number of ReadReq MSHR uncacheable cycles 70611103Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5692063000 # number of WriteReq MSHR uncacheable cycles 70711103Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5692063000 # number of WriteReq MSHR uncacheable cycles 70811103Snilay@cs.wisc.edusystem.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11522615000 # number of overall MSHR uncacheable cycles 70911103Snilay@cs.wisc.edusystem.cpu.dcache.overall_mshr_uncacheable_latency::total 11522615000 # number of overall MSHR uncacheable cycles 71011103Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.033202 # mshr miss rate for ReadReq accesses 71111103Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_mshr_miss_rate::total 0.033202 # mshr miss rate for ReadReq accesses 71211103Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015467 # mshr miss rate for WriteReq accesses 71311103Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015467 # mshr miss rate for WriteReq accesses 71411103Snilay@cs.wisc.edusystem.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.735180 # mshr miss rate for SoftPFReq accesses 71511103Snilay@cs.wisc.edusystem.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.735180 # mshr miss rate for SoftPFReq accesses 71611103Snilay@cs.wisc.edusystem.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.787057 # mshr miss rate for WriteLineReq accesses 71711103Snilay@cs.wisc.edusystem.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.787057 # mshr miss rate for WriteLineReq accesses 71811103Snilay@cs.wisc.edusystem.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.057334 # mshr miss rate for LoadLockedReq accesses 71911103Snilay@cs.wisc.edusystem.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.057334 # mshr miss rate for LoadLockedReq accesses 72010636Snilay@cs.wisc.edusystem.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000000 # mshr miss rate for StoreCondReq accesses 72110585Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000000 # mshr miss rate for StoreCondReq accesses 72211103Snilay@cs.wisc.edusystem.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.024842 # mshr miss rate for demand accesses 72311103Snilay@cs.wisc.edusystem.cpu.dcache.demand_mshr_miss_rate::total 0.024842 # mshr miss rate for demand accesses 72411103Snilay@cs.wisc.edusystem.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.029117 # mshr miss rate for overall accesses 72511103Snilay@cs.wisc.edusystem.cpu.dcache.overall_mshr_miss_rate::total 0.029117 # mshr miss rate for overall accesses 72611103Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15133.962918 # average ReadReq mshr miss latency 72711103Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15133.962918 # average ReadReq mshr miss latency 72811103Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33280.319641 # average WriteReq mshr miss latency 72911103Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33280.319641 # average WriteReq mshr miss latency 73011103Snilay@cs.wisc.edusystem.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16052.726721 # average SoftPFReq mshr miss latency 73111103Snilay@cs.wisc.edusystem.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16052.726721 # average SoftPFReq mshr miss latency 73211103Snilay@cs.wisc.edusystem.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 46099.699588 # average WriteLineReq mshr miss latency 73311103Snilay@cs.wisc.edusystem.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 46099.699588 # average WriteLineReq mshr miss latency 73411103Snilay@cs.wisc.edusystem.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13620.932450 # average LoadLockedReq mshr miss latency 73511103Snilay@cs.wisc.edusystem.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13620.932450 # average LoadLockedReq mshr miss latency 73610892Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 56750 # average StoreCondReq mshr miss latency 73710892Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 56750 # average StoreCondReq mshr miss latency 73811103Snilay@cs.wisc.edusystem.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20459.712643 # average overall mshr miss latency 73911103Snilay@cs.wisc.edusystem.cpu.dcache.demand_avg_mshr_miss_latency::total 20459.712643 # average overall mshr miss latency 74011103Snilay@cs.wisc.edusystem.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19790.084320 # average overall mshr miss latency 74111103Snilay@cs.wisc.edusystem.cpu.dcache.overall_avg_mshr_miss_latency::total 19790.084320 # average overall mshr miss latency 74211103Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 173018.546544 # average ReadReq mshr uncacheable latency 74311103Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 173018.546544 # average ReadReq mshr uncacheable latency 74411103Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 168868.869968 # average WriteReq mshr uncacheable latency 74511103Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 168868.869968 # average WriteReq mshr uncacheable latency 74611103Snilay@cs.wisc.edusystem.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 170943.462006 # average overall mshr uncacheable latency 74711103Snilay@cs.wisc.edusystem.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 170943.462006 # average overall mshr uncacheable latency 74810585Sandreas.hansson@arm.comsystem.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 74911103Snilay@cs.wisc.edusystem.cpu.icache.tags.replacements 24575522 # number of replacements 75011103Snilay@cs.wisc.edusystem.cpu.icache.tags.tagsinuse 511.918698 # Cycle average of tags in use 75111103Snilay@cs.wisc.edusystem.cpu.icache.tags.total_refs 428017274 # Total number of references to valid blocks. 75211103Snilay@cs.wisc.edusystem.cpu.icache.tags.sampled_refs 24576034 # Sample count of references to valid blocks. 75311103Snilay@cs.wisc.edusystem.cpu.icache.tags.avg_refs 17.416043 # Average number of references to valid blocks. 75411103Snilay@cs.wisc.edusystem.cpu.icache.tags.warmup_cycle 26893274500 # Cycle when the warmup percentage was hit. 75511103Snilay@cs.wisc.edusystem.cpu.icache.tags.occ_blocks::cpu.inst 511.918698 # Average occupied blocks per requestor 75610892Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_percent::cpu.inst 0.999841 # Average percentage of cache occupancy 75710892Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_percent::total 0.999841 # Average percentage of cache occupancy 75810585Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 75911103Snilay@cs.wisc.edusystem.cpu.icache.tags.age_task_id_blocks_1024::0 95 # Occupied blocks per task id 76011103Snilay@cs.wisc.edusystem.cpu.icache.tags.age_task_id_blocks_1024::1 299 # Occupied blocks per task id 76110892Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::2 118 # Occupied blocks per task id 76210585Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 76311103Snilay@cs.wisc.edusystem.cpu.icache.tags.tag_accesses 477169361 # Number of tag accesses 76411103Snilay@cs.wisc.edusystem.cpu.icache.tags.data_accesses 477169361 # Number of data accesses 76511103Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_hits::cpu.inst 428017274 # number of ReadReq hits 76611103Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_hits::total 428017274 # number of ReadReq hits 76711103Snilay@cs.wisc.edusystem.cpu.icache.demand_hits::cpu.inst 428017274 # number of demand (read+write) hits 76811103Snilay@cs.wisc.edusystem.cpu.icache.demand_hits::total 428017274 # number of demand (read+write) hits 76911103Snilay@cs.wisc.edusystem.cpu.icache.overall_hits::cpu.inst 428017274 # number of overall hits 77011103Snilay@cs.wisc.edusystem.cpu.icache.overall_hits::total 428017274 # number of overall hits 77111103Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_misses::cpu.inst 24576044 # number of ReadReq misses 77211103Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_misses::total 24576044 # number of ReadReq misses 77311103Snilay@cs.wisc.edusystem.cpu.icache.demand_misses::cpu.inst 24576044 # number of demand (read+write) misses 77411103Snilay@cs.wisc.edusystem.cpu.icache.demand_misses::total 24576044 # number of demand (read+write) misses 77511103Snilay@cs.wisc.edusystem.cpu.icache.overall_misses::cpu.inst 24576044 # number of overall misses 77611103Snilay@cs.wisc.edusystem.cpu.icache.overall_misses::total 24576044 # number of overall misses 77711103Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_miss_latency::cpu.inst 327136040500 # number of ReadReq miss cycles 77811103Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_miss_latency::total 327136040500 # number of ReadReq miss cycles 77911103Snilay@cs.wisc.edusystem.cpu.icache.demand_miss_latency::cpu.inst 327136040500 # number of demand (read+write) miss cycles 78011103Snilay@cs.wisc.edusystem.cpu.icache.demand_miss_latency::total 327136040500 # number of demand (read+write) miss cycles 78111103Snilay@cs.wisc.edusystem.cpu.icache.overall_miss_latency::cpu.inst 327136040500 # number of overall miss cycles 78211103Snilay@cs.wisc.edusystem.cpu.icache.overall_miss_latency::total 327136040500 # number of overall miss cycles 78311103Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_accesses::cpu.inst 452593318 # number of ReadReq accesses(hits+misses) 78411103Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_accesses::total 452593318 # number of ReadReq accesses(hits+misses) 78511103Snilay@cs.wisc.edusystem.cpu.icache.demand_accesses::cpu.inst 452593318 # number of demand (read+write) accesses 78611103Snilay@cs.wisc.edusystem.cpu.icache.demand_accesses::total 452593318 # number of demand (read+write) accesses 78711103Snilay@cs.wisc.edusystem.cpu.icache.overall_accesses::cpu.inst 452593318 # number of overall (read+write) accesses 78811103Snilay@cs.wisc.edusystem.cpu.icache.overall_accesses::total 452593318 # number of overall (read+write) accesses 78911103Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.054301 # miss rate for ReadReq accesses 79011103Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_miss_rate::total 0.054301 # miss rate for ReadReq accesses 79111103Snilay@cs.wisc.edusystem.cpu.icache.demand_miss_rate::cpu.inst 0.054301 # miss rate for demand accesses 79211103Snilay@cs.wisc.edusystem.cpu.icache.demand_miss_rate::total 0.054301 # miss rate for demand accesses 79311103Snilay@cs.wisc.edusystem.cpu.icache.overall_miss_rate::cpu.inst 0.054301 # miss rate for overall accesses 79411103Snilay@cs.wisc.edusystem.cpu.icache.overall_miss_rate::total 0.054301 # miss rate for overall accesses 79511103Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13311.175733 # average ReadReq miss latency 79611103Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_avg_miss_latency::total 13311.175733 # average ReadReq miss latency 79711103Snilay@cs.wisc.edusystem.cpu.icache.demand_avg_miss_latency::cpu.inst 13311.175733 # average overall miss latency 79811103Snilay@cs.wisc.edusystem.cpu.icache.demand_avg_miss_latency::total 13311.175733 # average overall miss latency 79911103Snilay@cs.wisc.edusystem.cpu.icache.overall_avg_miss_latency::cpu.inst 13311.175733 # average overall miss latency 80011103Snilay@cs.wisc.edusystem.cpu.icache.overall_avg_miss_latency::total 13311.175733 # average overall miss latency 80110585Sandreas.hansson@arm.comsystem.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 80210585Sandreas.hansson@arm.comsystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 80310585Sandreas.hansson@arm.comsystem.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 80410585Sandreas.hansson@arm.comsystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 80510585Sandreas.hansson@arm.comsystem.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 80610585Sandreas.hansson@arm.comsystem.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 80710585Sandreas.hansson@arm.comsystem.cpu.icache.fast_writes 0 # number of fast writes performed 80810585Sandreas.hansson@arm.comsystem.cpu.icache.cache_copies 0 # number of cache copies performed 80911103Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_mshr_misses::cpu.inst 24576044 # number of ReadReq MSHR misses 81011103Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_mshr_misses::total 24576044 # number of ReadReq MSHR misses 81111103Snilay@cs.wisc.edusystem.cpu.icache.demand_mshr_misses::cpu.inst 24576044 # number of demand (read+write) MSHR misses 81211103Snilay@cs.wisc.edusystem.cpu.icache.demand_mshr_misses::total 24576044 # number of demand (read+write) MSHR misses 81311103Snilay@cs.wisc.edusystem.cpu.icache.overall_mshr_misses::cpu.inst 24576044 # number of overall MSHR misses 81411103Snilay@cs.wisc.edusystem.cpu.icache.overall_mshr_misses::total 24576044 # number of overall MSHR misses 81510892Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 52295 # number of ReadReq MSHR uncacheable 81610892Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_uncacheable::total 52295 # number of ReadReq MSHR uncacheable 81710892Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 52295 # number of overall MSHR uncacheable misses 81810892Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_uncacheable_misses::total 52295 # number of overall MSHR uncacheable misses 81911103Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 302559997500 # number of ReadReq MSHR miss cycles 82011103Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_mshr_miss_latency::total 302559997500 # number of ReadReq MSHR miss cycles 82111103Snilay@cs.wisc.edusystem.cpu.icache.demand_mshr_miss_latency::cpu.inst 302559997500 # number of demand (read+write) MSHR miss cycles 82211103Snilay@cs.wisc.edusystem.cpu.icache.demand_mshr_miss_latency::total 302559997500 # number of demand (read+write) MSHR miss cycles 82311103Snilay@cs.wisc.edusystem.cpu.icache.overall_mshr_miss_latency::cpu.inst 302559997500 # number of overall MSHR miss cycles 82411103Snilay@cs.wisc.edusystem.cpu.icache.overall_mshr_miss_latency::total 302559997500 # number of overall MSHR miss cycles 82510892Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 4042938500 # number of ReadReq MSHR uncacheable cycles 82610892Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_uncacheable_latency::total 4042938500 # number of ReadReq MSHR uncacheable cycles 82710892Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 4042938500 # number of overall MSHR uncacheable cycles 82810892Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_uncacheable_latency::total 4042938500 # number of overall MSHR uncacheable cycles 82911103Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.054301 # mshr miss rate for ReadReq accesses 83011103Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_mshr_miss_rate::total 0.054301 # mshr miss rate for ReadReq accesses 83111103Snilay@cs.wisc.edusystem.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.054301 # mshr miss rate for demand accesses 83211103Snilay@cs.wisc.edusystem.cpu.icache.demand_mshr_miss_rate::total 0.054301 # mshr miss rate for demand accesses 83311103Snilay@cs.wisc.edusystem.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.054301 # mshr miss rate for overall accesses 83411103Snilay@cs.wisc.edusystem.cpu.icache.overall_mshr_miss_rate::total 0.054301 # mshr miss rate for overall accesses 83511103Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12311.175773 # average ReadReq mshr miss latency 83611103Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12311.175773 # average ReadReq mshr miss latency 83711103Snilay@cs.wisc.edusystem.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12311.175773 # average overall mshr miss latency 83811103Snilay@cs.wisc.edusystem.cpu.icache.demand_avg_mshr_miss_latency::total 12311.175773 # average overall mshr miss latency 83911103Snilay@cs.wisc.edusystem.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12311.175773 # average overall mshr miss latency 84011103Snilay@cs.wisc.edusystem.cpu.icache.overall_avg_mshr_miss_latency::total 12311.175773 # average overall mshr miss latency 84110892Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 77310.230424 # average ReadReq mshr uncacheable latency 84210892Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 77310.230424 # average ReadReq mshr uncacheable latency 84310892Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 77310.230424 # average overall mshr uncacheable latency 84410892Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_uncacheable_latency::total 77310.230424 # average overall mshr uncacheable latency 84510585Sandreas.hansson@arm.comsystem.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 84611103Snilay@cs.wisc.edusystem.cpu.l2cache.tags.replacements 1607082 # number of replacements 84711103Snilay@cs.wisc.edusystem.cpu.l2cache.tags.tagsinuse 65318.726670 # Cycle average of tags in use 84811103Snilay@cs.wisc.edusystem.cpu.l2cache.tags.total_refs 67354503 # Total number of references to valid blocks. 84911103Snilay@cs.wisc.edusystem.cpu.l2cache.tags.sampled_refs 1670310 # Sample count of references to valid blocks. 85011103Snilay@cs.wisc.edusystem.cpu.l2cache.tags.avg_refs 40.324552 # Average number of references to valid blocks. 85111103Snilay@cs.wisc.edusystem.cpu.l2cache.tags.warmup_cycle 24502286000 # Cycle when the warmup percentage was hit. 85211103Snilay@cs.wisc.edusystem.cpu.l2cache.tags.occ_blocks::writebacks 36002.307210 # Average occupied blocks per requestor 85311103Snilay@cs.wisc.edusystem.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 335.180696 # Average occupied blocks per requestor 85411103Snilay@cs.wisc.edusystem.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 433.791675 # Average occupied blocks per requestor 85511103Snilay@cs.wisc.edusystem.cpu.l2cache.tags.occ_blocks::cpu.inst 8203.980766 # Average occupied blocks per requestor 85611103Snilay@cs.wisc.edusystem.cpu.l2cache.tags.occ_blocks::cpu.data 20343.466323 # Average occupied blocks per requestor 85711103Snilay@cs.wisc.edusystem.cpu.l2cache.tags.occ_percent::writebacks 0.549352 # Average percentage of cache occupancy 85811103Snilay@cs.wisc.edusystem.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.005114 # Average percentage of cache occupancy 85911103Snilay@cs.wisc.edusystem.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.006619 # Average percentage of cache occupancy 86011103Snilay@cs.wisc.edusystem.cpu.l2cache.tags.occ_percent::cpu.inst 0.125183 # Average percentage of cache occupancy 86111103Snilay@cs.wisc.edusystem.cpu.l2cache.tags.occ_percent::cpu.data 0.310417 # Average percentage of cache occupancy 86211103Snilay@cs.wisc.edusystem.cpu.l2cache.tags.occ_percent::total 0.996685 # Average percentage of cache occupancy 86311103Snilay@cs.wisc.edusystem.cpu.l2cache.tags.occ_task_id_blocks::1023 219 # Occupied blocks per task id 86411103Snilay@cs.wisc.edusystem.cpu.l2cache.tags.occ_task_id_blocks::1024 63009 # Occupied blocks per task id 86510892Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id 86611103Snilay@cs.wisc.edusystem.cpu.l2cache.tags.age_task_id_blocks_1023::4 218 # Occupied blocks per task id 86711103Snilay@cs.wisc.edusystem.cpu.l2cache.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id 86811103Snilay@cs.wisc.edusystem.cpu.l2cache.tags.age_task_id_blocks_1024::1 524 # Occupied blocks per task id 86911103Snilay@cs.wisc.edusystem.cpu.l2cache.tags.age_task_id_blocks_1024::2 2413 # Occupied blocks per task id 87011103Snilay@cs.wisc.edusystem.cpu.l2cache.tags.age_task_id_blocks_1024::3 5473 # Occupied blocks per task id 87111103Snilay@cs.wisc.edusystem.cpu.l2cache.tags.age_task_id_blocks_1024::4 54554 # Occupied blocks per task id 87211103Snilay@cs.wisc.edusystem.cpu.l2cache.tags.occ_task_id_percent::1023 0.003342 # Percentage of cache occupancy per task id 87311103Snilay@cs.wisc.edusystem.cpu.l2cache.tags.occ_task_id_percent::1024 0.961441 # Percentage of cache occupancy per task id 87411103Snilay@cs.wisc.edusystem.cpu.l2cache.tags.tag_accesses 587356710 # Number of tag accesses 87511103Snilay@cs.wisc.edusystem.cpu.l2cache.tags.data_accesses 587356710 # Number of data accesses 87611103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 972528 # number of ReadReq hits 87711103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_hits::cpu.itb.walker 286301 # number of ReadReq hits 87811103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_hits::total 1258829 # number of ReadReq hits 87911103Snilay@cs.wisc.edusystem.cpu.l2cache.Writeback_hits::writebacks 8554549 # number of Writeback hits 88011103Snilay@cs.wisc.edusystem.cpu.l2cache.Writeback_hits::total 8554549 # number of Writeback hits 88111103Snilay@cs.wisc.edusystem.cpu.l2cache.UpgradeReq_hits::cpu.data 10855 # number of UpgradeReq hits 88211103Snilay@cs.wisc.edusystem.cpu.l2cache.UpgradeReq_hits::total 10855 # number of UpgradeReq hits 88311103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadExReq_hits::cpu.data 1654669 # number of ReadExReq hits 88411103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadExReq_hits::total 1654669 # number of ReadExReq hits 88511103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadCleanReq_hits::cpu.inst 24470106 # number of ReadCleanReq hits 88611103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadCleanReq_hits::total 24470106 # number of ReadCleanReq hits 88711103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadSharedReq_hits::cpu.data 7204785 # number of ReadSharedReq hits 88811103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadSharedReq_hits::total 7204785 # number of ReadSharedReq hits 88911103Snilay@cs.wisc.edusystem.cpu.l2cache.InvalidateReq_hits::cpu.data 700263 # number of InvalidateReq hits 89011103Snilay@cs.wisc.edusystem.cpu.l2cache.InvalidateReq_hits::total 700263 # number of InvalidateReq hits 89111103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_hits::cpu.dtb.walker 972528 # number of demand (read+write) hits 89211103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_hits::cpu.itb.walker 286301 # number of demand (read+write) hits 89311103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_hits::cpu.inst 24470106 # number of demand (read+write) hits 89411103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_hits::cpu.data 8859454 # number of demand (read+write) hits 89511103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_hits::total 34588389 # number of demand (read+write) hits 89611103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_hits::cpu.dtb.walker 972528 # number of overall hits 89711103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_hits::cpu.itb.walker 286301 # number of overall hits 89811103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_hits::cpu.inst 24470106 # number of overall hits 89911103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_hits::cpu.data 8859454 # number of overall hits 90011103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_hits::total 34588389 # number of overall hits 90111103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 6370 # number of ReadReq misses 90211103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5416 # number of ReadReq misses 90311103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_misses::total 11786 # number of ReadReq misses 90411103Snilay@cs.wisc.edusystem.cpu.l2cache.UpgradeReq_misses::cpu.data 38716 # number of UpgradeReq misses 90511103Snilay@cs.wisc.edusystem.cpu.l2cache.UpgradeReq_misses::total 38716 # number of UpgradeReq misses 90610892Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses 90710892Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses 90811103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadExReq_misses::cpu.data 709953 # number of ReadExReq misses 90911103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadExReq_misses::total 709953 # number of ReadExReq misses 91011103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadCleanReq_misses::cpu.inst 105935 # number of ReadCleanReq misses 91111103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadCleanReq_misses::total 105935 # number of ReadCleanReq misses 91211103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadSharedReq_misses::cpu.data 328366 # number of ReadSharedReq misses 91311103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadSharedReq_misses::total 328366 # number of ReadSharedReq misses 91411103Snilay@cs.wisc.edusystem.cpu.l2cache.InvalidateReq_misses::cpu.data 544692 # number of InvalidateReq misses 91511103Snilay@cs.wisc.edusystem.cpu.l2cache.InvalidateReq_misses::total 544692 # number of InvalidateReq misses 91611103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_misses::cpu.dtb.walker 6370 # number of demand (read+write) misses 91711103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_misses::cpu.itb.walker 5416 # number of demand (read+write) misses 91811103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_misses::cpu.inst 105935 # number of demand (read+write) misses 91911103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_misses::cpu.data 1038319 # number of demand (read+write) misses 92011103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_misses::total 1156040 # number of demand (read+write) misses 92111103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_misses::cpu.dtb.walker 6370 # number of overall misses 92211103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_misses::cpu.itb.walker 5416 # number of overall misses 92311103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_misses::cpu.inst 105935 # number of overall misses 92411103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_misses::cpu.data 1038319 # number of overall misses 92511103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_misses::total 1156040 # number of overall misses 92611103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 553122500 # number of ReadReq miss cycles 92711103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 470413000 # number of ReadReq miss cycles 92811103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_miss_latency::total 1023535500 # number of ReadReq miss cycles 92911103Snilay@cs.wisc.edusystem.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 578007500 # number of UpgradeReq miss cycles 93011103Snilay@cs.wisc.edusystem.cpu.l2cache.UpgradeReq_miss_latency::total 578007500 # number of UpgradeReq miss cycles 93110892Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 110500 # number of SCUpgradeReq miss cycles 93210892Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_miss_latency::total 110500 # number of SCUpgradeReq miss cycles 93311103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadExReq_miss_latency::cpu.data 58013412000 # number of ReadExReq miss cycles 93411103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadExReq_miss_latency::total 58013412000 # number of ReadExReq miss cycles 93511103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 8652629500 # number of ReadCleanReq miss cycles 93611103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadCleanReq_miss_latency::total 8652629500 # number of ReadCleanReq miss cycles 93711103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 27752985500 # number of ReadSharedReq miss cycles 93811103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadSharedReq_miss_latency::total 27752985500 # number of ReadSharedReq miss cycles 93911103Snilay@cs.wisc.edusystem.cpu.l2cache.InvalidateReq_miss_latency::cpu.data 47906162000 # number of InvalidateReq miss cycles 94011103Snilay@cs.wisc.edusystem.cpu.l2cache.InvalidateReq_miss_latency::total 47906162000 # number of InvalidateReq miss cycles 94111103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 553122500 # number of demand (read+write) miss cycles 94211103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_miss_latency::cpu.itb.walker 470413000 # number of demand (read+write) miss cycles 94311103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_miss_latency::cpu.inst 8652629500 # number of demand (read+write) miss cycles 94411103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_miss_latency::cpu.data 85766397500 # number of demand (read+write) miss cycles 94511103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_miss_latency::total 95442562500 # number of demand (read+write) miss cycles 94611103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 553122500 # number of overall miss cycles 94711103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_miss_latency::cpu.itb.walker 470413000 # number of overall miss cycles 94811103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_miss_latency::cpu.inst 8652629500 # number of overall miss cycles 94911103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_miss_latency::cpu.data 85766397500 # number of overall miss cycles 95011103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_miss_latency::total 95442562500 # number of overall miss cycles 95111103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 978898 # number of ReadReq accesses(hits+misses) 95211103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 291717 # number of ReadReq accesses(hits+misses) 95311103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_accesses::total 1270615 # number of ReadReq accesses(hits+misses) 95411103Snilay@cs.wisc.edusystem.cpu.l2cache.Writeback_accesses::writebacks 8554549 # number of Writeback accesses(hits+misses) 95511103Snilay@cs.wisc.edusystem.cpu.l2cache.Writeback_accesses::total 8554549 # number of Writeback accesses(hits+misses) 95611103Snilay@cs.wisc.edusystem.cpu.l2cache.UpgradeReq_accesses::cpu.data 49571 # number of UpgradeReq accesses(hits+misses) 95711103Snilay@cs.wisc.edusystem.cpu.l2cache.UpgradeReq_accesses::total 49571 # number of UpgradeReq accesses(hits+misses) 95810892Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses) 95910892Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) 96011103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadExReq_accesses::cpu.data 2364622 # number of ReadExReq accesses(hits+misses) 96111103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadExReq_accesses::total 2364622 # number of ReadExReq accesses(hits+misses) 96211103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 24576041 # number of ReadCleanReq accesses(hits+misses) 96311103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadCleanReq_accesses::total 24576041 # number of ReadCleanReq accesses(hits+misses) 96411103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadSharedReq_accesses::cpu.data 7533151 # number of ReadSharedReq accesses(hits+misses) 96511103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadSharedReq_accesses::total 7533151 # number of ReadSharedReq accesses(hits+misses) 96611103Snilay@cs.wisc.edusystem.cpu.l2cache.InvalidateReq_accesses::cpu.data 1244955 # number of InvalidateReq accesses(hits+misses) 96711103Snilay@cs.wisc.edusystem.cpu.l2cache.InvalidateReq_accesses::total 1244955 # number of InvalidateReq accesses(hits+misses) 96811103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_accesses::cpu.dtb.walker 978898 # number of demand (read+write) accesses 96911103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_accesses::cpu.itb.walker 291717 # number of demand (read+write) accesses 97011103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_accesses::cpu.inst 24576041 # number of demand (read+write) accesses 97111103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_accesses::cpu.data 9897773 # number of demand (read+write) accesses 97211103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_accesses::total 35744429 # number of demand (read+write) accesses 97311103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_accesses::cpu.dtb.walker 978898 # number of overall (read+write) accesses 97411103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_accesses::cpu.itb.walker 291717 # number of overall (read+write) accesses 97511103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_accesses::cpu.inst 24576041 # number of overall (read+write) accesses 97611103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_accesses::cpu.data 9897773 # number of overall (read+write) accesses 97711103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_accesses::total 35744429 # number of overall (read+write) accesses 97811103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.006507 # miss rate for ReadReq accesses 97911103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.018566 # miss rate for ReadReq accesses 98011103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_miss_rate::total 0.009276 # miss rate for ReadReq accesses 98111103Snilay@cs.wisc.edusystem.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.781021 # miss rate for UpgradeReq accesses 98211103Snilay@cs.wisc.edusystem.cpu.l2cache.UpgradeReq_miss_rate::total 0.781021 # miss rate for UpgradeReq accesses 98310636Snilay@cs.wisc.edusystem.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses 98410585Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 98511103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.300240 # miss rate for ReadExReq accesses 98611103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadExReq_miss_rate::total 0.300240 # miss rate for ReadExReq accesses 98711103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.004310 # miss rate for ReadCleanReq accesses 98811103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadCleanReq_miss_rate::total 0.004310 # miss rate for ReadCleanReq accesses 98911103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.043589 # miss rate for ReadSharedReq accesses 99011103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadSharedReq_miss_rate::total 0.043589 # miss rate for ReadSharedReq accesses 99111103Snilay@cs.wisc.edusystem.cpu.l2cache.InvalidateReq_miss_rate::cpu.data 0.437519 # miss rate for InvalidateReq accesses 99211103Snilay@cs.wisc.edusystem.cpu.l2cache.InvalidateReq_miss_rate::total 0.437519 # miss rate for InvalidateReq accesses 99311103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.006507 # miss rate for demand accesses 99411103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.018566 # miss rate for demand accesses 99511103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.004310 # miss rate for demand accesses 99611103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_miss_rate::cpu.data 0.104904 # miss rate for demand accesses 99711103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_miss_rate::total 0.032342 # miss rate for demand accesses 99811103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.006507 # miss rate for overall accesses 99911103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.018566 # miss rate for overall accesses 100011103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.004310 # miss rate for overall accesses 100111103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_miss_rate::cpu.data 0.104904 # miss rate for overall accesses 100211103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_miss_rate::total 0.032342 # miss rate for overall accesses 100311103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 86832.417582 # average ReadReq miss latency 100411103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 86856.166913 # average ReadReq miss latency 100511103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_avg_miss_latency::total 86843.331071 # average ReadReq miss latency 100611103Snilay@cs.wisc.edusystem.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 14929.421944 # average UpgradeReq miss latency 100711103Snilay@cs.wisc.edusystem.cpu.l2cache.UpgradeReq_avg_miss_latency::total 14929.421944 # average UpgradeReq miss latency 100810892Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 55250 # average SCUpgradeReq miss latency 100910892Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 55250 # average SCUpgradeReq miss latency 101011103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81714.440252 # average ReadExReq miss latency 101111103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadExReq_avg_miss_latency::total 81714.440252 # average ReadExReq miss latency 101211103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 81678.666163 # average ReadCleanReq miss latency 101311103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 81678.666163 # average ReadCleanReq miss latency 101411103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 84518.450449 # average ReadSharedReq miss latency 101511103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 84518.450449 # average ReadSharedReq miss latency 101611103Snilay@cs.wisc.edusystem.cpu.l2cache.InvalidateReq_avg_miss_latency::cpu.data 87950.919052 # average InvalidateReq miss latency 101711103Snilay@cs.wisc.edusystem.cpu.l2cache.InvalidateReq_avg_miss_latency::total 87950.919052 # average InvalidateReq miss latency 101811103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 86832.417582 # average overall miss latency 101911103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 86856.166913 # average overall miss latency 102011103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81678.666163 # average overall miss latency 102111103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_avg_miss_latency::cpu.data 82601.202039 # average overall miss latency 102211103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_avg_miss_latency::total 82559.913584 # average overall miss latency 102311103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 86832.417582 # average overall miss latency 102411103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 86856.166913 # average overall miss latency 102511103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81678.666163 # average overall miss latency 102611103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_avg_miss_latency::cpu.data 82601.202039 # average overall miss latency 102711103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_avg_miss_latency::total 82559.913584 # average overall miss latency 102810585Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 102910585Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 103010585Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 103110585Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 103210585Sandreas.hansson@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 103310585Sandreas.hansson@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 103410585Sandreas.hansson@arm.comsystem.cpu.l2cache.fast_writes 0 # number of fast writes performed 103510585Sandreas.hansson@arm.comsystem.cpu.l2cache.cache_copies 0 # number of cache copies performed 103611103Snilay@cs.wisc.edusystem.cpu.l2cache.writebacks::writebacks 1373638 # number of writebacks 103711103Snilay@cs.wisc.edusystem.cpu.l2cache.writebacks::total 1373638 # number of writebacks 103810892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 3 # number of ReadCleanReq MSHR hits 103910892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_hits::total 3 # number of ReadCleanReq MSHR hits 104010892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 21 # number of ReadSharedReq MSHR hits 104110892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_hits::total 21 # number of ReadSharedReq MSHR hits 104210892Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_hits::cpu.inst 3 # number of demand (read+write) MSHR hits 104310726Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_hits::cpu.data 21 # number of demand (read+write) MSHR hits 104410892Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_hits::total 24 # number of demand (read+write) MSHR hits 104510892Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_hits::cpu.inst 3 # number of overall MSHR hits 104610726Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_hits::cpu.data 21 # number of overall MSHR hits 104710892Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_hits::total 24 # number of overall MSHR hits 104811103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 6370 # number of ReadReq MSHR misses 104911103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 5416 # number of ReadReq MSHR misses 105011103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_mshr_misses::total 11786 # number of ReadReq MSHR misses 105111103Snilay@cs.wisc.edusystem.cpu.l2cache.CleanEvict_mshr_misses::writebacks 1102 # number of CleanEvict MSHR misses 105211103Snilay@cs.wisc.edusystem.cpu.l2cache.CleanEvict_mshr_misses::total 1102 # number of CleanEvict MSHR misses 105311103Snilay@cs.wisc.edusystem.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 38716 # number of UpgradeReq MSHR misses 105411103Snilay@cs.wisc.edusystem.cpu.l2cache.UpgradeReq_mshr_misses::total 38716 # number of UpgradeReq MSHR misses 105510892Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses 105610892Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses 105711103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 709953 # number of ReadExReq MSHR misses 105811103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadExReq_mshr_misses::total 709953 # number of ReadExReq MSHR misses 105911103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 105932 # number of ReadCleanReq MSHR misses 106011103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadCleanReq_mshr_misses::total 105932 # number of ReadCleanReq MSHR misses 106111103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 328345 # number of ReadSharedReq MSHR misses 106211103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadSharedReq_mshr_misses::total 328345 # number of ReadSharedReq MSHR misses 106311103Snilay@cs.wisc.edusystem.cpu.l2cache.InvalidateReq_mshr_misses::cpu.data 544692 # number of InvalidateReq MSHR misses 106411103Snilay@cs.wisc.edusystem.cpu.l2cache.InvalidateReq_mshr_misses::total 544692 # number of InvalidateReq MSHR misses 106511103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 6370 # number of demand (read+write) MSHR misses 106611103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 5416 # number of demand (read+write) MSHR misses 106711103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_mshr_misses::cpu.inst 105932 # number of demand (read+write) MSHR misses 106811103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_mshr_misses::cpu.data 1038298 # number of demand (read+write) MSHR misses 106911103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_mshr_misses::total 1156016 # number of demand (read+write) MSHR misses 107011103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 6370 # number of overall MSHR misses 107111103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 5416 # number of overall MSHR misses 107211103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_mshr_misses::cpu.inst 105932 # number of overall MSHR misses 107311103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_mshr_misses::cpu.data 1038298 # number of overall MSHR misses 107411103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_mshr_misses::total 1156016 # number of overall MSHR misses 107510892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 52295 # number of ReadReq MSHR uncacheable 107610892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 33699 # number of ReadReq MSHR uncacheable 107710892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_uncacheable::total 85994 # number of ReadReq MSHR uncacheable 107810892Sandreas.hansson@arm.comsystem.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 33707 # number of WriteReq MSHR uncacheable 107910892Sandreas.hansson@arm.comsystem.cpu.l2cache.WriteReq_mshr_uncacheable::total 33707 # number of WriteReq MSHR uncacheable 108010892Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 52295 # number of overall MSHR uncacheable misses 108110892Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 67406 # number of overall MSHR uncacheable misses 108210892Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_uncacheable_misses::total 119701 # number of overall MSHR uncacheable misses 108311103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 489422500 # number of ReadReq MSHR miss cycles 108411103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 416253000 # number of ReadReq MSHR miss cycles 108511103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_mshr_miss_latency::total 905675500 # number of ReadReq MSHR miss cycles 108611103Snilay@cs.wisc.edusystem.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 803927500 # number of UpgradeReq MSHR miss cycles 108711103Snilay@cs.wisc.edusystem.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 803927500 # number of UpgradeReq MSHR miss cycles 108810892Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 90500 # number of SCUpgradeReq MSHR miss cycles 108910892Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 90500 # number of SCUpgradeReq MSHR miss cycles 109011103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 50913882000 # number of ReadExReq MSHR miss cycles 109111103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadExReq_mshr_miss_latency::total 50913882000 # number of ReadExReq MSHR miss cycles 109211103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 7593134000 # number of ReadCleanReq MSHR miss cycles 109311103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 7593134000 # number of ReadCleanReq MSHR miss cycles 109411103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 24468048000 # number of ReadSharedReq MSHR miss cycles 109511103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 24468048000 # number of ReadSharedReq MSHR miss cycles 109611103Snilay@cs.wisc.edusystem.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data 42459242000 # number of InvalidateReq MSHR miss cycles 109711103Snilay@cs.wisc.edusystem.cpu.l2cache.InvalidateReq_mshr_miss_latency::total 42459242000 # number of InvalidateReq MSHR miss cycles 109811103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 489422500 # number of demand (read+write) MSHR miss cycles 109911103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 416253000 # number of demand (read+write) MSHR miss cycles 110011103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 7593134000 # number of demand (read+write) MSHR miss cycles 110111103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_mshr_miss_latency::cpu.data 75381930000 # number of demand (read+write) MSHR miss cycles 110211103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_mshr_miss_latency::total 83880739500 # number of demand (read+write) MSHR miss cycles 110311103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 489422500 # number of overall MSHR miss cycles 110411103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 416253000 # number of overall MSHR miss cycles 110511103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 7593134000 # number of overall MSHR miss cycles 110611103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_mshr_miss_latency::cpu.data 75381930000 # number of overall MSHR miss cycles 110711103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_mshr_miss_latency::total 83880739500 # number of overall MSHR miss cycles 110810892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 3232365500 # number of ReadReq MSHR uncacheable cycles 110911103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5409250000 # number of ReadReq MSHR uncacheable cycles 111011103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 8641615500 # number of ReadReq MSHR uncacheable cycles 111111103Snilay@cs.wisc.edusystem.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 5303815500 # number of WriteReq MSHR uncacheable cycles 111211103Snilay@cs.wisc.edusystem.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 5303815500 # number of WriteReq MSHR uncacheable cycles 111310892Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 3232365500 # number of overall MSHR uncacheable cycles 111411103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 10713065500 # number of overall MSHR uncacheable cycles 111511103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_mshr_uncacheable_latency::total 13945431000 # number of overall MSHR uncacheable cycles 111611103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.006507 # mshr miss rate for ReadReq accesses 111711103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.018566 # mshr miss rate for ReadReq accesses 111811103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.009276 # mshr miss rate for ReadReq accesses 111910892Sandreas.hansson@arm.comsystem.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 112010892Sandreas.hansson@arm.comsystem.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 112111103Snilay@cs.wisc.edusystem.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.781021 # mshr miss rate for UpgradeReq accesses 112211103Snilay@cs.wisc.edusystem.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.781021 # mshr miss rate for UpgradeReq accesses 112310636Snilay@cs.wisc.edusystem.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses 112410585Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 112511103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.300240 # mshr miss rate for ReadExReq accesses 112611103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.300240 # mshr miss rate for ReadExReq accesses 112711103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.004310 # mshr miss rate for ReadCleanReq accesses 112811103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.004310 # mshr miss rate for ReadCleanReq accesses 112911103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.043587 # mshr miss rate for ReadSharedReq accesses 113011103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.043587 # mshr miss rate for ReadSharedReq accesses 113111103Snilay@cs.wisc.edusystem.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.437519 # mshr miss rate for InvalidateReq accesses 113211103Snilay@cs.wisc.edusystem.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.437519 # mshr miss rate for InvalidateReq accesses 113311103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.006507 # mshr miss rate for demand accesses 113411103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.018566 # mshr miss rate for demand accesses 113511103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.004310 # mshr miss rate for demand accesses 113611103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.104902 # mshr miss rate for demand accesses 113711103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_mshr_miss_rate::total 0.032341 # mshr miss rate for demand accesses 113811103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.006507 # mshr miss rate for overall accesses 113911103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.018566 # mshr miss rate for overall accesses 114011103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.004310 # mshr miss rate for overall accesses 114111103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.104902 # mshr miss rate for overall accesses 114211103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_mshr_miss_rate::total 0.032341 # mshr miss rate for overall accesses 114311103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 76832.417582 # average ReadReq mshr miss latency 114411103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 76856.166913 # average ReadReq mshr miss latency 114511103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 76843.331071 # average ReadReq mshr miss latency 114611103Snilay@cs.wisc.edusystem.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 20764.735510 # average UpgradeReq mshr miss latency 114711103Snilay@cs.wisc.edusystem.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20764.735510 # average UpgradeReq mshr miss latency 114810892Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 45250 # average SCUpgradeReq mshr miss latency 114910892Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 45250 # average SCUpgradeReq mshr miss latency 115011103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71714.440252 # average ReadExReq mshr miss latency 115111103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71714.440252 # average ReadExReq mshr miss latency 115211103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 71679.322584 # average ReadCleanReq mshr miss latency 115311103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 71679.322584 # average ReadCleanReq mshr miss latency 115411103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 74519.325709 # average ReadSharedReq mshr miss latency 115511103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 74519.325709 # average ReadSharedReq mshr miss latency 115611103Snilay@cs.wisc.edusystem.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 77950.919052 # average InvalidateReq mshr miss latency 115711103Snilay@cs.wisc.edusystem.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 77950.919052 # average InvalidateReq mshr miss latency 115811103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 76832.417582 # average overall mshr miss latency 115911103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 76856.166913 # average overall mshr miss latency 116011103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71679.322584 # average overall mshr miss latency 116111103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72601.440049 # average overall mshr miss latency 116211103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_avg_mshr_miss_latency::total 72560.189046 # average overall mshr miss latency 116311103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 76832.417582 # average overall mshr miss latency 116411103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 76856.166913 # average overall mshr miss latency 116511103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71679.322584 # average overall mshr miss latency 116611103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72601.440049 # average overall mshr miss latency 116711103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_avg_mshr_miss_latency::total 72560.189046 # average overall mshr miss latency 116810892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 61810.220862 # average ReadReq mshr uncacheable latency 116911103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 160516.632541 # average ReadReq mshr uncacheable latency 117011103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 100490.912157 # average ReadReq mshr uncacheable latency 117111103Snilay@cs.wisc.edusystem.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 157350.565165 # average WriteReq mshr uncacheable latency 117211103Snilay@cs.wisc.edusystem.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 157350.565165 # average WriteReq mshr uncacheable latency 117310892Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 61810.220862 # average overall mshr uncacheable latency 117411103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 158933.410972 # average overall mshr uncacheable latency 117511103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 116502.209672 # average overall mshr uncacheable latency 117610585Sandreas.hansson@arm.comsystem.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 117711103Snilay@cs.wisc.edusystem.cpu.toL2Bus.trans_dist::ReadReq 1789463 # Transaction distribution 117811103Snilay@cs.wisc.edusystem.cpu.toL2Bus.trans_dist::ReadResp 33899423 # Transaction distribution 117910892Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::WriteReq 33707 # Transaction distribution 118010892Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::WriteResp 33707 # Transaction distribution 118111103Snilay@cs.wisc.edusystem.cpu.toL2Bus.trans_dist::Writeback 10034845 # Transaction distribution 118211103Snilay@cs.wisc.edusystem.cpu.toL2Bus.trans_dist::CleanEvict 27401014 # Transaction distribution 118311103Snilay@cs.wisc.edusystem.cpu.toL2Bus.trans_dist::UpgradeReq 49574 # Transaction distribution 118410892Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution 118511103Snilay@cs.wisc.edusystem.cpu.toL2Bus.trans_dist::UpgradeResp 49576 # Transaction distribution 118611103Snilay@cs.wisc.edusystem.cpu.toL2Bus.trans_dist::ReadExReq 2364622 # Transaction distribution 118711103Snilay@cs.wisc.edusystem.cpu.toL2Bus.trans_dist::ReadExResp 2364622 # Transaction distribution 118811103Snilay@cs.wisc.edusystem.cpu.toL2Bus.trans_dist::ReadCleanReq 24576044 # Transaction distribution 118911103Snilay@cs.wisc.edusystem.cpu.toL2Bus.trans_dist::ReadSharedReq 7542009 # Transaction distribution 119011103Snilay@cs.wisc.edusystem.cpu.toL2Bus.trans_dist::InvalidateReq 1351619 # Transaction distribution 119111103Snilay@cs.wisc.edusystem.cpu.toL2Bus.trans_dist::InvalidateResp 1244955 # Transaction distribution 119211103Snilay@cs.wisc.edusystem.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 73828388 # Packet count per connected master and slave (bytes) 119311103Snilay@cs.wisc.edusystem.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 33661752 # Packet count per connected master and slave (bytes) 119411103Snilay@cs.wisc.edusystem.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 699908 # Packet count per connected master and slave (bytes) 119511103Snilay@cs.wisc.edusystem.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2274176 # Packet count per connected master and slave (bytes) 119611103Snilay@cs.wisc.edusystem.cpu.toL2Bus.pkt_count::total 110464224 # Packet count per connected master and slave (bytes) 119711103Snilay@cs.wisc.edusystem.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1576213440 # Cumulative packet size per connected master and slave (bytes) 119811103Snilay@cs.wisc.edusystem.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1181188062 # Cumulative packet size per connected master and slave (bytes) 119911103Snilay@cs.wisc.edusystem.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2333736 # Cumulative packet size per connected master and slave (bytes) 120011103Snilay@cs.wisc.edusystem.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 7831184 # Cumulative packet size per connected master and slave (bytes) 120111103Snilay@cs.wisc.edusystem.cpu.toL2Bus.pkt_size::total 2767566422 # Cumulative packet size per connected master and slave (bytes) 120211103Snilay@cs.wisc.edusystem.cpu.toL2Bus.snoops 2271727 # Total snoops (count) 120311103Snilay@cs.wisc.edusystem.cpu.toL2Bus.snoop_fanout::samples 75147333 # Request fanout histogram 120411103Snilay@cs.wisc.edusystem.cpu.toL2Bus.snoop_fanout::mean 1.047128 # Request fanout histogram 120511103Snilay@cs.wisc.edusystem.cpu.toL2Bus.snoop_fanout::stdev 0.211913 # Request fanout histogram 120610585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 120710585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 120811103Snilay@cs.wisc.edusystem.cpu.toL2Bus.snoop_fanout::1 71605763 95.29% 95.29% # Request fanout histogram 120911103Snilay@cs.wisc.edusystem.cpu.toL2Bus.snoop_fanout::2 3541570 4.71% 100.00% # Request fanout histogram 121010585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 121110827Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 121210827Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 121311103Snilay@cs.wisc.edusystem.cpu.toL2Bus.snoop_fanout::total 75147333 # Request fanout histogram 121411103Snilay@cs.wisc.edusystem.cpu.toL2Bus.reqLayer0.occupancy 45226020496 # Layer occupancy (ticks) 121510585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 121611103Snilay@cs.wisc.edusystem.cpu.toL2Bus.snoopLayer0.occupancy 1150500 # Layer occupancy (ticks) 121710585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 121811103Snilay@cs.wisc.edusystem.cpu.toL2Bus.respLayer0.occupancy 36946016966 # Layer occupancy (ticks) 121910585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 122011103Snilay@cs.wisc.edusystem.cpu.toL2Bus.respLayer1.occupancy 15544978992 # Layer occupancy (ticks) 122110585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 122211103Snilay@cs.wisc.edusystem.cpu.toL2Bus.respLayer2.occupancy 408213455 # Layer occupancy (ticks) 122310585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 122411103Snilay@cs.wisc.edusystem.cpu.toL2Bus.respLayer3.occupancy 1295285984 # Layer occupancy (ticks) 122510585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 122611103Snilay@cs.wisc.edusystem.iobus.trans_dist::ReadReq 40306 # Transaction distribution 122711103Snilay@cs.wisc.edusystem.iobus.trans_dist::ReadResp 40306 # Transaction distribution 122810726Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteReq 136571 # Transaction distribution 122910892Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteResp 136571 # Transaction distribution 123010726Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes) 123110585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 123210585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) 123310585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) 123410585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 123510585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 123610585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 123710585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 123810585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) 123910585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 124010585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) 124110585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) 124210585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) 124310585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) 124410585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) 124510726Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes) 124611103Snilay@cs.wisc.edusystem.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230970 # Packet count per connected master and slave (bytes) 124711103Snilay@cs.wisc.edusystem.iobus.pkt_count_system.realview.ide.dma::total 230970 # Packet count per connected master and slave (bytes) 124810585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) 124910585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) 125011103Snilay@cs.wisc.edusystem.iobus.pkt_count::total 353754 # Packet count per connected master and slave (bytes) 125110726Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes) 125210585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) 125310585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) 125410585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) 125510585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 125610585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 125710585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 125810585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 125910585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) 126010585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 126110585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) 126210585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes) 126310585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) 126410585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) 126510585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) 126610726Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes) 126711103Snilay@cs.wisc.edusystem.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334312 # Cumulative packet size per connected master and slave (bytes) 126811103Snilay@cs.wisc.edusystem.iobus.pkt_size_system.realview.ide.dma::total 7334312 # Cumulative packet size per connected master and slave (bytes) 126910585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 127010585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) 127111103Snilay@cs.wisc.edusystem.iobus.pkt_size::total 7492232 # Cumulative packet size per connected master and slave (bytes) 127210726Sandreas.hansson@arm.comsystem.iobus.reqLayer0.occupancy 36301000 # Layer occupancy (ticks) 127310585Sandreas.hansson@arm.comsystem.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 127410585Sandreas.hansson@arm.comsystem.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) 127510585Sandreas.hansson@arm.comsystem.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 127610585Sandreas.hansson@arm.comsystem.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks) 127710585Sandreas.hansson@arm.comsystem.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 127810585Sandreas.hansson@arm.comsystem.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks) 127910585Sandreas.hansson@arm.comsystem.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 128010585Sandreas.hansson@arm.comsystem.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) 128110585Sandreas.hansson@arm.comsystem.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 128210585Sandreas.hansson@arm.comsystem.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) 128310585Sandreas.hansson@arm.comsystem.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 128410585Sandreas.hansson@arm.comsystem.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) 128510585Sandreas.hansson@arm.comsystem.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 128610585Sandreas.hansson@arm.comsystem.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) 128710585Sandreas.hansson@arm.comsystem.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 128810585Sandreas.hansson@arm.comsystem.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks) 128910585Sandreas.hansson@arm.comsystem.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 129010585Sandreas.hansson@arm.comsystem.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) 129110585Sandreas.hansson@arm.comsystem.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 129210585Sandreas.hansson@arm.comsystem.iobus.reqLayer23.occupancy 21947000 # Layer occupancy (ticks) 129310585Sandreas.hansson@arm.comsystem.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 129410585Sandreas.hansson@arm.comsystem.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks) 129510585Sandreas.hansson@arm.comsystem.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 129610585Sandreas.hansson@arm.comsystem.iobus.reqLayer25.occupancy 32658000 # Layer occupancy (ticks) 129710585Sandreas.hansson@arm.comsystem.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 129810585Sandreas.hansson@arm.comsystem.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) 129910585Sandreas.hansson@arm.comsystem.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 130011103Snilay@cs.wisc.edusystem.iobus.reqLayer27.occupancy 568890575 # Layer occupancy (ticks) 130110585Sandreas.hansson@arm.comsystem.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 130210585Sandreas.hansson@arm.comsystem.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) 130310585Sandreas.hansson@arm.comsystem.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) 130410726Sandreas.hansson@arm.comsystem.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks) 130510585Sandreas.hansson@arm.comsystem.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 130611103Snilay@cs.wisc.edusystem.iobus.respLayer3.occupancy 147730000 # Layer occupancy (ticks) 130710585Sandreas.hansson@arm.comsystem.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 130810892Sandreas.hansson@arm.comsystem.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) 130910585Sandreas.hansson@arm.comsystem.iobus.respLayer4.utilization 0.0 # Layer utilization (%) 131011103Snilay@cs.wisc.edusystem.iocache.tags.replacements 115467 # number of replacements 131111103Snilay@cs.wisc.edusystem.iocache.tags.tagsinuse 10.447125 # Cycle average of tags in use 131210585Sandreas.hansson@arm.comsystem.iocache.tags.total_refs 3 # Total number of references to valid blocks. 131311103Snilay@cs.wisc.edusystem.iocache.tags.sampled_refs 115483 # Sample count of references to valid blocks. 131410585Sandreas.hansson@arm.comsystem.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. 131511103Snilay@cs.wisc.edusystem.iocache.tags.warmup_cycle 13147039080000 # Cycle when the warmup percentage was hit. 131611103Snilay@cs.wisc.edusystem.iocache.tags.occ_blocks::realview.ethernet 3.519011 # Average occupied blocks per requestor 131711103Snilay@cs.wisc.edusystem.iocache.tags.occ_blocks::realview.ide 6.928115 # Average occupied blocks per requestor 131810892Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::realview.ethernet 0.219938 # Average percentage of cache occupancy 131911103Snilay@cs.wisc.edusystem.iocache.tags.occ_percent::realview.ide 0.433007 # Average percentage of cache occupancy 132011103Snilay@cs.wisc.edusystem.iocache.tags.occ_percent::total 0.652945 # Average percentage of cache occupancy 132110585Sandreas.hansson@arm.comsystem.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 132210585Sandreas.hansson@arm.comsystem.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 132310585Sandreas.hansson@arm.comsystem.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 132411103Snilay@cs.wisc.edusystem.iocache.tags.tag_accesses 1039722 # Number of tag accesses 132511103Snilay@cs.wisc.edusystem.iocache.tags.data_accesses 1039722 # Number of data accesses 132610585Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses 132711103Snilay@cs.wisc.edusystem.iocache.ReadReq_misses::realview.ide 8821 # number of ReadReq misses 132811103Snilay@cs.wisc.edusystem.iocache.ReadReq_misses::total 8858 # number of ReadReq misses 132910585Sandreas.hansson@arm.comsystem.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 133010585Sandreas.hansson@arm.comsystem.iocache.WriteReq_misses::total 3 # number of WriteReq misses 133110892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses 133210892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses 133310585Sandreas.hansson@arm.comsystem.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses 133411103Snilay@cs.wisc.edusystem.iocache.demand_misses::realview.ide 8821 # number of demand (read+write) misses 133511103Snilay@cs.wisc.edusystem.iocache.demand_misses::total 8861 # number of demand (read+write) misses 133610585Sandreas.hansson@arm.comsystem.iocache.overall_misses::realview.ethernet 40 # number of overall misses 133711103Snilay@cs.wisc.edusystem.iocache.overall_misses::realview.ide 8821 # number of overall misses 133811103Snilay@cs.wisc.edusystem.iocache.overall_misses::total 8861 # number of overall misses 133910892Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_latency::realview.ethernet 5069000 # number of ReadReq miss cycles 134011103Snilay@cs.wisc.edusystem.iocache.ReadReq_miss_latency::realview.ide 1605437158 # number of ReadReq miss cycles 134111103Snilay@cs.wisc.edusystem.iocache.ReadReq_miss_latency::total 1610506158 # number of ReadReq miss cycles 134210892Sandreas.hansson@arm.comsystem.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles 134310892Sandreas.hansson@arm.comsystem.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles 134411103Snilay@cs.wisc.edusystem.iocache.WriteLineReq_miss_latency::realview.ide 12610481417 # number of WriteLineReq miss cycles 134511103Snilay@cs.wisc.edusystem.iocache.WriteLineReq_miss_latency::total 12610481417 # number of WriteLineReq miss cycles 134610892Sandreas.hansson@arm.comsystem.iocache.demand_miss_latency::realview.ethernet 5420000 # number of demand (read+write) miss cycles 134711103Snilay@cs.wisc.edusystem.iocache.demand_miss_latency::realview.ide 1605437158 # number of demand (read+write) miss cycles 134811103Snilay@cs.wisc.edusystem.iocache.demand_miss_latency::total 1610857158 # number of demand (read+write) miss cycles 134910892Sandreas.hansson@arm.comsystem.iocache.overall_miss_latency::realview.ethernet 5420000 # number of overall miss cycles 135011103Snilay@cs.wisc.edusystem.iocache.overall_miss_latency::realview.ide 1605437158 # number of overall miss cycles 135111103Snilay@cs.wisc.edusystem.iocache.overall_miss_latency::total 1610857158 # number of overall miss cycles 135210585Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) 135311103Snilay@cs.wisc.edusystem.iocache.ReadReq_accesses::realview.ide 8821 # number of ReadReq accesses(hits+misses) 135411103Snilay@cs.wisc.edusystem.iocache.ReadReq_accesses::total 8858 # number of ReadReq accesses(hits+misses) 135510585Sandreas.hansson@arm.comsystem.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 135610585Sandreas.hansson@arm.comsystem.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 135710892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) 135810892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) 135910585Sandreas.hansson@arm.comsystem.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses 136011103Snilay@cs.wisc.edusystem.iocache.demand_accesses::realview.ide 8821 # number of demand (read+write) accesses 136111103Snilay@cs.wisc.edusystem.iocache.demand_accesses::total 8861 # number of demand (read+write) accesses 136210585Sandreas.hansson@arm.comsystem.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses 136311103Snilay@cs.wisc.edusystem.iocache.overall_accesses::realview.ide 8821 # number of overall (read+write) accesses 136411103Snilay@cs.wisc.edusystem.iocache.overall_accesses::total 8861 # number of overall (read+write) accesses 136510585Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 136610585Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 136710585Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 136810585Sandreas.hansson@arm.comsystem.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 136910585Sandreas.hansson@arm.comsystem.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 137010892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 137110892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 137210585Sandreas.hansson@arm.comsystem.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses 137310585Sandreas.hansson@arm.comsystem.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 137410585Sandreas.hansson@arm.comsystem.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 137510585Sandreas.hansson@arm.comsystem.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses 137610585Sandreas.hansson@arm.comsystem.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 137710585Sandreas.hansson@arm.comsystem.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 137810892Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_miss_latency::realview.ethernet 137000 # average ReadReq miss latency 137911103Snilay@cs.wisc.edusystem.iocache.ReadReq_avg_miss_latency::realview.ide 182001.718399 # average ReadReq miss latency 138011103Snilay@cs.wisc.edusystem.iocache.ReadReq_avg_miss_latency::total 181813.745541 # average ReadReq miss latency 138110892Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency 138210892Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency 138311103Snilay@cs.wisc.edusystem.iocache.WriteLineReq_avg_miss_latency::realview.ide 118226.218940 # average WriteLineReq miss latency 138411103Snilay@cs.wisc.edusystem.iocache.WriteLineReq_avg_miss_latency::total 118226.218940 # average WriteLineReq miss latency 138510892Sandreas.hansson@arm.comsystem.iocache.demand_avg_miss_latency::realview.ethernet 135500 # average overall miss latency 138611103Snilay@cs.wisc.edusystem.iocache.demand_avg_miss_latency::realview.ide 182001.718399 # average overall miss latency 138711103Snilay@cs.wisc.edusystem.iocache.demand_avg_miss_latency::total 181791.802054 # average overall miss latency 138810892Sandreas.hansson@arm.comsystem.iocache.overall_avg_miss_latency::realview.ethernet 135500 # average overall miss latency 138911103Snilay@cs.wisc.edusystem.iocache.overall_avg_miss_latency::realview.ide 182001.718399 # average overall miss latency 139011103Snilay@cs.wisc.edusystem.iocache.overall_avg_miss_latency::total 181791.802054 # average overall miss latency 139111103Snilay@cs.wisc.edusystem.iocache.blocked_cycles::no_mshrs 31114 # number of cycles access was blocked 139210585Sandreas.hansson@arm.comsystem.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 139311103Snilay@cs.wisc.edusystem.iocache.blocked::no_mshrs 3332 # number of cycles access was blocked 139410585Sandreas.hansson@arm.comsystem.iocache.blocked::no_targets 0 # number of cycles access was blocked 139511103Snilay@cs.wisc.edusystem.iocache.avg_blocked_cycles::no_mshrs 9.337935 # average number of cycles each access was blocked 139610585Sandreas.hansson@arm.comsystem.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 139710585Sandreas.hansson@arm.comsystem.iocache.fast_writes 0 # number of fast writes performed 139810585Sandreas.hansson@arm.comsystem.iocache.cache_copies 0 # number of cache copies performed 139910726Sandreas.hansson@arm.comsystem.iocache.writebacks::writebacks 106631 # number of writebacks 140010726Sandreas.hansson@arm.comsystem.iocache.writebacks::total 106631 # number of writebacks 140110585Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses 140211103Snilay@cs.wisc.edusystem.iocache.ReadReq_mshr_misses::realview.ide 8821 # number of ReadReq MSHR misses 140311103Snilay@cs.wisc.edusystem.iocache.ReadReq_mshr_misses::total 8858 # number of ReadReq MSHR misses 140410585Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses 140510585Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses 140610892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses 140710892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses 140810585Sandreas.hansson@arm.comsystem.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses 140911103Snilay@cs.wisc.edusystem.iocache.demand_mshr_misses::realview.ide 8821 # number of demand (read+write) MSHR misses 141011103Snilay@cs.wisc.edusystem.iocache.demand_mshr_misses::total 8861 # number of demand (read+write) MSHR misses 141110585Sandreas.hansson@arm.comsystem.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses 141211103Snilay@cs.wisc.edusystem.iocache.overall_mshr_misses::realview.ide 8821 # number of overall MSHR misses 141311103Snilay@cs.wisc.edusystem.iocache.overall_mshr_misses::total 8861 # number of overall MSHR misses 141410892Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3219000 # number of ReadReq MSHR miss cycles 141511103Snilay@cs.wisc.edusystem.iocache.ReadReq_mshr_miss_latency::realview.ide 1164387158 # number of ReadReq MSHR miss cycles 141611103Snilay@cs.wisc.edusystem.iocache.ReadReq_mshr_miss_latency::total 1167606158 # number of ReadReq MSHR miss cycles 141710892Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles 141810892Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles 141911103Snilay@cs.wisc.edusystem.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7277281417 # number of WriteLineReq MSHR miss cycles 142011103Snilay@cs.wisc.edusystem.iocache.WriteLineReq_mshr_miss_latency::total 7277281417 # number of WriteLineReq MSHR miss cycles 142110892Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_latency::realview.ethernet 3420000 # number of demand (read+write) MSHR miss cycles 142211103Snilay@cs.wisc.edusystem.iocache.demand_mshr_miss_latency::realview.ide 1164387158 # number of demand (read+write) MSHR miss cycles 142311103Snilay@cs.wisc.edusystem.iocache.demand_mshr_miss_latency::total 1167807158 # number of demand (read+write) MSHR miss cycles 142410892Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_latency::realview.ethernet 3420000 # number of overall MSHR miss cycles 142511103Snilay@cs.wisc.edusystem.iocache.overall_mshr_miss_latency::realview.ide 1164387158 # number of overall MSHR miss cycles 142611103Snilay@cs.wisc.edusystem.iocache.overall_mshr_miss_latency::total 1167807158 # number of overall MSHR miss cycles 142710585Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses 142810585Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 142910585Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 143010585Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses 143110585Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 143210892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 143310892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 143410585Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses 143510585Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 143610585Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 143710585Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses 143810585Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 143910585Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 144010892Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87000 # average ReadReq mshr miss latency 144111103Snilay@cs.wisc.edusystem.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 132001.718399 # average ReadReq mshr miss latency 144211103Snilay@cs.wisc.edusystem.iocache.ReadReq_avg_mshr_miss_latency::total 131813.745541 # average ReadReq mshr miss latency 144310892Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency 144410892Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency 144511103Snilay@cs.wisc.edusystem.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68226.218940 # average WriteLineReq mshr miss latency 144611103Snilay@cs.wisc.edusystem.iocache.WriteLineReq_avg_mshr_miss_latency::total 68226.218940 # average WriteLineReq mshr miss latency 144710892Sandreas.hansson@arm.comsystem.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85500 # average overall mshr miss latency 144811103Snilay@cs.wisc.edusystem.iocache.demand_avg_mshr_miss_latency::realview.ide 132001.718399 # average overall mshr miss latency 144911103Snilay@cs.wisc.edusystem.iocache.demand_avg_mshr_miss_latency::total 131791.802054 # average overall mshr miss latency 145010892Sandreas.hansson@arm.comsystem.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85500 # average overall mshr miss latency 145111103Snilay@cs.wisc.edusystem.iocache.overall_avg_mshr_miss_latency::realview.ide 132001.718399 # average overall mshr miss latency 145211103Snilay@cs.wisc.edusystem.iocache.overall_avg_mshr_miss_latency::total 131791.802054 # average overall mshr miss latency 145310585Sandreas.hansson@arm.comsystem.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 145410892Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadReq 85994 # Transaction distribution 145511103Snilay@cs.wisc.edusystem.membus.trans_dist::ReadResp 540915 # Transaction distribution 145610892Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteReq 33707 # Transaction distribution 145710892Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteResp 33707 # Transaction distribution 145811103Snilay@cs.wisc.edusystem.membus.trans_dist::Writeback 1480269 # Transaction distribution 145911103Snilay@cs.wisc.edusystem.membus.trans_dist::CleanEvict 239619 # Transaction distribution 146011103Snilay@cs.wisc.edusystem.membus.trans_dist::UpgradeReq 39541 # Transaction distribution 146110892Sandreas.hansson@arm.comsystem.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution 146211103Snilay@cs.wisc.edusystem.membus.trans_dist::UpgradeResp 39543 # Transaction distribution 146311103Snilay@cs.wisc.edusystem.membus.trans_dist::ReadExReq 1253823 # Transaction distribution 146411103Snilay@cs.wisc.edusystem.membus.trans_dist::ReadExResp 1253823 # Transaction distribution 146511103Snilay@cs.wisc.edusystem.membus.trans_dist::ReadSharedReq 454921 # Transaction distribution 146610892Sandreas.hansson@arm.comsystem.membus.trans_dist::InvalidateReq 106664 # Transaction distribution 146710892Sandreas.hansson@arm.comsystem.membus.trans_dist::InvalidateResp 106664 # Transaction distribution 146810726Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes) 146910515SAli.Saidi@ARM.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 32 # Packet count per connected master and slave (bytes) 147010892Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6922 # Packet count per connected master and slave (bytes) 147111103Snilay@cs.wisc.edusystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5195008 # Packet count per connected master and slave (bytes) 147211103Snilay@cs.wisc.edusystem.membus.pkt_count_system.cpu.l2cache.mem_side::total 5324666 # Packet count per connected master and slave (bytes) 147311103Snilay@cs.wisc.edusystem.membus.pkt_count_system.iocache.mem_side::system.physmem.port 341395 # Packet count per connected master and slave (bytes) 147411103Snilay@cs.wisc.edusystem.membus.pkt_count_system.iocache.mem_side::total 341395 # Packet count per connected master and slave (bytes) 147511103Snilay@cs.wisc.edusystem.membus.pkt_count::total 5666061 # Packet count per connected master and slave (bytes) 147610726Sandreas.hansson@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes) 147710515SAli.Saidi@ARM.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 740 # Cumulative packet size per connected master and slave (bytes) 147810892Sandreas.hansson@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13844 # Cumulative packet size per connected master and slave (bytes) 147911103Snilay@cs.wisc.edusystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 200030316 # Cumulative packet size per connected master and slave (bytes) 148011103Snilay@cs.wisc.edusystem.membus.pkt_size_system.cpu.l2cache.mem_side::total 200200734 # Cumulative packet size per connected master and slave (bytes) 148111103Snilay@cs.wisc.edusystem.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7233472 # Cumulative packet size per connected master and slave (bytes) 148211103Snilay@cs.wisc.edusystem.membus.pkt_size_system.iocache.mem_side::total 7233472 # Cumulative packet size per connected master and slave (bytes) 148311103Snilay@cs.wisc.edusystem.membus.pkt_size::total 207434206 # Cumulative packet size per connected master and slave (bytes) 148411103Snilay@cs.wisc.edusystem.membus.snoops 3131 # Total snoops (count) 148511103Snilay@cs.wisc.edusystem.membus.snoop_fanout::samples 3697223 # Request fanout histogram 148610515SAli.Saidi@ARM.comsystem.membus.snoop_fanout::mean 1 # Request fanout histogram 148710515SAli.Saidi@ARM.comsystem.membus.snoop_fanout::stdev 0 # Request fanout histogram 148810515SAli.Saidi@ARM.comsystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 148910515SAli.Saidi@ARM.comsystem.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 149011103Snilay@cs.wisc.edusystem.membus.snoop_fanout::1 3697223 100.00% 100.00% # Request fanout histogram 149110515SAli.Saidi@ARM.comsystem.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 149210515SAli.Saidi@ARM.comsystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 149310515SAli.Saidi@ARM.comsystem.membus.snoop_fanout::min_value 1 # Request fanout histogram 149410515SAli.Saidi@ARM.comsystem.membus.snoop_fanout::max_value 1 # Request fanout histogram 149511103Snilay@cs.wisc.edusystem.membus.snoop_fanout::total 3697223 # Request fanout histogram 149611103Snilay@cs.wisc.edusystem.membus.reqLayer0.occupancy 102366500 # Layer occupancy (ticks) 149710515SAli.Saidi@ARM.comsystem.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 149810726Sandreas.hansson@arm.comsystem.membus.reqLayer1.occupancy 19828 # Layer occupancy (ticks) 149910515SAli.Saidi@ARM.comsystem.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 150011103Snilay@cs.wisc.edusystem.membus.reqLayer2.occupancy 5756000 # Layer occupancy (ticks) 150110515SAli.Saidi@ARM.comsystem.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 150211103Snilay@cs.wisc.edusystem.membus.reqLayer5.occupancy 9961724084 # Layer occupancy (ticks) 150310515SAli.Saidi@ARM.comsystem.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 150411103Snilay@cs.wisc.edusystem.membus.respLayer2.occupancy 9396279986 # Layer occupancy (ticks) 150510515SAli.Saidi@ARM.comsystem.membus.respLayer2.utilization 0.0 # Layer utilization (%) 150611103Snilay@cs.wisc.edusystem.membus.respLayer3.occupancy 228925719 # Layer occupancy (ticks) 150710515SAli.Saidi@ARM.comsystem.membus.respLayer3.utilization 0.0 # Layer utilization (%) 150810515SAli.Saidi@ARM.comsystem.realview.ethernet.txBytes 966 # Bytes Transmitted 150910515SAli.Saidi@ARM.comsystem.realview.ethernet.txPackets 3 # Number of Packets Transmitted 151010515SAli.Saidi@ARM.comsystem.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device 151110515SAli.Saidi@ARM.comsystem.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device 151210515SAli.Saidi@ARM.comsystem.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 151310515SAli.Saidi@ARM.comsystem.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 151410515SAli.Saidi@ARM.comsystem.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 151510515SAli.Saidi@ARM.comsystem.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 151610515SAli.Saidi@ARM.comsystem.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 151710892Sandreas.hansson@arm.comsystem.realview.ethernet.totBandwidth 149 # Total Bandwidth (bits/s) 151810515SAli.Saidi@ARM.comsystem.realview.ethernet.totPackets 3 # Total Packets 151910515SAli.Saidi@ARM.comsystem.realview.ethernet.totBytes 966 # Total Bytes 152010515SAli.Saidi@ARM.comsystem.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) 152110892Sandreas.hansson@arm.comsystem.realview.ethernet.txBandwidth 149 # Transmit Bandwidth (bits/s) 152210515SAli.Saidi@ARM.comsystem.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) 152310515SAli.Saidi@ARM.comsystem.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 152410515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post 152510515SAli.Saidi@ARM.comsystem.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 152610515SAli.Saidi@ARM.comsystem.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 152710515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post 152810515SAli.Saidi@ARM.comsystem.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 152910515SAli.Saidi@ARM.comsystem.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 153010515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post 153110515SAli.Saidi@ARM.comsystem.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 153210515SAli.Saidi@ARM.comsystem.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 153310515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post 153410515SAli.Saidi@ARM.comsystem.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 153510515SAli.Saidi@ARM.comsystem.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 153610515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post 153710515SAli.Saidi@ARM.comsystem.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 153810515SAli.Saidi@ARM.comsystem.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 153910515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post 154010515SAli.Saidi@ARM.comsystem.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 154110515SAli.Saidi@ARM.comsystem.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 154210515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 154310515SAli.Saidi@ARM.comsystem.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 154410515SAli.Saidi@ARM.comsystem.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 154510515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 154610515SAli.Saidi@ARM.comsystem.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 154710515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 154810515SAli.Saidi@ARM.comsystem.realview.ethernet.postedInterrupts 13 # number of posts to CPU 154910515SAli.Saidi@ARM.comsystem.realview.ethernet.droppedPackets 0 # number of packets dropped 155011103Snilay@cs.wisc.edusystem.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks 155111014Sandreas.sandberg@arm.comsystem.realview.realview_io.osc_clcd.clock 42105 # Clock period in ticks 155211014Sandreas.sandberg@arm.comsystem.realview.realview_io.osc_cpu.clock 16667 # Clock period in ticks 155311014Sandreas.sandberg@arm.comsystem.realview.realview_io.osc_ddr.clock 25000 # Clock period in ticks 155411014Sandreas.sandberg@arm.comsystem.realview.realview_io.osc_hsbm.clock 25000 # Clock period in ticks 155511014Sandreas.sandberg@arm.comsystem.realview.realview_io.osc_mcc.clock 20000 # Clock period in ticks 155611014Sandreas.sandberg@arm.comsystem.realview.realview_io.osc_peripheral.clock 41667 # Clock period in ticks 155711014Sandreas.sandberg@arm.comsystem.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks 155811014Sandreas.sandberg@arm.comsystem.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks 155911014Sandreas.sandberg@arm.comsystem.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks 156010515SAli.Saidi@ARM.com 156110515SAli.Saidi@ARM.com---------- End Simulation Statistics ---------- 1562