stats.txt revision 11103
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 51.694125 # Number of seconds simulated 4sim_ticks 51694125219000 # Number of ticks simulated 5final_tick 51694125219000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 131034 # Simulator instruction rate (inst/s) 8host_op_rate 153967 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 7136466436 # Simulator tick rate (ticks/s) 10host_mem_usage 718208 # Number of bytes of host memory used 11host_seconds 7243.66 # Real time elapsed on the host 12sim_insts 949163000 # Number of instructions simulated 13sim_ops 1115282140 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.dtb.walker 407680 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.itb.walker 346624 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.inst 10124864 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.data 101217736 # Number of bytes read from this memory 20system.physmem.bytes_read::realview.ide 409088 # Number of bytes read from this memory 21system.physmem.bytes_read::total 112505992 # Number of bytes read from this memory 22system.physmem.bytes_inst_read::cpu.inst 10124864 # Number of instructions bytes read from this memory 23system.physmem.bytes_inst_read::total 10124864 # Number of instructions bytes read from this memory 24system.physmem.bytes_written::writebacks 94737216 # Number of bytes written to this memory 25system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory 26system.physmem.bytes_written::total 94757796 # Number of bytes written to this memory 27system.physmem.num_reads::cpu.dtb.walker 6370 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu.itb.walker 5416 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu.inst 158201 # Number of read requests responded to by this memory 30system.physmem.num_reads::cpu.data 1581540 # Number of read requests responded to by this memory 31system.physmem.num_reads::realview.ide 6392 # Number of read requests responded to by this memory 32system.physmem.num_reads::total 1757919 # Number of read requests responded to by this memory 33system.physmem.num_writes::writebacks 1480269 # Number of write requests responded to by this memory 34system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory 35system.physmem.num_writes::total 1482842 # Number of write requests responded to by this memory 36system.physmem.bw_read::cpu.dtb.walker 7886 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::cpu.itb.walker 6705 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu.inst 195861 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::cpu.data 1958012 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::realview.ide 7914 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_read::total 2176379 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_inst_read::cpu.inst 195861 # Instruction read bandwidth from this memory (bytes/s) 43system.physmem.bw_inst_read::total 195861 # Instruction read bandwidth from this memory (bytes/s) 44system.physmem.bw_write::writebacks 1832650 # Write bandwidth from this memory (bytes/s) 45system.physmem.bw_write::cpu.data 398 # Write bandwidth from this memory (bytes/s) 46system.physmem.bw_write::total 1833048 # Write bandwidth from this memory (bytes/s) 47system.physmem.bw_total::writebacks 1832650 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::cpu.dtb.walker 7886 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu.itb.walker 6705 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu.inst 195861 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::cpu.data 1958410 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::realview.ide 7914 # Total bandwidth to/from this memory (bytes/s) 53system.physmem.bw_total::total 4009426 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.readReqs 1757919 # Number of read requests accepted 55system.physmem.writeReqs 1482842 # Number of write requests accepted 56system.physmem.readBursts 1757919 # Number of DRAM read bursts, including those serviced by the write queue 57system.physmem.writeBursts 1482842 # Number of DRAM write bursts, including those merged in the write queue 58system.physmem.bytesReadDRAM 112457536 # Total number of bytes read from DRAM 59system.physmem.bytesReadWrQ 49280 # Total number of bytes read from write queue 60system.physmem.bytesWritten 94756288 # Total number of bytes written to DRAM 61system.physmem.bytesReadSys 112505992 # Total read bytes from the system interface side 62system.physmem.bytesWrittenSys 94757796 # Total written bytes from the system interface side 63system.physmem.servicedByWrQ 770 # Number of DRAM read bursts serviced by the write queue 64system.physmem.mergedWrBursts 2248 # Number of DRAM write bursts merged with an existing one 65system.physmem.neitherReadNorWriteReqs 146200 # Number of requests that are neither read nor write 66system.physmem.perBankRdBursts::0 105973 # Per bank write bursts 67system.physmem.perBankRdBursts::1 111407 # Per bank write bursts 68system.physmem.perBankRdBursts::2 105002 # Per bank write bursts 69system.physmem.perBankRdBursts::3 101812 # Per bank write bursts 70system.physmem.perBankRdBursts::4 108332 # Per bank write bursts 71system.physmem.perBankRdBursts::5 117578 # Per bank write bursts 72system.physmem.perBankRdBursts::6 104534 # Per bank write bursts 73system.physmem.perBankRdBursts::7 108687 # Per bank write bursts 74system.physmem.perBankRdBursts::8 103848 # Per bank write bursts 75system.physmem.perBankRdBursts::9 161007 # Per bank write bursts 76system.physmem.perBankRdBursts::10 107405 # Per bank write bursts 77system.physmem.perBankRdBursts::11 110838 # Per bank write bursts 78system.physmem.perBankRdBursts::12 104563 # Per bank write bursts 79system.physmem.perBankRdBursts::13 103815 # Per bank write bursts 80system.physmem.perBankRdBursts::14 100822 # Per bank write bursts 81system.physmem.perBankRdBursts::15 101526 # Per bank write bursts 82system.physmem.perBankWrBursts::0 90430 # Per bank write bursts 83system.physmem.perBankWrBursts::1 94995 # Per bank write bursts 84system.physmem.perBankWrBursts::2 91678 # Per bank write bursts 85system.physmem.perBankWrBursts::3 90022 # Per bank write bursts 86system.physmem.perBankWrBursts::4 94229 # Per bank write bursts 87system.physmem.perBankWrBursts::5 99888 # Per bank write bursts 88system.physmem.perBankWrBursts::6 89385 # Per bank write bursts 89system.physmem.perBankWrBursts::7 93994 # Per bank write bursts 90system.physmem.perBankWrBursts::8 90076 # Per bank write bursts 91system.physmem.perBankWrBursts::9 95745 # Per bank write bursts 92system.physmem.perBankWrBursts::10 91874 # Per bank write bursts 93system.physmem.perBankWrBursts::11 95898 # Per bank write bursts 94system.physmem.perBankWrBursts::12 91438 # Per bank write bursts 95system.physmem.perBankWrBursts::13 92023 # Per bank write bursts 96system.physmem.perBankWrBursts::14 89075 # Per bank write bursts 97system.physmem.perBankWrBursts::15 89817 # Per bank write bursts 98system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 99system.physmem.numWrRetry 27 # Number of times write queue was full causing retry 100system.physmem.totGap 51694123514000 # Total gap between requests 101system.physmem.readPktSize::0 0 # Read request sizes (log2) 102system.physmem.readPktSize::1 0 # Read request sizes (log2) 103system.physmem.readPktSize::2 0 # Read request sizes (log2) 104system.physmem.readPktSize::3 13 # Read request sizes (log2) 105system.physmem.readPktSize::4 2 # Read request sizes (log2) 106system.physmem.readPktSize::5 0 # Read request sizes (log2) 107system.physmem.readPktSize::6 1757904 # Read request sizes (log2) 108system.physmem.writePktSize::0 0 # Write request sizes (log2) 109system.physmem.writePktSize::1 0 # Write request sizes (log2) 110system.physmem.writePktSize::2 1 # Write request sizes (log2) 111system.physmem.writePktSize::3 2572 # Write request sizes (log2) 112system.physmem.writePktSize::4 0 # Write request sizes (log2) 113system.physmem.writePktSize::5 0 # Write request sizes (log2) 114system.physmem.writePktSize::6 1480269 # Write request sizes (log2) 115system.physmem.rdQLenPdf::0 1422025 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::1 328688 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::2 1048 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::3 351 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::4 481 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::5 469 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::6 492 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::7 522 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::8 773 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::9 906 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::10 358 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::11 190 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::12 168 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::13 130 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::14 117 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::15 106 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::16 93 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::17 92 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::18 77 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::19 57 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::20 4 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::21 2 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 147system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::15 15568 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::16 18151 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::17 71947 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::18 88213 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::19 88480 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::20 88386 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::21 88377 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::22 91264 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::23 92065 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::24 94405 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::25 93246 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::26 93724 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::27 90170 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::28 90391 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::29 100271 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::30 88772 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::31 90332 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::32 87233 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::33 738 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::34 612 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::35 700 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::36 613 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::37 492 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::38 421 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::39 484 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::40 399 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::41 400 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::42 350 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::43 281 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::44 352 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::45 261 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::46 306 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::47 263 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::48 275 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::49 253 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::50 240 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::51 271 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::52 253 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::53 203 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::54 244 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::55 219 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::56 182 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::57 159 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::58 123 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::59 105 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::60 110 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::61 129 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::62 63 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::63 83 # What write queue length does an incoming req see 211system.physmem.bytesPerActivate::samples 690739 # Bytes accessed per row activation 212system.physmem.bytesPerActivate::mean 299.988042 # Bytes accessed per row activation 213system.physmem.bytesPerActivate::gmean 174.369601 # Bytes accessed per row activation 214system.physmem.bytesPerActivate::stdev 327.443819 # Bytes accessed per row activation 215system.physmem.bytesPerActivate::0-127 271817 39.35% 39.35% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::128-255 165800 24.00% 63.35% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::256-383 63380 9.18% 72.53% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::384-511 36796 5.33% 77.86% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::512-639 26984 3.91% 81.76% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::640-767 18833 2.73% 84.49% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::768-895 14857 2.15% 86.64% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::896-1023 13605 1.97% 88.61% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::1024-1151 78667 11.39% 100.00% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::total 690739 # Bytes accessed per row activation 225system.physmem.rdPerTurnAround::samples 86593 # Reads before turning the bus around for writes 226system.physmem.rdPerTurnAround::mean 20.291686 # Reads before turning the bus around for writes 227system.physmem.rdPerTurnAround::stdev 270.345126 # Reads before turning the bus around for writes 228system.physmem.rdPerTurnAround::0-4095 86590 100.00% 100.00% # Reads before turning the bus around for writes 229system.physmem.rdPerTurnAround::4096-8191 1 0.00% 100.00% # Reads before turning the bus around for writes 230system.physmem.rdPerTurnAround::24576-28671 1 0.00% 100.00% # Reads before turning the bus around for writes 231system.physmem.rdPerTurnAround::73728-77823 1 0.00% 100.00% # Reads before turning the bus around for writes 232system.physmem.rdPerTurnAround::total 86593 # Reads before turning the bus around for writes 233system.physmem.wrPerTurnAround::samples 86593 # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::mean 17.097999 # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::gmean 16.728630 # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::stdev 5.809360 # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::16-19 84121 97.15% 97.15% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::20-23 149 0.17% 97.32% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::24-27 413 0.48% 97.79% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::28-31 198 0.23% 98.02% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::32-35 310 0.36% 98.38% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::36-39 507 0.59% 98.97% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::40-43 123 0.14% 99.11% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::44-47 35 0.04% 99.15% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::48-51 41 0.05% 99.20% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::52-55 24 0.03% 99.22% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::56-59 40 0.05% 99.27% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::60-63 29 0.03% 99.30% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::64-67 413 0.48% 99.78% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::68-71 31 0.04% 99.82% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::72-75 42 0.05% 99.86% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::76-79 40 0.05% 99.91% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::80-83 8 0.01% 99.92% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::84-87 3 0.00% 99.92% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::88-91 4 0.00% 99.93% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::92-95 4 0.00% 99.93% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::96-99 1 0.00% 99.93% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::100-103 4 0.00% 99.94% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::112-115 2 0.00% 99.94% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::120-123 1 0.00% 99.94% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::124-127 3 0.00% 99.95% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::128-131 31 0.04% 99.98% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::136-139 2 0.00% 99.98% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::140-143 2 0.00% 99.99% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::144-147 1 0.00% 99.99% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::148-151 3 0.00% 99.99% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::160-163 1 0.00% 99.99% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::164-167 2 0.00% 99.99% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::172-175 1 0.00% 100.00% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::176-179 4 0.00% 100.00% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::total 86593 # Writes before turning the bus around for reads 272system.physmem.totQLat 26847024830 # Total ticks spent queuing 273system.physmem.totMemAccLat 59793568580 # Total ticks spent from burst creation until serviced by the DRAM 274system.physmem.totBusLat 8785745000 # Total ticks spent in databus transfers 275system.physmem.avgQLat 15278.74 # Average queueing delay per DRAM burst 276system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 277system.physmem.avgMemAccLat 34028.74 # Average memory access latency per DRAM burst 278system.physmem.avgRdBW 2.18 # Average DRAM read bandwidth in MiByte/s 279system.physmem.avgWrBW 1.83 # Average achieved write bandwidth in MiByte/s 280system.physmem.avgRdBWSys 2.18 # Average system read bandwidth in MiByte/s 281system.physmem.avgWrBWSys 1.83 # Average system write bandwidth in MiByte/s 282system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 283system.physmem.busUtil 0.03 # Data bus utilization in percentage 284system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads 285system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes 286system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing 287system.physmem.avgWrQLen 23.96 # Average write queue length when enqueuing 288system.physmem.readRowHits 1436721 # Number of row buffer hits during reads 289system.physmem.writeRowHits 1110255 # Number of row buffer hits during writes 290system.physmem.readRowHitRate 81.76 # Row buffer hit rate for reads 291system.physmem.writeRowHitRate 74.99 # Row buffer hit rate for writes 292system.physmem.avgGap 15951229.82 # Average gap between requests 293system.physmem.pageHitRate 78.67 # Row buffer hit rate, read and write combined 294system.physmem_0.actEnergy 2651919480 # Energy for activate commands per rank (pJ) 295system.physmem_0.preEnergy 1446979875 # Energy for precharge commands per rank (pJ) 296system.physmem_0.readEnergy 6733888200 # Energy for read commands per rank (pJ) 297system.physmem_0.writeEnergy 4825144080 # Energy for write commands per rank (pJ) 298system.physmem_0.refreshEnergy 3376408666800 # Energy for refresh commands per rank (pJ) 299system.physmem_0.actBackEnergy 1308234674070 # Energy for active background per rank (pJ) 300system.physmem_0.preBackEnergy 29868898243500 # Energy for precharge background per rank (pJ) 301system.physmem_0.totalEnergy 34569199516005 # Total energy per rank (pJ) 302system.physmem_0.averagePower 668.725939 # Core power per rank (mW) 303system.physmem_0.memoryStateTime::IDLE 49688706621634 # Time in different power states 304system.physmem_0.memoryStateTime::REF 1726180300000 # Time in different power states 305system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 306system.physmem_0.memoryStateTime::ACT 279237825366 # Time in different power states 307system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 308system.physmem_1.actEnergy 2570067360 # Energy for activate commands per rank (pJ) 309system.physmem_1.preEnergy 1402318500 # Energy for precharge commands per rank (pJ) 310system.physmem_1.readEnergy 6971827200 # Energy for read commands per rank (pJ) 311system.physmem_1.writeEnergy 4768930080 # Energy for write commands per rank (pJ) 312system.physmem_1.refreshEnergy 3376408666800 # Energy for refresh commands per rank (pJ) 313system.physmem_1.actBackEnergy 1306063695690 # Energy for active background per rank (pJ) 314system.physmem_1.preBackEnergy 29870802610500 # Energy for precharge background per rank (pJ) 315system.physmem_1.totalEnergy 34568988116130 # Total energy per rank (pJ) 316system.physmem_1.averagePower 668.721850 # Core power per rank (mW) 317system.physmem_1.memoryStateTime::IDLE 49691848230640 # Time in different power states 318system.physmem_1.memoryStateTime::REF 1726180300000 # Time in different power states 319system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 320system.physmem_1.memoryStateTime::ACT 276092348110 # Time in different power states 321system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 322system.realview.nvmem.bytes_read::cpu.inst 704 # Number of bytes read from this memory 323system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory 324system.realview.nvmem.bytes_read::total 740 # Number of bytes read from this memory 325system.realview.nvmem.bytes_inst_read::cpu.inst 704 # Number of instructions bytes read from this memory 326system.realview.nvmem.bytes_inst_read::total 704 # Number of instructions bytes read from this memory 327system.realview.nvmem.num_reads::cpu.inst 11 # Number of read requests responded to by this memory 328system.realview.nvmem.num_reads::cpu.data 5 # Number of read requests responded to by this memory 329system.realview.nvmem.num_reads::total 16 # Number of read requests responded to by this memory 330system.realview.nvmem.bw_read::cpu.inst 14 # Total read bandwidth from this memory (bytes/s) 331system.realview.nvmem.bw_read::cpu.data 1 # Total read bandwidth from this memory (bytes/s) 332system.realview.nvmem.bw_read::total 14 # Total read bandwidth from this memory (bytes/s) 333system.realview.nvmem.bw_inst_read::cpu.inst 14 # Instruction read bandwidth from this memory (bytes/s) 334system.realview.nvmem.bw_inst_read::total 14 # Instruction read bandwidth from this memory (bytes/s) 335system.realview.nvmem.bw_total::cpu.inst 14 # Total bandwidth to/from this memory (bytes/s) 336system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s) 337system.realview.nvmem.bw_total::total 14 # Total bandwidth to/from this memory (bytes/s) 338system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 339system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 340system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 341system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. 342system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. 343system.cf0.dma_write_txs 1669 # Number of DMA write transactions. 344system.cpu.branchPred.lookups 260286663 # Number of BP lookups 345system.cpu.branchPred.condPredicted 182589592 # Number of conditional branches predicted 346system.cpu.branchPred.condIncorrect 12077009 # Number of conditional branches incorrect 347system.cpu.branchPred.BTBLookups 191806323 # Number of BTB lookups 348system.cpu.branchPred.BTBHits 136128585 # Number of BTB hits 349system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 350system.cpu.branchPred.BTBHitPct 70.971896 # BTB Hit Percentage 351system.cpu.branchPred.usedRAS 31602025 # Number of times the RAS was used to get a target. 352system.cpu.branchPred.RASInCorrect 2167880 # Number of incorrect RAS predictions. 353system.cpu_clk_domain.clock 500 # Clock period in ticks 354system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 355system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 356system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 357system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 358system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 359system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 360system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 361system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 362system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 363system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 364system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 365system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 366system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 367system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 368system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 369system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 370system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 371system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 372system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 373system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 374system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 375system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 376system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 377system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 378system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 379system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 380system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 381system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 382system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 383system.cpu.dtb.walker.walks 582770 # Table walker walks requested 384system.cpu.dtb.walker.walksLong 582770 # Table walker walks initiated with long descriptors 385system.cpu.dtb.walker.walksLongTerminationLevel::Level2 22376 # Level at which table walker walks with long descriptors terminate 386system.cpu.dtb.walker.walksLongTerminationLevel::Level3 191329 # Level at which table walker walks with long descriptors terminate 387system.cpu.dtb.walker.walkWaitTime::samples 582770 # Table walker wait (enqueue to first request) latency 388system.cpu.dtb.walker.walkWaitTime::0 582770 100.00% 100.00% # Table walker wait (enqueue to first request) latency 389system.cpu.dtb.walker.walkWaitTime::total 582770 # Table walker wait (enqueue to first request) latency 390system.cpu.dtb.walker.walkCompletionTime::samples 213705 # Table walker service (enqueue to completion) latency 391system.cpu.dtb.walker.walkCompletionTime::mean 26351.678716 # Table walker service (enqueue to completion) latency 392system.cpu.dtb.walker.walkCompletionTime::gmean 22931.447770 # Table walker service (enqueue to completion) latency 393system.cpu.dtb.walker.walkCompletionTime::stdev 15578.711548 # Table walker service (enqueue to completion) latency 394system.cpu.dtb.walker.walkCompletionTime::0-65535 211142 98.80% 98.80% # Table walker service (enqueue to completion) latency 395system.cpu.dtb.walker.walkCompletionTime::65536-131071 2168 1.01% 99.82% # Table walker service (enqueue to completion) latency 396system.cpu.dtb.walker.walkCompletionTime::131072-196607 149 0.07% 99.88% # Table walker service (enqueue to completion) latency 397system.cpu.dtb.walker.walkCompletionTime::196608-262143 124 0.06% 99.94% # Table walker service (enqueue to completion) latency 398system.cpu.dtb.walker.walkCompletionTime::262144-327679 84 0.04% 99.98% # Table walker service (enqueue to completion) latency 399system.cpu.dtb.walker.walkCompletionTime::327680-393215 25 0.01% 99.99% # Table walker service (enqueue to completion) latency 400system.cpu.dtb.walker.walkCompletionTime::393216-458751 6 0.00% 100.00% # Table walker service (enqueue to completion) latency 401system.cpu.dtb.walker.walkCompletionTime::458752-524287 6 0.00% 100.00% # Table walker service (enqueue to completion) latency 402system.cpu.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 403system.cpu.dtb.walker.walkCompletionTime::total 213705 # Table walker service (enqueue to completion) latency 404system.cpu.dtb.walker.walksPending::samples -58656296 # Table walker pending requests distribution 405system.cpu.dtb.walker.walksPending::0 -58656296 100.00% 100.00% # Table walker pending requests distribution 406system.cpu.dtb.walker.walksPending::total -58656296 # Table walker pending requests distribution 407system.cpu.dtb.walker.walkPageSizes::4K 191330 89.53% 89.53% # Table walker page sizes translated 408system.cpu.dtb.walker.walkPageSizes::2M 22376 10.47% 100.00% # Table walker page sizes translated 409system.cpu.dtb.walker.walkPageSizes::total 213706 # Table walker page sizes translated 410system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 582770 # Table walker requests started/completed, data/inst 411system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 412system.cpu.dtb.walker.walkRequestOrigin_Requested::total 582770 # Table walker requests started/completed, data/inst 413system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 213706 # Table walker requests started/completed, data/inst 414system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 415system.cpu.dtb.walker.walkRequestOrigin_Completed::total 213706 # Table walker requests started/completed, data/inst 416system.cpu.dtb.walker.walkRequestOrigin::total 796476 # Table walker requests started/completed, data/inst 417system.cpu.dtb.inst_hits 0 # ITB inst hits 418system.cpu.dtb.inst_misses 0 # ITB inst misses 419system.cpu.dtb.read_hits 183257458 # DTB read hits 420system.cpu.dtb.read_misses 481031 # DTB read misses 421system.cpu.dtb.write_hits 162586595 # DTB write hits 422system.cpu.dtb.write_misses 101739 # DTB write misses 423system.cpu.dtb.flush_tlb 11 # Number of times complete TLB was flushed 424system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 425system.cpu.dtb.flush_tlb_mva_asid 47231 # Number of times TLB was flushed by MVA & ASID 426system.cpu.dtb.flush_tlb_asid 1111 # Number of times TLB was flushed by ASID 427system.cpu.dtb.flush_entries 80339 # Number of entries that have been flushed from TLB 428system.cpu.dtb.align_faults 1450 # Number of TLB faults due to alignment restrictions 429system.cpu.dtb.prefetch_faults 15121 # Number of TLB faults due to prefetch 430system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 431system.cpu.dtb.perms_faults 23575 # Number of TLB faults due to permissions restrictions 432system.cpu.dtb.read_accesses 183738489 # DTB read accesses 433system.cpu.dtb.write_accesses 162688334 # DTB write accesses 434system.cpu.dtb.inst_accesses 0 # ITB inst accesses 435system.cpu.dtb.hits 345844053 # DTB hits 436system.cpu.dtb.misses 582770 # DTB misses 437system.cpu.dtb.accesses 346426823 # DTB accesses 438system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 439system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 440system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 441system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 442system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 443system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 444system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 445system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 446system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 447system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 448system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 449system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 450system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 451system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 452system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 453system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 454system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 455system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 456system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 457system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 458system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 459system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 460system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 461system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 462system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 463system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 464system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 465system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 466system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 467system.cpu.itb.walker.walks 136614 # Table walker walks requested 468system.cpu.itb.walker.walksLong 136614 # Table walker walks initiated with long descriptors 469system.cpu.itb.walker.walksLongTerminationLevel::Level2 1073 # Level at which table walker walks with long descriptors terminate 470system.cpu.itb.walker.walksLongTerminationLevel::Level3 118911 # Level at which table walker walks with long descriptors terminate 471system.cpu.itb.walker.walkWaitTime::samples 136614 # Table walker wait (enqueue to first request) latency 472system.cpu.itb.walker.walkWaitTime::0 136614 100.00% 100.00% # Table walker wait (enqueue to first request) latency 473system.cpu.itb.walker.walkWaitTime::total 136614 # Table walker wait (enqueue to first request) latency 474system.cpu.itb.walker.walkCompletionTime::samples 119984 # Table walker service (enqueue to completion) latency 475system.cpu.itb.walker.walkCompletionTime::mean 28837.324143 # Table walker service (enqueue to completion) latency 476system.cpu.itb.walker.walkCompletionTime::gmean 25253.165818 # Table walker service (enqueue to completion) latency 477system.cpu.itb.walker.walkCompletionTime::stdev 17670.490053 # Table walker service (enqueue to completion) latency 478system.cpu.itb.walker.walkCompletionTime::0-65535 116985 97.50% 97.50% # Table walker service (enqueue to completion) latency 479system.cpu.itb.walker.walkCompletionTime::65536-131071 2707 2.26% 99.76% # Table walker service (enqueue to completion) latency 480system.cpu.itb.walker.walkCompletionTime::131072-196607 180 0.15% 99.91% # Table walker service (enqueue to completion) latency 481system.cpu.itb.walker.walkCompletionTime::196608-262143 56 0.05% 99.95% # Table walker service (enqueue to completion) latency 482system.cpu.itb.walker.walkCompletionTime::262144-327679 24 0.02% 99.97% # Table walker service (enqueue to completion) latency 483system.cpu.itb.walker.walkCompletionTime::327680-393215 27 0.02% 100.00% # Table walker service (enqueue to completion) latency 484system.cpu.itb.walker.walkCompletionTime::393216-458751 3 0.00% 100.00% # Table walker service (enqueue to completion) latency 485system.cpu.itb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 486system.cpu.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 487system.cpu.itb.walker.walkCompletionTime::total 119984 # Table walker service (enqueue to completion) latency 488system.cpu.itb.walker.walksPending::samples -59528796 # Table walker pending requests distribution 489system.cpu.itb.walker.walksPending::0 -59528796 100.00% 100.00% # Table walker pending requests distribution 490system.cpu.itb.walker.walksPending::total -59528796 # Table walker pending requests distribution 491system.cpu.itb.walker.walkPageSizes::4K 118911 99.11% 99.11% # Table walker page sizes translated 492system.cpu.itb.walker.walkPageSizes::2M 1073 0.89% 100.00% # Table walker page sizes translated 493system.cpu.itb.walker.walkPageSizes::total 119984 # Table walker page sizes translated 494system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 495system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 136614 # Table walker requests started/completed, data/inst 496system.cpu.itb.walker.walkRequestOrigin_Requested::total 136614 # Table walker requests started/completed, data/inst 497system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 498system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 119984 # Table walker requests started/completed, data/inst 499system.cpu.itb.walker.walkRequestOrigin_Completed::total 119984 # Table walker requests started/completed, data/inst 500system.cpu.itb.walker.walkRequestOrigin::total 256598 # Table walker requests started/completed, data/inst 501system.cpu.itb.inst_hits 452975639 # ITB inst hits 502system.cpu.itb.inst_misses 136614 # ITB inst misses 503system.cpu.itb.read_hits 0 # DTB read hits 504system.cpu.itb.read_misses 0 # DTB read misses 505system.cpu.itb.write_hits 0 # DTB write hits 506system.cpu.itb.write_misses 0 # DTB write misses 507system.cpu.itb.flush_tlb 11 # Number of times complete TLB was flushed 508system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 509system.cpu.itb.flush_tlb_mva_asid 47231 # Number of times TLB was flushed by MVA & ASID 510system.cpu.itb.flush_tlb_asid 1111 # Number of times TLB was flushed by ASID 511system.cpu.itb.flush_entries 57698 # Number of entries that have been flushed from TLB 512system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 513system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 514system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 515system.cpu.itb.perms_faults 370160 # Number of TLB faults due to permissions restrictions 516system.cpu.itb.read_accesses 0 # DTB read accesses 517system.cpu.itb.write_accesses 0 # DTB write accesses 518system.cpu.itb.inst_accesses 453112253 # ITB inst accesses 519system.cpu.itb.hits 452975639 # DTB hits 520system.cpu.itb.misses 136614 # DTB misses 521system.cpu.itb.accesses 453112253 # DTB accesses 522system.cpu.numCycles 2511767999 # number of cpu cycles simulated 523system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 524system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 525system.cpu.committedInsts 949163000 # Number of instructions committed 526system.cpu.committedOps 1115282140 # Number of ops (including micro ops) committed 527system.cpu.discardedOps 97160712 # Number of ops (including micro ops) which were discarded before commit 528system.cpu.numFetchSuspends 7743 # Number of times Execute suspended instruction fetching 529system.cpu.quiesceCycles 100877722288 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 530system.cpu.cpi 2.646298 # CPI: cycles per instruction 531system.cpu.ipc 0.377886 # IPC: instructions per cycle 532system.cpu.kern.inst.arm 0 # number of arm instructions executed 533system.cpu.kern.inst.quiesce 19481 # number of quiesce instructions executed 534system.cpu.tickCycles 1790897935 # Number of cycles that the object actually ticked 535system.cpu.idleCycles 720870064 # Total number of cycles that the object has spent stopped 536system.cpu.dcache.tags.replacements 11142195 # number of replacements 537system.cpu.dcache.tags.tagsinuse 511.957822 # Cycle average of tags in use 538system.cpu.dcache.tags.total_refs 329410408 # Total number of references to valid blocks. 539system.cpu.dcache.tags.sampled_refs 11142707 # Sample count of references to valid blocks. 540system.cpu.dcache.tags.avg_refs 29.562871 # Average number of references to valid blocks. 541system.cpu.dcache.tags.warmup_cycle 4277412500 # Cycle when the warmup percentage was hit. 542system.cpu.dcache.tags.occ_blocks::cpu.data 511.957822 # Average occupied blocks per requestor 543system.cpu.dcache.tags.occ_percent::cpu.data 0.999918 # Average percentage of cache occupancy 544system.cpu.dcache.tags.occ_percent::total 0.999918 # Average percentage of cache occupancy 545system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 546system.cpu.dcache.tags.age_task_id_blocks_1024::0 70 # Occupied blocks per task id 547system.cpu.dcache.tags.age_task_id_blocks_1024::1 385 # Occupied blocks per task id 548system.cpu.dcache.tags.age_task_id_blocks_1024::2 57 # Occupied blocks per task id 549system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 550system.cpu.dcache.tags.tag_accesses 1384553632 # Number of tag accesses 551system.cpu.dcache.tags.data_accesses 1384553632 # Number of data accesses 552system.cpu.dcache.ReadReq_hits::cpu.data 168394927 # number of ReadReq hits 553system.cpu.dcache.ReadReq_hits::total 168394927 # number of ReadReq hits 554system.cpu.dcache.WriteReq_hits::cpu.data 151754199 # number of WriteReq hits 555system.cpu.dcache.WriteReq_hits::total 151754199 # number of WriteReq hits 556system.cpu.dcache.SoftPFReq_hits::cpu.data 523439 # number of SoftPFReq hits 557system.cpu.dcache.SoftPFReq_hits::total 523439 # number of SoftPFReq hits 558system.cpu.dcache.WriteLineReq_hits::cpu.data 336679 # number of WriteLineReq hits 559system.cpu.dcache.WriteLineReq_hits::total 336679 # number of WriteLineReq hits 560system.cpu.dcache.LoadLockedReq_hits::cpu.data 4017108 # number of LoadLockedReq hits 561system.cpu.dcache.LoadLockedReq_hits::total 4017108 # number of LoadLockedReq hits 562system.cpu.dcache.StoreCondReq_hits::cpu.data 4334477 # number of StoreCondReq hits 563system.cpu.dcache.StoreCondReq_hits::total 4334477 # number of StoreCondReq hits 564system.cpu.dcache.demand_hits::cpu.data 320149126 # number of demand (read+write) hits 565system.cpu.dcache.demand_hits::total 320149126 # number of demand (read+write) hits 566system.cpu.dcache.overall_hits::cpu.data 320672565 # number of overall hits 567system.cpu.dcache.overall_hits::total 320672565 # number of overall hits 568system.cpu.dcache.ReadReq_misses::cpu.data 6628843 # number of ReadReq misses 569system.cpu.dcache.ReadReq_misses::total 6628843 # number of ReadReq misses 570system.cpu.dcache.WriteReq_misses::cpu.data 4317749 # number of WriteReq misses 571system.cpu.dcache.WriteReq_misses::total 4317749 # number of WriteReq misses 572system.cpu.dcache.SoftPFReq_misses::cpu.data 1481094 # number of SoftPFReq misses 573system.cpu.dcache.SoftPFReq_misses::total 1481094 # number of SoftPFReq misses 574system.cpu.dcache.WriteLineReq_misses::cpu.data 1245106 # number of WriteLineReq misses 575system.cpu.dcache.WriteLineReq_misses::total 1245106 # number of WriteLineReq misses 576system.cpu.dcache.LoadLockedReq_misses::cpu.data 319103 # number of LoadLockedReq misses 577system.cpu.dcache.LoadLockedReq_misses::total 319103 # number of LoadLockedReq misses 578system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses 579system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses 580system.cpu.dcache.demand_misses::cpu.data 10946592 # number of demand (read+write) misses 581system.cpu.dcache.demand_misses::total 10946592 # number of demand (read+write) misses 582system.cpu.dcache.overall_misses::cpu.data 12427686 # number of overall misses 583system.cpu.dcache.overall_misses::total 12427686 # number of overall misses 584system.cpu.dcache.ReadReq_miss_latency::cpu.data 107264639000 # number of ReadReq miss cycles 585system.cpu.dcache.ReadReq_miss_latency::total 107264639000 # number of ReadReq miss cycles 586system.cpu.dcache.WriteReq_miss_latency::cpu.data 153170066000 # number of WriteReq miss cycles 587system.cpu.dcache.WriteReq_miss_latency::total 153170066000 # number of WriteReq miss cycles 588system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 58641269000 # number of WriteLineReq miss cycles 589system.cpu.dcache.WriteLineReq_miss_latency::total 58641269000 # number of WriteLineReq miss cycles 590system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 4837420500 # number of LoadLockedReq miss cycles 591system.cpu.dcache.LoadLockedReq_miss_latency::total 4837420500 # number of LoadLockedReq miss cycles 592system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 115500 # number of StoreCondReq miss cycles 593system.cpu.dcache.StoreCondReq_miss_latency::total 115500 # number of StoreCondReq miss cycles 594system.cpu.dcache.demand_miss_latency::cpu.data 260434705000 # number of demand (read+write) miss cycles 595system.cpu.dcache.demand_miss_latency::total 260434705000 # number of demand (read+write) miss cycles 596system.cpu.dcache.overall_miss_latency::cpu.data 260434705000 # number of overall miss cycles 597system.cpu.dcache.overall_miss_latency::total 260434705000 # number of overall miss cycles 598system.cpu.dcache.ReadReq_accesses::cpu.data 175023770 # number of ReadReq accesses(hits+misses) 599system.cpu.dcache.ReadReq_accesses::total 175023770 # number of ReadReq accesses(hits+misses) 600system.cpu.dcache.WriteReq_accesses::cpu.data 156071948 # number of WriteReq accesses(hits+misses) 601system.cpu.dcache.WriteReq_accesses::total 156071948 # number of WriteReq accesses(hits+misses) 602system.cpu.dcache.SoftPFReq_accesses::cpu.data 2004533 # number of SoftPFReq accesses(hits+misses) 603system.cpu.dcache.SoftPFReq_accesses::total 2004533 # number of SoftPFReq accesses(hits+misses) 604system.cpu.dcache.WriteLineReq_accesses::cpu.data 1581785 # number of WriteLineReq accesses(hits+misses) 605system.cpu.dcache.WriteLineReq_accesses::total 1581785 # number of WriteLineReq accesses(hits+misses) 606system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4336211 # number of LoadLockedReq accesses(hits+misses) 607system.cpu.dcache.LoadLockedReq_accesses::total 4336211 # number of LoadLockedReq accesses(hits+misses) 608system.cpu.dcache.StoreCondReq_accesses::cpu.data 4334479 # number of StoreCondReq accesses(hits+misses) 609system.cpu.dcache.StoreCondReq_accesses::total 4334479 # number of StoreCondReq accesses(hits+misses) 610system.cpu.dcache.demand_accesses::cpu.data 331095718 # number of demand (read+write) accesses 611system.cpu.dcache.demand_accesses::total 331095718 # number of demand (read+write) accesses 612system.cpu.dcache.overall_accesses::cpu.data 333100251 # number of overall (read+write) accesses 613system.cpu.dcache.overall_accesses::total 333100251 # number of overall (read+write) accesses 614system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.037874 # miss rate for ReadReq accesses 615system.cpu.dcache.ReadReq_miss_rate::total 0.037874 # miss rate for ReadReq accesses 616system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.027665 # miss rate for WriteReq accesses 617system.cpu.dcache.WriteReq_miss_rate::total 0.027665 # miss rate for WriteReq accesses 618system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.738872 # miss rate for SoftPFReq accesses 619system.cpu.dcache.SoftPFReq_miss_rate::total 0.738872 # miss rate for SoftPFReq accesses 620system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.787152 # miss rate for WriteLineReq accesses 621system.cpu.dcache.WriteLineReq_miss_rate::total 0.787152 # miss rate for WriteLineReq accesses 622system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.073590 # miss rate for LoadLockedReq accesses 623system.cpu.dcache.LoadLockedReq_miss_rate::total 0.073590 # miss rate for LoadLockedReq accesses 624system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000000 # miss rate for StoreCondReq accesses 625system.cpu.dcache.StoreCondReq_miss_rate::total 0.000000 # miss rate for StoreCondReq accesses 626system.cpu.dcache.demand_miss_rate::cpu.data 0.033062 # miss rate for demand accesses 627system.cpu.dcache.demand_miss_rate::total 0.033062 # miss rate for demand accesses 628system.cpu.dcache.overall_miss_rate::cpu.data 0.037309 # miss rate for overall accesses 629system.cpu.dcache.overall_miss_rate::total 0.037309 # miss rate for overall accesses 630system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16181.502413 # average ReadReq miss latency 631system.cpu.dcache.ReadReq_avg_miss_latency::total 16181.502413 # average ReadReq miss latency 632system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35474.518320 # average WriteReq miss latency 633system.cpu.dcache.WriteReq_avg_miss_latency::total 35474.518320 # average WriteReq miss latency 634system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 47097.410983 # average WriteLineReq miss latency 635system.cpu.dcache.WriteLineReq_avg_miss_latency::total 47097.410983 # average WriteLineReq miss latency 636system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15159.432848 # average LoadLockedReq miss latency 637system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15159.432848 # average LoadLockedReq miss latency 638system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 57750 # average StoreCondReq miss latency 639system.cpu.dcache.StoreCondReq_avg_miss_latency::total 57750 # average StoreCondReq miss latency 640system.cpu.dcache.demand_avg_miss_latency::cpu.data 23791.395989 # average overall miss latency 641system.cpu.dcache.demand_avg_miss_latency::total 23791.395989 # average overall miss latency 642system.cpu.dcache.overall_avg_miss_latency::cpu.data 20956.009429 # average overall miss latency 643system.cpu.dcache.overall_avg_miss_latency::total 20956.009429 # average overall miss latency 644system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 645system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 646system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 647system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 648system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 649system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 650system.cpu.dcache.fast_writes 0 # number of fast writes performed 651system.cpu.dcache.cache_copies 0 # number of cache copies performed 652system.cpu.dcache.writebacks::writebacks 8554549 # number of writebacks 653system.cpu.dcache.writebacks::total 8554549 # number of writebacks 654system.cpu.dcache.ReadReq_mshr_hits::cpu.data 817761 # number of ReadReq MSHR hits 655system.cpu.dcache.ReadReq_mshr_hits::total 817761 # number of ReadReq MSHR hits 656system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1903794 # number of WriteReq MSHR hits 657system.cpu.dcache.WriteReq_mshr_hits::total 1903794 # number of WriteReq MSHR hits 658system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data 151 # number of WriteLineReq MSHR hits 659system.cpu.dcache.WriteLineReq_mshr_hits::total 151 # number of WriteLineReq MSHR hits 660system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 70489 # number of LoadLockedReq MSHR hits 661system.cpu.dcache.LoadLockedReq_mshr_hits::total 70489 # number of LoadLockedReq MSHR hits 662system.cpu.dcache.demand_mshr_hits::cpu.data 2721555 # number of demand (read+write) MSHR hits 663system.cpu.dcache.demand_mshr_hits::total 2721555 # number of demand (read+write) MSHR hits 664system.cpu.dcache.overall_mshr_hits::cpu.data 2721555 # number of overall MSHR hits 665system.cpu.dcache.overall_mshr_hits::total 2721555 # number of overall MSHR hits 666system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5811082 # number of ReadReq MSHR misses 667system.cpu.dcache.ReadReq_mshr_misses::total 5811082 # number of ReadReq MSHR misses 668system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2413955 # number of WriteReq MSHR misses 669system.cpu.dcache.WriteReq_mshr_misses::total 2413955 # number of WriteReq MSHR misses 670system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1473693 # number of SoftPFReq MSHR misses 671system.cpu.dcache.SoftPFReq_mshr_misses::total 1473693 # number of SoftPFReq MSHR misses 672system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1244955 # number of WriteLineReq MSHR misses 673system.cpu.dcache.WriteLineReq_mshr_misses::total 1244955 # number of WriteLineReq MSHR misses 674system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 248614 # number of LoadLockedReq MSHR misses 675system.cpu.dcache.LoadLockedReq_mshr_misses::total 248614 # number of LoadLockedReq MSHR misses 676system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses 677system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses 678system.cpu.dcache.demand_mshr_misses::cpu.data 8225037 # number of demand (read+write) MSHR misses 679system.cpu.dcache.demand_mshr_misses::total 8225037 # number of demand (read+write) MSHR misses 680system.cpu.dcache.overall_mshr_misses::cpu.data 9698730 # number of overall MSHR misses 681system.cpu.dcache.overall_mshr_misses::total 9698730 # number of overall MSHR misses 682system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33699 # number of ReadReq MSHR uncacheable 683system.cpu.dcache.ReadReq_mshr_uncacheable::total 33699 # number of ReadReq MSHR uncacheable 684system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33707 # number of WriteReq MSHR uncacheable 685system.cpu.dcache.WriteReq_mshr_uncacheable::total 33707 # number of WriteReq MSHR uncacheable 686system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67406 # number of overall MSHR uncacheable misses 687system.cpu.dcache.overall_mshr_uncacheable_misses::total 67406 # number of overall MSHR uncacheable misses 688system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 87944699500 # number of ReadReq MSHR miss cycles 689system.cpu.dcache.ReadReq_mshr_miss_latency::total 87944699500 # number of ReadReq MSHR miss cycles 690system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 80337194000 # number of WriteReq MSHR miss cycles 691system.cpu.dcache.WriteReq_mshr_miss_latency::total 80337194000 # number of WriteReq MSHR miss cycles 692system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 23656791000 # number of SoftPFReq MSHR miss cycles 693system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 23656791000 # number of SoftPFReq MSHR miss cycles 694system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 57392051500 # number of WriteLineReq MSHR miss cycles 695system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 57392051500 # number of WriteLineReq MSHR miss cycles 696system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3386354500 # number of LoadLockedReq MSHR miss cycles 697system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3386354500 # number of LoadLockedReq MSHR miss cycles 698system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 113500 # number of StoreCondReq MSHR miss cycles 699system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 113500 # number of StoreCondReq MSHR miss cycles 700system.cpu.dcache.demand_mshr_miss_latency::cpu.data 168281893500 # number of demand (read+write) MSHR miss cycles 701system.cpu.dcache.demand_mshr_miss_latency::total 168281893500 # number of demand (read+write) MSHR miss cycles 702system.cpu.dcache.overall_mshr_miss_latency::cpu.data 191938684500 # number of overall MSHR miss cycles 703system.cpu.dcache.overall_mshr_miss_latency::total 191938684500 # number of overall MSHR miss cycles 704system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5830552000 # number of ReadReq MSHR uncacheable cycles 705system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5830552000 # number of ReadReq MSHR uncacheable cycles 706system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5692063000 # number of WriteReq MSHR uncacheable cycles 707system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5692063000 # number of WriteReq MSHR uncacheable cycles 708system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11522615000 # number of overall MSHR uncacheable cycles 709system.cpu.dcache.overall_mshr_uncacheable_latency::total 11522615000 # number of overall MSHR uncacheable cycles 710system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.033202 # mshr miss rate for ReadReq accesses 711system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.033202 # mshr miss rate for ReadReq accesses 712system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015467 # mshr miss rate for WriteReq accesses 713system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015467 # mshr miss rate for WriteReq accesses 714system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.735180 # mshr miss rate for SoftPFReq accesses 715system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.735180 # mshr miss rate for SoftPFReq accesses 716system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.787057 # mshr miss rate for WriteLineReq accesses 717system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.787057 # mshr miss rate for WriteLineReq accesses 718system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.057334 # mshr miss rate for LoadLockedReq accesses 719system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.057334 # mshr miss rate for LoadLockedReq accesses 720system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000000 # mshr miss rate for StoreCondReq accesses 721system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000000 # mshr miss rate for StoreCondReq accesses 722system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.024842 # mshr miss rate for demand accesses 723system.cpu.dcache.demand_mshr_miss_rate::total 0.024842 # mshr miss rate for demand accesses 724system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.029117 # mshr miss rate for overall accesses 725system.cpu.dcache.overall_mshr_miss_rate::total 0.029117 # mshr miss rate for overall accesses 726system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15133.962918 # average ReadReq mshr miss latency 727system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15133.962918 # average ReadReq mshr miss latency 728system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33280.319641 # average WriteReq mshr miss latency 729system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33280.319641 # average WriteReq mshr miss latency 730system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16052.726721 # average SoftPFReq mshr miss latency 731system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16052.726721 # average SoftPFReq mshr miss latency 732system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 46099.699588 # average WriteLineReq mshr miss latency 733system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 46099.699588 # average WriteLineReq mshr miss latency 734system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13620.932450 # average LoadLockedReq mshr miss latency 735system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13620.932450 # average LoadLockedReq mshr miss latency 736system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 56750 # average StoreCondReq mshr miss latency 737system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 56750 # average StoreCondReq mshr miss latency 738system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20459.712643 # average overall mshr miss latency 739system.cpu.dcache.demand_avg_mshr_miss_latency::total 20459.712643 # average overall mshr miss latency 740system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19790.084320 # average overall mshr miss latency 741system.cpu.dcache.overall_avg_mshr_miss_latency::total 19790.084320 # average overall mshr miss latency 742system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 173018.546544 # average ReadReq mshr uncacheable latency 743system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 173018.546544 # average ReadReq mshr uncacheable latency 744system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 168868.869968 # average WriteReq mshr uncacheable latency 745system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 168868.869968 # average WriteReq mshr uncacheable latency 746system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 170943.462006 # average overall mshr uncacheable latency 747system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 170943.462006 # average overall mshr uncacheable latency 748system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 749system.cpu.icache.tags.replacements 24575522 # number of replacements 750system.cpu.icache.tags.tagsinuse 511.918698 # Cycle average of tags in use 751system.cpu.icache.tags.total_refs 428017274 # Total number of references to valid blocks. 752system.cpu.icache.tags.sampled_refs 24576034 # Sample count of references to valid blocks. 753system.cpu.icache.tags.avg_refs 17.416043 # Average number of references to valid blocks. 754system.cpu.icache.tags.warmup_cycle 26893274500 # Cycle when the warmup percentage was hit. 755system.cpu.icache.tags.occ_blocks::cpu.inst 511.918698 # Average occupied blocks per requestor 756system.cpu.icache.tags.occ_percent::cpu.inst 0.999841 # Average percentage of cache occupancy 757system.cpu.icache.tags.occ_percent::total 0.999841 # Average percentage of cache occupancy 758system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 759system.cpu.icache.tags.age_task_id_blocks_1024::0 95 # Occupied blocks per task id 760system.cpu.icache.tags.age_task_id_blocks_1024::1 299 # Occupied blocks per task id 761system.cpu.icache.tags.age_task_id_blocks_1024::2 118 # Occupied blocks per task id 762system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 763system.cpu.icache.tags.tag_accesses 477169361 # Number of tag accesses 764system.cpu.icache.tags.data_accesses 477169361 # Number of data accesses 765system.cpu.icache.ReadReq_hits::cpu.inst 428017274 # number of ReadReq hits 766system.cpu.icache.ReadReq_hits::total 428017274 # number of ReadReq hits 767system.cpu.icache.demand_hits::cpu.inst 428017274 # number of demand (read+write) hits 768system.cpu.icache.demand_hits::total 428017274 # number of demand (read+write) hits 769system.cpu.icache.overall_hits::cpu.inst 428017274 # number of overall hits 770system.cpu.icache.overall_hits::total 428017274 # number of overall hits 771system.cpu.icache.ReadReq_misses::cpu.inst 24576044 # number of ReadReq misses 772system.cpu.icache.ReadReq_misses::total 24576044 # number of ReadReq misses 773system.cpu.icache.demand_misses::cpu.inst 24576044 # number of demand (read+write) misses 774system.cpu.icache.demand_misses::total 24576044 # number of demand (read+write) misses 775system.cpu.icache.overall_misses::cpu.inst 24576044 # number of overall misses 776system.cpu.icache.overall_misses::total 24576044 # number of overall misses 777system.cpu.icache.ReadReq_miss_latency::cpu.inst 327136040500 # number of ReadReq miss cycles 778system.cpu.icache.ReadReq_miss_latency::total 327136040500 # number of ReadReq miss cycles 779system.cpu.icache.demand_miss_latency::cpu.inst 327136040500 # number of demand (read+write) miss cycles 780system.cpu.icache.demand_miss_latency::total 327136040500 # number of demand (read+write) miss cycles 781system.cpu.icache.overall_miss_latency::cpu.inst 327136040500 # number of overall miss cycles 782system.cpu.icache.overall_miss_latency::total 327136040500 # number of overall miss cycles 783system.cpu.icache.ReadReq_accesses::cpu.inst 452593318 # number of ReadReq accesses(hits+misses) 784system.cpu.icache.ReadReq_accesses::total 452593318 # number of ReadReq accesses(hits+misses) 785system.cpu.icache.demand_accesses::cpu.inst 452593318 # number of demand (read+write) accesses 786system.cpu.icache.demand_accesses::total 452593318 # number of demand (read+write) accesses 787system.cpu.icache.overall_accesses::cpu.inst 452593318 # number of overall (read+write) accesses 788system.cpu.icache.overall_accesses::total 452593318 # number of overall (read+write) accesses 789system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.054301 # miss rate for ReadReq accesses 790system.cpu.icache.ReadReq_miss_rate::total 0.054301 # miss rate for ReadReq accesses 791system.cpu.icache.demand_miss_rate::cpu.inst 0.054301 # miss rate for demand accesses 792system.cpu.icache.demand_miss_rate::total 0.054301 # miss rate for demand accesses 793system.cpu.icache.overall_miss_rate::cpu.inst 0.054301 # miss rate for overall accesses 794system.cpu.icache.overall_miss_rate::total 0.054301 # miss rate for overall accesses 795system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13311.175733 # average ReadReq miss latency 796system.cpu.icache.ReadReq_avg_miss_latency::total 13311.175733 # average ReadReq miss latency 797system.cpu.icache.demand_avg_miss_latency::cpu.inst 13311.175733 # average overall miss latency 798system.cpu.icache.demand_avg_miss_latency::total 13311.175733 # average overall miss latency 799system.cpu.icache.overall_avg_miss_latency::cpu.inst 13311.175733 # average overall miss latency 800system.cpu.icache.overall_avg_miss_latency::total 13311.175733 # average overall miss latency 801system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 802system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 803system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 804system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 805system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 806system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 807system.cpu.icache.fast_writes 0 # number of fast writes performed 808system.cpu.icache.cache_copies 0 # number of cache copies performed 809system.cpu.icache.ReadReq_mshr_misses::cpu.inst 24576044 # number of ReadReq MSHR misses 810system.cpu.icache.ReadReq_mshr_misses::total 24576044 # number of ReadReq MSHR misses 811system.cpu.icache.demand_mshr_misses::cpu.inst 24576044 # number of demand (read+write) MSHR misses 812system.cpu.icache.demand_mshr_misses::total 24576044 # number of demand (read+write) MSHR misses 813system.cpu.icache.overall_mshr_misses::cpu.inst 24576044 # number of overall MSHR misses 814system.cpu.icache.overall_mshr_misses::total 24576044 # number of overall MSHR misses 815system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 52295 # number of ReadReq MSHR uncacheable 816system.cpu.icache.ReadReq_mshr_uncacheable::total 52295 # number of ReadReq MSHR uncacheable 817system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 52295 # number of overall MSHR uncacheable misses 818system.cpu.icache.overall_mshr_uncacheable_misses::total 52295 # number of overall MSHR uncacheable misses 819system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 302559997500 # number of ReadReq MSHR miss cycles 820system.cpu.icache.ReadReq_mshr_miss_latency::total 302559997500 # number of ReadReq MSHR miss cycles 821system.cpu.icache.demand_mshr_miss_latency::cpu.inst 302559997500 # number of demand (read+write) MSHR miss cycles 822system.cpu.icache.demand_mshr_miss_latency::total 302559997500 # number of demand (read+write) MSHR miss cycles 823system.cpu.icache.overall_mshr_miss_latency::cpu.inst 302559997500 # number of overall MSHR miss cycles 824system.cpu.icache.overall_mshr_miss_latency::total 302559997500 # number of overall MSHR miss cycles 825system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 4042938500 # number of ReadReq MSHR uncacheable cycles 826system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 4042938500 # number of ReadReq MSHR uncacheable cycles 827system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 4042938500 # number of overall MSHR uncacheable cycles 828system.cpu.icache.overall_mshr_uncacheable_latency::total 4042938500 # number of overall MSHR uncacheable cycles 829system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.054301 # mshr miss rate for ReadReq accesses 830system.cpu.icache.ReadReq_mshr_miss_rate::total 0.054301 # mshr miss rate for ReadReq accesses 831system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.054301 # mshr miss rate for demand accesses 832system.cpu.icache.demand_mshr_miss_rate::total 0.054301 # mshr miss rate for demand accesses 833system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.054301 # mshr miss rate for overall accesses 834system.cpu.icache.overall_mshr_miss_rate::total 0.054301 # mshr miss rate for overall accesses 835system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12311.175773 # average ReadReq mshr miss latency 836system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12311.175773 # average ReadReq mshr miss latency 837system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12311.175773 # average overall mshr miss latency 838system.cpu.icache.demand_avg_mshr_miss_latency::total 12311.175773 # average overall mshr miss latency 839system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12311.175773 # average overall mshr miss latency 840system.cpu.icache.overall_avg_mshr_miss_latency::total 12311.175773 # average overall mshr miss latency 841system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 77310.230424 # average ReadReq mshr uncacheable latency 842system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 77310.230424 # average ReadReq mshr uncacheable latency 843system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 77310.230424 # average overall mshr uncacheable latency 844system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 77310.230424 # average overall mshr uncacheable latency 845system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 846system.cpu.l2cache.tags.replacements 1607082 # number of replacements 847system.cpu.l2cache.tags.tagsinuse 65318.726670 # Cycle average of tags in use 848system.cpu.l2cache.tags.total_refs 67354503 # Total number of references to valid blocks. 849system.cpu.l2cache.tags.sampled_refs 1670310 # Sample count of references to valid blocks. 850system.cpu.l2cache.tags.avg_refs 40.324552 # Average number of references to valid blocks. 851system.cpu.l2cache.tags.warmup_cycle 24502286000 # Cycle when the warmup percentage was hit. 852system.cpu.l2cache.tags.occ_blocks::writebacks 36002.307210 # Average occupied blocks per requestor 853system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 335.180696 # Average occupied blocks per requestor 854system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 433.791675 # Average occupied blocks per requestor 855system.cpu.l2cache.tags.occ_blocks::cpu.inst 8203.980766 # Average occupied blocks per requestor 856system.cpu.l2cache.tags.occ_blocks::cpu.data 20343.466323 # Average occupied blocks per requestor 857system.cpu.l2cache.tags.occ_percent::writebacks 0.549352 # Average percentage of cache occupancy 858system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.005114 # Average percentage of cache occupancy 859system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.006619 # Average percentage of cache occupancy 860system.cpu.l2cache.tags.occ_percent::cpu.inst 0.125183 # Average percentage of cache occupancy 861system.cpu.l2cache.tags.occ_percent::cpu.data 0.310417 # Average percentage of cache occupancy 862system.cpu.l2cache.tags.occ_percent::total 0.996685 # Average percentage of cache occupancy 863system.cpu.l2cache.tags.occ_task_id_blocks::1023 219 # Occupied blocks per task id 864system.cpu.l2cache.tags.occ_task_id_blocks::1024 63009 # Occupied blocks per task id 865system.cpu.l2cache.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id 866system.cpu.l2cache.tags.age_task_id_blocks_1023::4 218 # Occupied blocks per task id 867system.cpu.l2cache.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id 868system.cpu.l2cache.tags.age_task_id_blocks_1024::1 524 # Occupied blocks per task id 869system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2413 # Occupied blocks per task id 870system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5473 # Occupied blocks per task id 871system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54554 # Occupied blocks per task id 872system.cpu.l2cache.tags.occ_task_id_percent::1023 0.003342 # Percentage of cache occupancy per task id 873system.cpu.l2cache.tags.occ_task_id_percent::1024 0.961441 # Percentage of cache occupancy per task id 874system.cpu.l2cache.tags.tag_accesses 587356710 # Number of tag accesses 875system.cpu.l2cache.tags.data_accesses 587356710 # Number of data accesses 876system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 972528 # number of ReadReq hits 877system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 286301 # number of ReadReq hits 878system.cpu.l2cache.ReadReq_hits::total 1258829 # number of ReadReq hits 879system.cpu.l2cache.Writeback_hits::writebacks 8554549 # number of Writeback hits 880system.cpu.l2cache.Writeback_hits::total 8554549 # number of Writeback hits 881system.cpu.l2cache.UpgradeReq_hits::cpu.data 10855 # number of UpgradeReq hits 882system.cpu.l2cache.UpgradeReq_hits::total 10855 # number of UpgradeReq hits 883system.cpu.l2cache.ReadExReq_hits::cpu.data 1654669 # number of ReadExReq hits 884system.cpu.l2cache.ReadExReq_hits::total 1654669 # number of ReadExReq hits 885system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 24470106 # number of ReadCleanReq hits 886system.cpu.l2cache.ReadCleanReq_hits::total 24470106 # number of ReadCleanReq hits 887system.cpu.l2cache.ReadSharedReq_hits::cpu.data 7204785 # number of ReadSharedReq hits 888system.cpu.l2cache.ReadSharedReq_hits::total 7204785 # number of ReadSharedReq hits 889system.cpu.l2cache.InvalidateReq_hits::cpu.data 700263 # number of InvalidateReq hits 890system.cpu.l2cache.InvalidateReq_hits::total 700263 # number of InvalidateReq hits 891system.cpu.l2cache.demand_hits::cpu.dtb.walker 972528 # number of demand (read+write) hits 892system.cpu.l2cache.demand_hits::cpu.itb.walker 286301 # number of demand (read+write) hits 893system.cpu.l2cache.demand_hits::cpu.inst 24470106 # number of demand (read+write) hits 894system.cpu.l2cache.demand_hits::cpu.data 8859454 # number of demand (read+write) hits 895system.cpu.l2cache.demand_hits::total 34588389 # number of demand (read+write) hits 896system.cpu.l2cache.overall_hits::cpu.dtb.walker 972528 # number of overall hits 897system.cpu.l2cache.overall_hits::cpu.itb.walker 286301 # number of overall hits 898system.cpu.l2cache.overall_hits::cpu.inst 24470106 # number of overall hits 899system.cpu.l2cache.overall_hits::cpu.data 8859454 # number of overall hits 900system.cpu.l2cache.overall_hits::total 34588389 # number of overall hits 901system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 6370 # number of ReadReq misses 902system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5416 # number of ReadReq misses 903system.cpu.l2cache.ReadReq_misses::total 11786 # number of ReadReq misses 904system.cpu.l2cache.UpgradeReq_misses::cpu.data 38716 # number of UpgradeReq misses 905system.cpu.l2cache.UpgradeReq_misses::total 38716 # number of UpgradeReq misses 906system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses 907system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses 908system.cpu.l2cache.ReadExReq_misses::cpu.data 709953 # number of ReadExReq misses 909system.cpu.l2cache.ReadExReq_misses::total 709953 # number of ReadExReq misses 910system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 105935 # number of ReadCleanReq misses 911system.cpu.l2cache.ReadCleanReq_misses::total 105935 # number of ReadCleanReq misses 912system.cpu.l2cache.ReadSharedReq_misses::cpu.data 328366 # number of ReadSharedReq misses 913system.cpu.l2cache.ReadSharedReq_misses::total 328366 # number of ReadSharedReq misses 914system.cpu.l2cache.InvalidateReq_misses::cpu.data 544692 # number of InvalidateReq misses 915system.cpu.l2cache.InvalidateReq_misses::total 544692 # number of InvalidateReq misses 916system.cpu.l2cache.demand_misses::cpu.dtb.walker 6370 # number of demand (read+write) misses 917system.cpu.l2cache.demand_misses::cpu.itb.walker 5416 # number of demand (read+write) misses 918system.cpu.l2cache.demand_misses::cpu.inst 105935 # number of demand (read+write) misses 919system.cpu.l2cache.demand_misses::cpu.data 1038319 # number of demand (read+write) misses 920system.cpu.l2cache.demand_misses::total 1156040 # number of demand (read+write) misses 921system.cpu.l2cache.overall_misses::cpu.dtb.walker 6370 # number of overall misses 922system.cpu.l2cache.overall_misses::cpu.itb.walker 5416 # number of overall misses 923system.cpu.l2cache.overall_misses::cpu.inst 105935 # number of overall misses 924system.cpu.l2cache.overall_misses::cpu.data 1038319 # number of overall misses 925system.cpu.l2cache.overall_misses::total 1156040 # number of overall misses 926system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 553122500 # number of ReadReq miss cycles 927system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 470413000 # number of ReadReq miss cycles 928system.cpu.l2cache.ReadReq_miss_latency::total 1023535500 # number of ReadReq miss cycles 929system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 578007500 # number of UpgradeReq miss cycles 930system.cpu.l2cache.UpgradeReq_miss_latency::total 578007500 # number of UpgradeReq miss cycles 931system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 110500 # number of SCUpgradeReq miss cycles 932system.cpu.l2cache.SCUpgradeReq_miss_latency::total 110500 # number of SCUpgradeReq miss cycles 933system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 58013412000 # number of ReadExReq miss cycles 934system.cpu.l2cache.ReadExReq_miss_latency::total 58013412000 # number of ReadExReq miss cycles 935system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 8652629500 # number of ReadCleanReq miss cycles 936system.cpu.l2cache.ReadCleanReq_miss_latency::total 8652629500 # number of ReadCleanReq miss cycles 937system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 27752985500 # number of ReadSharedReq miss cycles 938system.cpu.l2cache.ReadSharedReq_miss_latency::total 27752985500 # number of ReadSharedReq miss cycles 939system.cpu.l2cache.InvalidateReq_miss_latency::cpu.data 47906162000 # number of InvalidateReq miss cycles 940system.cpu.l2cache.InvalidateReq_miss_latency::total 47906162000 # number of InvalidateReq miss cycles 941system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 553122500 # number of demand (read+write) miss cycles 942system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 470413000 # number of demand (read+write) miss cycles 943system.cpu.l2cache.demand_miss_latency::cpu.inst 8652629500 # number of demand (read+write) miss cycles 944system.cpu.l2cache.demand_miss_latency::cpu.data 85766397500 # number of demand (read+write) miss cycles 945system.cpu.l2cache.demand_miss_latency::total 95442562500 # number of demand (read+write) miss cycles 946system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 553122500 # number of overall miss cycles 947system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 470413000 # number of overall miss cycles 948system.cpu.l2cache.overall_miss_latency::cpu.inst 8652629500 # number of overall miss cycles 949system.cpu.l2cache.overall_miss_latency::cpu.data 85766397500 # number of overall miss cycles 950system.cpu.l2cache.overall_miss_latency::total 95442562500 # number of overall miss cycles 951system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 978898 # number of ReadReq accesses(hits+misses) 952system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 291717 # number of ReadReq accesses(hits+misses) 953system.cpu.l2cache.ReadReq_accesses::total 1270615 # number of ReadReq accesses(hits+misses) 954system.cpu.l2cache.Writeback_accesses::writebacks 8554549 # number of Writeback accesses(hits+misses) 955system.cpu.l2cache.Writeback_accesses::total 8554549 # number of Writeback accesses(hits+misses) 956system.cpu.l2cache.UpgradeReq_accesses::cpu.data 49571 # number of UpgradeReq accesses(hits+misses) 957system.cpu.l2cache.UpgradeReq_accesses::total 49571 # number of UpgradeReq accesses(hits+misses) 958system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses) 959system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) 960system.cpu.l2cache.ReadExReq_accesses::cpu.data 2364622 # number of ReadExReq accesses(hits+misses) 961system.cpu.l2cache.ReadExReq_accesses::total 2364622 # number of ReadExReq accesses(hits+misses) 962system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 24576041 # number of ReadCleanReq accesses(hits+misses) 963system.cpu.l2cache.ReadCleanReq_accesses::total 24576041 # number of ReadCleanReq accesses(hits+misses) 964system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 7533151 # number of ReadSharedReq accesses(hits+misses) 965system.cpu.l2cache.ReadSharedReq_accesses::total 7533151 # number of ReadSharedReq accesses(hits+misses) 966system.cpu.l2cache.InvalidateReq_accesses::cpu.data 1244955 # number of InvalidateReq accesses(hits+misses) 967system.cpu.l2cache.InvalidateReq_accesses::total 1244955 # number of InvalidateReq accesses(hits+misses) 968system.cpu.l2cache.demand_accesses::cpu.dtb.walker 978898 # number of demand (read+write) accesses 969system.cpu.l2cache.demand_accesses::cpu.itb.walker 291717 # number of demand (read+write) accesses 970system.cpu.l2cache.demand_accesses::cpu.inst 24576041 # number of demand (read+write) accesses 971system.cpu.l2cache.demand_accesses::cpu.data 9897773 # number of demand (read+write) accesses 972system.cpu.l2cache.demand_accesses::total 35744429 # number of demand (read+write) accesses 973system.cpu.l2cache.overall_accesses::cpu.dtb.walker 978898 # number of overall (read+write) accesses 974system.cpu.l2cache.overall_accesses::cpu.itb.walker 291717 # number of overall (read+write) accesses 975system.cpu.l2cache.overall_accesses::cpu.inst 24576041 # number of overall (read+write) accesses 976system.cpu.l2cache.overall_accesses::cpu.data 9897773 # number of overall (read+write) accesses 977system.cpu.l2cache.overall_accesses::total 35744429 # number of overall (read+write) accesses 978system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.006507 # miss rate for ReadReq accesses 979system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.018566 # miss rate for ReadReq accesses 980system.cpu.l2cache.ReadReq_miss_rate::total 0.009276 # miss rate for ReadReq accesses 981system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.781021 # miss rate for UpgradeReq accesses 982system.cpu.l2cache.UpgradeReq_miss_rate::total 0.781021 # miss rate for UpgradeReq accesses 983system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses 984system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 985system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.300240 # miss rate for ReadExReq accesses 986system.cpu.l2cache.ReadExReq_miss_rate::total 0.300240 # miss rate for ReadExReq accesses 987system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.004310 # miss rate for ReadCleanReq accesses 988system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.004310 # miss rate for ReadCleanReq accesses 989system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.043589 # miss rate for ReadSharedReq accesses 990system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.043589 # miss rate for ReadSharedReq accesses 991system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data 0.437519 # miss rate for InvalidateReq accesses 992system.cpu.l2cache.InvalidateReq_miss_rate::total 0.437519 # miss rate for InvalidateReq accesses 993system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.006507 # miss rate for demand accesses 994system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.018566 # miss rate for demand accesses 995system.cpu.l2cache.demand_miss_rate::cpu.inst 0.004310 # miss rate for demand accesses 996system.cpu.l2cache.demand_miss_rate::cpu.data 0.104904 # miss rate for demand accesses 997system.cpu.l2cache.demand_miss_rate::total 0.032342 # miss rate for demand accesses 998system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.006507 # miss rate for overall accesses 999system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.018566 # miss rate for overall accesses 1000system.cpu.l2cache.overall_miss_rate::cpu.inst 0.004310 # miss rate for overall accesses 1001system.cpu.l2cache.overall_miss_rate::cpu.data 0.104904 # miss rate for overall accesses 1002system.cpu.l2cache.overall_miss_rate::total 0.032342 # miss rate for overall accesses 1003system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 86832.417582 # average ReadReq miss latency 1004system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 86856.166913 # average ReadReq miss latency 1005system.cpu.l2cache.ReadReq_avg_miss_latency::total 86843.331071 # average ReadReq miss latency 1006system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 14929.421944 # average UpgradeReq miss latency 1007system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 14929.421944 # average UpgradeReq miss latency 1008system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 55250 # average SCUpgradeReq miss latency 1009system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 55250 # average SCUpgradeReq miss latency 1010system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81714.440252 # average ReadExReq miss latency 1011system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81714.440252 # average ReadExReq miss latency 1012system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 81678.666163 # average ReadCleanReq miss latency 1013system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 81678.666163 # average ReadCleanReq miss latency 1014system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 84518.450449 # average ReadSharedReq miss latency 1015system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 84518.450449 # average ReadSharedReq miss latency 1016system.cpu.l2cache.InvalidateReq_avg_miss_latency::cpu.data 87950.919052 # average InvalidateReq miss latency 1017system.cpu.l2cache.InvalidateReq_avg_miss_latency::total 87950.919052 # average InvalidateReq miss latency 1018system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 86832.417582 # average overall miss latency 1019system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 86856.166913 # average overall miss latency 1020system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81678.666163 # average overall miss latency 1021system.cpu.l2cache.demand_avg_miss_latency::cpu.data 82601.202039 # average overall miss latency 1022system.cpu.l2cache.demand_avg_miss_latency::total 82559.913584 # average overall miss latency 1023system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 86832.417582 # average overall miss latency 1024system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 86856.166913 # average overall miss latency 1025system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81678.666163 # average overall miss latency 1026system.cpu.l2cache.overall_avg_miss_latency::cpu.data 82601.202039 # average overall miss latency 1027system.cpu.l2cache.overall_avg_miss_latency::total 82559.913584 # average overall miss latency 1028system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1029system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1030system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1031system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1032system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1033system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1034system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1035system.cpu.l2cache.cache_copies 0 # number of cache copies performed 1036system.cpu.l2cache.writebacks::writebacks 1373638 # number of writebacks 1037system.cpu.l2cache.writebacks::total 1373638 # number of writebacks 1038system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 3 # number of ReadCleanReq MSHR hits 1039system.cpu.l2cache.ReadCleanReq_mshr_hits::total 3 # number of ReadCleanReq MSHR hits 1040system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 21 # number of ReadSharedReq MSHR hits 1041system.cpu.l2cache.ReadSharedReq_mshr_hits::total 21 # number of ReadSharedReq MSHR hits 1042system.cpu.l2cache.demand_mshr_hits::cpu.inst 3 # number of demand (read+write) MSHR hits 1043system.cpu.l2cache.demand_mshr_hits::cpu.data 21 # number of demand (read+write) MSHR hits 1044system.cpu.l2cache.demand_mshr_hits::total 24 # number of demand (read+write) MSHR hits 1045system.cpu.l2cache.overall_mshr_hits::cpu.inst 3 # number of overall MSHR hits 1046system.cpu.l2cache.overall_mshr_hits::cpu.data 21 # number of overall MSHR hits 1047system.cpu.l2cache.overall_mshr_hits::total 24 # number of overall MSHR hits 1048system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 6370 # number of ReadReq MSHR misses 1049system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 5416 # number of ReadReq MSHR misses 1050system.cpu.l2cache.ReadReq_mshr_misses::total 11786 # number of ReadReq MSHR misses 1051system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 1102 # number of CleanEvict MSHR misses 1052system.cpu.l2cache.CleanEvict_mshr_misses::total 1102 # number of CleanEvict MSHR misses 1053system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 38716 # number of UpgradeReq MSHR misses 1054system.cpu.l2cache.UpgradeReq_mshr_misses::total 38716 # number of UpgradeReq MSHR misses 1055system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses 1056system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses 1057system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 709953 # number of ReadExReq MSHR misses 1058system.cpu.l2cache.ReadExReq_mshr_misses::total 709953 # number of ReadExReq MSHR misses 1059system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 105932 # number of ReadCleanReq MSHR misses 1060system.cpu.l2cache.ReadCleanReq_mshr_misses::total 105932 # number of ReadCleanReq MSHR misses 1061system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 328345 # number of ReadSharedReq MSHR misses 1062system.cpu.l2cache.ReadSharedReq_mshr_misses::total 328345 # number of ReadSharedReq MSHR misses 1063system.cpu.l2cache.InvalidateReq_mshr_misses::cpu.data 544692 # number of InvalidateReq MSHR misses 1064system.cpu.l2cache.InvalidateReq_mshr_misses::total 544692 # number of InvalidateReq MSHR misses 1065system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 6370 # number of demand (read+write) MSHR misses 1066system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 5416 # number of demand (read+write) MSHR misses 1067system.cpu.l2cache.demand_mshr_misses::cpu.inst 105932 # number of demand (read+write) MSHR misses 1068system.cpu.l2cache.demand_mshr_misses::cpu.data 1038298 # number of demand (read+write) MSHR misses 1069system.cpu.l2cache.demand_mshr_misses::total 1156016 # number of demand (read+write) MSHR misses 1070system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 6370 # number of overall MSHR misses 1071system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 5416 # number of overall MSHR misses 1072system.cpu.l2cache.overall_mshr_misses::cpu.inst 105932 # number of overall MSHR misses 1073system.cpu.l2cache.overall_mshr_misses::cpu.data 1038298 # number of overall MSHR misses 1074system.cpu.l2cache.overall_mshr_misses::total 1156016 # number of overall MSHR misses 1075system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 52295 # number of ReadReq MSHR uncacheable 1076system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 33699 # number of ReadReq MSHR uncacheable 1077system.cpu.l2cache.ReadReq_mshr_uncacheable::total 85994 # number of ReadReq MSHR uncacheable 1078system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 33707 # number of WriteReq MSHR uncacheable 1079system.cpu.l2cache.WriteReq_mshr_uncacheable::total 33707 # number of WriteReq MSHR uncacheable 1080system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 52295 # number of overall MSHR uncacheable misses 1081system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 67406 # number of overall MSHR uncacheable misses 1082system.cpu.l2cache.overall_mshr_uncacheable_misses::total 119701 # number of overall MSHR uncacheable misses 1083system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 489422500 # number of ReadReq MSHR miss cycles 1084system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 416253000 # number of ReadReq MSHR miss cycles 1085system.cpu.l2cache.ReadReq_mshr_miss_latency::total 905675500 # number of ReadReq MSHR miss cycles 1086system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 803927500 # number of UpgradeReq MSHR miss cycles 1087system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 803927500 # number of UpgradeReq MSHR miss cycles 1088system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 90500 # number of SCUpgradeReq MSHR miss cycles 1089system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 90500 # number of SCUpgradeReq MSHR miss cycles 1090system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 50913882000 # number of ReadExReq MSHR miss cycles 1091system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 50913882000 # number of ReadExReq MSHR miss cycles 1092system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 7593134000 # number of ReadCleanReq MSHR miss cycles 1093system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 7593134000 # number of ReadCleanReq MSHR miss cycles 1094system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 24468048000 # number of ReadSharedReq MSHR miss cycles 1095system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 24468048000 # number of ReadSharedReq MSHR miss cycles 1096system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data 42459242000 # number of InvalidateReq MSHR miss cycles 1097system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total 42459242000 # number of InvalidateReq MSHR miss cycles 1098system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 489422500 # number of demand (read+write) MSHR miss cycles 1099system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 416253000 # number of demand (read+write) MSHR miss cycles 1100system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 7593134000 # number of demand (read+write) MSHR miss cycles 1101system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 75381930000 # number of demand (read+write) MSHR miss cycles 1102system.cpu.l2cache.demand_mshr_miss_latency::total 83880739500 # number of demand (read+write) MSHR miss cycles 1103system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 489422500 # number of overall MSHR miss cycles 1104system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 416253000 # number of overall MSHR miss cycles 1105system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 7593134000 # number of overall MSHR miss cycles 1106system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 75381930000 # number of overall MSHR miss cycles 1107system.cpu.l2cache.overall_mshr_miss_latency::total 83880739500 # number of overall MSHR miss cycles 1108system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 3232365500 # number of ReadReq MSHR uncacheable cycles 1109system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5409250000 # number of ReadReq MSHR uncacheable cycles 1110system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 8641615500 # number of ReadReq MSHR uncacheable cycles 1111system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 5303815500 # number of WriteReq MSHR uncacheable cycles 1112system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 5303815500 # number of WriteReq MSHR uncacheable cycles 1113system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 3232365500 # number of overall MSHR uncacheable cycles 1114system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 10713065500 # number of overall MSHR uncacheable cycles 1115system.cpu.l2cache.overall_mshr_uncacheable_latency::total 13945431000 # number of overall MSHR uncacheable cycles 1116system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.006507 # mshr miss rate for ReadReq accesses 1117system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.018566 # mshr miss rate for ReadReq accesses 1118system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.009276 # mshr miss rate for ReadReq accesses 1119system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 1120system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 1121system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.781021 # mshr miss rate for UpgradeReq accesses 1122system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.781021 # mshr miss rate for UpgradeReq accesses 1123system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses 1124system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 1125system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.300240 # mshr miss rate for ReadExReq accesses 1126system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.300240 # mshr miss rate for ReadExReq accesses 1127system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.004310 # mshr miss rate for ReadCleanReq accesses 1128system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.004310 # mshr miss rate for ReadCleanReq accesses 1129system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.043587 # mshr miss rate for ReadSharedReq accesses 1130system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.043587 # mshr miss rate for ReadSharedReq accesses 1131system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.437519 # mshr miss rate for InvalidateReq accesses 1132system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.437519 # mshr miss rate for InvalidateReq accesses 1133system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.006507 # mshr miss rate for demand accesses 1134system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.018566 # mshr miss rate for demand accesses 1135system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.004310 # mshr miss rate for demand accesses 1136system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.104902 # mshr miss rate for demand accesses 1137system.cpu.l2cache.demand_mshr_miss_rate::total 0.032341 # mshr miss rate for demand accesses 1138system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.006507 # mshr miss rate for overall accesses 1139system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.018566 # mshr miss rate for overall accesses 1140system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.004310 # mshr miss rate for overall accesses 1141system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.104902 # mshr miss rate for overall accesses 1142system.cpu.l2cache.overall_mshr_miss_rate::total 0.032341 # mshr miss rate for overall accesses 1143system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 76832.417582 # average ReadReq mshr miss latency 1144system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 76856.166913 # average ReadReq mshr miss latency 1145system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 76843.331071 # average ReadReq mshr miss latency 1146system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 20764.735510 # average UpgradeReq mshr miss latency 1147system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20764.735510 # average UpgradeReq mshr miss latency 1148system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 45250 # average SCUpgradeReq mshr miss latency 1149system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 45250 # average SCUpgradeReq mshr miss latency 1150system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71714.440252 # average ReadExReq mshr miss latency 1151system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71714.440252 # average ReadExReq mshr miss latency 1152system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 71679.322584 # average ReadCleanReq mshr miss latency 1153system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 71679.322584 # average ReadCleanReq mshr miss latency 1154system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 74519.325709 # average ReadSharedReq mshr miss latency 1155system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 74519.325709 # average ReadSharedReq mshr miss latency 1156system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 77950.919052 # average InvalidateReq mshr miss latency 1157system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 77950.919052 # average InvalidateReq mshr miss latency 1158system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 76832.417582 # average overall mshr miss latency 1159system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 76856.166913 # average overall mshr miss latency 1160system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71679.322584 # average overall mshr miss latency 1161system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72601.440049 # average overall mshr miss latency 1162system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72560.189046 # average overall mshr miss latency 1163system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 76832.417582 # average overall mshr miss latency 1164system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 76856.166913 # average overall mshr miss latency 1165system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71679.322584 # average overall mshr miss latency 1166system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72601.440049 # average overall mshr miss latency 1167system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72560.189046 # average overall mshr miss latency 1168system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 61810.220862 # average ReadReq mshr uncacheable latency 1169system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 160516.632541 # average ReadReq mshr uncacheable latency 1170system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 100490.912157 # average ReadReq mshr uncacheable latency 1171system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 157350.565165 # average WriteReq mshr uncacheable latency 1172system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 157350.565165 # average WriteReq mshr uncacheable latency 1173system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 61810.220862 # average overall mshr uncacheable latency 1174system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 158933.410972 # average overall mshr uncacheable latency 1175system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 116502.209672 # average overall mshr uncacheable latency 1176system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1177system.cpu.toL2Bus.trans_dist::ReadReq 1789463 # Transaction distribution 1178system.cpu.toL2Bus.trans_dist::ReadResp 33899423 # Transaction distribution 1179system.cpu.toL2Bus.trans_dist::WriteReq 33707 # Transaction distribution 1180system.cpu.toL2Bus.trans_dist::WriteResp 33707 # Transaction distribution 1181system.cpu.toL2Bus.trans_dist::Writeback 10034845 # Transaction distribution 1182system.cpu.toL2Bus.trans_dist::CleanEvict 27401014 # Transaction distribution 1183system.cpu.toL2Bus.trans_dist::UpgradeReq 49574 # Transaction distribution 1184system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution 1185system.cpu.toL2Bus.trans_dist::UpgradeResp 49576 # Transaction distribution 1186system.cpu.toL2Bus.trans_dist::ReadExReq 2364622 # Transaction distribution 1187system.cpu.toL2Bus.trans_dist::ReadExResp 2364622 # Transaction distribution 1188system.cpu.toL2Bus.trans_dist::ReadCleanReq 24576044 # Transaction distribution 1189system.cpu.toL2Bus.trans_dist::ReadSharedReq 7542009 # Transaction distribution 1190system.cpu.toL2Bus.trans_dist::InvalidateReq 1351619 # Transaction distribution 1191system.cpu.toL2Bus.trans_dist::InvalidateResp 1244955 # Transaction distribution 1192system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 73828388 # Packet count per connected master and slave (bytes) 1193system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 33661752 # Packet count per connected master and slave (bytes) 1194system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 699908 # Packet count per connected master and slave (bytes) 1195system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2274176 # Packet count per connected master and slave (bytes) 1196system.cpu.toL2Bus.pkt_count::total 110464224 # Packet count per connected master and slave (bytes) 1197system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1576213440 # Cumulative packet size per connected master and slave (bytes) 1198system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1181188062 # Cumulative packet size per connected master and slave (bytes) 1199system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2333736 # Cumulative packet size per connected master and slave (bytes) 1200system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 7831184 # Cumulative packet size per connected master and slave (bytes) 1201system.cpu.toL2Bus.pkt_size::total 2767566422 # Cumulative packet size per connected master and slave (bytes) 1202system.cpu.toL2Bus.snoops 2271727 # Total snoops (count) 1203system.cpu.toL2Bus.snoop_fanout::samples 75147333 # Request fanout histogram 1204system.cpu.toL2Bus.snoop_fanout::mean 1.047128 # Request fanout histogram 1205system.cpu.toL2Bus.snoop_fanout::stdev 0.211913 # Request fanout histogram 1206system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1207system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1208system.cpu.toL2Bus.snoop_fanout::1 71605763 95.29% 95.29% # Request fanout histogram 1209system.cpu.toL2Bus.snoop_fanout::2 3541570 4.71% 100.00% # Request fanout histogram 1210system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1211system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 1212system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 1213system.cpu.toL2Bus.snoop_fanout::total 75147333 # Request fanout histogram 1214system.cpu.toL2Bus.reqLayer0.occupancy 45226020496 # Layer occupancy (ticks) 1215system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 1216system.cpu.toL2Bus.snoopLayer0.occupancy 1150500 # Layer occupancy (ticks) 1217system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1218system.cpu.toL2Bus.respLayer0.occupancy 36946016966 # Layer occupancy (ticks) 1219system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 1220system.cpu.toL2Bus.respLayer1.occupancy 15544978992 # Layer occupancy (ticks) 1221system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 1222system.cpu.toL2Bus.respLayer2.occupancy 408213455 # Layer occupancy (ticks) 1223system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1224system.cpu.toL2Bus.respLayer3.occupancy 1295285984 # Layer occupancy (ticks) 1225system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1226system.iobus.trans_dist::ReadReq 40306 # Transaction distribution 1227system.iobus.trans_dist::ReadResp 40306 # Transaction distribution 1228system.iobus.trans_dist::WriteReq 136571 # Transaction distribution 1229system.iobus.trans_dist::WriteResp 136571 # Transaction distribution 1230system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes) 1231system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 1232system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) 1233system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) 1234system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 1235system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 1236system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 1237system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 1238system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) 1239system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 1240system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) 1241system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) 1242system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) 1243system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) 1244system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) 1245system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes) 1246system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230970 # Packet count per connected master and slave (bytes) 1247system.iobus.pkt_count_system.realview.ide.dma::total 230970 # Packet count per connected master and slave (bytes) 1248system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) 1249system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) 1250system.iobus.pkt_count::total 353754 # Packet count per connected master and slave (bytes) 1251system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes) 1252system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) 1253system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) 1254system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) 1255system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 1256system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1257system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1258system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1259system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) 1260system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1261system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) 1262system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes) 1263system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) 1264system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) 1265system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) 1266system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes) 1267system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334312 # Cumulative packet size per connected master and slave (bytes) 1268system.iobus.pkt_size_system.realview.ide.dma::total 7334312 # Cumulative packet size per connected master and slave (bytes) 1269system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 1270system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) 1271system.iobus.pkt_size::total 7492232 # Cumulative packet size per connected master and slave (bytes) 1272system.iobus.reqLayer0.occupancy 36301000 # Layer occupancy (ticks) 1273system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 1274system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) 1275system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 1276system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks) 1277system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 1278system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks) 1279system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 1280system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) 1281system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 1282system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) 1283system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 1284system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) 1285system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 1286system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) 1287system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 1288system.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks) 1289system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 1290system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) 1291system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 1292system.iobus.reqLayer23.occupancy 21947000 # Layer occupancy (ticks) 1293system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 1294system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks) 1295system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 1296system.iobus.reqLayer25.occupancy 32658000 # Layer occupancy (ticks) 1297system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 1298system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) 1299system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 1300system.iobus.reqLayer27.occupancy 568890575 # Layer occupancy (ticks) 1301system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 1302system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) 1303system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) 1304system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks) 1305system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 1306system.iobus.respLayer3.occupancy 147730000 # Layer occupancy (ticks) 1307system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 1308system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) 1309system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) 1310system.iocache.tags.replacements 115467 # number of replacements 1311system.iocache.tags.tagsinuse 10.447125 # Cycle average of tags in use 1312system.iocache.tags.total_refs 3 # Total number of references to valid blocks. 1313system.iocache.tags.sampled_refs 115483 # Sample count of references to valid blocks. 1314system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. 1315system.iocache.tags.warmup_cycle 13147039080000 # Cycle when the warmup percentage was hit. 1316system.iocache.tags.occ_blocks::realview.ethernet 3.519011 # Average occupied blocks per requestor 1317system.iocache.tags.occ_blocks::realview.ide 6.928115 # Average occupied blocks per requestor 1318system.iocache.tags.occ_percent::realview.ethernet 0.219938 # Average percentage of cache occupancy 1319system.iocache.tags.occ_percent::realview.ide 0.433007 # Average percentage of cache occupancy 1320system.iocache.tags.occ_percent::total 0.652945 # Average percentage of cache occupancy 1321system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1322system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 1323system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1324system.iocache.tags.tag_accesses 1039722 # Number of tag accesses 1325system.iocache.tags.data_accesses 1039722 # Number of data accesses 1326system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses 1327system.iocache.ReadReq_misses::realview.ide 8821 # number of ReadReq misses 1328system.iocache.ReadReq_misses::total 8858 # number of ReadReq misses 1329system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 1330system.iocache.WriteReq_misses::total 3 # number of WriteReq misses 1331system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses 1332system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses 1333system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses 1334system.iocache.demand_misses::realview.ide 8821 # number of demand (read+write) misses 1335system.iocache.demand_misses::total 8861 # number of demand (read+write) misses 1336system.iocache.overall_misses::realview.ethernet 40 # number of overall misses 1337system.iocache.overall_misses::realview.ide 8821 # number of overall misses 1338system.iocache.overall_misses::total 8861 # number of overall misses 1339system.iocache.ReadReq_miss_latency::realview.ethernet 5069000 # number of ReadReq miss cycles 1340system.iocache.ReadReq_miss_latency::realview.ide 1605437158 # number of ReadReq miss cycles 1341system.iocache.ReadReq_miss_latency::total 1610506158 # number of ReadReq miss cycles 1342system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles 1343system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles 1344system.iocache.WriteLineReq_miss_latency::realview.ide 12610481417 # number of WriteLineReq miss cycles 1345system.iocache.WriteLineReq_miss_latency::total 12610481417 # number of WriteLineReq miss cycles 1346system.iocache.demand_miss_latency::realview.ethernet 5420000 # number of demand (read+write) miss cycles 1347system.iocache.demand_miss_latency::realview.ide 1605437158 # number of demand (read+write) miss cycles 1348system.iocache.demand_miss_latency::total 1610857158 # number of demand (read+write) miss cycles 1349system.iocache.overall_miss_latency::realview.ethernet 5420000 # number of overall miss cycles 1350system.iocache.overall_miss_latency::realview.ide 1605437158 # number of overall miss cycles 1351system.iocache.overall_miss_latency::total 1610857158 # number of overall miss cycles 1352system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) 1353system.iocache.ReadReq_accesses::realview.ide 8821 # number of ReadReq accesses(hits+misses) 1354system.iocache.ReadReq_accesses::total 8858 # number of ReadReq accesses(hits+misses) 1355system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 1356system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 1357system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) 1358system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) 1359system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses 1360system.iocache.demand_accesses::realview.ide 8821 # number of demand (read+write) accesses 1361system.iocache.demand_accesses::total 8861 # number of demand (read+write) accesses 1362system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses 1363system.iocache.overall_accesses::realview.ide 8821 # number of overall (read+write) accesses 1364system.iocache.overall_accesses::total 8861 # number of overall (read+write) accesses 1365system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 1366system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 1367system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1368system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 1369system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 1370system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 1371system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 1372system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses 1373system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 1374system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1375system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses 1376system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 1377system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 1378system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137000 # average ReadReq miss latency 1379system.iocache.ReadReq_avg_miss_latency::realview.ide 182001.718399 # average ReadReq miss latency 1380system.iocache.ReadReq_avg_miss_latency::total 181813.745541 # average ReadReq miss latency 1381system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency 1382system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency 1383system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118226.218940 # average WriteLineReq miss latency 1384system.iocache.WriteLineReq_avg_miss_latency::total 118226.218940 # average WriteLineReq miss latency 1385system.iocache.demand_avg_miss_latency::realview.ethernet 135500 # average overall miss latency 1386system.iocache.demand_avg_miss_latency::realview.ide 182001.718399 # average overall miss latency 1387system.iocache.demand_avg_miss_latency::total 181791.802054 # average overall miss latency 1388system.iocache.overall_avg_miss_latency::realview.ethernet 135500 # average overall miss latency 1389system.iocache.overall_avg_miss_latency::realview.ide 182001.718399 # average overall miss latency 1390system.iocache.overall_avg_miss_latency::total 181791.802054 # average overall miss latency 1391system.iocache.blocked_cycles::no_mshrs 31114 # number of cycles access was blocked 1392system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1393system.iocache.blocked::no_mshrs 3332 # number of cycles access was blocked 1394system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1395system.iocache.avg_blocked_cycles::no_mshrs 9.337935 # average number of cycles each access was blocked 1396system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1397system.iocache.fast_writes 0 # number of fast writes performed 1398system.iocache.cache_copies 0 # number of cache copies performed 1399system.iocache.writebacks::writebacks 106631 # number of writebacks 1400system.iocache.writebacks::total 106631 # number of writebacks 1401system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses 1402system.iocache.ReadReq_mshr_misses::realview.ide 8821 # number of ReadReq MSHR misses 1403system.iocache.ReadReq_mshr_misses::total 8858 # number of ReadReq MSHR misses 1404system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses 1405system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses 1406system.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses 1407system.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses 1408system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses 1409system.iocache.demand_mshr_misses::realview.ide 8821 # number of demand (read+write) MSHR misses 1410system.iocache.demand_mshr_misses::total 8861 # number of demand (read+write) MSHR misses 1411system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses 1412system.iocache.overall_mshr_misses::realview.ide 8821 # number of overall MSHR misses 1413system.iocache.overall_mshr_misses::total 8861 # number of overall MSHR misses 1414system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3219000 # number of ReadReq MSHR miss cycles 1415system.iocache.ReadReq_mshr_miss_latency::realview.ide 1164387158 # number of ReadReq MSHR miss cycles 1416system.iocache.ReadReq_mshr_miss_latency::total 1167606158 # number of ReadReq MSHR miss cycles 1417system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles 1418system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles 1419system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7277281417 # number of WriteLineReq MSHR miss cycles 1420system.iocache.WriteLineReq_mshr_miss_latency::total 7277281417 # number of WriteLineReq MSHR miss cycles 1421system.iocache.demand_mshr_miss_latency::realview.ethernet 3420000 # number of demand (read+write) MSHR miss cycles 1422system.iocache.demand_mshr_miss_latency::realview.ide 1164387158 # number of demand (read+write) MSHR miss cycles 1423system.iocache.demand_mshr_miss_latency::total 1167807158 # number of demand (read+write) MSHR miss cycles 1424system.iocache.overall_mshr_miss_latency::realview.ethernet 3420000 # number of overall MSHR miss cycles 1425system.iocache.overall_mshr_miss_latency::realview.ide 1164387158 # number of overall MSHR miss cycles 1426system.iocache.overall_mshr_miss_latency::total 1167807158 # number of overall MSHR miss cycles 1427system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses 1428system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 1429system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1430system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses 1431system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 1432system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 1433system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 1434system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses 1435system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 1436system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1437system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses 1438system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 1439system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 1440system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87000 # average ReadReq mshr miss latency 1441system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 132001.718399 # average ReadReq mshr miss latency 1442system.iocache.ReadReq_avg_mshr_miss_latency::total 131813.745541 # average ReadReq mshr miss latency 1443system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency 1444system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency 1445system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68226.218940 # average WriteLineReq mshr miss latency 1446system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68226.218940 # average WriteLineReq mshr miss latency 1447system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85500 # average overall mshr miss latency 1448system.iocache.demand_avg_mshr_miss_latency::realview.ide 132001.718399 # average overall mshr miss latency 1449system.iocache.demand_avg_mshr_miss_latency::total 131791.802054 # average overall mshr miss latency 1450system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85500 # average overall mshr miss latency 1451system.iocache.overall_avg_mshr_miss_latency::realview.ide 132001.718399 # average overall mshr miss latency 1452system.iocache.overall_avg_mshr_miss_latency::total 131791.802054 # average overall mshr miss latency 1453system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1454system.membus.trans_dist::ReadReq 85994 # Transaction distribution 1455system.membus.trans_dist::ReadResp 540915 # Transaction distribution 1456system.membus.trans_dist::WriteReq 33707 # Transaction distribution 1457system.membus.trans_dist::WriteResp 33707 # Transaction distribution 1458system.membus.trans_dist::Writeback 1480269 # Transaction distribution 1459system.membus.trans_dist::CleanEvict 239619 # Transaction distribution 1460system.membus.trans_dist::UpgradeReq 39541 # Transaction distribution 1461system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution 1462system.membus.trans_dist::UpgradeResp 39543 # Transaction distribution 1463system.membus.trans_dist::ReadExReq 1253823 # Transaction distribution 1464system.membus.trans_dist::ReadExResp 1253823 # Transaction distribution 1465system.membus.trans_dist::ReadSharedReq 454921 # Transaction distribution 1466system.membus.trans_dist::InvalidateReq 106664 # Transaction distribution 1467system.membus.trans_dist::InvalidateResp 106664 # Transaction distribution 1468system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes) 1469system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 32 # Packet count per connected master and slave (bytes) 1470system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6922 # Packet count per connected master and slave (bytes) 1471system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5195008 # Packet count per connected master and slave (bytes) 1472system.membus.pkt_count_system.cpu.l2cache.mem_side::total 5324666 # Packet count per connected master and slave (bytes) 1473system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 341395 # Packet count per connected master and slave (bytes) 1474system.membus.pkt_count_system.iocache.mem_side::total 341395 # Packet count per connected master and slave (bytes) 1475system.membus.pkt_count::total 5666061 # Packet count per connected master and slave (bytes) 1476system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes) 1477system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 740 # Cumulative packet size per connected master and slave (bytes) 1478system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13844 # Cumulative packet size per connected master and slave (bytes) 1479system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 200030316 # Cumulative packet size per connected master and slave (bytes) 1480system.membus.pkt_size_system.cpu.l2cache.mem_side::total 200200734 # Cumulative packet size per connected master and slave (bytes) 1481system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7233472 # Cumulative packet size per connected master and slave (bytes) 1482system.membus.pkt_size_system.iocache.mem_side::total 7233472 # Cumulative packet size per connected master and slave (bytes) 1483system.membus.pkt_size::total 207434206 # Cumulative packet size per connected master and slave (bytes) 1484system.membus.snoops 3131 # Total snoops (count) 1485system.membus.snoop_fanout::samples 3697223 # Request fanout histogram 1486system.membus.snoop_fanout::mean 1 # Request fanout histogram 1487system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1488system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1489system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1490system.membus.snoop_fanout::1 3697223 100.00% 100.00% # Request fanout histogram 1491system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1492system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1493system.membus.snoop_fanout::min_value 1 # Request fanout histogram 1494system.membus.snoop_fanout::max_value 1 # Request fanout histogram 1495system.membus.snoop_fanout::total 3697223 # Request fanout histogram 1496system.membus.reqLayer0.occupancy 102366500 # Layer occupancy (ticks) 1497system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 1498system.membus.reqLayer1.occupancy 19828 # Layer occupancy (ticks) 1499system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 1500system.membus.reqLayer2.occupancy 5756000 # Layer occupancy (ticks) 1501system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 1502system.membus.reqLayer5.occupancy 9961724084 # Layer occupancy (ticks) 1503system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 1504system.membus.respLayer2.occupancy 9396279986 # Layer occupancy (ticks) 1505system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 1506system.membus.respLayer3.occupancy 228925719 # Layer occupancy (ticks) 1507system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 1508system.realview.ethernet.txBytes 966 # Bytes Transmitted 1509system.realview.ethernet.txPackets 3 # Number of Packets Transmitted 1510system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device 1511system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device 1512system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 1513system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1514system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1515system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 1516system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 1517system.realview.ethernet.totBandwidth 149 # Total Bandwidth (bits/s) 1518system.realview.ethernet.totPackets 3 # Total Packets 1519system.realview.ethernet.totBytes 966 # Total Bytes 1520system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) 1521system.realview.ethernet.txBandwidth 149 # Transmit Bandwidth (bits/s) 1522system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) 1523system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 1524system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post 1525system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 1526system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 1527system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post 1528system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 1529system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 1530system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post 1531system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 1532system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 1533system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post 1534system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 1535system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 1536system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post 1537system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 1538system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 1539system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post 1540system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 1541system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 1542system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 1543system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 1544system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 1545system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 1546system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 1547system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 1548system.realview.ethernet.postedInterrupts 13 # number of posts to CPU 1549system.realview.ethernet.droppedPackets 0 # number of packets dropped 1550system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks 1551system.realview.realview_io.osc_clcd.clock 42105 # Clock period in ticks 1552system.realview.realview_io.osc_cpu.clock 16667 # Clock period in ticks 1553system.realview.realview_io.osc_ddr.clock 25000 # Clock period in ticks 1554system.realview.realview_io.osc_hsbm.clock 25000 # Clock period in ticks 1555system.realview.realview_io.osc_mcc.clock 20000 # Clock period in ticks 1556system.realview.realview_io.osc_peripheral.clock 41667 # Clock period in ticks 1557system.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks 1558system.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks 1559system.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks 1560 1561---------- End Simulation Statistics ---------- 1562