stats.txt revision 10628
110515SAli.Saidi@ARM.com 210515SAli.Saidi@ARM.com---------- Begin Simulation Statistics ---------- 310628Sandreas.hansson@arm.comsim_seconds 51.728175 # Number of seconds simulated 410628Sandreas.hansson@arm.comsim_ticks 51728174627500 # Number of ticks simulated 510628Sandreas.hansson@arm.comfinal_tick 51728174627500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 610515SAli.Saidi@ARM.comsim_freq 1000000000000 # Frequency of simulated ticks 710628Sandreas.hansson@arm.comhost_inst_rate 184836 # Simulator instruction rate (inst/s) 810628Sandreas.hansson@arm.comhost_op_rate 217188 # Simulator op (including micro ops) rate (op/s) 910628Sandreas.hansson@arm.comhost_tick_rate 10028441874 # Simulator tick rate (ticks/s) 1010628Sandreas.hansson@arm.comhost_mem_usage 718288 # Number of bytes of host memory used 1110628Sandreas.hansson@arm.comhost_seconds 5158.15 # Real time elapsed on the host 1210628Sandreas.hansson@arm.comsim_insts 953410832 # Number of instructions simulated 1310628Sandreas.hansson@arm.comsim_ops 1120287994 # Number of ops (including micro ops) simulated 1410515SAli.Saidi@ARM.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1510515SAli.Saidi@ARM.comsystem.clk_domain.clock 1000 # Clock period in ticks 1610628Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.dtb.walker 394816 # Number of bytes read from this memory 1710628Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.itb.walker 334912 # Number of bytes read from this memory 1810628Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.inst 77628104 # Number of bytes read from this memory 1910628Sandreas.hansson@arm.comsystem.physmem.bytes_read::realview.ide 424256 # Number of bytes read from this memory 2010628Sandreas.hansson@arm.comsystem.physmem.bytes_read::total 78782088 # Number of bytes read from this memory 2110628Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu.inst 10241472 # Number of instructions bytes read from this memory 2210628Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::total 10241472 # Number of instructions bytes read from this memory 2310628Sandreas.hansson@arm.comsystem.physmem.bytes_written::writebacks 95103808 # Number of bytes written to this memory 2410585Sandreas.hansson@arm.comsystem.physmem.bytes_written::cpu.inst 20580 # Number of bytes written to this memory 2510628Sandreas.hansson@arm.comsystem.physmem.bytes_written::total 95124388 # Number of bytes written to this memory 2610628Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.dtb.walker 6169 # Number of read requests responded to by this memory 2710628Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.itb.walker 5233 # Number of read requests responded to by this memory 2810628Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.inst 1212952 # Number of read requests responded to by this memory 2910628Sandreas.hansson@arm.comsystem.physmem.num_reads::realview.ide 6629 # Number of read requests responded to by this memory 3010628Sandreas.hansson@arm.comsystem.physmem.num_reads::total 1230983 # Number of read requests responded to by this memory 3110628Sandreas.hansson@arm.comsystem.physmem.num_writes::writebacks 1485997 # Number of write requests responded to by this memory 3210585Sandreas.hansson@arm.comsystem.physmem.num_writes::cpu.inst 2573 # Number of write requests responded to by this memory 3310628Sandreas.hansson@arm.comsystem.physmem.num_writes::total 1488570 # Number of write requests responded to by this memory 3410628Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.dtb.walker 7633 # Total read bandwidth from this memory (bytes/s) 3510628Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.itb.walker 6474 # Total read bandwidth from this memory (bytes/s) 3610628Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.inst 1500693 # Total read bandwidth from this memory (bytes/s) 3710628Sandreas.hansson@arm.comsystem.physmem.bw_read::realview.ide 8202 # Total read bandwidth from this memory (bytes/s) 3810628Sandreas.hansson@arm.comsystem.physmem.bw_read::total 1523002 # Total read bandwidth from this memory (bytes/s) 3910628Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu.inst 197986 # Instruction read bandwidth from this memory (bytes/s) 4010628Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::total 197986 # Instruction read bandwidth from this memory (bytes/s) 4110628Sandreas.hansson@arm.comsystem.physmem.bw_write::writebacks 1838530 # Write bandwidth from this memory (bytes/s) 4210585Sandreas.hansson@arm.comsystem.physmem.bw_write::cpu.inst 398 # Write bandwidth from this memory (bytes/s) 4310628Sandreas.hansson@arm.comsystem.physmem.bw_write::total 1838928 # Write bandwidth from this memory (bytes/s) 4410628Sandreas.hansson@arm.comsystem.physmem.bw_total::writebacks 1838530 # Total bandwidth to/from this memory (bytes/s) 4510628Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.dtb.walker 7633 # Total bandwidth to/from this memory (bytes/s) 4610628Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.itb.walker 6474 # Total bandwidth to/from this memory (bytes/s) 4710628Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.inst 1501091 # Total bandwidth to/from this memory (bytes/s) 4810628Sandreas.hansson@arm.comsystem.physmem.bw_total::realview.ide 8202 # Total bandwidth to/from this memory (bytes/s) 4910628Sandreas.hansson@arm.comsystem.physmem.bw_total::total 3361929 # Total bandwidth to/from this memory (bytes/s) 5010628Sandreas.hansson@arm.comsystem.physmem.readReqs 1230983 # Number of read requests accepted 5110628Sandreas.hansson@arm.comsystem.physmem.writeReqs 2135785 # Number of write requests accepted 5210628Sandreas.hansson@arm.comsystem.physmem.readBursts 1230983 # Number of DRAM read bursts, including those serviced by the write queue 5310628Sandreas.hansson@arm.comsystem.physmem.writeBursts 2135785 # Number of DRAM write bursts, including those merged in the write queue 5410628Sandreas.hansson@arm.comsystem.physmem.bytesReadDRAM 78738176 # Total number of bytes read from DRAM 5510628Sandreas.hansson@arm.comsystem.physmem.bytesReadWrQ 44736 # Total number of bytes read from write queue 5610628Sandreas.hansson@arm.comsystem.physmem.bytesWritten 136238784 # Total number of bytes written to DRAM 5710628Sandreas.hansson@arm.comsystem.physmem.bytesReadSys 78782088 # Total read bytes from the system interface side 5810628Sandreas.hansson@arm.comsystem.physmem.bytesWrittenSys 136546148 # Total written bytes from the system interface side 5910628Sandreas.hansson@arm.comsystem.physmem.servicedByWrQ 699 # Number of DRAM read bursts serviced by the write queue 6010628Sandreas.hansson@arm.comsystem.physmem.mergedWrBursts 7032 # Number of DRAM write bursts merged with an existing one 6110628Sandreas.hansson@arm.comsystem.physmem.neitherReadNorWriteReqs 39789 # Number of requests that are neither read nor write 6210628Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::0 72855 # Per bank write bursts 6310628Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::1 77589 # Per bank write bursts 6410628Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::2 71702 # Per bank write bursts 6510628Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::3 69206 # Per bank write bursts 6610628Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::4 71012 # Per bank write bursts 6710628Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::5 79882 # Per bank write bursts 6810628Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::6 74555 # Per bank write bursts 6910628Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::7 73696 # Per bank write bursts 7010628Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::8 66951 # Per bank write bursts 7110628Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::9 130748 # Per bank write bursts 7210628Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::10 72702 # Per bank write bursts 7310628Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::11 77684 # Per bank write bursts 7410628Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::12 73029 # Per bank write bursts 7510628Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::13 75645 # Per bank write bursts 7610628Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::14 69035 # Per bank write bursts 7710628Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::15 73993 # Per bank write bursts 7810628Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::0 130105 # Per bank write bursts 7910628Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::1 136647 # Per bank write bursts 8010628Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::2 132594 # Per bank write bursts 8110628Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::3 132058 # Per bank write bursts 8210628Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::4 132790 # Per bank write bursts 8310628Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::5 135723 # Per bank write bursts 8410628Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::6 131916 # Per bank write bursts 8510628Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::7 135307 # Per bank write bursts 8610628Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::8 129762 # Per bank write bursts 8710628Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::9 138269 # Per bank write bursts 8810628Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::10 133041 # Per bank write bursts 8910628Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::11 135411 # Per bank write bursts 9010628Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::12 131809 # Per bank write bursts 9110628Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::13 134107 # Per bank write bursts 9210628Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::14 128778 # Per bank write bursts 9310628Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::15 130414 # Per bank write bursts 9410515SAli.Saidi@ARM.comsystem.physmem.numRdRetry 0 # Number of times read queue was full causing retry 9510585Sandreas.hansson@arm.comsystem.physmem.numWrRetry 1 # Number of times write queue was full causing retry 9610628Sandreas.hansson@arm.comsystem.physmem.totGap 51728172924500 # Total gap between requests 9710515SAli.Saidi@ARM.comsystem.physmem.readPktSize::0 0 # Read request sizes (log2) 9810515SAli.Saidi@ARM.comsystem.physmem.readPktSize::1 0 # Read request sizes (log2) 9910515SAli.Saidi@ARM.comsystem.physmem.readPktSize::2 0 # Read request sizes (log2) 10010515SAli.Saidi@ARM.comsystem.physmem.readPktSize::3 13 # Read request sizes (log2) 10110515SAli.Saidi@ARM.comsystem.physmem.readPktSize::4 2 # Read request sizes (log2) 10210515SAli.Saidi@ARM.comsystem.physmem.readPktSize::5 0 # Read request sizes (log2) 10310628Sandreas.hansson@arm.comsystem.physmem.readPktSize::6 1230968 # Read request sizes (log2) 10410515SAli.Saidi@ARM.comsystem.physmem.writePktSize::0 0 # Write request sizes (log2) 10510515SAli.Saidi@ARM.comsystem.physmem.writePktSize::1 0 # Write request sizes (log2) 10610515SAli.Saidi@ARM.comsystem.physmem.writePktSize::2 1 # Write request sizes (log2) 10710515SAli.Saidi@ARM.comsystem.physmem.writePktSize::3 2572 # Write request sizes (log2) 10810515SAli.Saidi@ARM.comsystem.physmem.writePktSize::4 0 # Write request sizes (log2) 10910515SAli.Saidi@ARM.comsystem.physmem.writePktSize::5 0 # Write request sizes (log2) 11010628Sandreas.hansson@arm.comsystem.physmem.writePktSize::6 2133212 # Write request sizes (log2) 11110628Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::0 1193516 # What read queue length does an incoming req see 11210628Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::1 30294 # What read queue length does an incoming req see 11310628Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::2 2468 # What read queue length does an incoming req see 11410628Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::3 634 # What read queue length does an incoming req see 11510628Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::4 774 # What read queue length does an incoming req see 11610628Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::5 445 # What read queue length does an incoming req see 11710628Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::6 402 # What read queue length does an incoming req see 11810628Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::7 326 # What read queue length does an incoming req see 11910628Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::8 225 # What read queue length does an incoming req see 12010628Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::9 151 # What read queue length does an incoming req see 12110628Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::10 141 # What read queue length does an incoming req see 12210628Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::11 133 # What read queue length does an incoming req see 12310628Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::12 117 # What read queue length does an incoming req see 12410628Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::13 116 # What read queue length does an incoming req see 12510628Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::14 112 # What read queue length does an incoming req see 12610628Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::15 108 # What read queue length does an incoming req see 12710628Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::16 93 # What read queue length does an incoming req see 12810628Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::17 91 # What read queue length does an incoming req see 12910628Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::18 75 # What read queue length does an incoming req see 13010628Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::19 59 # What read queue length does an incoming req see 13110628Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::20 3 # What read queue length does an incoming req see 13210628Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see 13310515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 13410515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 13510515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 13610515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 13710515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 13810515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 13910515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 14010515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 14110515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 14210515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 14310515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 14410515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 14510515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 14610515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 14710515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 14810515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 14910515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 15010515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 15110515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 15210515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 15310515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 15410515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 15510515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 15610515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 15710515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 15810628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::15 48810 # What write queue length does an incoming req see 15910628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::16 75161 # What write queue length does an incoming req see 16010628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::17 120471 # What write queue length does an incoming req see 16110628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::18 133680 # What write queue length does an incoming req see 16210628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::19 129638 # What write queue length does an incoming req see 16310628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::20 132279 # What write queue length does an incoming req see 16410628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::21 134371 # What write queue length does an incoming req see 16510628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::22 139270 # What write queue length does an incoming req see 16610628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::23 139351 # What write queue length does an incoming req see 16710628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::24 138718 # What write queue length does an incoming req see 16810628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::25 134041 # What write queue length does an incoming req see 16910628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::26 121456 # What write queue length does an incoming req see 17010628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::27 116921 # What write queue length does an incoming req see 17110628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::28 112653 # What write queue length does an incoming req see 17210628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::29 104822 # What write queue length does an incoming req see 17310628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::30 103529 # What write queue length does an incoming req see 17410628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::31 102348 # What write queue length does an incoming req see 17510628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::32 101456 # What write queue length does an incoming req see 17610628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::33 3528 # What write queue length does an incoming req see 17710628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::34 3145 # What write queue length does an incoming req see 17810628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::35 3077 # What write queue length does an incoming req see 17910628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::36 2746 # What write queue length does an incoming req see 18010628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::37 2646 # What write queue length does an incoming req see 18110628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::38 2462 # What write queue length does an incoming req see 18210628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::39 2396 # What write queue length does an incoming req see 18310628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::40 2343 # What write queue length does an incoming req see 18410628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::41 2218 # What write queue length does an incoming req see 18510628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::42 2043 # What write queue length does an incoming req see 18610628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::43 1968 # What write queue length does an incoming req see 18710628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::44 1747 # What write queue length does an incoming req see 18810628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::45 1501 # What write queue length does an incoming req see 18910628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::46 1440 # What write queue length does an incoming req see 19010628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::47 1271 # What write queue length does an incoming req see 19110628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::48 1084 # What write queue length does an incoming req see 19210628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::49 914 # What write queue length does an incoming req see 19310628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::50 813 # What write queue length does an incoming req see 19410628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::51 704 # What write queue length does an incoming req see 19510628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::52 545 # What write queue length does an incoming req see 19610628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::53 394 # What write queue length does an incoming req see 19710628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::54 297 # What write queue length does an incoming req see 19810628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::55 183 # What write queue length does an incoming req see 19910628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::56 128 # What write queue length does an incoming req see 20010628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::57 90 # What write queue length does an incoming req see 20110628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::58 45 # What write queue length does an incoming req see 20210628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::59 16 # What write queue length does an incoming req see 20310628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::60 11 # What write queue length does an incoming req see 20410628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::61 5 # What write queue length does an incoming req see 20510628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::62 1 # What write queue length does an incoming req see 20610628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::63 2 # What write queue length does an incoming req see 20710628Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::samples 724941 # Bytes accessed per row activation 20810628Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::mean 296.543548 # Bytes accessed per row activation 20910628Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::gmean 170.840359 # Bytes accessed per row activation 21010628Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::stdev 329.964737 # Bytes accessed per row activation 21110628Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::0-127 292739 40.38% 40.38% # Bytes accessed per row activation 21210628Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::128-255 175978 24.27% 64.66% # Bytes accessed per row activation 21310628Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::256-383 64522 8.90% 73.56% # Bytes accessed per row activation 21410628Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::384-511 36242 5.00% 78.56% # Bytes accessed per row activation 21510628Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::512-639 25200 3.48% 82.03% # Bytes accessed per row activation 21610628Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::640-767 17306 2.39% 84.42% # Bytes accessed per row activation 21710628Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::768-895 13334 1.84% 86.26% # Bytes accessed per row activation 21810628Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::896-1023 11857 1.64% 87.89% # Bytes accessed per row activation 21910628Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::1024-1151 87763 12.11% 100.00% # Bytes accessed per row activation 22010628Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::total 724941 # Bytes accessed per row activation 22110628Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::samples 98383 # Reads before turning the bus around for writes 22210628Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::mean 12.504427 # Reads before turning the bus around for writes 22310628Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::stdev 125.607658 # Reads before turning the bus around for writes 22410628Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::0-1023 98380 100.00% 100.00% # Reads before turning the bus around for writes 22510628Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::1024-2047 1 0.00% 100.00% # Reads before turning the bus around for writes 22610585Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::25600-26623 1 0.00% 100.00% # Reads before turning the bus around for writes 22710585Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::28672-29695 1 0.00% 100.00% # Reads before turning the bus around for writes 22810628Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::total 98383 # Reads before turning the bus around for writes 22910628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::samples 98383 # Writes before turning the bus around for reads 23010628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::mean 21.637183 # Writes before turning the bus around for reads 23110628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::gmean 20.054808 # Writes before turning the bus around for reads 23210628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::stdev 12.113777 # Writes before turning the bus around for reads 23310628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::16-23 71754 72.93% 72.93% # Writes before turning the bus around for reads 23410628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::24-31 19885 20.21% 93.15% # Writes before turning the bus around for reads 23510628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::32-39 3061 3.11% 96.26% # Writes before turning the bus around for reads 23610628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::40-47 745 0.76% 97.01% # Writes before turning the bus around for reads 23710628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::48-55 867 0.88% 97.89% # Writes before turning the bus around for reads 23810628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::56-63 408 0.41% 98.31% # Writes before turning the bus around for reads 23910628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::64-71 354 0.36% 98.67% # Writes before turning the bus around for reads 24010628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::72-79 234 0.24% 98.91% # Writes before turning the bus around for reads 24110628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::80-87 298 0.30% 99.21% # Writes before turning the bus around for reads 24210628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::88-95 183 0.19% 99.40% # Writes before turning the bus around for reads 24310628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::96-103 211 0.21% 99.61% # Writes before turning the bus around for reads 24410628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::104-111 51 0.05% 99.66% # Writes before turning the bus around for reads 24510628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::112-119 56 0.06% 99.72% # Writes before turning the bus around for reads 24610628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::120-127 41 0.04% 99.76% # Writes before turning the bus around for reads 24710628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::128-135 125 0.13% 99.89% # Writes before turning the bus around for reads 24810628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::136-143 21 0.02% 99.91% # Writes before turning the bus around for reads 24910628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::144-151 37 0.04% 99.95% # Writes before turning the bus around for reads 25010628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::152-159 9 0.01% 99.96% # Writes before turning the bus around for reads 25110628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::160-167 12 0.01% 99.97% # Writes before turning the bus around for reads 25210628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::168-175 3 0.00% 99.97% # Writes before turning the bus around for reads 25310628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::176-183 4 0.00% 99.98% # Writes before turning the bus around for reads 25410628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::184-191 7 0.01% 99.98% # Writes before turning the bus around for reads 25510628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::192-199 1 0.00% 99.98% # Writes before turning the bus around for reads 25610628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::200-207 4 0.00% 99.99% # Writes before turning the bus around for reads 25710628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::208-215 4 0.00% 99.99% # Writes before turning the bus around for reads 25810628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::216-223 1 0.00% 99.99% # Writes before turning the bus around for reads 25910628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::224-231 3 0.00% 100.00% # Writes before turning the bus around for reads 26010628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::240-247 1 0.00% 100.00% # Writes before turning the bus around for reads 26110628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::248-255 2 0.00% 100.00% # Writes before turning the bus around for reads 26210585Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::256-263 1 0.00% 100.00% # Writes before turning the bus around for reads 26310628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::total 98383 # Writes before turning the bus around for reads 26410628Sandreas.hansson@arm.comsystem.physmem.totQLat 15890716010 # Total ticks spent queuing 26510628Sandreas.hansson@arm.comsystem.physmem.totMemAccLat 38958541010 # Total ticks spent from burst creation until serviced by the DRAM 26610628Sandreas.hansson@arm.comsystem.physmem.totBusLat 6151420000 # Total ticks spent in databus transfers 26710628Sandreas.hansson@arm.comsystem.physmem.avgQLat 12916.30 # Average queueing delay per DRAM burst 26810515SAli.Saidi@ARM.comsystem.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 26910628Sandreas.hansson@arm.comsystem.physmem.avgMemAccLat 31666.30 # Average memory access latency per DRAM burst 27010585Sandreas.hansson@arm.comsystem.physmem.avgRdBW 1.52 # Average DRAM read bandwidth in MiByte/s 27110628Sandreas.hansson@arm.comsystem.physmem.avgWrBW 2.63 # Average achieved write bandwidth in MiByte/s 27210585Sandreas.hansson@arm.comsystem.physmem.avgRdBWSys 1.52 # Average system read bandwidth in MiByte/s 27310585Sandreas.hansson@arm.comsystem.physmem.avgWrBWSys 2.64 # Average system write bandwidth in MiByte/s 27410515SAli.Saidi@ARM.comsystem.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 27510585Sandreas.hansson@arm.comsystem.physmem.busUtil 0.03 # Data bus utilization in percentage 27610515SAli.Saidi@ARM.comsystem.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads 27710515SAli.Saidi@ARM.comsystem.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes 27810515SAli.Saidi@ARM.comsystem.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing 27910628Sandreas.hansson@arm.comsystem.physmem.avgWrQLen 24.58 # Average write queue length when enqueuing 28010628Sandreas.hansson@arm.comsystem.physmem.readRowHits 953619 # Number of row buffer hits during reads 28110628Sandreas.hansson@arm.comsystem.physmem.writeRowHits 1680454 # Number of row buffer hits during writes 28210628Sandreas.hansson@arm.comsystem.physmem.readRowHitRate 77.51 # Row buffer hit rate for reads 28310628Sandreas.hansson@arm.comsystem.physmem.writeRowHitRate 78.94 # Row buffer hit rate for writes 28410628Sandreas.hansson@arm.comsystem.physmem.avgGap 15364341.39 # Average gap between requests 28510628Sandreas.hansson@arm.comsystem.physmem.pageHitRate 78.42 # Row buffer hit rate, read and write combined 28610628Sandreas.hansson@arm.comsystem.physmem_0.actEnergy 2748558960 # Energy for activate commands per rank (pJ) 28710628Sandreas.hansson@arm.comsystem.physmem_0.preEnergy 1499709750 # Energy for precharge commands per rank (pJ) 28810628Sandreas.hansson@arm.comsystem.physmem_0.readEnergy 4605829800 # Energy for read commands per rank (pJ) 28910628Sandreas.hansson@arm.comsystem.physmem_0.writeEnergy 6915067200 # Energy for write commands per rank (pJ) 29010628Sandreas.hansson@arm.comsystem.physmem_0.refreshEnergy 3378632599680 # Energy for refresh commands per rank (pJ) 29110628Sandreas.hansson@arm.comsystem.physmem_0.actBackEnergy 1310572243215 # Energy for active background per rank (pJ) 29210628Sandreas.hansson@arm.comsystem.physmem_0.preBackEnergy 29887277315250 # Energy for precharge background per rank (pJ) 29310628Sandreas.hansson@arm.comsystem.physmem_0.totalEnergy 34592251323855 # Total energy per rank (pJ) 29410628Sandreas.hansson@arm.comsystem.physmem_0.averagePower 668.731394 # Core power per rank (mW) 29510628Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::IDLE 49719326487750 # Time in different power states 29610628Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::REF 1727317280000 # Time in different power states 29710628Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 29810628Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::ACT 281530424750 # Time in different power states 29910628Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 30010628Sandreas.hansson@arm.comsystem.physmem_1.actEnergy 2731995000 # Energy for activate commands per rank (pJ) 30110628Sandreas.hansson@arm.comsystem.physmem_1.preEnergy 1490671875 # Energy for precharge commands per rank (pJ) 30210628Sandreas.hansson@arm.comsystem.physmem_1.readEnergy 4990338600 # Energy for read commands per rank (pJ) 30310628Sandreas.hansson@arm.comsystem.physmem_1.writeEnergy 6879109680 # Energy for write commands per rank (pJ) 30410628Sandreas.hansson@arm.comsystem.physmem_1.refreshEnergy 3378632599680 # Energy for refresh commands per rank (pJ) 30510628Sandreas.hansson@arm.comsystem.physmem_1.actBackEnergy 1309819963770 # Energy for active background per rank (pJ) 30610628Sandreas.hansson@arm.comsystem.physmem_1.preBackEnergy 29887937201250 # Energy for precharge background per rank (pJ) 30710628Sandreas.hansson@arm.comsystem.physmem_1.totalEnergy 34592481879855 # Total energy per rank (pJ) 30810628Sandreas.hansson@arm.comsystem.physmem_1.averagePower 668.735851 # Core power per rank (mW) 30910628Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::IDLE 49720391571002 # Time in different power states 31010628Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::REF 1727317280000 # Time in different power states 31110628Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 31210628Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::ACT 280461298998 # Time in different power states 31310628Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 31410515SAli.Saidi@ARM.comsystem.realview.nvmem.bytes_read::cpu.inst 740 # Number of bytes read from this memory 31510515SAli.Saidi@ARM.comsystem.realview.nvmem.bytes_read::total 740 # Number of bytes read from this memory 31610515SAli.Saidi@ARM.comsystem.realview.nvmem.bytes_inst_read::cpu.inst 704 # Number of instructions bytes read from this memory 31710515SAli.Saidi@ARM.comsystem.realview.nvmem.bytes_inst_read::total 704 # Number of instructions bytes read from this memory 31810515SAli.Saidi@ARM.comsystem.realview.nvmem.num_reads::cpu.inst 16 # Number of read requests responded to by this memory 31910515SAli.Saidi@ARM.comsystem.realview.nvmem.num_reads::total 16 # Number of read requests responded to by this memory 32010515SAli.Saidi@ARM.comsystem.realview.nvmem.bw_read::cpu.inst 14 # Total read bandwidth from this memory (bytes/s) 32110515SAli.Saidi@ARM.comsystem.realview.nvmem.bw_read::total 14 # Total read bandwidth from this memory (bytes/s) 32210515SAli.Saidi@ARM.comsystem.realview.nvmem.bw_inst_read::cpu.inst 14 # Instruction read bandwidth from this memory (bytes/s) 32310515SAli.Saidi@ARM.comsystem.realview.nvmem.bw_inst_read::total 14 # Instruction read bandwidth from this memory (bytes/s) 32410515SAli.Saidi@ARM.comsystem.realview.nvmem.bw_total::cpu.inst 14 # Total bandwidth to/from this memory (bytes/s) 32510515SAli.Saidi@ARM.comsystem.realview.nvmem.bw_total::total 14 # Total bandwidth to/from this memory (bytes/s) 32610585Sandreas.hansson@arm.comsystem.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 32710585Sandreas.hansson@arm.comsystem.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 32810585Sandreas.hansson@arm.comsystem.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 32910585Sandreas.hansson@arm.comsystem.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. 33010585Sandreas.hansson@arm.comsystem.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. 33110585Sandreas.hansson@arm.comsystem.cf0.dma_write_txs 1669 # Number of DMA write transactions. 33210628Sandreas.hansson@arm.comsystem.cpu.branchPred.lookups 261740307 # Number of BP lookups 33310628Sandreas.hansson@arm.comsystem.cpu.branchPred.condPredicted 183617747 # Number of conditional branches predicted 33410628Sandreas.hansson@arm.comsystem.cpu.branchPred.condIncorrect 12193617 # Number of conditional branches incorrect 33510628Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBLookups 193974198 # Number of BTB lookups 33610628Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBHits 136954935 # Number of BTB hits 33710585Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 33810628Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBHitPct 70.604718 # BTB Hit Percentage 33910628Sandreas.hansson@arm.comsystem.cpu.branchPred.usedRAS 31757981 # Number of times the RAS was used to get a target. 34010628Sandreas.hansson@arm.comsystem.cpu.branchPred.RASInCorrect 2120874 # Number of incorrect RAS predictions. 34110585Sandreas.hansson@arm.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 34210628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 34310628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 34410628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 34510628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 34610628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 34710628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 34810628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 34910628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 35010585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 35110585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 35210585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 35310585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 35410585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 35510585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 35610585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 35710585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 35810585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 35910585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 36010585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 36110585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 36210585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 36310585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 36410585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 36510585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 36610585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 36710585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 36810585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 36910585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 37010585Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 37110628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walks 587644 # Table walker walks requested 37210628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walksLong 587644 # Table walker walks initiated with long descriptors 37310628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walksLongTerminationLevel::Level2 20971 # Level at which table walker walks with long descriptors terminate 37410628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walksLongTerminationLevel::Level3 193860 # Level at which table walker walks with long descriptors terminate 37510628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkWaitTime::samples 587644 # Table walker wait (enqueue to first request) latency 37610628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkWaitTime::0 587644 100.00% 100.00% # Table walker wait (enqueue to first request) latency 37710628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkWaitTime::total 587644 # Table walker wait (enqueue to first request) latency 37810628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkCompletionTime::samples 214831 # Table walker service (enqueue to completion) latency 37910628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkCompletionTime::mean 23073.231987 # Table walker service (enqueue to completion) latency 38010628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkCompletionTime::gmean 18856.280230 # Table walker service (enqueue to completion) latency 38110628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkCompletionTime::stdev 14797.492454 # Table walker service (enqueue to completion) latency 38210628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkCompletionTime::0-65535 212337 98.84% 98.84% # Table walker service (enqueue to completion) latency 38310628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkCompletionTime::65536-131071 2138 1.00% 99.83% # Table walker service (enqueue to completion) latency 38410628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkCompletionTime::131072-196607 152 0.07% 99.91% # Table walker service (enqueue to completion) latency 38510628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkCompletionTime::196608-262143 133 0.06% 99.97% # Table walker service (enqueue to completion) latency 38610628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkCompletionTime::262144-327679 38 0.02% 99.98% # Table walker service (enqueue to completion) latency 38710628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkCompletionTime::327680-393215 25 0.01% 100.00% # Table walker service (enqueue to completion) latency 38810628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkCompletionTime::393216-458751 6 0.00% 100.00% # Table walker service (enqueue to completion) latency 38910628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 39010628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 39110628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkCompletionTime::total 214831 # Table walker service (enqueue to completion) latency 39210628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walksPending::samples -243009796 # Table walker pending requests distribution 39310628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walksPending::0 -243009796 100.00% 100.00% # Table walker pending requests distribution 39410628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walksPending::total -243009796 # Table walker pending requests distribution 39510628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkPageSizes::4K 193861 90.24% 90.24% # Table walker page sizes translated 39610628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkPageSizes::2M 20971 9.76% 100.00% # Table walker page sizes translated 39710628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkPageSizes::total 214832 # Table walker page sizes translated 39810628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Requested::Data 587644 # Table walker requests started/completed, data/inst 39910628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 40010628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Requested::total 587644 # Table walker requests started/completed, data/inst 40110628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Completed::Data 214832 # Table walker requests started/completed, data/inst 40210628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 40310628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Completed::total 214832 # Table walker requests started/completed, data/inst 40410628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin::total 802476 # Table walker requests started/completed, data/inst 40510585Sandreas.hansson@arm.comsystem.cpu.dtb.inst_hits 0 # ITB inst hits 40610585Sandreas.hansson@arm.comsystem.cpu.dtb.inst_misses 0 # ITB inst misses 40710628Sandreas.hansson@arm.comsystem.cpu.dtb.read_hits 184101010 # DTB read hits 40810628Sandreas.hansson@arm.comsystem.cpu.dtb.read_misses 486113 # DTB read misses 40910628Sandreas.hansson@arm.comsystem.cpu.dtb.write_hits 163332837 # DTB write hits 41010628Sandreas.hansson@arm.comsystem.cpu.dtb.write_misses 101531 # DTB write misses 41110585Sandreas.hansson@arm.comsystem.cpu.dtb.flush_tlb 11 # Number of times complete TLB was flushed 41210585Sandreas.hansson@arm.comsystem.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 41310628Sandreas.hansson@arm.comsystem.cpu.dtb.flush_tlb_mva_asid 47436 # Number of times TLB was flushed by MVA & ASID 41410585Sandreas.hansson@arm.comsystem.cpu.dtb.flush_tlb_asid 1113 # Number of times TLB was flushed by ASID 41510628Sandreas.hansson@arm.comsystem.cpu.dtb.flush_entries 79171 # Number of entries that have been flushed from TLB 41610628Sandreas.hansson@arm.comsystem.cpu.dtb.align_faults 889 # Number of TLB faults due to alignment restrictions 41710628Sandreas.hansson@arm.comsystem.cpu.dtb.prefetch_faults 14871 # Number of TLB faults due to prefetch 41810585Sandreas.hansson@arm.comsystem.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 41910628Sandreas.hansson@arm.comsystem.cpu.dtb.perms_faults 23598 # Number of TLB faults due to permissions restrictions 42010628Sandreas.hansson@arm.comsystem.cpu.dtb.read_accesses 184587123 # DTB read accesses 42110628Sandreas.hansson@arm.comsystem.cpu.dtb.write_accesses 163434368 # DTB write accesses 42210585Sandreas.hansson@arm.comsystem.cpu.dtb.inst_accesses 0 # ITB inst accesses 42310628Sandreas.hansson@arm.comsystem.cpu.dtb.hits 347433847 # DTB hits 42410628Sandreas.hansson@arm.comsystem.cpu.dtb.misses 587644 # DTB misses 42510628Sandreas.hansson@arm.comsystem.cpu.dtb.accesses 348021491 # DTB accesses 42610628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 42710628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 42810628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 42910628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 43010628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 43110628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 43210628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 43310628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 43410585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 43510585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 43610585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 43710585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 43810585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 43910585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 44010585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 44110585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 44210585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 44310585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 44410585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 44510585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 44610585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 44710585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 44810585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 44910585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 45010585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 45110585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 45210585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 45310585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 45410585Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 45510628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walks 136955 # Table walker walks requested 45610628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walksLong 136955 # Table walker walks initiated with long descriptors 45710628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walksLongTerminationLevel::Level2 1083 # Level at which table walker walks with long descriptors terminate 45810628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walksLongTerminationLevel::Level3 119238 # Level at which table walker walks with long descriptors terminate 45910628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkWaitTime::samples 136955 # Table walker wait (enqueue to first request) latency 46010628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkWaitTime::0 136955 100.00% 100.00% # Table walker wait (enqueue to first request) latency 46110628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkWaitTime::total 136955 # Table walker wait (enqueue to first request) latency 46210628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkCompletionTime::samples 120321 # Table walker service (enqueue to completion) latency 46310628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkCompletionTime::mean 25178.697160 # Table walker service (enqueue to completion) latency 46410628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkCompletionTime::gmean 21090.590253 # Table walker service (enqueue to completion) latency 46510628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkCompletionTime::stdev 16725.174106 # Table walker service (enqueue to completion) latency 46610628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkCompletionTime::0-65535 117467 97.63% 97.63% # Table walker service (enqueue to completion) latency 46710628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkCompletionTime::65536-131071 2593 2.16% 99.78% # Table walker service (enqueue to completion) latency 46810628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkCompletionTime::131072-196607 161 0.13% 99.92% # Table walker service (enqueue to completion) latency 46910628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkCompletionTime::196608-262143 40 0.03% 99.95% # Table walker service (enqueue to completion) latency 47010628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkCompletionTime::262144-327679 38 0.03% 99.98% # Table walker service (enqueue to completion) latency 47110628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkCompletionTime::327680-393215 20 0.02% 100.00% # Table walker service (enqueue to completion) latency 47210628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 47310628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 47410628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkCompletionTime::total 120321 # Table walker service (enqueue to completion) latency 47510628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walksPending::samples -243525796 # Table walker pending requests distribution 47610628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walksPending::0 -243525796 100.00% 100.00% # Table walker pending requests distribution 47710628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walksPending::total -243525796 # Table walker pending requests distribution 47810628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkPageSizes::4K 119238 99.10% 99.10% # Table walker page sizes translated 47910628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkPageSizes::2M 1083 0.90% 100.00% # Table walker page sizes translated 48010628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkPageSizes::total 120321 # Table walker page sizes translated 48110628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 48210628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Requested::Inst 136955 # Table walker requests started/completed, data/inst 48310628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Requested::total 136955 # Table walker requests started/completed, data/inst 48410628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 48510628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Completed::Inst 120321 # Table walker requests started/completed, data/inst 48610628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Completed::total 120321 # Table walker requests started/completed, data/inst 48710628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin::total 257276 # Table walker requests started/completed, data/inst 48810628Sandreas.hansson@arm.comsystem.cpu.itb.inst_hits 455989522 # ITB inst hits 48910628Sandreas.hansson@arm.comsystem.cpu.itb.inst_misses 136955 # ITB inst misses 49010585Sandreas.hansson@arm.comsystem.cpu.itb.read_hits 0 # DTB read hits 49110585Sandreas.hansson@arm.comsystem.cpu.itb.read_misses 0 # DTB read misses 49210585Sandreas.hansson@arm.comsystem.cpu.itb.write_hits 0 # DTB write hits 49310585Sandreas.hansson@arm.comsystem.cpu.itb.write_misses 0 # DTB write misses 49410585Sandreas.hansson@arm.comsystem.cpu.itb.flush_tlb 11 # Number of times complete TLB was flushed 49510585Sandreas.hansson@arm.comsystem.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 49610628Sandreas.hansson@arm.comsystem.cpu.itb.flush_tlb_mva_asid 47436 # Number of times TLB was flushed by MVA & ASID 49710585Sandreas.hansson@arm.comsystem.cpu.itb.flush_tlb_asid 1113 # Number of times TLB was flushed by ASID 49810628Sandreas.hansson@arm.comsystem.cpu.itb.flush_entries 56761 # Number of entries that have been flushed from TLB 49910585Sandreas.hansson@arm.comsystem.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 50010585Sandreas.hansson@arm.comsystem.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 50110585Sandreas.hansson@arm.comsystem.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 50210628Sandreas.hansson@arm.comsystem.cpu.itb.perms_faults 364272 # Number of TLB faults due to permissions restrictions 50310585Sandreas.hansson@arm.comsystem.cpu.itb.read_accesses 0 # DTB read accesses 50410585Sandreas.hansson@arm.comsystem.cpu.itb.write_accesses 0 # DTB write accesses 50510628Sandreas.hansson@arm.comsystem.cpu.itb.inst_accesses 456126477 # ITB inst accesses 50610628Sandreas.hansson@arm.comsystem.cpu.itb.hits 455989522 # DTB hits 50710628Sandreas.hansson@arm.comsystem.cpu.itb.misses 136955 # DTB misses 50810628Sandreas.hansson@arm.comsystem.cpu.itb.accesses 456126477 # DTB accesses 50910628Sandreas.hansson@arm.comsystem.cpu.numCycles 2523007146 # number of cpu cycles simulated 51010585Sandreas.hansson@arm.comsystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 51110585Sandreas.hansson@arm.comsystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 51210628Sandreas.hansson@arm.comsystem.cpu.committedInsts 953410832 # Number of instructions committed 51310628Sandreas.hansson@arm.comsystem.cpu.committedOps 1120287994 # Number of ops (including micro ops) committed 51410628Sandreas.hansson@arm.comsystem.cpu.discardedOps 97416264 # Number of ops (including micro ops) which were discarded before commit 51510628Sandreas.hansson@arm.comsystem.cpu.numFetchSuspends 7771 # Number of times Execute suspended instruction fetching 51610628Sandreas.hansson@arm.comsystem.cpu.quiesceCycles 100934517430 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 51710628Sandreas.hansson@arm.comsystem.cpu.cpi 2.646296 # CPI: cycles per instruction 51810628Sandreas.hansson@arm.comsystem.cpu.ipc 0.377887 # IPC: instructions per cycle 51910585Sandreas.hansson@arm.comsystem.cpu.kern.inst.arm 0 # number of arm instructions executed 52010628Sandreas.hansson@arm.comsystem.cpu.kern.inst.quiesce 16631 # number of quiesce instructions executed 52110628Sandreas.hansson@arm.comsystem.cpu.tickCycles 1807938889 # Number of cycles that the object actually ticked 52210628Sandreas.hansson@arm.comsystem.cpu.idleCycles 715068257 # Total number of cycles that the object has spent stopped 52310628Sandreas.hansson@arm.comsystem.cpu.dcache.tags.replacements 11209162 # number of replacements 52410628Sandreas.hansson@arm.comsystem.cpu.dcache.tags.tagsinuse 511.959689 # Cycle average of tags in use 52510628Sandreas.hansson@arm.comsystem.cpu.dcache.tags.total_refs 331084794 # Total number of references to valid blocks. 52610628Sandreas.hansson@arm.comsystem.cpu.dcache.tags.sampled_refs 11209674 # Sample count of references to valid blocks. 52710628Sandreas.hansson@arm.comsystem.cpu.dcache.tags.avg_refs 29.535631 # Average number of references to valid blocks. 52810585Sandreas.hansson@arm.comsystem.cpu.dcache.tags.warmup_cycle 4089991250 # Cycle when the warmup percentage was hit. 52910628Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_blocks::cpu.inst 511.959689 # Average occupied blocks per requestor 53010585Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_percent::cpu.inst 0.999921 # Average percentage of cache occupancy 53110585Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_percent::total 0.999921 # Average percentage of cache occupancy 53210585Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 53310628Sandreas.hansson@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::0 70 # Occupied blocks per task id 53410628Sandreas.hansson@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::1 392 # Occupied blocks per task id 53510628Sandreas.hansson@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::2 48 # Occupied blocks per task id 53610585Sandreas.hansson@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id 53710585Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 53810628Sandreas.hansson@arm.comsystem.cpu.dcache.tags.tag_accesses 1391009936 # Number of tag accesses 53910628Sandreas.hansson@arm.comsystem.cpu.dcache.tags.data_accesses 1391009936 # Number of data accesses 54010628Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::cpu.inst 169770938 # number of ReadReq hits 54110628Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::total 169770938 # number of ReadReq hits 54210628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_hits::cpu.inst 152453541 # number of WriteReq hits 54310628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_hits::total 152453541 # number of WriteReq hits 54410628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteInvalidateReq_hits::cpu.inst 337498 # number of WriteInvalidateReq hits 54510628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteInvalidateReq_hits::total 337498 # number of WriteInvalidateReq hits 54610628Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_hits::cpu.inst 4114364 # number of LoadLockedReq hits 54710628Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_hits::total 4114364 # number of LoadLockedReq hits 54810628Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_hits::cpu.inst 4358642 # number of StoreCondReq hits 54910628Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_hits::total 4358642 # number of StoreCondReq hits 55010628Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::cpu.inst 322224479 # number of demand (read+write) hits 55110628Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::total 322224479 # number of demand (read+write) hits 55210628Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::cpu.inst 322224479 # number of overall hits 55310628Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::total 322224479 # number of overall hits 55410628Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::cpu.inst 8085158 # number of ReadReq misses 55510628Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::total 8085158 # number of ReadReq misses 55610628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::cpu.inst 4338895 # number of WriteReq misses 55710628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::total 4338895 # number of WriteReq misses 55810628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteInvalidateReq_misses::cpu.inst 1245002 # number of WriteInvalidateReq misses 55910628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteInvalidateReq_misses::total 1245002 # number of WriteInvalidateReq misses 56010628Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_misses::cpu.inst 246013 # number of LoadLockedReq misses 56110628Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_misses::total 246013 # number of LoadLockedReq misses 56210585Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_misses::cpu.inst 2 # number of StoreCondReq misses 56310585Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses 56410628Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::cpu.inst 12424053 # number of demand (read+write) misses 56510628Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::total 12424053 # number of demand (read+write) misses 56610628Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::cpu.inst 12424053 # number of overall misses 56710628Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::total 12424053 # number of overall misses 56810628Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_latency::cpu.inst 128824080247 # number of ReadReq miss cycles 56910628Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_latency::total 128824080247 # number of ReadReq miss cycles 57010628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_latency::cpu.inst 144514675403 # number of WriteReq miss cycles 57110628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_latency::total 144514675403 # number of WriteReq miss cycles 57210628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteInvalidateReq_miss_latency::cpu.inst 29607413192 # number of WriteInvalidateReq miss cycles 57310628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteInvalidateReq_miss_latency::total 29607413192 # number of WriteInvalidateReq miss cycles 57410628Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_latency::cpu.inst 3571422003 # number of LoadLockedReq miss cycles 57510628Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_latency::total 3571422003 # number of LoadLockedReq miss cycles 57610585Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_miss_latency::cpu.inst 150500 # number of StoreCondReq miss cycles 57710585Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_miss_latency::total 150500 # number of StoreCondReq miss cycles 57810628Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_latency::cpu.inst 273338755650 # number of demand (read+write) miss cycles 57910628Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_latency::total 273338755650 # number of demand (read+write) miss cycles 58010628Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_latency::cpu.inst 273338755650 # number of overall miss cycles 58110628Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_latency::total 273338755650 # number of overall miss cycles 58210628Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::cpu.inst 177856096 # number of ReadReq accesses(hits+misses) 58310628Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::total 177856096 # number of ReadReq accesses(hits+misses) 58410628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_accesses::cpu.inst 156792436 # number of WriteReq accesses(hits+misses) 58510628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_accesses::total 156792436 # number of WriteReq accesses(hits+misses) 58610628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteInvalidateReq_accesses::cpu.inst 1582500 # number of WriteInvalidateReq accesses(hits+misses) 58710628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteInvalidateReq_accesses::total 1582500 # number of WriteInvalidateReq accesses(hits+misses) 58810628Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::cpu.inst 4360377 # number of LoadLockedReq accesses(hits+misses) 58910628Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::total 4360377 # number of LoadLockedReq accesses(hits+misses) 59010628Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_accesses::cpu.inst 4358644 # number of StoreCondReq accesses(hits+misses) 59110628Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_accesses::total 4358644 # number of StoreCondReq accesses(hits+misses) 59210628Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::cpu.inst 334648532 # number of demand (read+write) accesses 59310628Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::total 334648532 # number of demand (read+write) accesses 59410628Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::cpu.inst 334648532 # number of overall (read+write) accesses 59510628Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::total 334648532 # number of overall (read+write) accesses 59610628Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.045459 # miss rate for ReadReq accesses 59710628Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_rate::total 0.045459 # miss rate for ReadReq accesses 59810628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.027673 # miss rate for WriteReq accesses 59910628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_rate::total 0.027673 # miss rate for WriteReq accesses 60010628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteInvalidateReq_miss_rate::cpu.inst 0.786731 # miss rate for WriteInvalidateReq accesses 60110628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteInvalidateReq_miss_rate::total 0.786731 # miss rate for WriteInvalidateReq accesses 60210628Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_rate::cpu.inst 0.056420 # miss rate for LoadLockedReq accesses 60310628Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_rate::total 0.056420 # miss rate for LoadLockedReq accesses 60410585Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_miss_rate::cpu.inst 0.000000 # miss rate for StoreCondReq accesses 60510585Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_miss_rate::total 0.000000 # miss rate for StoreCondReq accesses 60610628Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_rate::cpu.inst 0.037126 # miss rate for demand accesses 60710628Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_rate::total 0.037126 # miss rate for demand accesses 60810628Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_rate::cpu.inst 0.037126 # miss rate for overall accesses 60910628Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_rate::total 0.037126 # miss rate for overall accesses 61010628Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 15933.402940 # average ReadReq miss latency 61110628Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::total 15933.402940 # average ReadReq miss latency 61210628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 33306.792490 # average WriteReq miss latency 61310628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::total 33306.792490 # average WriteReq miss latency 61410628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteInvalidateReq_avg_miss_latency::cpu.inst 23781.016570 # average WriteInvalidateReq miss latency 61510628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteInvalidateReq_avg_miss_latency::total 23781.016570 # average WriteInvalidateReq miss latency 61610628Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.inst 14517.208452 # average LoadLockedReq miss latency 61710628Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14517.208452 # average LoadLockedReq miss latency 61810585Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.inst 75250 # average StoreCondReq miss latency 61910585Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_avg_miss_latency::total 75250 # average StoreCondReq miss latency 62010628Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_miss_latency::cpu.inst 22000.771862 # average overall miss latency 62110628Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_miss_latency::total 22000.771862 # average overall miss latency 62210628Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_miss_latency::cpu.inst 22000.771862 # average overall miss latency 62310628Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_miss_latency::total 22000.771862 # average overall miss latency 62410585Sandreas.hansson@arm.comsystem.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 62510585Sandreas.hansson@arm.comsystem.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 62610585Sandreas.hansson@arm.comsystem.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 62710585Sandreas.hansson@arm.comsystem.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 62810585Sandreas.hansson@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 62910585Sandreas.hansson@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 63010585Sandreas.hansson@arm.comsystem.cpu.dcache.fast_writes 0 # number of fast writes performed 63110585Sandreas.hansson@arm.comsystem.cpu.dcache.cache_copies 0 # number of cache copies performed 63210628Sandreas.hansson@arm.comsystem.cpu.dcache.writebacks::writebacks 8593512 # number of writebacks 63310628Sandreas.hansson@arm.comsystem.cpu.dcache.writebacks::total 8593512 # number of writebacks 63410628Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::cpu.inst 755938 # number of ReadReq MSHR hits 63510628Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::total 755938 # number of ReadReq MSHR hits 63610628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::cpu.inst 1899458 # number of WriteReq MSHR hits 63710628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::total 1899458 # number of WriteReq MSHR hits 63810628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteInvalidateReq_mshr_hits::cpu.inst 141 # number of WriteInvalidateReq MSHR hits 63910628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteInvalidateReq_mshr_hits::total 141 # number of WriteInvalidateReq MSHR hits 64010628Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_hits::cpu.inst 4 # number of LoadLockedReq MSHR hits 64110628Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_hits::total 4 # number of LoadLockedReq MSHR hits 64210628Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_hits::cpu.inst 2655396 # number of demand (read+write) MSHR hits 64310628Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_hits::total 2655396 # number of demand (read+write) MSHR hits 64410628Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_hits::cpu.inst 2655396 # number of overall MSHR hits 64510628Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_hits::total 2655396 # number of overall MSHR hits 64610628Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::cpu.inst 7329220 # number of ReadReq MSHR misses 64710628Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::total 7329220 # number of ReadReq MSHR misses 64810628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::cpu.inst 2439437 # number of WriteReq MSHR misses 64910628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::total 2439437 # number of WriteReq MSHR misses 65010628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteInvalidateReq_mshr_misses::cpu.inst 1244861 # number of WriteInvalidateReq MSHR misses 65110628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteInvalidateReq_mshr_misses::total 1244861 # number of WriteInvalidateReq MSHR misses 65210628Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_misses::cpu.inst 246009 # number of LoadLockedReq MSHR misses 65310628Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_misses::total 246009 # number of LoadLockedReq MSHR misses 65410585Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_mshr_misses::cpu.inst 2 # number of StoreCondReq MSHR misses 65510585Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses 65610628Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_misses::cpu.inst 9768657 # number of demand (read+write) MSHR misses 65710628Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_misses::total 9768657 # number of demand (read+write) MSHR misses 65810628Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_misses::cpu.inst 9768657 # number of overall MSHR misses 65910628Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_misses::total 9768657 # number of overall MSHR misses 66010628Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 102525908749 # number of ReadReq MSHR miss cycles 66110628Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::total 102525908749 # number of ReadReq MSHR miss cycles 66210628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 73694416463 # number of WriteReq MSHR miss cycles 66310628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::total 73694416463 # number of WriteReq MSHR miss cycles 66410628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::cpu.inst 27114416558 # number of WriteInvalidateReq MSHR miss cycles 66510628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::total 27114416558 # number of WriteInvalidateReq MSHR miss cycles 66610628Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.inst 3077572997 # number of LoadLockedReq MSHR miss cycles 66710628Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3077572997 # number of LoadLockedReq MSHR miss cycles 66810585Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.inst 146500 # number of StoreCondReq MSHR miss cycles 66910585Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_mshr_miss_latency::total 146500 # number of StoreCondReq MSHR miss cycles 67010628Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::cpu.inst 176220325212 # number of demand (read+write) MSHR miss cycles 67110628Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::total 176220325212 # number of demand (read+write) MSHR miss cycles 67210628Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::cpu.inst 176220325212 # number of overall MSHR miss cycles 67310628Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::total 176220325212 # number of overall MSHR miss cycles 67410628Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.inst 5727815999 # number of ReadReq MSHR uncacheable cycles 67510628Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5727815999 # number of ReadReq MSHR uncacheable cycles 67610628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.inst 5585117500 # number of WriteReq MSHR uncacheable cycles 67710628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5585117500 # number of WriteReq MSHR uncacheable cycles 67810628Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_uncacheable_latency::cpu.inst 11312933499 # number of overall MSHR uncacheable cycles 67910628Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_uncacheable_latency::total 11312933499 # number of overall MSHR uncacheable cycles 68010628Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.041209 # mshr miss rate for ReadReq accesses 68110628Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::total 0.041209 # mshr miss rate for ReadReq accesses 68210628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.015558 # mshr miss rate for WriteReq accesses 68310628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015558 # mshr miss rate for WriteReq accesses 68410628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::cpu.inst 0.786642 # mshr miss rate for WriteInvalidateReq accesses 68510628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.786642 # mshr miss rate for WriteInvalidateReq accesses 68610628Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.inst 0.056419 # mshr miss rate for LoadLockedReq accesses 68710628Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.056419 # mshr miss rate for LoadLockedReq accesses 68810585Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for StoreCondReq accesses 68910585Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000000 # mshr miss rate for StoreCondReq accesses 69010628Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.029191 # mshr miss rate for demand accesses 69110628Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::total 0.029191 # mshr miss rate for demand accesses 69210628Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.029191 # mshr miss rate for overall accesses 69310628Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::total 0.029191 # mshr miss rate for overall accesses 69410628Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 13988.652101 # average ReadReq mshr miss latency 69510628Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13988.652101 # average ReadReq mshr miss latency 69610628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 30209.600192 # average WriteReq mshr miss latency 69710628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30209.600192 # average WriteReq mshr miss latency 69810628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.inst 21781.079621 # average WriteInvalidateReq mshr miss latency 69910628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 21781.079621 # average WriteInvalidateReq mshr miss latency 70010628Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.inst 12510.001654 # average LoadLockedReq mshr miss latency 70110628Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12510.001654 # average LoadLockedReq mshr miss latency 70210585Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.inst 73250 # average StoreCondReq mshr miss latency 70310585Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 73250 # average StoreCondReq mshr miss latency 70410628Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 18039.360499 # average overall mshr miss latency 70510628Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::total 18039.360499 # average overall mshr miss latency 70610628Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 18039.360499 # average overall mshr miss latency 70710628Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::total 18039.360499 # average overall mshr miss latency 70810585Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 70910585Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 71010585Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst inf # average WriteReq mshr uncacheable latency 71110585Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 71210585Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 71310585Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 71410585Sandreas.hansson@arm.comsystem.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 71510628Sandreas.hansson@arm.comsystem.cpu.icache.tags.replacements 24725990 # number of replacements 71610628Sandreas.hansson@arm.comsystem.cpu.icache.tags.tagsinuse 511.931995 # Cycle average of tags in use 71710628Sandreas.hansson@arm.comsystem.cpu.icache.tags.total_refs 430886861 # Total number of references to valid blocks. 71810628Sandreas.hansson@arm.comsystem.cpu.icache.tags.sampled_refs 24726502 # Sample count of references to valid blocks. 71910628Sandreas.hansson@arm.comsystem.cpu.icache.tags.avg_refs 17.426115 # Average number of references to valid blocks. 72010628Sandreas.hansson@arm.comsystem.cpu.icache.tags.warmup_cycle 21192166000 # Cycle when the warmup percentage was hit. 72110628Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_blocks::cpu.inst 511.931995 # Average occupied blocks per requestor 72210585Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_percent::cpu.inst 0.999867 # Average percentage of cache occupancy 72310585Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_percent::total 0.999867 # Average percentage of cache occupancy 72410585Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 72510585Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::0 96 # Occupied blocks per task id 72610628Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::1 273 # Occupied blocks per task id 72710628Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::2 143 # Occupied blocks per task id 72810585Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 72910628Sandreas.hansson@arm.comsystem.cpu.icache.tags.tag_accesses 480339884 # Number of tag accesses 73010628Sandreas.hansson@arm.comsystem.cpu.icache.tags.data_accesses 480339884 # Number of data accesses 73110628Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::cpu.inst 430886861 # number of ReadReq hits 73210628Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::total 430886861 # number of ReadReq hits 73310628Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::cpu.inst 430886861 # number of demand (read+write) hits 73410628Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::total 430886861 # number of demand (read+write) hits 73510628Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::cpu.inst 430886861 # number of overall hits 73610628Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::total 430886861 # number of overall hits 73710628Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::cpu.inst 24726512 # number of ReadReq misses 73810628Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::total 24726512 # number of ReadReq misses 73910628Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::cpu.inst 24726512 # number of demand (read+write) misses 74010628Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::total 24726512 # number of demand (read+write) misses 74110628Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::cpu.inst 24726512 # number of overall misses 74210628Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::total 24726512 # number of overall misses 74310628Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_latency::cpu.inst 328589993689 # number of ReadReq miss cycles 74410628Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_latency::total 328589993689 # number of ReadReq miss cycles 74510628Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_latency::cpu.inst 328589993689 # number of demand (read+write) miss cycles 74610628Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_latency::total 328589993689 # number of demand (read+write) miss cycles 74710628Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_latency::cpu.inst 328589993689 # number of overall miss cycles 74810628Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_latency::total 328589993689 # number of overall miss cycles 74910628Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::cpu.inst 455613373 # number of ReadReq accesses(hits+misses) 75010628Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::total 455613373 # number of ReadReq accesses(hits+misses) 75110628Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::cpu.inst 455613373 # number of demand (read+write) accesses 75210628Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::total 455613373 # number of demand (read+write) accesses 75310628Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::cpu.inst 455613373 # number of overall (read+write) accesses 75410628Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::total 455613373 # number of overall (read+write) accesses 75510628Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.054271 # miss rate for ReadReq accesses 75610628Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_rate::total 0.054271 # miss rate for ReadReq accesses 75710628Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_rate::cpu.inst 0.054271 # miss rate for demand accesses 75810628Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_rate::total 0.054271 # miss rate for demand accesses 75910628Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_rate::cpu.inst 0.054271 # miss rate for overall accesses 76010628Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_rate::total 0.054271 # miss rate for overall accesses 76110628Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13288.974753 # average ReadReq miss latency 76210628Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::total 13288.974753 # average ReadReq miss latency 76310628Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_miss_latency::cpu.inst 13288.974753 # average overall miss latency 76410628Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_miss_latency::total 13288.974753 # average overall miss latency 76510628Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_miss_latency::cpu.inst 13288.974753 # average overall miss latency 76610628Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_miss_latency::total 13288.974753 # average overall miss latency 76710585Sandreas.hansson@arm.comsystem.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 76810585Sandreas.hansson@arm.comsystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 76910585Sandreas.hansson@arm.comsystem.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 77010585Sandreas.hansson@arm.comsystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 77110585Sandreas.hansson@arm.comsystem.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 77210585Sandreas.hansson@arm.comsystem.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 77310585Sandreas.hansson@arm.comsystem.cpu.icache.fast_writes 0 # number of fast writes performed 77410585Sandreas.hansson@arm.comsystem.cpu.icache.cache_copies 0 # number of cache copies performed 77510628Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_misses::cpu.inst 24726512 # number of ReadReq MSHR misses 77610628Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_misses::total 24726512 # number of ReadReq MSHR misses 77710628Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_misses::cpu.inst 24726512 # number of demand (read+write) MSHR misses 77810628Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_misses::total 24726512 # number of demand (read+write) MSHR misses 77910628Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_misses::cpu.inst 24726512 # number of overall MSHR misses 78010628Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_misses::total 24726512 # number of overall MSHR misses 78110628Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 279088621775 # number of ReadReq MSHR miss cycles 78210628Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::total 279088621775 # number of ReadReq MSHR miss cycles 78310628Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_latency::cpu.inst 279088621775 # number of demand (read+write) MSHR miss cycles 78410628Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_latency::total 279088621775 # number of demand (read+write) MSHR miss cycles 78510628Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_latency::cpu.inst 279088621775 # number of overall MSHR miss cycles 78610628Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_latency::total 279088621775 # number of overall MSHR miss cycles 78710585Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 3812277750 # number of ReadReq MSHR uncacheable cycles 78810585Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_uncacheable_latency::total 3812277750 # number of ReadReq MSHR uncacheable cycles 78910585Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 3812277750 # number of overall MSHR uncacheable cycles 79010585Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_uncacheable_latency::total 3812277750 # number of overall MSHR uncacheable cycles 79110628Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.054271 # mshr miss rate for ReadReq accesses 79210628Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::total 0.054271 # mshr miss rate for ReadReq accesses 79310628Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.054271 # mshr miss rate for demand accesses 79410628Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_rate::total 0.054271 # mshr miss rate for demand accesses 79510628Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.054271 # mshr miss rate for overall accesses 79610628Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_rate::total 0.054271 # mshr miss rate for overall accesses 79710628Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11287.019446 # average ReadReq mshr miss latency 79810628Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11287.019446 # average ReadReq mshr miss latency 79910628Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11287.019446 # average overall mshr miss latency 80010628Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::total 11287.019446 # average overall mshr miss latency 80110628Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11287.019446 # average overall mshr miss latency 80210628Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::total 11287.019446 # average overall mshr miss latency 80310585Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 80410585Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 80510585Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 80610585Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 80710585Sandreas.hansson@arm.comsystem.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 80810628Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.replacements 1618545 # number of replacements 80910628Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.tagsinuse 65358.053127 # Cycle average of tags in use 81010628Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.total_refs 40402502 # Total number of references to valid blocks. 81110628Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.sampled_refs 1681764 # Sample count of references to valid blocks. 81210628Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.avg_refs 24.023883 # Average number of references to valid blocks. 81310585Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.warmup_cycle 5745484000 # Cycle when the warmup percentage was hit. 81410628Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::writebacks 36067.634498 # Average occupied blocks per requestor 81510628Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 340.939586 # Average occupied blocks per requestor 81610628Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 425.072148 # Average occupied blocks per requestor 81710628Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.inst 28524.406895 # Average occupied blocks per requestor 81810628Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::writebacks 0.550348 # Average percentage of cache occupancy 81910628Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.005202 # Average percentage of cache occupancy 82010628Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.006486 # Average percentage of cache occupancy 82110628Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.inst 0.435248 # Average percentage of cache occupancy 82210628Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::total 0.997285 # Average percentage of cache occupancy 82310628Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_task_id_blocks::1023 346 # Occupied blocks per task id 82410628Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_task_id_blocks::1024 62873 # Occupied blocks per task id 82510628Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1023::4 346 # Occupied blocks per task id 82610628Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id 82710628Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::1 513 # Occupied blocks per task id 82810628Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::2 2402 # Occupied blocks per task id 82910628Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::3 5577 # Occupied blocks per task id 83010628Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::4 54331 # Occupied blocks per task id 83110628Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_task_id_percent::1023 0.005280 # Percentage of cache occupancy per task id 83210628Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_task_id_percent::1024 0.959366 # Percentage of cache occupancy per task id 83310628Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.tag_accesses 371551924 # Number of tag accesses 83410628Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.data_accesses 371551924 # Number of data accesses 83510628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 967297 # number of ReadReq hits 83610628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_hits::cpu.itb.walker 281175 # number of ReadReq hits 83710628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_hits::cpu.inst 31858848 # number of ReadReq hits 83810628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_hits::total 33107320 # number of ReadReq hits 83910628Sandreas.hansson@arm.comsystem.cpu.l2cache.Writeback_hits::writebacks 8593512 # number of Writeback hits 84010628Sandreas.hansson@arm.comsystem.cpu.l2cache.Writeback_hits::total 8593512 # number of Writeback hits 84110628Sandreas.hansson@arm.comsystem.cpu.l2cache.WriteInvalidateReq_hits::cpu.inst 704117 # number of WriteInvalidateReq hits 84210628Sandreas.hansson@arm.comsystem.cpu.l2cache.WriteInvalidateReq_hits::total 704117 # number of WriteInvalidateReq hits 84310628Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_hits::cpu.inst 10834 # number of UpgradeReq hits 84410628Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_hits::total 10834 # number of UpgradeReq hits 84510628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_hits::cpu.inst 1670528 # number of ReadExReq hits 84610628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_hits::total 1670528 # number of ReadExReq hits 84710628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.dtb.walker 967297 # number of demand (read+write) hits 84810628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.itb.walker 281175 # number of demand (read+write) hits 84910628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.inst 33529376 # number of demand (read+write) hits 85010628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::total 34777848 # number of demand (read+write) hits 85110628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.dtb.walker 967297 # number of overall hits 85210628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.itb.walker 281175 # number of overall hits 85310628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.inst 33529376 # number of overall hits 85410628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::total 34777848 # number of overall hits 85510628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 6169 # number of ReadReq misses 85610628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5233 # number of ReadReq misses 85710628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::cpu.inst 442678 # number of ReadReq misses 85810628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::total 454080 # number of ReadReq misses 85910628Sandreas.hansson@arm.comsystem.cpu.l2cache.WriteInvalidateReq_misses::cpu.inst 540744 # number of WriteInvalidateReq misses 86010628Sandreas.hansson@arm.comsystem.cpu.l2cache.WriteInvalidateReq_misses::total 540744 # number of WriteInvalidateReq misses 86110628Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_misses::cpu.inst 38969 # number of UpgradeReq misses 86210628Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_misses::total 38969 # number of UpgradeReq misses 86310585Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_misses::cpu.inst 2 # number of SCUpgradeReq misses 86410585Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses 86510628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_misses::cpu.inst 719318 # number of ReadExReq misses 86610628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_misses::total 719318 # number of ReadExReq misses 86710628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.dtb.walker 6169 # number of demand (read+write) misses 86810628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.itb.walker 5233 # number of demand (read+write) misses 86910628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.inst 1161996 # number of demand (read+write) misses 87010628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::total 1173398 # number of demand (read+write) misses 87110628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.dtb.walker 6169 # number of overall misses 87210628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.itb.walker 5233 # number of overall misses 87310628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.inst 1161996 # number of overall misses 87410628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::total 1173398 # number of overall misses 87510628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 490563500 # number of ReadReq miss cycles 87610628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 420808500 # number of ReadReq miss cycles 87710628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.inst 33361514961 # number of ReadReq miss cycles 87810628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::total 34272886961 # number of ReadReq miss cycles 87910628Sandreas.hansson@arm.comsystem.cpu.l2cache.WriteInvalidateReq_miss_latency::cpu.inst 4498807 # number of WriteInvalidateReq miss cycles 88010628Sandreas.hansson@arm.comsystem.cpu.l2cache.WriteInvalidateReq_miss_latency::total 4498807 # number of WriteInvalidateReq miss cycles 88110628Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_miss_latency::cpu.inst 431949947 # number of UpgradeReq miss cycles 88210628Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_miss_latency::total 431949947 # number of UpgradeReq miss cycles 88310585Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.inst 144500 # number of SCUpgradeReq miss cycles 88410585Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_miss_latency::total 144500 # number of SCUpgradeReq miss cycles 88510628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 53534470118 # number of ReadExReq miss cycles 88610628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::total 53534470118 # number of ReadExReq miss cycles 88710628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 490563500 # number of demand (read+write) miss cycles 88810628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.itb.walker 420808500 # number of demand (read+write) miss cycles 88910628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.inst 86895985079 # number of demand (read+write) miss cycles 89010628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::total 87807357079 # number of demand (read+write) miss cycles 89110628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 490563500 # number of overall miss cycles 89210628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.itb.walker 420808500 # number of overall miss cycles 89310628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.inst 86895985079 # number of overall miss cycles 89410628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::total 87807357079 # number of overall miss cycles 89510628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 973466 # number of ReadReq accesses(hits+misses) 89610628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 286408 # number of ReadReq accesses(hits+misses) 89710628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::cpu.inst 32301526 # number of ReadReq accesses(hits+misses) 89810628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::total 33561400 # number of ReadReq accesses(hits+misses) 89910628Sandreas.hansson@arm.comsystem.cpu.l2cache.Writeback_accesses::writebacks 8593512 # number of Writeback accesses(hits+misses) 90010628Sandreas.hansson@arm.comsystem.cpu.l2cache.Writeback_accesses::total 8593512 # number of Writeback accesses(hits+misses) 90110628Sandreas.hansson@arm.comsystem.cpu.l2cache.WriteInvalidateReq_accesses::cpu.inst 1244861 # number of WriteInvalidateReq accesses(hits+misses) 90210628Sandreas.hansson@arm.comsystem.cpu.l2cache.WriteInvalidateReq_accesses::total 1244861 # number of WriteInvalidateReq accesses(hits+misses) 90310628Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_accesses::cpu.inst 49803 # number of UpgradeReq accesses(hits+misses) 90410628Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_accesses::total 49803 # number of UpgradeReq accesses(hits+misses) 90510585Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_accesses::cpu.inst 2 # number of SCUpgradeReq accesses(hits+misses) 90610585Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) 90710628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.inst 2389846 # number of ReadExReq accesses(hits+misses) 90810628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_accesses::total 2389846 # number of ReadExReq accesses(hits+misses) 90910628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.dtb.walker 973466 # number of demand (read+write) accesses 91010628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.itb.walker 286408 # number of demand (read+write) accesses 91110628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.inst 34691372 # number of demand (read+write) accesses 91210628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::total 35951246 # number of demand (read+write) accesses 91310628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.dtb.walker 973466 # number of overall (read+write) accesses 91410628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.itb.walker 286408 # number of overall (read+write) accesses 91510628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.inst 34691372 # number of overall (read+write) accesses 91610628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::total 35951246 # number of overall (read+write) accesses 91710628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.006337 # miss rate for ReadReq accesses 91810628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.018271 # miss rate for ReadReq accesses 91910628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.013705 # miss rate for ReadReq accesses 92010628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::total 0.013530 # miss rate for ReadReq accesses 92110628Sandreas.hansson@arm.comsystem.cpu.l2cache.WriteInvalidateReq_miss_rate::cpu.inst 0.434381 # miss rate for WriteInvalidateReq accesses 92210628Sandreas.hansson@arm.comsystem.cpu.l2cache.WriteInvalidateReq_miss_rate::total 0.434381 # miss rate for WriteInvalidateReq accesses 92310628Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_miss_rate::cpu.inst 0.782463 # miss rate for UpgradeReq accesses 92410628Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_miss_rate::total 0.782463 # miss rate for UpgradeReq accesses 92510585Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.inst 1 # miss rate for SCUpgradeReq accesses 92610585Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 92710628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.300989 # miss rate for ReadExReq accesses 92810628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::total 0.300989 # miss rate for ReadExReq accesses 92910628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.006337 # miss rate for demand accesses 93010628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.018271 # miss rate for demand accesses 93110628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.033495 # miss rate for demand accesses 93210628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::total 0.032639 # miss rate for demand accesses 93310628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.006337 # miss rate for overall accesses 93410628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.018271 # miss rate for overall accesses 93510628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.033495 # miss rate for overall accesses 93610628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::total 0.032639 # miss rate for overall accesses 93710628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 79520.748906 # average ReadReq miss latency 93810628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 80414.389452 # average ReadReq miss latency 93910628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 75362.938662 # average ReadReq miss latency 94010628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::total 75477.640418 # average ReadReq miss latency 94110628Sandreas.hansson@arm.comsystem.cpu.l2cache.WriteInvalidateReq_avg_miss_latency::cpu.inst 8.319661 # average WriteInvalidateReq miss latency 94210628Sandreas.hansson@arm.comsystem.cpu.l2cache.WriteInvalidateReq_avg_miss_latency::total 8.319661 # average WriteInvalidateReq miss latency 94310628Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.inst 11084.450384 # average UpgradeReq miss latency 94410628Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_avg_miss_latency::total 11084.450384 # average UpgradeReq miss latency 94510585Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.inst 72250 # average SCUpgradeReq miss latency 94610585Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 72250 # average SCUpgradeReq miss latency 94710628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 74423.926717 # average ReadExReq miss latency 94810628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::total 74423.926717 # average ReadExReq miss latency 94910628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 79520.748906 # average overall miss latency 95010628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 80414.389452 # average overall miss latency 95110628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74781.655943 # average overall miss latency 95210628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::total 74831.691446 # average overall miss latency 95310628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 79520.748906 # average overall miss latency 95410628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 80414.389452 # average overall miss latency 95510628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74781.655943 # average overall miss latency 95610628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::total 74831.691446 # average overall miss latency 95710585Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 95810585Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 95910585Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 96010585Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 96110585Sandreas.hansson@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 96210585Sandreas.hansson@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 96310585Sandreas.hansson@arm.comsystem.cpu.l2cache.fast_writes 0 # number of fast writes performed 96410585Sandreas.hansson@arm.comsystem.cpu.l2cache.cache_copies 0 # number of cache copies performed 96510628Sandreas.hansson@arm.comsystem.cpu.l2cache.writebacks::writebacks 1379367 # number of writebacks 96610628Sandreas.hansson@arm.comsystem.cpu.l2cache.writebacks::total 1379367 # number of writebacks 96710628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 22 # number of ReadReq MSHR hits 96810628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_hits::total 22 # number of ReadReq MSHR hits 96910628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_hits::cpu.inst 22 # number of demand (read+write) MSHR hits 97010628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_hits::total 22 # number of demand (read+write) MSHR hits 97110628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_hits::cpu.inst 22 # number of overall MSHR hits 97210628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_hits::total 22 # number of overall MSHR hits 97310628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 6169 # number of ReadReq MSHR misses 97410628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 5233 # number of ReadReq MSHR misses 97510628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 442656 # number of ReadReq MSHR misses 97610628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::total 454058 # number of ReadReq MSHR misses 97710628Sandreas.hansson@arm.comsystem.cpu.l2cache.WriteInvalidateReq_mshr_misses::cpu.inst 540744 # number of WriteInvalidateReq MSHR misses 97810628Sandreas.hansson@arm.comsystem.cpu.l2cache.WriteInvalidateReq_mshr_misses::total 540744 # number of WriteInvalidateReq MSHR misses 97910628Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_misses::cpu.inst 38969 # number of UpgradeReq MSHR misses 98010628Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_misses::total 38969 # number of UpgradeReq MSHR misses 98110585Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.inst 2 # number of SCUpgradeReq MSHR misses 98210585Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses 98310628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 719318 # number of ReadExReq MSHR misses 98410628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_misses::total 719318 # number of ReadExReq MSHR misses 98510628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 6169 # number of demand (read+write) MSHR misses 98610628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 5233 # number of demand (read+write) MSHR misses 98710628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.inst 1161974 # number of demand (read+write) MSHR misses 98810628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::total 1173376 # number of demand (read+write) MSHR misses 98910628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 6169 # number of overall MSHR misses 99010628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 5233 # number of overall MSHR misses 99110628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.inst 1161974 # number of overall MSHR misses 99210628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::total 1173376 # number of overall MSHR misses 99310628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 413632000 # number of ReadReq MSHR miss cycles 99410628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 355518000 # number of ReadReq MSHR miss cycles 99510628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 27784615785 # number of ReadReq MSHR miss cycles 99610628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::total 28553765785 # number of ReadReq MSHR miss cycles 99710628Sandreas.hansson@arm.comsystem.cpu.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu.inst 12667521943 # number of WriteInvalidateReq MSHR miss cycles 99810628Sandreas.hansson@arm.comsystem.cpu.l2cache.WriteInvalidateReq_mshr_miss_latency::total 12667521943 # number of WriteInvalidateReq MSHR miss cycles 99910628Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.inst 390061961 # number of UpgradeReq MSHR miss cycles 100010628Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 390061961 # number of UpgradeReq MSHR miss cycles 100110585Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.inst 120500 # number of SCUpgradeReq MSHR miss cycles 100210585Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 120500 # number of SCUpgradeReq MSHR miss cycles 100310628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 44297743880 # number of ReadExReq MSHR miss cycles 100410628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::total 44297743880 # number of ReadExReq MSHR miss cycles 100510628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 413632000 # number of demand (read+write) MSHR miss cycles 100610628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 355518000 # number of demand (read+write) MSHR miss cycles 100710628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 72082359665 # number of demand (read+write) MSHR miss cycles 100810628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::total 72851509665 # number of demand (read+write) MSHR miss cycles 100910628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 413632000 # number of overall MSHR miss cycles 101010628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 355518000 # number of overall MSHR miss cycles 101110628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 72082359665 # number of overall MSHR miss cycles 101210628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::total 72851509665 # number of overall MSHR miss cycles 101310628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 8006368251 # number of ReadReq MSHR uncacheable cycles 101410628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 8006368251 # number of ReadReq MSHR uncacheable cycles 101510628Sandreas.hansson@arm.comsystem.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.inst 5177591000 # number of WriteReq MSHR uncacheable cycles 101610628Sandreas.hansson@arm.comsystem.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 5177591000 # number of WriteReq MSHR uncacheable cycles 101710628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 13183959251 # number of overall MSHR uncacheable cycles 101810628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_uncacheable_latency::total 13183959251 # number of overall MSHR uncacheable cycles 101910628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.006337 # mshr miss rate for ReadReq accesses 102010628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.018271 # mshr miss rate for ReadReq accesses 102110628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.013704 # mshr miss rate for ReadReq accesses 102210628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.013529 # mshr miss rate for ReadReq accesses 102310628Sandreas.hansson@arm.comsystem.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu.inst 0.434381 # mshr miss rate for WriteInvalidateReq accesses 102410628Sandreas.hansson@arm.comsystem.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.434381 # mshr miss rate for WriteInvalidateReq accesses 102510628Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.inst 0.782463 # mshr miss rate for UpgradeReq accesses 102610628Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.782463 # mshr miss rate for UpgradeReq accesses 102710585Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for SCUpgradeReq accesses 102810585Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 102910628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.300989 # mshr miss rate for ReadExReq accesses 103010628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.300989 # mshr miss rate for ReadExReq accesses 103110628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.006337 # mshr miss rate for demand accesses 103210628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.018271 # mshr miss rate for demand accesses 103310628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.033495 # mshr miss rate for demand accesses 103410628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::total 0.032638 # mshr miss rate for demand accesses 103510628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.006337 # mshr miss rate for overall accesses 103610628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.018271 # mshr miss rate for overall accesses 103710628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.033495 # mshr miss rate for overall accesses 103810628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::total 0.032638 # mshr miss rate for overall accesses 103910628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 67050.089155 # average ReadReq mshr miss latency 104010628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 67937.703038 # average ReadReq mshr miss latency 104110628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62767.963803 # average ReadReq mshr miss latency 104210628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62885.723377 # average ReadReq mshr miss latency 104310628Sandreas.hansson@arm.comsystem.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.inst 23426.098011 # average WriteInvalidateReq mshr miss latency 104410628Sandreas.hansson@arm.comsystem.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 23426.098011 # average WriteInvalidateReq mshr miss latency 104510628Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.inst 10009.545049 # average UpgradeReq mshr miss latency 104610628Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10009.545049 # average UpgradeReq mshr miss latency 104710585Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.inst 60250 # average SCUpgradeReq mshr miss latency 104810585Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 60250 # average SCUpgradeReq mshr miss latency 104910628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 61582.977042 # average ReadExReq mshr miss latency 105010628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61582.977042 # average ReadExReq mshr miss latency 105110628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 67050.089155 # average overall mshr miss latency 105210628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 67937.703038 # average overall mshr miss latency 105310628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62034.399793 # average overall mshr miss latency 105410628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::total 62087.097116 # average overall mshr miss latency 105510628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 67050.089155 # average overall mshr miss latency 105610628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 67937.703038 # average overall mshr miss latency 105710628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62034.399793 # average overall mshr miss latency 105810628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::total 62087.097116 # average overall mshr miss latency 105910585Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 106010585Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 106110585Sandreas.hansson@arm.comsystem.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst inf # average WriteReq mshr uncacheable latency 106210585Sandreas.hansson@arm.comsystem.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 106310585Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 106410585Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 106510585Sandreas.hansson@arm.comsystem.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 106610628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadReq 34111380 # Transaction distribution 106710628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadResp 34103268 # Transaction distribution 106810628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::WriteReq 33870 # Transaction distribution 106910628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::WriteResp 33870 # Transaction distribution 107010628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::Writeback 8593512 # Transaction distribution 107110628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::WriteInvalidateReq 1351525 # Transaction distribution 107210628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::WriteInvalidateResp 1244861 # Transaction distribution 107310628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::UpgradeReq 49806 # Transaction distribution 107410585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution 107510628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::UpgradeResp 49808 # Transaction distribution 107610628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExReq 2389846 # Transaction distribution 107710628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExResp 2389846 # Transaction distribution 107810628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 49557548 # Packet count per connected master and slave (bytes) 107910628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 31248640 # Packet count per connected master and slave (bytes) 108010628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 695589 # Packet count per connected master and slave (bytes) 108110628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2279215 # Packet count per connected master and slave (bytes) 108210628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count::total 83780992 # Packet count per connected master and slave (bytes) 108310628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1585841408 # Cumulative packet size per connected master and slave (bytes) 108410628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1267646988 # Cumulative packet size per connected master and slave (bytes) 108510628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2291264 # Cumulative packet size per connected master and slave (bytes) 108610628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 7787728 # Cumulative packet size per connected master and slave (bytes) 108710628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size::total 2863567388 # Cumulative packet size per connected master and slave (bytes) 108810628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoops 571370 # Total snoops (count) 108910628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::samples 46410026 # Request fanout histogram 109010628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::mean 5.002490 # Request fanout histogram 109110628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::stdev 0.049834 # Request fanout histogram 109210585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 109310585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 109410585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 109510585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 109610585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 109710585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 109810628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::5 46294483 99.75% 99.75% # Request fanout histogram 109910628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::6 115543 0.25% 100.00% # Request fanout histogram 110010585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 110110585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 110210585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram 110310628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::total 46410026 # Request fanout histogram 110410628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.reqLayer0.occupancy 33063458385 # Layer occupancy (ticks) 110510585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 110610628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoopLayer0.occupancy 1149000 # Layer occupancy (ticks) 110710585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 110810628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer0.occupancy 37204558207 # Layer occupancy (ticks) 110910585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 111010628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer1.occupancy 15864083234 # Layer occupancy (ticks) 111110585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 111210628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer2.occupancy 409855669 # Layer occupancy (ticks) 111310585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 111410628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer3.occupancy 1306481232 # Layer occupancy (ticks) 111510585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 111610628Sandreas.hansson@arm.comsystem.iobus.trans_dist::ReadReq 40405 # Transaction distribution 111710628Sandreas.hansson@arm.comsystem.iobus.trans_dist::ReadResp 40405 # Transaction distribution 111810585Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteReq 136733 # Transaction distribution 111910585Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteResp 30069 # Transaction distribution 112010585Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteInvalidateResp 106664 # Transaction distribution 112110585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 48308 # Packet count per connected master and slave (bytes) 112210585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 112310585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) 112410585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) 112510585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 112610585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 112710585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 112810585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 112910585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) 113010585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 113110585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) 113210585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) 113310585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) 113410585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) 113510585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) 113610585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::total 123190 # Packet count per connected master and slave (bytes) 113710628Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231006 # Packet count per connected master and slave (bytes) 113810628Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.realview.ide.dma::total 231006 # Packet count per connected master and slave (bytes) 113910585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) 114010585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) 114110628Sandreas.hansson@arm.comsystem.iobus.pkt_count::total 354276 # Packet count per connected master and slave (bytes) 114210585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48328 # Cumulative packet size per connected master and slave (bytes) 114310585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) 114410585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) 114510585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) 114610585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 114710585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 114810585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 114910585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 115010585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) 115110585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 115210585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) 115310585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes) 115410585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) 115510585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) 115610585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) 115710585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::total 156320 # Cumulative packet size per connected master and slave (bytes) 115810628Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334456 # Cumulative packet size per connected master and slave (bytes) 115910628Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.realview.ide.dma::total 7334456 # Cumulative packet size per connected master and slave (bytes) 116010585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 116110585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) 116210628Sandreas.hansson@arm.comsystem.iobus.pkt_size::total 7492862 # Cumulative packet size per connected master and slave (bytes) 116310585Sandreas.hansson@arm.comsystem.iobus.reqLayer0.occupancy 36706000 # Layer occupancy (ticks) 116410585Sandreas.hansson@arm.comsystem.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 116510585Sandreas.hansson@arm.comsystem.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) 116610585Sandreas.hansson@arm.comsystem.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 116710585Sandreas.hansson@arm.comsystem.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks) 116810585Sandreas.hansson@arm.comsystem.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 116910585Sandreas.hansson@arm.comsystem.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks) 117010585Sandreas.hansson@arm.comsystem.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 117110585Sandreas.hansson@arm.comsystem.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) 117210585Sandreas.hansson@arm.comsystem.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 117310585Sandreas.hansson@arm.comsystem.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) 117410585Sandreas.hansson@arm.comsystem.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 117510585Sandreas.hansson@arm.comsystem.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) 117610585Sandreas.hansson@arm.comsystem.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 117710585Sandreas.hansson@arm.comsystem.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) 117810585Sandreas.hansson@arm.comsystem.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 117910585Sandreas.hansson@arm.comsystem.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks) 118010585Sandreas.hansson@arm.comsystem.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 118110585Sandreas.hansson@arm.comsystem.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) 118210585Sandreas.hansson@arm.comsystem.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 118310585Sandreas.hansson@arm.comsystem.iobus.reqLayer23.occupancy 21947000 # Layer occupancy (ticks) 118410585Sandreas.hansson@arm.comsystem.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 118510585Sandreas.hansson@arm.comsystem.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks) 118610585Sandreas.hansson@arm.comsystem.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 118710585Sandreas.hansson@arm.comsystem.iobus.reqLayer25.occupancy 32658000 # Layer occupancy (ticks) 118810585Sandreas.hansson@arm.comsystem.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 118910585Sandreas.hansson@arm.comsystem.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) 119010585Sandreas.hansson@arm.comsystem.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 119110628Sandreas.hansson@arm.comsystem.iobus.reqLayer27.occupancy 1042384689 # Layer occupancy (ticks) 119210585Sandreas.hansson@arm.comsystem.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 119310585Sandreas.hansson@arm.comsystem.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) 119410585Sandreas.hansson@arm.comsystem.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) 119510585Sandreas.hansson@arm.comsystem.iobus.respLayer0.occupancy 93124000 # Layer occupancy (ticks) 119610585Sandreas.hansson@arm.comsystem.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 119710628Sandreas.hansson@arm.comsystem.iobus.respLayer3.occupancy 179052263 # Layer occupancy (ticks) 119810585Sandreas.hansson@arm.comsystem.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 119910585Sandreas.hansson@arm.comsystem.iobus.respLayer4.occupancy 297000 # Layer occupancy (ticks) 120010585Sandreas.hansson@arm.comsystem.iobus.respLayer4.utilization 0.0 # Layer utilization (%) 120110628Sandreas.hansson@arm.comsystem.iocache.tags.replacements 115484 # number of replacements 120210628Sandreas.hansson@arm.comsystem.iocache.tags.tagsinuse 10.452585 # Cycle average of tags in use 120310585Sandreas.hansson@arm.comsystem.iocache.tags.total_refs 3 # Total number of references to valid blocks. 120410628Sandreas.hansson@arm.comsystem.iocache.tags.sampled_refs 115500 # Sample count of references to valid blocks. 120510585Sandreas.hansson@arm.comsystem.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. 120610628Sandreas.hansson@arm.comsystem.iocache.tags.warmup_cycle 13141230176000 # Cycle when the warmup percentage was hit. 120710628Sandreas.hansson@arm.comsystem.iocache.tags.occ_blocks::realview.ethernet 3.516704 # Average occupied blocks per requestor 120810628Sandreas.hansson@arm.comsystem.iocache.tags.occ_blocks::realview.ide 6.935881 # Average occupied blocks per requestor 120910628Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::realview.ethernet 0.219794 # Average percentage of cache occupancy 121010628Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::realview.ide 0.433493 # Average percentage of cache occupancy 121110628Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::total 0.653287 # Average percentage of cache occupancy 121210585Sandreas.hansson@arm.comsystem.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 121310585Sandreas.hansson@arm.comsystem.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 121410585Sandreas.hansson@arm.comsystem.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 121510628Sandreas.hansson@arm.comsystem.iocache.tags.tag_accesses 1039884 # Number of tag accesses 121610628Sandreas.hansson@arm.comsystem.iocache.tags.data_accesses 1039884 # Number of data accesses 121710585Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses 121810628Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::realview.ide 8839 # number of ReadReq misses 121910628Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::total 8876 # number of ReadReq misses 122010585Sandreas.hansson@arm.comsystem.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 122110585Sandreas.hansson@arm.comsystem.iocache.WriteReq_misses::total 3 # number of WriteReq misses 122210585Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_misses::realview.ide 106664 # number of WriteInvalidateReq misses 122310585Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_misses::total 106664 # number of WriteInvalidateReq misses 122410585Sandreas.hansson@arm.comsystem.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses 122510628Sandreas.hansson@arm.comsystem.iocache.demand_misses::realview.ide 8839 # number of demand (read+write) misses 122610628Sandreas.hansson@arm.comsystem.iocache.demand_misses::total 8879 # number of demand (read+write) misses 122710585Sandreas.hansson@arm.comsystem.iocache.overall_misses::realview.ethernet 40 # number of overall misses 122810628Sandreas.hansson@arm.comsystem.iocache.overall_misses::realview.ide 8839 # number of overall misses 122910628Sandreas.hansson@arm.comsystem.iocache.overall_misses::total 8879 # number of overall misses 123010585Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_latency::realview.ethernet 5485000 # number of ReadReq miss cycles 123110628Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_latency::realview.ide 1924538358 # number of ReadReq miss cycles 123210628Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_latency::total 1930023358 # number of ReadReq miss cycles 123310585Sandreas.hansson@arm.comsystem.iocache.WriteReq_miss_latency::realview.ethernet 339000 # number of WriteReq miss cycles 123410585Sandreas.hansson@arm.comsystem.iocache.WriteReq_miss_latency::total 339000 # number of WriteReq miss cycles 123510628Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_miss_latency::realview.ide 28851084068 # number of WriteInvalidateReq miss cycles 123610628Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_miss_latency::total 28851084068 # number of WriteInvalidateReq miss cycles 123710585Sandreas.hansson@arm.comsystem.iocache.demand_miss_latency::realview.ethernet 5824000 # number of demand (read+write) miss cycles 123810628Sandreas.hansson@arm.comsystem.iocache.demand_miss_latency::realview.ide 1924538358 # number of demand (read+write) miss cycles 123910628Sandreas.hansson@arm.comsystem.iocache.demand_miss_latency::total 1930362358 # number of demand (read+write) miss cycles 124010585Sandreas.hansson@arm.comsystem.iocache.overall_miss_latency::realview.ethernet 5824000 # number of overall miss cycles 124110628Sandreas.hansson@arm.comsystem.iocache.overall_miss_latency::realview.ide 1924538358 # number of overall miss cycles 124210628Sandreas.hansson@arm.comsystem.iocache.overall_miss_latency::total 1930362358 # number of overall miss cycles 124310585Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) 124410628Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::realview.ide 8839 # number of ReadReq accesses(hits+misses) 124510628Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::total 8876 # number of ReadReq accesses(hits+misses) 124610585Sandreas.hansson@arm.comsystem.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 124710585Sandreas.hansson@arm.comsystem.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 124810585Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_accesses::realview.ide 106664 # number of WriteInvalidateReq accesses(hits+misses) 124910585Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_accesses::total 106664 # number of WriteInvalidateReq accesses(hits+misses) 125010585Sandreas.hansson@arm.comsystem.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses 125110628Sandreas.hansson@arm.comsystem.iocache.demand_accesses::realview.ide 8839 # number of demand (read+write) accesses 125210628Sandreas.hansson@arm.comsystem.iocache.demand_accesses::total 8879 # number of demand (read+write) accesses 125310585Sandreas.hansson@arm.comsystem.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses 125410628Sandreas.hansson@arm.comsystem.iocache.overall_accesses::realview.ide 8839 # number of overall (read+write) accesses 125510628Sandreas.hansson@arm.comsystem.iocache.overall_accesses::total 8879 # number of overall (read+write) accesses 125610585Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 125710585Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 125810585Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 125910585Sandreas.hansson@arm.comsystem.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 126010585Sandreas.hansson@arm.comsystem.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 126110585Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses 126210585Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses 126310585Sandreas.hansson@arm.comsystem.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses 126410585Sandreas.hansson@arm.comsystem.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 126510585Sandreas.hansson@arm.comsystem.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 126610585Sandreas.hansson@arm.comsystem.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses 126710585Sandreas.hansson@arm.comsystem.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 126810585Sandreas.hansson@arm.comsystem.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 126910585Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_miss_latency::realview.ethernet 148243.243243 # average ReadReq miss latency 127010628Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_miss_latency::realview.ide 217732.589433 # average ReadReq miss latency 127110628Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_miss_latency::total 217442.920009 # average ReadReq miss latency 127210585Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_miss_latency::realview.ethernet 113000 # average WriteReq miss latency 127310585Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_miss_latency::total 113000 # average WriteReq miss latency 127410628Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 270485.675279 # average WriteInvalidateReq miss latency 127510628Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_avg_miss_latency::total 270485.675279 # average WriteInvalidateReq miss latency 127610585Sandreas.hansson@arm.comsystem.iocache.demand_avg_miss_latency::realview.ethernet 145600 # average overall miss latency 127710628Sandreas.hansson@arm.comsystem.iocache.demand_avg_miss_latency::realview.ide 217732.589433 # average overall miss latency 127810628Sandreas.hansson@arm.comsystem.iocache.demand_avg_miss_latency::total 217407.631265 # average overall miss latency 127910585Sandreas.hansson@arm.comsystem.iocache.overall_avg_miss_latency::realview.ethernet 145600 # average overall miss latency 128010628Sandreas.hansson@arm.comsystem.iocache.overall_avg_miss_latency::realview.ide 217732.589433 # average overall miss latency 128110628Sandreas.hansson@arm.comsystem.iocache.overall_avg_miss_latency::total 217407.631265 # average overall miss latency 128210628Sandreas.hansson@arm.comsystem.iocache.blocked_cycles::no_mshrs 225366 # number of cycles access was blocked 128310585Sandreas.hansson@arm.comsystem.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 128410628Sandreas.hansson@arm.comsystem.iocache.blocked::no_mshrs 27560 # number of cycles access was blocked 128510585Sandreas.hansson@arm.comsystem.iocache.blocked::no_targets 0 # number of cycles access was blocked 128610628Sandreas.hansson@arm.comsystem.iocache.avg_blocked_cycles::no_mshrs 8.177286 # average number of cycles each access was blocked 128710585Sandreas.hansson@arm.comsystem.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 128810585Sandreas.hansson@arm.comsystem.iocache.fast_writes 0 # number of fast writes performed 128910585Sandreas.hansson@arm.comsystem.iocache.cache_copies 0 # number of cache copies performed 129010585Sandreas.hansson@arm.comsystem.iocache.writebacks::writebacks 106630 # number of writebacks 129110585Sandreas.hansson@arm.comsystem.iocache.writebacks::total 106630 # number of writebacks 129210585Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses 129310628Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_misses::realview.ide 8839 # number of ReadReq MSHR misses 129410628Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_misses::total 8876 # number of ReadReq MSHR misses 129510585Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses 129610585Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses 129710585Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_mshr_misses::realview.ide 106664 # number of WriteInvalidateReq MSHR misses 129810585Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_mshr_misses::total 106664 # number of WriteInvalidateReq MSHR misses 129910585Sandreas.hansson@arm.comsystem.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses 130010628Sandreas.hansson@arm.comsystem.iocache.demand_mshr_misses::realview.ide 8839 # number of demand (read+write) MSHR misses 130110628Sandreas.hansson@arm.comsystem.iocache.demand_mshr_misses::total 8879 # number of demand (read+write) MSHR misses 130210585Sandreas.hansson@arm.comsystem.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses 130310628Sandreas.hansson@arm.comsystem.iocache.overall_mshr_misses::realview.ide 8839 # number of overall MSHR misses 130410628Sandreas.hansson@arm.comsystem.iocache.overall_mshr_misses::total 8879 # number of overall MSHR misses 130510585Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3561000 # number of ReadReq MSHR miss cycles 130610628Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_latency::realview.ide 1464798862 # number of ReadReq MSHR miss cycles 130710628Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_latency::total 1468359862 # number of ReadReq MSHR miss cycles 130810585Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_miss_latency::realview.ethernet 183000 # number of WriteReq MSHR miss cycles 130910585Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_miss_latency::total 183000 # number of WriteReq MSHR miss cycles 131010628Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 23304534090 # number of WriteInvalidateReq MSHR miss cycles 131110628Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_mshr_miss_latency::total 23304534090 # number of WriteInvalidateReq MSHR miss cycles 131210585Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_latency::realview.ethernet 3744000 # number of demand (read+write) MSHR miss cycles 131310628Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_latency::realview.ide 1464798862 # number of demand (read+write) MSHR miss cycles 131410628Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_latency::total 1468542862 # number of demand (read+write) MSHR miss cycles 131510585Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_latency::realview.ethernet 3744000 # number of overall MSHR miss cycles 131610628Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_latency::realview.ide 1464798862 # number of overall MSHR miss cycles 131710628Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_latency::total 1468542862 # number of overall MSHR miss cycles 131810585Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses 131910585Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 132010585Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 132110585Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses 132210585Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 132310585Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses 132410585Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses 132510585Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses 132610585Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 132710585Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 132810585Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses 132910585Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 133010585Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 133110585Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 96243.243243 # average ReadReq mshr miss latency 133210628Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 165719.975337 # average ReadReq mshr miss latency 133310628Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::total 165430.358495 # average ReadReq mshr miss latency 133410585Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 61000 # average WriteReq mshr miss latency 133510585Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency 133610628Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 218485.469230 # average WriteInvalidateReq mshr miss latency 133710628Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 218485.469230 # average WriteInvalidateReq mshr miss latency 133810585Sandreas.hansson@arm.comsystem.iocache.demand_avg_mshr_miss_latency::realview.ethernet 93600 # average overall mshr miss latency 133910628Sandreas.hansson@arm.comsystem.iocache.demand_avg_mshr_miss_latency::realview.ide 165719.975337 # average overall mshr miss latency 134010628Sandreas.hansson@arm.comsystem.iocache.demand_avg_mshr_miss_latency::total 165395.073995 # average overall mshr miss latency 134110585Sandreas.hansson@arm.comsystem.iocache.overall_avg_mshr_miss_latency::realview.ethernet 93600 # average overall mshr miss latency 134210628Sandreas.hansson@arm.comsystem.iocache.overall_avg_mshr_miss_latency::realview.ide 165719.975337 # average overall mshr miss latency 134310628Sandreas.hansson@arm.comsystem.iocache.overall_avg_mshr_miss_latency::total 165395.073995 # average overall mshr miss latency 134410585Sandreas.hansson@arm.comsystem.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 134510628Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadReq 548979 # Transaction distribution 134610628Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadResp 548979 # Transaction distribution 134710628Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteReq 33870 # Transaction distribution 134810628Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteResp 33870 # Transaction distribution 134910628Sandreas.hansson@arm.comsystem.membus.trans_dist::Writeback 1485997 # Transaction distribution 135010628Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteInvalidateReq 647215 # Transaction distribution 135110628Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteInvalidateResp 647215 # Transaction distribution 135210628Sandreas.hansson@arm.comsystem.membus.trans_dist::UpgradeReq 39795 # Transaction distribution 135310585Sandreas.hansson@arm.comsystem.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution 135410628Sandreas.hansson@arm.comsystem.membus.trans_dist::UpgradeResp 39797 # Transaction distribution 135510628Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExReq 718688 # Transaction distribution 135610628Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExResp 718688 # Transaction distribution 135710515SAli.Saidi@ARM.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 123190 # Packet count per connected master and slave (bytes) 135810515SAli.Saidi@ARM.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 32 # Packet count per connected master and slave (bytes) 135910628Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6926 # Packet count per connected master and slave (bytes) 136010628Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4994566 # Packet count per connected master and slave (bytes) 136110628Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::total 5124714 # Packet count per connected master and slave (bytes) 136210628Sandreas.hansson@arm.comsystem.membus.pkt_count_system.iocache.mem_side::system.physmem.port 335466 # Packet count per connected master and slave (bytes) 136310628Sandreas.hansson@arm.comsystem.membus.pkt_count_system.iocache.mem_side::total 335466 # Packet count per connected master and slave (bytes) 136410628Sandreas.hansson@arm.comsystem.membus.pkt_count::total 5460180 # Packet count per connected master and slave (bytes) 136510515SAli.Saidi@ARM.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 156320 # Cumulative packet size per connected master and slave (bytes) 136610515SAli.Saidi@ARM.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 740 # Cumulative packet size per connected master and slave (bytes) 136710628Sandreas.hansson@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13852 # Cumulative packet size per connected master and slave (bytes) 136810628Sandreas.hansson@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 201253164 # Cumulative packet size per connected master and slave (bytes) 136910628Sandreas.hansson@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::total 201424076 # Cumulative packet size per connected master and slave (bytes) 137010628Sandreas.hansson@arm.comsystem.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14075072 # Cumulative packet size per connected master and slave (bytes) 137110628Sandreas.hansson@arm.comsystem.membus.pkt_size_system.iocache.mem_side::total 14075072 # Cumulative packet size per connected master and slave (bytes) 137210628Sandreas.hansson@arm.comsystem.membus.pkt_size::total 215499148 # Cumulative packet size per connected master and slave (bytes) 137310628Sandreas.hansson@arm.comsystem.membus.snoops 2915 # Total snoops (count) 137410628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::samples 3354632 # Request fanout histogram 137510515SAli.Saidi@ARM.comsystem.membus.snoop_fanout::mean 1 # Request fanout histogram 137610515SAli.Saidi@ARM.comsystem.membus.snoop_fanout::stdev 0 # Request fanout histogram 137710515SAli.Saidi@ARM.comsystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 137810515SAli.Saidi@ARM.comsystem.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 137910628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::1 3354632 100.00% 100.00% # Request fanout histogram 138010515SAli.Saidi@ARM.comsystem.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 138110515SAli.Saidi@ARM.comsystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 138210515SAli.Saidi@ARM.comsystem.membus.snoop_fanout::min_value 1 # Request fanout histogram 138310515SAli.Saidi@ARM.comsystem.membus.snoop_fanout::max_value 1 # Request fanout histogram 138410628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::total 3354632 # Request fanout histogram 138510628Sandreas.hansson@arm.comsystem.membus.reqLayer0.occupancy 113785000 # Layer occupancy (ticks) 138610515SAli.Saidi@ARM.comsystem.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 138710515SAli.Saidi@ARM.comsystem.membus.reqLayer1.occupancy 23328 # Layer occupancy (ticks) 138810515SAli.Saidi@ARM.comsystem.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 138910628Sandreas.hansson@arm.comsystem.membus.reqLayer2.occupancy 5606499 # Layer occupancy (ticks) 139010515SAli.Saidi@ARM.comsystem.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 139110628Sandreas.hansson@arm.comsystem.membus.reqLayer5.occupancy 21358745741 # Layer occupancy (ticks) 139210515SAli.Saidi@ARM.comsystem.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 139310628Sandreas.hansson@arm.comsystem.membus.respLayer2.occupancy 12484485177 # Layer occupancy (ticks) 139410515SAli.Saidi@ARM.comsystem.membus.respLayer2.utilization 0.0 # Layer utilization (%) 139510628Sandreas.hansson@arm.comsystem.membus.respLayer3.occupancy 186617737 # Layer occupancy (ticks) 139610515SAli.Saidi@ARM.comsystem.membus.respLayer3.utilization 0.0 # Layer utilization (%) 139710515SAli.Saidi@ARM.comsystem.realview.ethernet.txBytes 966 # Bytes Transmitted 139810515SAli.Saidi@ARM.comsystem.realview.ethernet.txPackets 3 # Number of Packets Transmitted 139910515SAli.Saidi@ARM.comsystem.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device 140010515SAli.Saidi@ARM.comsystem.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device 140110515SAli.Saidi@ARM.comsystem.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 140210515SAli.Saidi@ARM.comsystem.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 140310515SAli.Saidi@ARM.comsystem.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 140410515SAli.Saidi@ARM.comsystem.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 140510515SAli.Saidi@ARM.comsystem.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 140610628Sandreas.hansson@arm.comsystem.realview.ethernet.totBandwidth 149 # Total Bandwidth (bits/s) 140710515SAli.Saidi@ARM.comsystem.realview.ethernet.totPackets 3 # Total Packets 140810515SAli.Saidi@ARM.comsystem.realview.ethernet.totBytes 966 # Total Bytes 140910515SAli.Saidi@ARM.comsystem.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) 141010628Sandreas.hansson@arm.comsystem.realview.ethernet.txBandwidth 149 # Transmit Bandwidth (bits/s) 141110515SAli.Saidi@ARM.comsystem.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) 141210515SAli.Saidi@ARM.comsystem.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 141310515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post 141410515SAli.Saidi@ARM.comsystem.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 141510515SAli.Saidi@ARM.comsystem.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 141610515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post 141710515SAli.Saidi@ARM.comsystem.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 141810515SAli.Saidi@ARM.comsystem.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 141910515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post 142010515SAli.Saidi@ARM.comsystem.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 142110515SAli.Saidi@ARM.comsystem.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 142210515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post 142310515SAli.Saidi@ARM.comsystem.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 142410515SAli.Saidi@ARM.comsystem.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 142510515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post 142610515SAli.Saidi@ARM.comsystem.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 142710515SAli.Saidi@ARM.comsystem.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 142810515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post 142910515SAli.Saidi@ARM.comsystem.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 143010515SAli.Saidi@ARM.comsystem.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 143110515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 143210515SAli.Saidi@ARM.comsystem.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 143310515SAli.Saidi@ARM.comsystem.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 143410515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 143510515SAli.Saidi@ARM.comsystem.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 143610515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 143710515SAli.Saidi@ARM.comsystem.realview.ethernet.postedInterrupts 13 # number of posts to CPU 143810515SAli.Saidi@ARM.comsystem.realview.ethernet.droppedPackets 0 # number of packets dropped 143910515SAli.Saidi@ARM.com 144010515SAli.Saidi@ARM.com---------- End Simulation Statistics ---------- 1441