stats.txt revision 10628
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 51.728175 # Number of seconds simulated 4sim_ticks 51728174627500 # Number of ticks simulated 5final_tick 51728174627500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 184836 # Simulator instruction rate (inst/s) 8host_op_rate 217188 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 10028441874 # Simulator tick rate (ticks/s) 10host_mem_usage 718288 # Number of bytes of host memory used 11host_seconds 5158.15 # Real time elapsed on the host 12sim_insts 953410832 # Number of instructions simulated 13sim_ops 1120287994 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.dtb.walker 394816 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.itb.walker 334912 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.inst 77628104 # Number of bytes read from this memory 19system.physmem.bytes_read::realview.ide 424256 # Number of bytes read from this memory 20system.physmem.bytes_read::total 78782088 # Number of bytes read from this memory 21system.physmem.bytes_inst_read::cpu.inst 10241472 # Number of instructions bytes read from this memory 22system.physmem.bytes_inst_read::total 10241472 # Number of instructions bytes read from this memory 23system.physmem.bytes_written::writebacks 95103808 # Number of bytes written to this memory 24system.physmem.bytes_written::cpu.inst 20580 # Number of bytes written to this memory 25system.physmem.bytes_written::total 95124388 # Number of bytes written to this memory 26system.physmem.num_reads::cpu.dtb.walker 6169 # Number of read requests responded to by this memory 27system.physmem.num_reads::cpu.itb.walker 5233 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu.inst 1212952 # Number of read requests responded to by this memory 29system.physmem.num_reads::realview.ide 6629 # Number of read requests responded to by this memory 30system.physmem.num_reads::total 1230983 # Number of read requests responded to by this memory 31system.physmem.num_writes::writebacks 1485997 # Number of write requests responded to by this memory 32system.physmem.num_writes::cpu.inst 2573 # Number of write requests responded to by this memory 33system.physmem.num_writes::total 1488570 # Number of write requests responded to by this memory 34system.physmem.bw_read::cpu.dtb.walker 7633 # Total read bandwidth from this memory (bytes/s) 35system.physmem.bw_read::cpu.itb.walker 6474 # Total read bandwidth from this memory (bytes/s) 36system.physmem.bw_read::cpu.inst 1500693 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::realview.ide 8202 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::total 1523002 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_inst_read::cpu.inst 197986 # Instruction read bandwidth from this memory (bytes/s) 40system.physmem.bw_inst_read::total 197986 # Instruction read bandwidth from this memory (bytes/s) 41system.physmem.bw_write::writebacks 1838530 # Write bandwidth from this memory (bytes/s) 42system.physmem.bw_write::cpu.inst 398 # Write bandwidth from this memory (bytes/s) 43system.physmem.bw_write::total 1838928 # Write bandwidth from this memory (bytes/s) 44system.physmem.bw_total::writebacks 1838530 # Total bandwidth to/from this memory (bytes/s) 45system.physmem.bw_total::cpu.dtb.walker 7633 # Total bandwidth to/from this memory (bytes/s) 46system.physmem.bw_total::cpu.itb.walker 6474 # Total bandwidth to/from this memory (bytes/s) 47system.physmem.bw_total::cpu.inst 1501091 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::realview.ide 8202 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::total 3361929 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.readReqs 1230983 # Number of read requests accepted 51system.physmem.writeReqs 2135785 # Number of write requests accepted 52system.physmem.readBursts 1230983 # Number of DRAM read bursts, including those serviced by the write queue 53system.physmem.writeBursts 2135785 # Number of DRAM write bursts, including those merged in the write queue 54system.physmem.bytesReadDRAM 78738176 # Total number of bytes read from DRAM 55system.physmem.bytesReadWrQ 44736 # Total number of bytes read from write queue 56system.physmem.bytesWritten 136238784 # Total number of bytes written to DRAM 57system.physmem.bytesReadSys 78782088 # Total read bytes from the system interface side 58system.physmem.bytesWrittenSys 136546148 # Total written bytes from the system interface side 59system.physmem.servicedByWrQ 699 # Number of DRAM read bursts serviced by the write queue 60system.physmem.mergedWrBursts 7032 # Number of DRAM write bursts merged with an existing one 61system.physmem.neitherReadNorWriteReqs 39789 # Number of requests that are neither read nor write 62system.physmem.perBankRdBursts::0 72855 # Per bank write bursts 63system.physmem.perBankRdBursts::1 77589 # Per bank write bursts 64system.physmem.perBankRdBursts::2 71702 # Per bank write bursts 65system.physmem.perBankRdBursts::3 69206 # Per bank write bursts 66system.physmem.perBankRdBursts::4 71012 # Per bank write bursts 67system.physmem.perBankRdBursts::5 79882 # Per bank write bursts 68system.physmem.perBankRdBursts::6 74555 # Per bank write bursts 69system.physmem.perBankRdBursts::7 73696 # Per bank write bursts 70system.physmem.perBankRdBursts::8 66951 # Per bank write bursts 71system.physmem.perBankRdBursts::9 130748 # Per bank write bursts 72system.physmem.perBankRdBursts::10 72702 # Per bank write bursts 73system.physmem.perBankRdBursts::11 77684 # Per bank write bursts 74system.physmem.perBankRdBursts::12 73029 # Per bank write bursts 75system.physmem.perBankRdBursts::13 75645 # Per bank write bursts 76system.physmem.perBankRdBursts::14 69035 # Per bank write bursts 77system.physmem.perBankRdBursts::15 73993 # Per bank write bursts 78system.physmem.perBankWrBursts::0 130105 # Per bank write bursts 79system.physmem.perBankWrBursts::1 136647 # Per bank write bursts 80system.physmem.perBankWrBursts::2 132594 # Per bank write bursts 81system.physmem.perBankWrBursts::3 132058 # Per bank write bursts 82system.physmem.perBankWrBursts::4 132790 # Per bank write bursts 83system.physmem.perBankWrBursts::5 135723 # Per bank write bursts 84system.physmem.perBankWrBursts::6 131916 # Per bank write bursts 85system.physmem.perBankWrBursts::7 135307 # Per bank write bursts 86system.physmem.perBankWrBursts::8 129762 # Per bank write bursts 87system.physmem.perBankWrBursts::9 138269 # Per bank write bursts 88system.physmem.perBankWrBursts::10 133041 # Per bank write bursts 89system.physmem.perBankWrBursts::11 135411 # Per bank write bursts 90system.physmem.perBankWrBursts::12 131809 # Per bank write bursts 91system.physmem.perBankWrBursts::13 134107 # Per bank write bursts 92system.physmem.perBankWrBursts::14 128778 # Per bank write bursts 93system.physmem.perBankWrBursts::15 130414 # Per bank write bursts 94system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 95system.physmem.numWrRetry 1 # Number of times write queue was full causing retry 96system.physmem.totGap 51728172924500 # Total gap between requests 97system.physmem.readPktSize::0 0 # Read request sizes (log2) 98system.physmem.readPktSize::1 0 # Read request sizes (log2) 99system.physmem.readPktSize::2 0 # Read request sizes (log2) 100system.physmem.readPktSize::3 13 # Read request sizes (log2) 101system.physmem.readPktSize::4 2 # Read request sizes (log2) 102system.physmem.readPktSize::5 0 # Read request sizes (log2) 103system.physmem.readPktSize::6 1230968 # Read request sizes (log2) 104system.physmem.writePktSize::0 0 # Write request sizes (log2) 105system.physmem.writePktSize::1 0 # Write request sizes (log2) 106system.physmem.writePktSize::2 1 # Write request sizes (log2) 107system.physmem.writePktSize::3 2572 # Write request sizes (log2) 108system.physmem.writePktSize::4 0 # Write request sizes (log2) 109system.physmem.writePktSize::5 0 # Write request sizes (log2) 110system.physmem.writePktSize::6 2133212 # Write request sizes (log2) 111system.physmem.rdQLenPdf::0 1193516 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::1 30294 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::2 2468 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::3 634 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::4 774 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::5 445 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::6 402 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::7 326 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::8 225 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::9 151 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::10 141 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::11 133 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::12 117 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::13 116 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::14 112 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::15 108 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::16 93 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::17 91 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::18 75 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::19 59 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::20 3 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 143system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::15 48810 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::16 75161 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::17 120471 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::18 133680 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::19 129638 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::20 132279 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::21 134371 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::22 139270 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::23 139351 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::24 138718 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::25 134041 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::26 121456 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::27 116921 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::28 112653 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::29 104822 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::30 103529 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::31 102348 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::32 101456 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::33 3528 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::34 3145 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::35 3077 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::36 2746 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::37 2646 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::38 2462 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::39 2396 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::40 2343 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::41 2218 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::42 2043 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::43 1968 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::44 1747 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::45 1501 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::46 1440 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::47 1271 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::48 1084 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::49 914 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::50 813 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::51 704 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::52 545 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::53 394 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::54 297 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::55 183 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::56 128 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::57 90 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::58 45 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::59 16 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::60 11 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::61 5 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::62 1 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::63 2 # What write queue length does an incoming req see 207system.physmem.bytesPerActivate::samples 724941 # Bytes accessed per row activation 208system.physmem.bytesPerActivate::mean 296.543548 # Bytes accessed per row activation 209system.physmem.bytesPerActivate::gmean 170.840359 # Bytes accessed per row activation 210system.physmem.bytesPerActivate::stdev 329.964737 # Bytes accessed per row activation 211system.physmem.bytesPerActivate::0-127 292739 40.38% 40.38% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::128-255 175978 24.27% 64.66% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::256-383 64522 8.90% 73.56% # Bytes accessed per row activation 214system.physmem.bytesPerActivate::384-511 36242 5.00% 78.56% # Bytes accessed per row activation 215system.physmem.bytesPerActivate::512-639 25200 3.48% 82.03% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::640-767 17306 2.39% 84.42% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::768-895 13334 1.84% 86.26% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::896-1023 11857 1.64% 87.89% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::1024-1151 87763 12.11% 100.00% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::total 724941 # Bytes accessed per row activation 221system.physmem.rdPerTurnAround::samples 98383 # Reads before turning the bus around for writes 222system.physmem.rdPerTurnAround::mean 12.504427 # Reads before turning the bus around for writes 223system.physmem.rdPerTurnAround::stdev 125.607658 # Reads before turning the bus around for writes 224system.physmem.rdPerTurnAround::0-1023 98380 100.00% 100.00% # Reads before turning the bus around for writes 225system.physmem.rdPerTurnAround::1024-2047 1 0.00% 100.00% # Reads before turning the bus around for writes 226system.physmem.rdPerTurnAround::25600-26623 1 0.00% 100.00% # Reads before turning the bus around for writes 227system.physmem.rdPerTurnAround::28672-29695 1 0.00% 100.00% # Reads before turning the bus around for writes 228system.physmem.rdPerTurnAround::total 98383 # Reads before turning the bus around for writes 229system.physmem.wrPerTurnAround::samples 98383 # Writes before turning the bus around for reads 230system.physmem.wrPerTurnAround::mean 21.637183 # Writes before turning the bus around for reads 231system.physmem.wrPerTurnAround::gmean 20.054808 # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::stdev 12.113777 # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::16-23 71754 72.93% 72.93% # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::24-31 19885 20.21% 93.15% # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::32-39 3061 3.11% 96.26% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::40-47 745 0.76% 97.01% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::48-55 867 0.88% 97.89% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::56-63 408 0.41% 98.31% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::64-71 354 0.36% 98.67% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::72-79 234 0.24% 98.91% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::80-87 298 0.30% 99.21% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::88-95 183 0.19% 99.40% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::96-103 211 0.21% 99.61% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::104-111 51 0.05% 99.66% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::112-119 56 0.06% 99.72% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::120-127 41 0.04% 99.76% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::128-135 125 0.13% 99.89% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::136-143 21 0.02% 99.91% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::144-151 37 0.04% 99.95% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::152-159 9 0.01% 99.96% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::160-167 12 0.01% 99.97% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::168-175 3 0.00% 99.97% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::176-183 4 0.00% 99.98% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::184-191 7 0.01% 99.98% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::192-199 1 0.00% 99.98% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::200-207 4 0.00% 99.99% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::208-215 4 0.00% 99.99% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::216-223 1 0.00% 99.99% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::224-231 3 0.00% 100.00% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::240-247 1 0.00% 100.00% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::248-255 2 0.00% 100.00% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::256-263 1 0.00% 100.00% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::total 98383 # Writes before turning the bus around for reads 264system.physmem.totQLat 15890716010 # Total ticks spent queuing 265system.physmem.totMemAccLat 38958541010 # Total ticks spent from burst creation until serviced by the DRAM 266system.physmem.totBusLat 6151420000 # Total ticks spent in databus transfers 267system.physmem.avgQLat 12916.30 # Average queueing delay per DRAM burst 268system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 269system.physmem.avgMemAccLat 31666.30 # Average memory access latency per DRAM burst 270system.physmem.avgRdBW 1.52 # Average DRAM read bandwidth in MiByte/s 271system.physmem.avgWrBW 2.63 # Average achieved write bandwidth in MiByte/s 272system.physmem.avgRdBWSys 1.52 # Average system read bandwidth in MiByte/s 273system.physmem.avgWrBWSys 2.64 # Average system write bandwidth in MiByte/s 274system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 275system.physmem.busUtil 0.03 # Data bus utilization in percentage 276system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads 277system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes 278system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing 279system.physmem.avgWrQLen 24.58 # Average write queue length when enqueuing 280system.physmem.readRowHits 953619 # Number of row buffer hits during reads 281system.physmem.writeRowHits 1680454 # Number of row buffer hits during writes 282system.physmem.readRowHitRate 77.51 # Row buffer hit rate for reads 283system.physmem.writeRowHitRate 78.94 # Row buffer hit rate for writes 284system.physmem.avgGap 15364341.39 # Average gap between requests 285system.physmem.pageHitRate 78.42 # Row buffer hit rate, read and write combined 286system.physmem_0.actEnergy 2748558960 # Energy for activate commands per rank (pJ) 287system.physmem_0.preEnergy 1499709750 # Energy for precharge commands per rank (pJ) 288system.physmem_0.readEnergy 4605829800 # Energy for read commands per rank (pJ) 289system.physmem_0.writeEnergy 6915067200 # Energy for write commands per rank (pJ) 290system.physmem_0.refreshEnergy 3378632599680 # Energy for refresh commands per rank (pJ) 291system.physmem_0.actBackEnergy 1310572243215 # Energy for active background per rank (pJ) 292system.physmem_0.preBackEnergy 29887277315250 # Energy for precharge background per rank (pJ) 293system.physmem_0.totalEnergy 34592251323855 # Total energy per rank (pJ) 294system.physmem_0.averagePower 668.731394 # Core power per rank (mW) 295system.physmem_0.memoryStateTime::IDLE 49719326487750 # Time in different power states 296system.physmem_0.memoryStateTime::REF 1727317280000 # Time in different power states 297system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 298system.physmem_0.memoryStateTime::ACT 281530424750 # Time in different power states 299system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 300system.physmem_1.actEnergy 2731995000 # Energy for activate commands per rank (pJ) 301system.physmem_1.preEnergy 1490671875 # Energy for precharge commands per rank (pJ) 302system.physmem_1.readEnergy 4990338600 # Energy for read commands per rank (pJ) 303system.physmem_1.writeEnergy 6879109680 # Energy for write commands per rank (pJ) 304system.physmem_1.refreshEnergy 3378632599680 # Energy for refresh commands per rank (pJ) 305system.physmem_1.actBackEnergy 1309819963770 # Energy for active background per rank (pJ) 306system.physmem_1.preBackEnergy 29887937201250 # Energy for precharge background per rank (pJ) 307system.physmem_1.totalEnergy 34592481879855 # Total energy per rank (pJ) 308system.physmem_1.averagePower 668.735851 # Core power per rank (mW) 309system.physmem_1.memoryStateTime::IDLE 49720391571002 # Time in different power states 310system.physmem_1.memoryStateTime::REF 1727317280000 # Time in different power states 311system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 312system.physmem_1.memoryStateTime::ACT 280461298998 # Time in different power states 313system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 314system.realview.nvmem.bytes_read::cpu.inst 740 # Number of bytes read from this memory 315system.realview.nvmem.bytes_read::total 740 # Number of bytes read from this memory 316system.realview.nvmem.bytes_inst_read::cpu.inst 704 # Number of instructions bytes read from this memory 317system.realview.nvmem.bytes_inst_read::total 704 # Number of instructions bytes read from this memory 318system.realview.nvmem.num_reads::cpu.inst 16 # Number of read requests responded to by this memory 319system.realview.nvmem.num_reads::total 16 # Number of read requests responded to by this memory 320system.realview.nvmem.bw_read::cpu.inst 14 # Total read bandwidth from this memory (bytes/s) 321system.realview.nvmem.bw_read::total 14 # Total read bandwidth from this memory (bytes/s) 322system.realview.nvmem.bw_inst_read::cpu.inst 14 # Instruction read bandwidth from this memory (bytes/s) 323system.realview.nvmem.bw_inst_read::total 14 # Instruction read bandwidth from this memory (bytes/s) 324system.realview.nvmem.bw_total::cpu.inst 14 # Total bandwidth to/from this memory (bytes/s) 325system.realview.nvmem.bw_total::total 14 # Total bandwidth to/from this memory (bytes/s) 326system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 327system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 328system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 329system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. 330system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. 331system.cf0.dma_write_txs 1669 # Number of DMA write transactions. 332system.cpu.branchPred.lookups 261740307 # Number of BP lookups 333system.cpu.branchPred.condPredicted 183617747 # Number of conditional branches predicted 334system.cpu.branchPred.condIncorrect 12193617 # Number of conditional branches incorrect 335system.cpu.branchPred.BTBLookups 193974198 # Number of BTB lookups 336system.cpu.branchPred.BTBHits 136954935 # Number of BTB hits 337system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 338system.cpu.branchPred.BTBHitPct 70.604718 # BTB Hit Percentage 339system.cpu.branchPred.usedRAS 31757981 # Number of times the RAS was used to get a target. 340system.cpu.branchPred.RASInCorrect 2120874 # Number of incorrect RAS predictions. 341system.cpu_clk_domain.clock 500 # Clock period in ticks 342system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 343system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 344system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 345system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 346system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 347system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 348system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 349system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 350system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 351system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 352system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 353system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 354system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 355system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 356system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 357system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 358system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 359system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 360system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 361system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 362system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 363system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 364system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 365system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 366system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 367system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 368system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 369system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 370system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 371system.cpu.dtb.walker.walks 587644 # Table walker walks requested 372system.cpu.dtb.walker.walksLong 587644 # Table walker walks initiated with long descriptors 373system.cpu.dtb.walker.walksLongTerminationLevel::Level2 20971 # Level at which table walker walks with long descriptors terminate 374system.cpu.dtb.walker.walksLongTerminationLevel::Level3 193860 # Level at which table walker walks with long descriptors terminate 375system.cpu.dtb.walker.walkWaitTime::samples 587644 # Table walker wait (enqueue to first request) latency 376system.cpu.dtb.walker.walkWaitTime::0 587644 100.00% 100.00% # Table walker wait (enqueue to first request) latency 377system.cpu.dtb.walker.walkWaitTime::total 587644 # Table walker wait (enqueue to first request) latency 378system.cpu.dtb.walker.walkCompletionTime::samples 214831 # Table walker service (enqueue to completion) latency 379system.cpu.dtb.walker.walkCompletionTime::mean 23073.231987 # Table walker service (enqueue to completion) latency 380system.cpu.dtb.walker.walkCompletionTime::gmean 18856.280230 # Table walker service (enqueue to completion) latency 381system.cpu.dtb.walker.walkCompletionTime::stdev 14797.492454 # Table walker service (enqueue to completion) latency 382system.cpu.dtb.walker.walkCompletionTime::0-65535 212337 98.84% 98.84% # Table walker service (enqueue to completion) latency 383system.cpu.dtb.walker.walkCompletionTime::65536-131071 2138 1.00% 99.83% # Table walker service (enqueue to completion) latency 384system.cpu.dtb.walker.walkCompletionTime::131072-196607 152 0.07% 99.91% # Table walker service (enqueue to completion) latency 385system.cpu.dtb.walker.walkCompletionTime::196608-262143 133 0.06% 99.97% # Table walker service (enqueue to completion) latency 386system.cpu.dtb.walker.walkCompletionTime::262144-327679 38 0.02% 99.98% # Table walker service (enqueue to completion) latency 387system.cpu.dtb.walker.walkCompletionTime::327680-393215 25 0.01% 100.00% # Table walker service (enqueue to completion) latency 388system.cpu.dtb.walker.walkCompletionTime::393216-458751 6 0.00% 100.00% # Table walker service (enqueue to completion) latency 389system.cpu.dtb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 390system.cpu.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 391system.cpu.dtb.walker.walkCompletionTime::total 214831 # Table walker service (enqueue to completion) latency 392system.cpu.dtb.walker.walksPending::samples -243009796 # Table walker pending requests distribution 393system.cpu.dtb.walker.walksPending::0 -243009796 100.00% 100.00% # Table walker pending requests distribution 394system.cpu.dtb.walker.walksPending::total -243009796 # Table walker pending requests distribution 395system.cpu.dtb.walker.walkPageSizes::4K 193861 90.24% 90.24% # Table walker page sizes translated 396system.cpu.dtb.walker.walkPageSizes::2M 20971 9.76% 100.00% # Table walker page sizes translated 397system.cpu.dtb.walker.walkPageSizes::total 214832 # Table walker page sizes translated 398system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 587644 # Table walker requests started/completed, data/inst 399system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 400system.cpu.dtb.walker.walkRequestOrigin_Requested::total 587644 # Table walker requests started/completed, data/inst 401system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 214832 # Table walker requests started/completed, data/inst 402system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 403system.cpu.dtb.walker.walkRequestOrigin_Completed::total 214832 # Table walker requests started/completed, data/inst 404system.cpu.dtb.walker.walkRequestOrigin::total 802476 # Table walker requests started/completed, data/inst 405system.cpu.dtb.inst_hits 0 # ITB inst hits 406system.cpu.dtb.inst_misses 0 # ITB inst misses 407system.cpu.dtb.read_hits 184101010 # DTB read hits 408system.cpu.dtb.read_misses 486113 # DTB read misses 409system.cpu.dtb.write_hits 163332837 # DTB write hits 410system.cpu.dtb.write_misses 101531 # DTB write misses 411system.cpu.dtb.flush_tlb 11 # Number of times complete TLB was flushed 412system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 413system.cpu.dtb.flush_tlb_mva_asid 47436 # Number of times TLB was flushed by MVA & ASID 414system.cpu.dtb.flush_tlb_asid 1113 # Number of times TLB was flushed by ASID 415system.cpu.dtb.flush_entries 79171 # Number of entries that have been flushed from TLB 416system.cpu.dtb.align_faults 889 # Number of TLB faults due to alignment restrictions 417system.cpu.dtb.prefetch_faults 14871 # Number of TLB faults due to prefetch 418system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 419system.cpu.dtb.perms_faults 23598 # Number of TLB faults due to permissions restrictions 420system.cpu.dtb.read_accesses 184587123 # DTB read accesses 421system.cpu.dtb.write_accesses 163434368 # DTB write accesses 422system.cpu.dtb.inst_accesses 0 # ITB inst accesses 423system.cpu.dtb.hits 347433847 # DTB hits 424system.cpu.dtb.misses 587644 # DTB misses 425system.cpu.dtb.accesses 348021491 # DTB accesses 426system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 427system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 428system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 429system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 430system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 431system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 432system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 433system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 434system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 435system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 436system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 437system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 438system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 439system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 440system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 441system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 442system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 443system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 444system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 445system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 446system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 447system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 448system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 449system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 450system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 451system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 452system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 453system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 454system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 455system.cpu.itb.walker.walks 136955 # Table walker walks requested 456system.cpu.itb.walker.walksLong 136955 # Table walker walks initiated with long descriptors 457system.cpu.itb.walker.walksLongTerminationLevel::Level2 1083 # Level at which table walker walks with long descriptors terminate 458system.cpu.itb.walker.walksLongTerminationLevel::Level3 119238 # Level at which table walker walks with long descriptors terminate 459system.cpu.itb.walker.walkWaitTime::samples 136955 # Table walker wait (enqueue to first request) latency 460system.cpu.itb.walker.walkWaitTime::0 136955 100.00% 100.00% # Table walker wait (enqueue to first request) latency 461system.cpu.itb.walker.walkWaitTime::total 136955 # Table walker wait (enqueue to first request) latency 462system.cpu.itb.walker.walkCompletionTime::samples 120321 # Table walker service (enqueue to completion) latency 463system.cpu.itb.walker.walkCompletionTime::mean 25178.697160 # Table walker service (enqueue to completion) latency 464system.cpu.itb.walker.walkCompletionTime::gmean 21090.590253 # Table walker service (enqueue to completion) latency 465system.cpu.itb.walker.walkCompletionTime::stdev 16725.174106 # Table walker service (enqueue to completion) latency 466system.cpu.itb.walker.walkCompletionTime::0-65535 117467 97.63% 97.63% # Table walker service (enqueue to completion) latency 467system.cpu.itb.walker.walkCompletionTime::65536-131071 2593 2.16% 99.78% # Table walker service (enqueue to completion) latency 468system.cpu.itb.walker.walkCompletionTime::131072-196607 161 0.13% 99.92% # Table walker service (enqueue to completion) latency 469system.cpu.itb.walker.walkCompletionTime::196608-262143 40 0.03% 99.95% # Table walker service (enqueue to completion) latency 470system.cpu.itb.walker.walkCompletionTime::262144-327679 38 0.03% 99.98% # Table walker service (enqueue to completion) latency 471system.cpu.itb.walker.walkCompletionTime::327680-393215 20 0.02% 100.00% # Table walker service (enqueue to completion) latency 472system.cpu.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 473system.cpu.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 474system.cpu.itb.walker.walkCompletionTime::total 120321 # Table walker service (enqueue to completion) latency 475system.cpu.itb.walker.walksPending::samples -243525796 # Table walker pending requests distribution 476system.cpu.itb.walker.walksPending::0 -243525796 100.00% 100.00% # Table walker pending requests distribution 477system.cpu.itb.walker.walksPending::total -243525796 # Table walker pending requests distribution 478system.cpu.itb.walker.walkPageSizes::4K 119238 99.10% 99.10% # Table walker page sizes translated 479system.cpu.itb.walker.walkPageSizes::2M 1083 0.90% 100.00% # Table walker page sizes translated 480system.cpu.itb.walker.walkPageSizes::total 120321 # Table walker page sizes translated 481system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 482system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 136955 # Table walker requests started/completed, data/inst 483system.cpu.itb.walker.walkRequestOrigin_Requested::total 136955 # Table walker requests started/completed, data/inst 484system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 485system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 120321 # Table walker requests started/completed, data/inst 486system.cpu.itb.walker.walkRequestOrigin_Completed::total 120321 # Table walker requests started/completed, data/inst 487system.cpu.itb.walker.walkRequestOrigin::total 257276 # Table walker requests started/completed, data/inst 488system.cpu.itb.inst_hits 455989522 # ITB inst hits 489system.cpu.itb.inst_misses 136955 # ITB inst misses 490system.cpu.itb.read_hits 0 # DTB read hits 491system.cpu.itb.read_misses 0 # DTB read misses 492system.cpu.itb.write_hits 0 # DTB write hits 493system.cpu.itb.write_misses 0 # DTB write misses 494system.cpu.itb.flush_tlb 11 # Number of times complete TLB was flushed 495system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 496system.cpu.itb.flush_tlb_mva_asid 47436 # Number of times TLB was flushed by MVA & ASID 497system.cpu.itb.flush_tlb_asid 1113 # Number of times TLB was flushed by ASID 498system.cpu.itb.flush_entries 56761 # Number of entries that have been flushed from TLB 499system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 500system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 501system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 502system.cpu.itb.perms_faults 364272 # Number of TLB faults due to permissions restrictions 503system.cpu.itb.read_accesses 0 # DTB read accesses 504system.cpu.itb.write_accesses 0 # DTB write accesses 505system.cpu.itb.inst_accesses 456126477 # ITB inst accesses 506system.cpu.itb.hits 455989522 # DTB hits 507system.cpu.itb.misses 136955 # DTB misses 508system.cpu.itb.accesses 456126477 # DTB accesses 509system.cpu.numCycles 2523007146 # number of cpu cycles simulated 510system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 511system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 512system.cpu.committedInsts 953410832 # Number of instructions committed 513system.cpu.committedOps 1120287994 # Number of ops (including micro ops) committed 514system.cpu.discardedOps 97416264 # Number of ops (including micro ops) which were discarded before commit 515system.cpu.numFetchSuspends 7771 # Number of times Execute suspended instruction fetching 516system.cpu.quiesceCycles 100934517430 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 517system.cpu.cpi 2.646296 # CPI: cycles per instruction 518system.cpu.ipc 0.377887 # IPC: instructions per cycle 519system.cpu.kern.inst.arm 0 # number of arm instructions executed 520system.cpu.kern.inst.quiesce 16631 # number of quiesce instructions executed 521system.cpu.tickCycles 1807938889 # Number of cycles that the object actually ticked 522system.cpu.idleCycles 715068257 # Total number of cycles that the object has spent stopped 523system.cpu.dcache.tags.replacements 11209162 # number of replacements 524system.cpu.dcache.tags.tagsinuse 511.959689 # Cycle average of tags in use 525system.cpu.dcache.tags.total_refs 331084794 # Total number of references to valid blocks. 526system.cpu.dcache.tags.sampled_refs 11209674 # Sample count of references to valid blocks. 527system.cpu.dcache.tags.avg_refs 29.535631 # Average number of references to valid blocks. 528system.cpu.dcache.tags.warmup_cycle 4089991250 # Cycle when the warmup percentage was hit. 529system.cpu.dcache.tags.occ_blocks::cpu.inst 511.959689 # Average occupied blocks per requestor 530system.cpu.dcache.tags.occ_percent::cpu.inst 0.999921 # Average percentage of cache occupancy 531system.cpu.dcache.tags.occ_percent::total 0.999921 # Average percentage of cache occupancy 532system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 533system.cpu.dcache.tags.age_task_id_blocks_1024::0 70 # Occupied blocks per task id 534system.cpu.dcache.tags.age_task_id_blocks_1024::1 392 # Occupied blocks per task id 535system.cpu.dcache.tags.age_task_id_blocks_1024::2 48 # Occupied blocks per task id 536system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id 537system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 538system.cpu.dcache.tags.tag_accesses 1391009936 # Number of tag accesses 539system.cpu.dcache.tags.data_accesses 1391009936 # Number of data accesses 540system.cpu.dcache.ReadReq_hits::cpu.inst 169770938 # number of ReadReq hits 541system.cpu.dcache.ReadReq_hits::total 169770938 # number of ReadReq hits 542system.cpu.dcache.WriteReq_hits::cpu.inst 152453541 # number of WriteReq hits 543system.cpu.dcache.WriteReq_hits::total 152453541 # number of WriteReq hits 544system.cpu.dcache.WriteInvalidateReq_hits::cpu.inst 337498 # number of WriteInvalidateReq hits 545system.cpu.dcache.WriteInvalidateReq_hits::total 337498 # number of WriteInvalidateReq hits 546system.cpu.dcache.LoadLockedReq_hits::cpu.inst 4114364 # number of LoadLockedReq hits 547system.cpu.dcache.LoadLockedReq_hits::total 4114364 # number of LoadLockedReq hits 548system.cpu.dcache.StoreCondReq_hits::cpu.inst 4358642 # number of StoreCondReq hits 549system.cpu.dcache.StoreCondReq_hits::total 4358642 # number of StoreCondReq hits 550system.cpu.dcache.demand_hits::cpu.inst 322224479 # number of demand (read+write) hits 551system.cpu.dcache.demand_hits::total 322224479 # number of demand (read+write) hits 552system.cpu.dcache.overall_hits::cpu.inst 322224479 # number of overall hits 553system.cpu.dcache.overall_hits::total 322224479 # number of overall hits 554system.cpu.dcache.ReadReq_misses::cpu.inst 8085158 # number of ReadReq misses 555system.cpu.dcache.ReadReq_misses::total 8085158 # number of ReadReq misses 556system.cpu.dcache.WriteReq_misses::cpu.inst 4338895 # number of WriteReq misses 557system.cpu.dcache.WriteReq_misses::total 4338895 # number of WriteReq misses 558system.cpu.dcache.WriteInvalidateReq_misses::cpu.inst 1245002 # number of WriteInvalidateReq misses 559system.cpu.dcache.WriteInvalidateReq_misses::total 1245002 # number of WriteInvalidateReq misses 560system.cpu.dcache.LoadLockedReq_misses::cpu.inst 246013 # number of LoadLockedReq misses 561system.cpu.dcache.LoadLockedReq_misses::total 246013 # number of LoadLockedReq misses 562system.cpu.dcache.StoreCondReq_misses::cpu.inst 2 # number of StoreCondReq misses 563system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses 564system.cpu.dcache.demand_misses::cpu.inst 12424053 # number of demand (read+write) misses 565system.cpu.dcache.demand_misses::total 12424053 # number of demand (read+write) misses 566system.cpu.dcache.overall_misses::cpu.inst 12424053 # number of overall misses 567system.cpu.dcache.overall_misses::total 12424053 # number of overall misses 568system.cpu.dcache.ReadReq_miss_latency::cpu.inst 128824080247 # number of ReadReq miss cycles 569system.cpu.dcache.ReadReq_miss_latency::total 128824080247 # number of ReadReq miss cycles 570system.cpu.dcache.WriteReq_miss_latency::cpu.inst 144514675403 # number of WriteReq miss cycles 571system.cpu.dcache.WriteReq_miss_latency::total 144514675403 # number of WriteReq miss cycles 572system.cpu.dcache.WriteInvalidateReq_miss_latency::cpu.inst 29607413192 # number of WriteInvalidateReq miss cycles 573system.cpu.dcache.WriteInvalidateReq_miss_latency::total 29607413192 # number of WriteInvalidateReq miss cycles 574system.cpu.dcache.LoadLockedReq_miss_latency::cpu.inst 3571422003 # number of LoadLockedReq miss cycles 575system.cpu.dcache.LoadLockedReq_miss_latency::total 3571422003 # number of LoadLockedReq miss cycles 576system.cpu.dcache.StoreCondReq_miss_latency::cpu.inst 150500 # number of StoreCondReq miss cycles 577system.cpu.dcache.StoreCondReq_miss_latency::total 150500 # number of StoreCondReq miss cycles 578system.cpu.dcache.demand_miss_latency::cpu.inst 273338755650 # number of demand (read+write) miss cycles 579system.cpu.dcache.demand_miss_latency::total 273338755650 # number of demand (read+write) miss cycles 580system.cpu.dcache.overall_miss_latency::cpu.inst 273338755650 # number of overall miss cycles 581system.cpu.dcache.overall_miss_latency::total 273338755650 # number of overall miss cycles 582system.cpu.dcache.ReadReq_accesses::cpu.inst 177856096 # number of ReadReq accesses(hits+misses) 583system.cpu.dcache.ReadReq_accesses::total 177856096 # number of ReadReq accesses(hits+misses) 584system.cpu.dcache.WriteReq_accesses::cpu.inst 156792436 # number of WriteReq accesses(hits+misses) 585system.cpu.dcache.WriteReq_accesses::total 156792436 # number of WriteReq accesses(hits+misses) 586system.cpu.dcache.WriteInvalidateReq_accesses::cpu.inst 1582500 # number of WriteInvalidateReq accesses(hits+misses) 587system.cpu.dcache.WriteInvalidateReq_accesses::total 1582500 # number of WriteInvalidateReq accesses(hits+misses) 588system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 4360377 # number of LoadLockedReq accesses(hits+misses) 589system.cpu.dcache.LoadLockedReq_accesses::total 4360377 # number of LoadLockedReq accesses(hits+misses) 590system.cpu.dcache.StoreCondReq_accesses::cpu.inst 4358644 # number of StoreCondReq accesses(hits+misses) 591system.cpu.dcache.StoreCondReq_accesses::total 4358644 # number of StoreCondReq accesses(hits+misses) 592system.cpu.dcache.demand_accesses::cpu.inst 334648532 # number of demand (read+write) accesses 593system.cpu.dcache.demand_accesses::total 334648532 # number of demand (read+write) accesses 594system.cpu.dcache.overall_accesses::cpu.inst 334648532 # number of overall (read+write) accesses 595system.cpu.dcache.overall_accesses::total 334648532 # number of overall (read+write) accesses 596system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.045459 # miss rate for ReadReq accesses 597system.cpu.dcache.ReadReq_miss_rate::total 0.045459 # miss rate for ReadReq accesses 598system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.027673 # miss rate for WriteReq accesses 599system.cpu.dcache.WriteReq_miss_rate::total 0.027673 # miss rate for WriteReq accesses 600system.cpu.dcache.WriteInvalidateReq_miss_rate::cpu.inst 0.786731 # miss rate for WriteInvalidateReq accesses 601system.cpu.dcache.WriteInvalidateReq_miss_rate::total 0.786731 # miss rate for WriteInvalidateReq accesses 602system.cpu.dcache.LoadLockedReq_miss_rate::cpu.inst 0.056420 # miss rate for LoadLockedReq accesses 603system.cpu.dcache.LoadLockedReq_miss_rate::total 0.056420 # miss rate for LoadLockedReq accesses 604system.cpu.dcache.StoreCondReq_miss_rate::cpu.inst 0.000000 # miss rate for StoreCondReq accesses 605system.cpu.dcache.StoreCondReq_miss_rate::total 0.000000 # miss rate for StoreCondReq accesses 606system.cpu.dcache.demand_miss_rate::cpu.inst 0.037126 # miss rate for demand accesses 607system.cpu.dcache.demand_miss_rate::total 0.037126 # miss rate for demand accesses 608system.cpu.dcache.overall_miss_rate::cpu.inst 0.037126 # miss rate for overall accesses 609system.cpu.dcache.overall_miss_rate::total 0.037126 # miss rate for overall accesses 610system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 15933.402940 # average ReadReq miss latency 611system.cpu.dcache.ReadReq_avg_miss_latency::total 15933.402940 # average ReadReq miss latency 612system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 33306.792490 # average WriteReq miss latency 613system.cpu.dcache.WriteReq_avg_miss_latency::total 33306.792490 # average WriteReq miss latency 614system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::cpu.inst 23781.016570 # average WriteInvalidateReq miss latency 615system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::total 23781.016570 # average WriteInvalidateReq miss latency 616system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.inst 14517.208452 # average LoadLockedReq miss latency 617system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14517.208452 # average LoadLockedReq miss latency 618system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.inst 75250 # average StoreCondReq miss latency 619system.cpu.dcache.StoreCondReq_avg_miss_latency::total 75250 # average StoreCondReq miss latency 620system.cpu.dcache.demand_avg_miss_latency::cpu.inst 22000.771862 # average overall miss latency 621system.cpu.dcache.demand_avg_miss_latency::total 22000.771862 # average overall miss latency 622system.cpu.dcache.overall_avg_miss_latency::cpu.inst 22000.771862 # average overall miss latency 623system.cpu.dcache.overall_avg_miss_latency::total 22000.771862 # average overall miss latency 624system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 625system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 626system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 627system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 628system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 629system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 630system.cpu.dcache.fast_writes 0 # number of fast writes performed 631system.cpu.dcache.cache_copies 0 # number of cache copies performed 632system.cpu.dcache.writebacks::writebacks 8593512 # number of writebacks 633system.cpu.dcache.writebacks::total 8593512 # number of writebacks 634system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 755938 # number of ReadReq MSHR hits 635system.cpu.dcache.ReadReq_mshr_hits::total 755938 # number of ReadReq MSHR hits 636system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 1899458 # number of WriteReq MSHR hits 637system.cpu.dcache.WriteReq_mshr_hits::total 1899458 # number of WriteReq MSHR hits 638system.cpu.dcache.WriteInvalidateReq_mshr_hits::cpu.inst 141 # number of WriteInvalidateReq MSHR hits 639system.cpu.dcache.WriteInvalidateReq_mshr_hits::total 141 # number of WriteInvalidateReq MSHR hits 640system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.inst 4 # number of LoadLockedReq MSHR hits 641system.cpu.dcache.LoadLockedReq_mshr_hits::total 4 # number of LoadLockedReq MSHR hits 642system.cpu.dcache.demand_mshr_hits::cpu.inst 2655396 # number of demand (read+write) MSHR hits 643system.cpu.dcache.demand_mshr_hits::total 2655396 # number of demand (read+write) MSHR hits 644system.cpu.dcache.overall_mshr_hits::cpu.inst 2655396 # number of overall MSHR hits 645system.cpu.dcache.overall_mshr_hits::total 2655396 # number of overall MSHR hits 646system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 7329220 # number of ReadReq MSHR misses 647system.cpu.dcache.ReadReq_mshr_misses::total 7329220 # number of ReadReq MSHR misses 648system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 2439437 # number of WriteReq MSHR misses 649system.cpu.dcache.WriteReq_mshr_misses::total 2439437 # number of WriteReq MSHR misses 650system.cpu.dcache.WriteInvalidateReq_mshr_misses::cpu.inst 1244861 # number of WriteInvalidateReq MSHR misses 651system.cpu.dcache.WriteInvalidateReq_mshr_misses::total 1244861 # number of WriteInvalidateReq MSHR misses 652system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.inst 246009 # number of LoadLockedReq MSHR misses 653system.cpu.dcache.LoadLockedReq_mshr_misses::total 246009 # number of LoadLockedReq MSHR misses 654system.cpu.dcache.StoreCondReq_mshr_misses::cpu.inst 2 # number of StoreCondReq MSHR misses 655system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses 656system.cpu.dcache.demand_mshr_misses::cpu.inst 9768657 # number of demand (read+write) MSHR misses 657system.cpu.dcache.demand_mshr_misses::total 9768657 # number of demand (read+write) MSHR misses 658system.cpu.dcache.overall_mshr_misses::cpu.inst 9768657 # number of overall MSHR misses 659system.cpu.dcache.overall_mshr_misses::total 9768657 # number of overall MSHR misses 660system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 102525908749 # number of ReadReq MSHR miss cycles 661system.cpu.dcache.ReadReq_mshr_miss_latency::total 102525908749 # number of ReadReq MSHR miss cycles 662system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 73694416463 # number of WriteReq MSHR miss cycles 663system.cpu.dcache.WriteReq_mshr_miss_latency::total 73694416463 # number of WriteReq MSHR miss cycles 664system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::cpu.inst 27114416558 # number of WriteInvalidateReq MSHR miss cycles 665system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::total 27114416558 # number of WriteInvalidateReq MSHR miss cycles 666system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.inst 3077572997 # number of LoadLockedReq MSHR miss cycles 667system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3077572997 # number of LoadLockedReq MSHR miss cycles 668system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.inst 146500 # number of StoreCondReq MSHR miss cycles 669system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 146500 # number of StoreCondReq MSHR miss cycles 670system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 176220325212 # number of demand (read+write) MSHR miss cycles 671system.cpu.dcache.demand_mshr_miss_latency::total 176220325212 # number of demand (read+write) MSHR miss cycles 672system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 176220325212 # number of overall MSHR miss cycles 673system.cpu.dcache.overall_mshr_miss_latency::total 176220325212 # number of overall MSHR miss cycles 674system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.inst 5727815999 # number of ReadReq MSHR uncacheable cycles 675system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5727815999 # number of ReadReq MSHR uncacheable cycles 676system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.inst 5585117500 # number of WriteReq MSHR uncacheable cycles 677system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5585117500 # number of WriteReq MSHR uncacheable cycles 678system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.inst 11312933499 # number of overall MSHR uncacheable cycles 679system.cpu.dcache.overall_mshr_uncacheable_latency::total 11312933499 # number of overall MSHR uncacheable cycles 680system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.041209 # mshr miss rate for ReadReq accesses 681system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.041209 # mshr miss rate for ReadReq accesses 682system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.015558 # mshr miss rate for WriteReq accesses 683system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015558 # mshr miss rate for WriteReq accesses 684system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::cpu.inst 0.786642 # mshr miss rate for WriteInvalidateReq accesses 685system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.786642 # mshr miss rate for WriteInvalidateReq accesses 686system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.inst 0.056419 # mshr miss rate for LoadLockedReq accesses 687system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.056419 # mshr miss rate for LoadLockedReq accesses 688system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for StoreCondReq accesses 689system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000000 # mshr miss rate for StoreCondReq accesses 690system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.029191 # mshr miss rate for demand accesses 691system.cpu.dcache.demand_mshr_miss_rate::total 0.029191 # mshr miss rate for demand accesses 692system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.029191 # mshr miss rate for overall accesses 693system.cpu.dcache.overall_mshr_miss_rate::total 0.029191 # mshr miss rate for overall accesses 694system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 13988.652101 # average ReadReq mshr miss latency 695system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13988.652101 # average ReadReq mshr miss latency 696system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 30209.600192 # average WriteReq mshr miss latency 697system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30209.600192 # average WriteReq mshr miss latency 698system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.inst 21781.079621 # average WriteInvalidateReq mshr miss latency 699system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 21781.079621 # average WriteInvalidateReq mshr miss latency 700system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.inst 12510.001654 # average LoadLockedReq mshr miss latency 701system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12510.001654 # average LoadLockedReq mshr miss latency 702system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.inst 73250 # average StoreCondReq mshr miss latency 703system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 73250 # average StoreCondReq mshr miss latency 704system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 18039.360499 # average overall mshr miss latency 705system.cpu.dcache.demand_avg_mshr_miss_latency::total 18039.360499 # average overall mshr miss latency 706system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 18039.360499 # average overall mshr miss latency 707system.cpu.dcache.overall_avg_mshr_miss_latency::total 18039.360499 # average overall mshr miss latency 708system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 709system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 710system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst inf # average WriteReq mshr uncacheable latency 711system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 712system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 713system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 714system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 715system.cpu.icache.tags.replacements 24725990 # number of replacements 716system.cpu.icache.tags.tagsinuse 511.931995 # Cycle average of tags in use 717system.cpu.icache.tags.total_refs 430886861 # Total number of references to valid blocks. 718system.cpu.icache.tags.sampled_refs 24726502 # Sample count of references to valid blocks. 719system.cpu.icache.tags.avg_refs 17.426115 # Average number of references to valid blocks. 720system.cpu.icache.tags.warmup_cycle 21192166000 # Cycle when the warmup percentage was hit. 721system.cpu.icache.tags.occ_blocks::cpu.inst 511.931995 # Average occupied blocks per requestor 722system.cpu.icache.tags.occ_percent::cpu.inst 0.999867 # Average percentage of cache occupancy 723system.cpu.icache.tags.occ_percent::total 0.999867 # Average percentage of cache occupancy 724system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 725system.cpu.icache.tags.age_task_id_blocks_1024::0 96 # Occupied blocks per task id 726system.cpu.icache.tags.age_task_id_blocks_1024::1 273 # Occupied blocks per task id 727system.cpu.icache.tags.age_task_id_blocks_1024::2 143 # Occupied blocks per task id 728system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 729system.cpu.icache.tags.tag_accesses 480339884 # Number of tag accesses 730system.cpu.icache.tags.data_accesses 480339884 # Number of data accesses 731system.cpu.icache.ReadReq_hits::cpu.inst 430886861 # number of ReadReq hits 732system.cpu.icache.ReadReq_hits::total 430886861 # number of ReadReq hits 733system.cpu.icache.demand_hits::cpu.inst 430886861 # number of demand (read+write) hits 734system.cpu.icache.demand_hits::total 430886861 # number of demand (read+write) hits 735system.cpu.icache.overall_hits::cpu.inst 430886861 # number of overall hits 736system.cpu.icache.overall_hits::total 430886861 # number of overall hits 737system.cpu.icache.ReadReq_misses::cpu.inst 24726512 # number of ReadReq misses 738system.cpu.icache.ReadReq_misses::total 24726512 # number of ReadReq misses 739system.cpu.icache.demand_misses::cpu.inst 24726512 # number of demand (read+write) misses 740system.cpu.icache.demand_misses::total 24726512 # number of demand (read+write) misses 741system.cpu.icache.overall_misses::cpu.inst 24726512 # number of overall misses 742system.cpu.icache.overall_misses::total 24726512 # number of overall misses 743system.cpu.icache.ReadReq_miss_latency::cpu.inst 328589993689 # number of ReadReq miss cycles 744system.cpu.icache.ReadReq_miss_latency::total 328589993689 # number of ReadReq miss cycles 745system.cpu.icache.demand_miss_latency::cpu.inst 328589993689 # number of demand (read+write) miss cycles 746system.cpu.icache.demand_miss_latency::total 328589993689 # number of demand (read+write) miss cycles 747system.cpu.icache.overall_miss_latency::cpu.inst 328589993689 # number of overall miss cycles 748system.cpu.icache.overall_miss_latency::total 328589993689 # number of overall miss cycles 749system.cpu.icache.ReadReq_accesses::cpu.inst 455613373 # number of ReadReq accesses(hits+misses) 750system.cpu.icache.ReadReq_accesses::total 455613373 # number of ReadReq accesses(hits+misses) 751system.cpu.icache.demand_accesses::cpu.inst 455613373 # number of demand (read+write) accesses 752system.cpu.icache.demand_accesses::total 455613373 # number of demand (read+write) accesses 753system.cpu.icache.overall_accesses::cpu.inst 455613373 # number of overall (read+write) accesses 754system.cpu.icache.overall_accesses::total 455613373 # number of overall (read+write) accesses 755system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.054271 # miss rate for ReadReq accesses 756system.cpu.icache.ReadReq_miss_rate::total 0.054271 # miss rate for ReadReq accesses 757system.cpu.icache.demand_miss_rate::cpu.inst 0.054271 # miss rate for demand accesses 758system.cpu.icache.demand_miss_rate::total 0.054271 # miss rate for demand accesses 759system.cpu.icache.overall_miss_rate::cpu.inst 0.054271 # miss rate for overall accesses 760system.cpu.icache.overall_miss_rate::total 0.054271 # miss rate for overall accesses 761system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13288.974753 # average ReadReq miss latency 762system.cpu.icache.ReadReq_avg_miss_latency::total 13288.974753 # average ReadReq miss latency 763system.cpu.icache.demand_avg_miss_latency::cpu.inst 13288.974753 # average overall miss latency 764system.cpu.icache.demand_avg_miss_latency::total 13288.974753 # average overall miss latency 765system.cpu.icache.overall_avg_miss_latency::cpu.inst 13288.974753 # average overall miss latency 766system.cpu.icache.overall_avg_miss_latency::total 13288.974753 # average overall miss latency 767system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 768system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 769system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 770system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 771system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 772system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 773system.cpu.icache.fast_writes 0 # number of fast writes performed 774system.cpu.icache.cache_copies 0 # number of cache copies performed 775system.cpu.icache.ReadReq_mshr_misses::cpu.inst 24726512 # number of ReadReq MSHR misses 776system.cpu.icache.ReadReq_mshr_misses::total 24726512 # number of ReadReq MSHR misses 777system.cpu.icache.demand_mshr_misses::cpu.inst 24726512 # number of demand (read+write) MSHR misses 778system.cpu.icache.demand_mshr_misses::total 24726512 # number of demand (read+write) MSHR misses 779system.cpu.icache.overall_mshr_misses::cpu.inst 24726512 # number of overall MSHR misses 780system.cpu.icache.overall_mshr_misses::total 24726512 # number of overall MSHR misses 781system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 279088621775 # number of ReadReq MSHR miss cycles 782system.cpu.icache.ReadReq_mshr_miss_latency::total 279088621775 # number of ReadReq MSHR miss cycles 783system.cpu.icache.demand_mshr_miss_latency::cpu.inst 279088621775 # number of demand (read+write) MSHR miss cycles 784system.cpu.icache.demand_mshr_miss_latency::total 279088621775 # number of demand (read+write) MSHR miss cycles 785system.cpu.icache.overall_mshr_miss_latency::cpu.inst 279088621775 # number of overall MSHR miss cycles 786system.cpu.icache.overall_mshr_miss_latency::total 279088621775 # number of overall MSHR miss cycles 787system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 3812277750 # number of ReadReq MSHR uncacheable cycles 788system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 3812277750 # number of ReadReq MSHR uncacheable cycles 789system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 3812277750 # number of overall MSHR uncacheable cycles 790system.cpu.icache.overall_mshr_uncacheable_latency::total 3812277750 # number of overall MSHR uncacheable cycles 791system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.054271 # mshr miss rate for ReadReq accesses 792system.cpu.icache.ReadReq_mshr_miss_rate::total 0.054271 # mshr miss rate for ReadReq accesses 793system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.054271 # mshr miss rate for demand accesses 794system.cpu.icache.demand_mshr_miss_rate::total 0.054271 # mshr miss rate for demand accesses 795system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.054271 # mshr miss rate for overall accesses 796system.cpu.icache.overall_mshr_miss_rate::total 0.054271 # mshr miss rate for overall accesses 797system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11287.019446 # average ReadReq mshr miss latency 798system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11287.019446 # average ReadReq mshr miss latency 799system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11287.019446 # average overall mshr miss latency 800system.cpu.icache.demand_avg_mshr_miss_latency::total 11287.019446 # average overall mshr miss latency 801system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11287.019446 # average overall mshr miss latency 802system.cpu.icache.overall_avg_mshr_miss_latency::total 11287.019446 # average overall mshr miss latency 803system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 804system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 805system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 806system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 807system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 808system.cpu.l2cache.tags.replacements 1618545 # number of replacements 809system.cpu.l2cache.tags.tagsinuse 65358.053127 # Cycle average of tags in use 810system.cpu.l2cache.tags.total_refs 40402502 # Total number of references to valid blocks. 811system.cpu.l2cache.tags.sampled_refs 1681764 # Sample count of references to valid blocks. 812system.cpu.l2cache.tags.avg_refs 24.023883 # Average number of references to valid blocks. 813system.cpu.l2cache.tags.warmup_cycle 5745484000 # Cycle when the warmup percentage was hit. 814system.cpu.l2cache.tags.occ_blocks::writebacks 36067.634498 # Average occupied blocks per requestor 815system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 340.939586 # Average occupied blocks per requestor 816system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 425.072148 # Average occupied blocks per requestor 817system.cpu.l2cache.tags.occ_blocks::cpu.inst 28524.406895 # Average occupied blocks per requestor 818system.cpu.l2cache.tags.occ_percent::writebacks 0.550348 # Average percentage of cache occupancy 819system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.005202 # Average percentage of cache occupancy 820system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.006486 # Average percentage of cache occupancy 821system.cpu.l2cache.tags.occ_percent::cpu.inst 0.435248 # Average percentage of cache occupancy 822system.cpu.l2cache.tags.occ_percent::total 0.997285 # Average percentage of cache occupancy 823system.cpu.l2cache.tags.occ_task_id_blocks::1023 346 # Occupied blocks per task id 824system.cpu.l2cache.tags.occ_task_id_blocks::1024 62873 # Occupied blocks per task id 825system.cpu.l2cache.tags.age_task_id_blocks_1023::4 346 # Occupied blocks per task id 826system.cpu.l2cache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id 827system.cpu.l2cache.tags.age_task_id_blocks_1024::1 513 # Occupied blocks per task id 828system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2402 # Occupied blocks per task id 829system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5577 # Occupied blocks per task id 830system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54331 # Occupied blocks per task id 831system.cpu.l2cache.tags.occ_task_id_percent::1023 0.005280 # Percentage of cache occupancy per task id 832system.cpu.l2cache.tags.occ_task_id_percent::1024 0.959366 # Percentage of cache occupancy per task id 833system.cpu.l2cache.tags.tag_accesses 371551924 # Number of tag accesses 834system.cpu.l2cache.tags.data_accesses 371551924 # Number of data accesses 835system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 967297 # number of ReadReq hits 836system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 281175 # number of ReadReq hits 837system.cpu.l2cache.ReadReq_hits::cpu.inst 31858848 # number of ReadReq hits 838system.cpu.l2cache.ReadReq_hits::total 33107320 # number of ReadReq hits 839system.cpu.l2cache.Writeback_hits::writebacks 8593512 # number of Writeback hits 840system.cpu.l2cache.Writeback_hits::total 8593512 # number of Writeback hits 841system.cpu.l2cache.WriteInvalidateReq_hits::cpu.inst 704117 # number of WriteInvalidateReq hits 842system.cpu.l2cache.WriteInvalidateReq_hits::total 704117 # number of WriteInvalidateReq hits 843system.cpu.l2cache.UpgradeReq_hits::cpu.inst 10834 # number of UpgradeReq hits 844system.cpu.l2cache.UpgradeReq_hits::total 10834 # number of UpgradeReq hits 845system.cpu.l2cache.ReadExReq_hits::cpu.inst 1670528 # number of ReadExReq hits 846system.cpu.l2cache.ReadExReq_hits::total 1670528 # number of ReadExReq hits 847system.cpu.l2cache.demand_hits::cpu.dtb.walker 967297 # number of demand (read+write) hits 848system.cpu.l2cache.demand_hits::cpu.itb.walker 281175 # number of demand (read+write) hits 849system.cpu.l2cache.demand_hits::cpu.inst 33529376 # number of demand (read+write) hits 850system.cpu.l2cache.demand_hits::total 34777848 # number of demand (read+write) hits 851system.cpu.l2cache.overall_hits::cpu.dtb.walker 967297 # number of overall hits 852system.cpu.l2cache.overall_hits::cpu.itb.walker 281175 # number of overall hits 853system.cpu.l2cache.overall_hits::cpu.inst 33529376 # number of overall hits 854system.cpu.l2cache.overall_hits::total 34777848 # number of overall hits 855system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 6169 # number of ReadReq misses 856system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5233 # number of ReadReq misses 857system.cpu.l2cache.ReadReq_misses::cpu.inst 442678 # number of ReadReq misses 858system.cpu.l2cache.ReadReq_misses::total 454080 # number of ReadReq misses 859system.cpu.l2cache.WriteInvalidateReq_misses::cpu.inst 540744 # number of WriteInvalidateReq misses 860system.cpu.l2cache.WriteInvalidateReq_misses::total 540744 # number of WriteInvalidateReq misses 861system.cpu.l2cache.UpgradeReq_misses::cpu.inst 38969 # number of UpgradeReq misses 862system.cpu.l2cache.UpgradeReq_misses::total 38969 # number of UpgradeReq misses 863system.cpu.l2cache.SCUpgradeReq_misses::cpu.inst 2 # number of SCUpgradeReq misses 864system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses 865system.cpu.l2cache.ReadExReq_misses::cpu.inst 719318 # number of ReadExReq misses 866system.cpu.l2cache.ReadExReq_misses::total 719318 # number of ReadExReq misses 867system.cpu.l2cache.demand_misses::cpu.dtb.walker 6169 # number of demand (read+write) misses 868system.cpu.l2cache.demand_misses::cpu.itb.walker 5233 # number of demand (read+write) misses 869system.cpu.l2cache.demand_misses::cpu.inst 1161996 # number of demand (read+write) misses 870system.cpu.l2cache.demand_misses::total 1173398 # number of demand (read+write) misses 871system.cpu.l2cache.overall_misses::cpu.dtb.walker 6169 # number of overall misses 872system.cpu.l2cache.overall_misses::cpu.itb.walker 5233 # number of overall misses 873system.cpu.l2cache.overall_misses::cpu.inst 1161996 # number of overall misses 874system.cpu.l2cache.overall_misses::total 1173398 # number of overall misses 875system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 490563500 # number of ReadReq miss cycles 876system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 420808500 # number of ReadReq miss cycles 877system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 33361514961 # number of ReadReq miss cycles 878system.cpu.l2cache.ReadReq_miss_latency::total 34272886961 # number of ReadReq miss cycles 879system.cpu.l2cache.WriteInvalidateReq_miss_latency::cpu.inst 4498807 # number of WriteInvalidateReq miss cycles 880system.cpu.l2cache.WriteInvalidateReq_miss_latency::total 4498807 # number of WriteInvalidateReq miss cycles 881system.cpu.l2cache.UpgradeReq_miss_latency::cpu.inst 431949947 # number of UpgradeReq miss cycles 882system.cpu.l2cache.UpgradeReq_miss_latency::total 431949947 # number of UpgradeReq miss cycles 883system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.inst 144500 # number of SCUpgradeReq miss cycles 884system.cpu.l2cache.SCUpgradeReq_miss_latency::total 144500 # number of SCUpgradeReq miss cycles 885system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 53534470118 # number of ReadExReq miss cycles 886system.cpu.l2cache.ReadExReq_miss_latency::total 53534470118 # number of ReadExReq miss cycles 887system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 490563500 # number of demand (read+write) miss cycles 888system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 420808500 # number of demand (read+write) miss cycles 889system.cpu.l2cache.demand_miss_latency::cpu.inst 86895985079 # number of demand (read+write) miss cycles 890system.cpu.l2cache.demand_miss_latency::total 87807357079 # number of demand (read+write) miss cycles 891system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 490563500 # number of overall miss cycles 892system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 420808500 # number of overall miss cycles 893system.cpu.l2cache.overall_miss_latency::cpu.inst 86895985079 # number of overall miss cycles 894system.cpu.l2cache.overall_miss_latency::total 87807357079 # number of overall miss cycles 895system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 973466 # number of ReadReq accesses(hits+misses) 896system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 286408 # number of ReadReq accesses(hits+misses) 897system.cpu.l2cache.ReadReq_accesses::cpu.inst 32301526 # number of ReadReq accesses(hits+misses) 898system.cpu.l2cache.ReadReq_accesses::total 33561400 # number of ReadReq accesses(hits+misses) 899system.cpu.l2cache.Writeback_accesses::writebacks 8593512 # number of Writeback accesses(hits+misses) 900system.cpu.l2cache.Writeback_accesses::total 8593512 # number of Writeback accesses(hits+misses) 901system.cpu.l2cache.WriteInvalidateReq_accesses::cpu.inst 1244861 # number of WriteInvalidateReq accesses(hits+misses) 902system.cpu.l2cache.WriteInvalidateReq_accesses::total 1244861 # number of WriteInvalidateReq accesses(hits+misses) 903system.cpu.l2cache.UpgradeReq_accesses::cpu.inst 49803 # number of UpgradeReq accesses(hits+misses) 904system.cpu.l2cache.UpgradeReq_accesses::total 49803 # number of UpgradeReq accesses(hits+misses) 905system.cpu.l2cache.SCUpgradeReq_accesses::cpu.inst 2 # number of SCUpgradeReq accesses(hits+misses) 906system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) 907system.cpu.l2cache.ReadExReq_accesses::cpu.inst 2389846 # number of ReadExReq accesses(hits+misses) 908system.cpu.l2cache.ReadExReq_accesses::total 2389846 # number of ReadExReq accesses(hits+misses) 909system.cpu.l2cache.demand_accesses::cpu.dtb.walker 973466 # number of demand (read+write) accesses 910system.cpu.l2cache.demand_accesses::cpu.itb.walker 286408 # number of demand (read+write) accesses 911system.cpu.l2cache.demand_accesses::cpu.inst 34691372 # number of demand (read+write) accesses 912system.cpu.l2cache.demand_accesses::total 35951246 # number of demand (read+write) accesses 913system.cpu.l2cache.overall_accesses::cpu.dtb.walker 973466 # number of overall (read+write) accesses 914system.cpu.l2cache.overall_accesses::cpu.itb.walker 286408 # number of overall (read+write) accesses 915system.cpu.l2cache.overall_accesses::cpu.inst 34691372 # number of overall (read+write) accesses 916system.cpu.l2cache.overall_accesses::total 35951246 # number of overall (read+write) accesses 917system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.006337 # miss rate for ReadReq accesses 918system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.018271 # miss rate for ReadReq accesses 919system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.013705 # miss rate for ReadReq accesses 920system.cpu.l2cache.ReadReq_miss_rate::total 0.013530 # miss rate for ReadReq accesses 921system.cpu.l2cache.WriteInvalidateReq_miss_rate::cpu.inst 0.434381 # miss rate for WriteInvalidateReq accesses 922system.cpu.l2cache.WriteInvalidateReq_miss_rate::total 0.434381 # miss rate for WriteInvalidateReq accesses 923system.cpu.l2cache.UpgradeReq_miss_rate::cpu.inst 0.782463 # miss rate for UpgradeReq accesses 924system.cpu.l2cache.UpgradeReq_miss_rate::total 0.782463 # miss rate for UpgradeReq accesses 925system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.inst 1 # miss rate for SCUpgradeReq accesses 926system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 927system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.300989 # miss rate for ReadExReq accesses 928system.cpu.l2cache.ReadExReq_miss_rate::total 0.300989 # miss rate for ReadExReq accesses 929system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.006337 # miss rate for demand accesses 930system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.018271 # miss rate for demand accesses 931system.cpu.l2cache.demand_miss_rate::cpu.inst 0.033495 # miss rate for demand accesses 932system.cpu.l2cache.demand_miss_rate::total 0.032639 # miss rate for demand accesses 933system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.006337 # miss rate for overall accesses 934system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.018271 # miss rate for overall accesses 935system.cpu.l2cache.overall_miss_rate::cpu.inst 0.033495 # miss rate for overall accesses 936system.cpu.l2cache.overall_miss_rate::total 0.032639 # miss rate for overall accesses 937system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 79520.748906 # average ReadReq miss latency 938system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 80414.389452 # average ReadReq miss latency 939system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 75362.938662 # average ReadReq miss latency 940system.cpu.l2cache.ReadReq_avg_miss_latency::total 75477.640418 # average ReadReq miss latency 941system.cpu.l2cache.WriteInvalidateReq_avg_miss_latency::cpu.inst 8.319661 # average WriteInvalidateReq miss latency 942system.cpu.l2cache.WriteInvalidateReq_avg_miss_latency::total 8.319661 # average WriteInvalidateReq miss latency 943system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.inst 11084.450384 # average UpgradeReq miss latency 944system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 11084.450384 # average UpgradeReq miss latency 945system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.inst 72250 # average SCUpgradeReq miss latency 946system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 72250 # average SCUpgradeReq miss latency 947system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 74423.926717 # average ReadExReq miss latency 948system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74423.926717 # average ReadExReq miss latency 949system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 79520.748906 # average overall miss latency 950system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 80414.389452 # average overall miss latency 951system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74781.655943 # average overall miss latency 952system.cpu.l2cache.demand_avg_miss_latency::total 74831.691446 # average overall miss latency 953system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 79520.748906 # average overall miss latency 954system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 80414.389452 # average overall miss latency 955system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74781.655943 # average overall miss latency 956system.cpu.l2cache.overall_avg_miss_latency::total 74831.691446 # average overall miss latency 957system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 958system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 959system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 960system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 961system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 962system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 963system.cpu.l2cache.fast_writes 0 # number of fast writes performed 964system.cpu.l2cache.cache_copies 0 # number of cache copies performed 965system.cpu.l2cache.writebacks::writebacks 1379367 # number of writebacks 966system.cpu.l2cache.writebacks::total 1379367 # number of writebacks 967system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 22 # number of ReadReq MSHR hits 968system.cpu.l2cache.ReadReq_mshr_hits::total 22 # number of ReadReq MSHR hits 969system.cpu.l2cache.demand_mshr_hits::cpu.inst 22 # number of demand (read+write) MSHR hits 970system.cpu.l2cache.demand_mshr_hits::total 22 # number of demand (read+write) MSHR hits 971system.cpu.l2cache.overall_mshr_hits::cpu.inst 22 # number of overall MSHR hits 972system.cpu.l2cache.overall_mshr_hits::total 22 # number of overall MSHR hits 973system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 6169 # number of ReadReq MSHR misses 974system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 5233 # number of ReadReq MSHR misses 975system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 442656 # number of ReadReq MSHR misses 976system.cpu.l2cache.ReadReq_mshr_misses::total 454058 # number of ReadReq MSHR misses 977system.cpu.l2cache.WriteInvalidateReq_mshr_misses::cpu.inst 540744 # number of WriteInvalidateReq MSHR misses 978system.cpu.l2cache.WriteInvalidateReq_mshr_misses::total 540744 # number of WriteInvalidateReq MSHR misses 979system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.inst 38969 # number of UpgradeReq MSHR misses 980system.cpu.l2cache.UpgradeReq_mshr_misses::total 38969 # number of UpgradeReq MSHR misses 981system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.inst 2 # number of SCUpgradeReq MSHR misses 982system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses 983system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 719318 # number of ReadExReq MSHR misses 984system.cpu.l2cache.ReadExReq_mshr_misses::total 719318 # number of ReadExReq MSHR misses 985system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 6169 # number of demand (read+write) MSHR misses 986system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 5233 # number of demand (read+write) MSHR misses 987system.cpu.l2cache.demand_mshr_misses::cpu.inst 1161974 # number of demand (read+write) MSHR misses 988system.cpu.l2cache.demand_mshr_misses::total 1173376 # number of demand (read+write) MSHR misses 989system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 6169 # number of overall MSHR misses 990system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 5233 # number of overall MSHR misses 991system.cpu.l2cache.overall_mshr_misses::cpu.inst 1161974 # number of overall MSHR misses 992system.cpu.l2cache.overall_mshr_misses::total 1173376 # number of overall MSHR misses 993system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 413632000 # number of ReadReq MSHR miss cycles 994system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 355518000 # number of ReadReq MSHR miss cycles 995system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 27784615785 # number of ReadReq MSHR miss cycles 996system.cpu.l2cache.ReadReq_mshr_miss_latency::total 28553765785 # number of ReadReq MSHR miss cycles 997system.cpu.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu.inst 12667521943 # number of WriteInvalidateReq MSHR miss cycles 998system.cpu.l2cache.WriteInvalidateReq_mshr_miss_latency::total 12667521943 # number of WriteInvalidateReq MSHR miss cycles 999system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.inst 390061961 # number of UpgradeReq MSHR miss cycles 1000system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 390061961 # number of UpgradeReq MSHR miss cycles 1001system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.inst 120500 # number of SCUpgradeReq MSHR miss cycles 1002system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 120500 # number of SCUpgradeReq MSHR miss cycles 1003system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 44297743880 # number of ReadExReq MSHR miss cycles 1004system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 44297743880 # number of ReadExReq MSHR miss cycles 1005system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 413632000 # number of demand (read+write) MSHR miss cycles 1006system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 355518000 # number of demand (read+write) MSHR miss cycles 1007system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 72082359665 # number of demand (read+write) MSHR miss cycles 1008system.cpu.l2cache.demand_mshr_miss_latency::total 72851509665 # number of demand (read+write) MSHR miss cycles 1009system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 413632000 # number of overall MSHR miss cycles 1010system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 355518000 # number of overall MSHR miss cycles 1011system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 72082359665 # number of overall MSHR miss cycles 1012system.cpu.l2cache.overall_mshr_miss_latency::total 72851509665 # number of overall MSHR miss cycles 1013system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 8006368251 # number of ReadReq MSHR uncacheable cycles 1014system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 8006368251 # number of ReadReq MSHR uncacheable cycles 1015system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.inst 5177591000 # number of WriteReq MSHR uncacheable cycles 1016system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 5177591000 # number of WriteReq MSHR uncacheable cycles 1017system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 13183959251 # number of overall MSHR uncacheable cycles 1018system.cpu.l2cache.overall_mshr_uncacheable_latency::total 13183959251 # number of overall MSHR uncacheable cycles 1019system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.006337 # mshr miss rate for ReadReq accesses 1020system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.018271 # mshr miss rate for ReadReq accesses 1021system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.013704 # mshr miss rate for ReadReq accesses 1022system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.013529 # mshr miss rate for ReadReq accesses 1023system.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu.inst 0.434381 # mshr miss rate for WriteInvalidateReq accesses 1024system.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.434381 # mshr miss rate for WriteInvalidateReq accesses 1025system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.inst 0.782463 # mshr miss rate for UpgradeReq accesses 1026system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.782463 # mshr miss rate for UpgradeReq accesses 1027system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for SCUpgradeReq accesses 1028system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 1029system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.300989 # mshr miss rate for ReadExReq accesses 1030system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.300989 # mshr miss rate for ReadExReq accesses 1031system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.006337 # mshr miss rate for demand accesses 1032system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.018271 # mshr miss rate for demand accesses 1033system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.033495 # mshr miss rate for demand accesses 1034system.cpu.l2cache.demand_mshr_miss_rate::total 0.032638 # mshr miss rate for demand accesses 1035system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.006337 # mshr miss rate for overall accesses 1036system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.018271 # mshr miss rate for overall accesses 1037system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.033495 # mshr miss rate for overall accesses 1038system.cpu.l2cache.overall_mshr_miss_rate::total 0.032638 # mshr miss rate for overall accesses 1039system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 67050.089155 # average ReadReq mshr miss latency 1040system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 67937.703038 # average ReadReq mshr miss latency 1041system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62767.963803 # average ReadReq mshr miss latency 1042system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62885.723377 # average ReadReq mshr miss latency 1043system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.inst 23426.098011 # average WriteInvalidateReq mshr miss latency 1044system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 23426.098011 # average WriteInvalidateReq mshr miss latency 1045system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.inst 10009.545049 # average UpgradeReq mshr miss latency 1046system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10009.545049 # average UpgradeReq mshr miss latency 1047system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.inst 60250 # average SCUpgradeReq mshr miss latency 1048system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 60250 # average SCUpgradeReq mshr miss latency 1049system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 61582.977042 # average ReadExReq mshr miss latency 1050system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61582.977042 # average ReadExReq mshr miss latency 1051system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 67050.089155 # average overall mshr miss latency 1052system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 67937.703038 # average overall mshr miss latency 1053system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62034.399793 # average overall mshr miss latency 1054system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62087.097116 # average overall mshr miss latency 1055system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 67050.089155 # average overall mshr miss latency 1056system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 67937.703038 # average overall mshr miss latency 1057system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62034.399793 # average overall mshr miss latency 1058system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62087.097116 # average overall mshr miss latency 1059system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 1060system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1061system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst inf # average WriteReq mshr uncacheable latency 1062system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1063system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 1064system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1065system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1066system.cpu.toL2Bus.trans_dist::ReadReq 34111380 # Transaction distribution 1067system.cpu.toL2Bus.trans_dist::ReadResp 34103268 # Transaction distribution 1068system.cpu.toL2Bus.trans_dist::WriteReq 33870 # Transaction distribution 1069system.cpu.toL2Bus.trans_dist::WriteResp 33870 # Transaction distribution 1070system.cpu.toL2Bus.trans_dist::Writeback 8593512 # Transaction distribution 1071system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 1351525 # Transaction distribution 1072system.cpu.toL2Bus.trans_dist::WriteInvalidateResp 1244861 # Transaction distribution 1073system.cpu.toL2Bus.trans_dist::UpgradeReq 49806 # Transaction distribution 1074system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution 1075system.cpu.toL2Bus.trans_dist::UpgradeResp 49808 # Transaction distribution 1076system.cpu.toL2Bus.trans_dist::ReadExReq 2389846 # Transaction distribution 1077system.cpu.toL2Bus.trans_dist::ReadExResp 2389846 # Transaction distribution 1078system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 49557548 # Packet count per connected master and slave (bytes) 1079system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 31248640 # Packet count per connected master and slave (bytes) 1080system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 695589 # Packet count per connected master and slave (bytes) 1081system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2279215 # Packet count per connected master and slave (bytes) 1082system.cpu.toL2Bus.pkt_count::total 83780992 # Packet count per connected master and slave (bytes) 1083system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1585841408 # Cumulative packet size per connected master and slave (bytes) 1084system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1267646988 # Cumulative packet size per connected master and slave (bytes) 1085system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2291264 # Cumulative packet size per connected master and slave (bytes) 1086system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 7787728 # Cumulative packet size per connected master and slave (bytes) 1087system.cpu.toL2Bus.pkt_size::total 2863567388 # Cumulative packet size per connected master and slave (bytes) 1088system.cpu.toL2Bus.snoops 571370 # Total snoops (count) 1089system.cpu.toL2Bus.snoop_fanout::samples 46410026 # Request fanout histogram 1090system.cpu.toL2Bus.snoop_fanout::mean 5.002490 # Request fanout histogram 1091system.cpu.toL2Bus.snoop_fanout::stdev 0.049834 # Request fanout histogram 1092system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1093system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1094system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1095system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 1096system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 1097system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 1098system.cpu.toL2Bus.snoop_fanout::5 46294483 99.75% 99.75% # Request fanout histogram 1099system.cpu.toL2Bus.snoop_fanout::6 115543 0.25% 100.00% # Request fanout histogram 1100system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1101system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 1102system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram 1103system.cpu.toL2Bus.snoop_fanout::total 46410026 # Request fanout histogram 1104system.cpu.toL2Bus.reqLayer0.occupancy 33063458385 # Layer occupancy (ticks) 1105system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 1106system.cpu.toL2Bus.snoopLayer0.occupancy 1149000 # Layer occupancy (ticks) 1107system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1108system.cpu.toL2Bus.respLayer0.occupancy 37204558207 # Layer occupancy (ticks) 1109system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 1110system.cpu.toL2Bus.respLayer1.occupancy 15864083234 # Layer occupancy (ticks) 1111system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 1112system.cpu.toL2Bus.respLayer2.occupancy 409855669 # Layer occupancy (ticks) 1113system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1114system.cpu.toL2Bus.respLayer3.occupancy 1306481232 # Layer occupancy (ticks) 1115system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1116system.iobus.trans_dist::ReadReq 40405 # Transaction distribution 1117system.iobus.trans_dist::ReadResp 40405 # Transaction distribution 1118system.iobus.trans_dist::WriteReq 136733 # Transaction distribution 1119system.iobus.trans_dist::WriteResp 30069 # Transaction distribution 1120system.iobus.trans_dist::WriteInvalidateResp 106664 # Transaction distribution 1121system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 48308 # Packet count per connected master and slave (bytes) 1122system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 1123system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) 1124system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) 1125system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 1126system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 1127system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 1128system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 1129system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) 1130system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 1131system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) 1132system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) 1133system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) 1134system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) 1135system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) 1136system.iobus.pkt_count_system.bridge.master::total 123190 # Packet count per connected master and slave (bytes) 1137system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231006 # Packet count per connected master and slave (bytes) 1138system.iobus.pkt_count_system.realview.ide.dma::total 231006 # Packet count per connected master and slave (bytes) 1139system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) 1140system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) 1141system.iobus.pkt_count::total 354276 # Packet count per connected master and slave (bytes) 1142system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48328 # Cumulative packet size per connected master and slave (bytes) 1143system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) 1144system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) 1145system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) 1146system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 1147system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1148system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1149system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1150system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) 1151system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1152system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) 1153system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes) 1154system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) 1155system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) 1156system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) 1157system.iobus.pkt_size_system.bridge.master::total 156320 # Cumulative packet size per connected master and slave (bytes) 1158system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334456 # Cumulative packet size per connected master and slave (bytes) 1159system.iobus.pkt_size_system.realview.ide.dma::total 7334456 # Cumulative packet size per connected master and slave (bytes) 1160system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 1161system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) 1162system.iobus.pkt_size::total 7492862 # Cumulative packet size per connected master and slave (bytes) 1163system.iobus.reqLayer0.occupancy 36706000 # Layer occupancy (ticks) 1164system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 1165system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) 1166system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 1167system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks) 1168system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 1169system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks) 1170system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 1171system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) 1172system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 1173system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) 1174system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 1175system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) 1176system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 1177system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) 1178system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 1179system.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks) 1180system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 1181system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) 1182system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 1183system.iobus.reqLayer23.occupancy 21947000 # Layer occupancy (ticks) 1184system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 1185system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks) 1186system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 1187system.iobus.reqLayer25.occupancy 32658000 # Layer occupancy (ticks) 1188system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 1189system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) 1190system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 1191system.iobus.reqLayer27.occupancy 1042384689 # Layer occupancy (ticks) 1192system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 1193system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) 1194system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) 1195system.iobus.respLayer0.occupancy 93124000 # Layer occupancy (ticks) 1196system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 1197system.iobus.respLayer3.occupancy 179052263 # Layer occupancy (ticks) 1198system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 1199system.iobus.respLayer4.occupancy 297000 # Layer occupancy (ticks) 1200system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) 1201system.iocache.tags.replacements 115484 # number of replacements 1202system.iocache.tags.tagsinuse 10.452585 # Cycle average of tags in use 1203system.iocache.tags.total_refs 3 # Total number of references to valid blocks. 1204system.iocache.tags.sampled_refs 115500 # Sample count of references to valid blocks. 1205system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. 1206system.iocache.tags.warmup_cycle 13141230176000 # Cycle when the warmup percentage was hit. 1207system.iocache.tags.occ_blocks::realview.ethernet 3.516704 # Average occupied blocks per requestor 1208system.iocache.tags.occ_blocks::realview.ide 6.935881 # Average occupied blocks per requestor 1209system.iocache.tags.occ_percent::realview.ethernet 0.219794 # Average percentage of cache occupancy 1210system.iocache.tags.occ_percent::realview.ide 0.433493 # Average percentage of cache occupancy 1211system.iocache.tags.occ_percent::total 0.653287 # Average percentage of cache occupancy 1212system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1213system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 1214system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1215system.iocache.tags.tag_accesses 1039884 # Number of tag accesses 1216system.iocache.tags.data_accesses 1039884 # Number of data accesses 1217system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses 1218system.iocache.ReadReq_misses::realview.ide 8839 # number of ReadReq misses 1219system.iocache.ReadReq_misses::total 8876 # number of ReadReq misses 1220system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 1221system.iocache.WriteReq_misses::total 3 # number of WriteReq misses 1222system.iocache.WriteInvalidateReq_misses::realview.ide 106664 # number of WriteInvalidateReq misses 1223system.iocache.WriteInvalidateReq_misses::total 106664 # number of WriteInvalidateReq misses 1224system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses 1225system.iocache.demand_misses::realview.ide 8839 # number of demand (read+write) misses 1226system.iocache.demand_misses::total 8879 # number of demand (read+write) misses 1227system.iocache.overall_misses::realview.ethernet 40 # number of overall misses 1228system.iocache.overall_misses::realview.ide 8839 # number of overall misses 1229system.iocache.overall_misses::total 8879 # number of overall misses 1230system.iocache.ReadReq_miss_latency::realview.ethernet 5485000 # number of ReadReq miss cycles 1231system.iocache.ReadReq_miss_latency::realview.ide 1924538358 # number of ReadReq miss cycles 1232system.iocache.ReadReq_miss_latency::total 1930023358 # number of ReadReq miss cycles 1233system.iocache.WriteReq_miss_latency::realview.ethernet 339000 # number of WriteReq miss cycles 1234system.iocache.WriteReq_miss_latency::total 339000 # number of WriteReq miss cycles 1235system.iocache.WriteInvalidateReq_miss_latency::realview.ide 28851084068 # number of WriteInvalidateReq miss cycles 1236system.iocache.WriteInvalidateReq_miss_latency::total 28851084068 # number of WriteInvalidateReq miss cycles 1237system.iocache.demand_miss_latency::realview.ethernet 5824000 # number of demand (read+write) miss cycles 1238system.iocache.demand_miss_latency::realview.ide 1924538358 # number of demand (read+write) miss cycles 1239system.iocache.demand_miss_latency::total 1930362358 # number of demand (read+write) miss cycles 1240system.iocache.overall_miss_latency::realview.ethernet 5824000 # number of overall miss cycles 1241system.iocache.overall_miss_latency::realview.ide 1924538358 # number of overall miss cycles 1242system.iocache.overall_miss_latency::total 1930362358 # number of overall miss cycles 1243system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) 1244system.iocache.ReadReq_accesses::realview.ide 8839 # number of ReadReq accesses(hits+misses) 1245system.iocache.ReadReq_accesses::total 8876 # number of ReadReq accesses(hits+misses) 1246system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 1247system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 1248system.iocache.WriteInvalidateReq_accesses::realview.ide 106664 # number of WriteInvalidateReq accesses(hits+misses) 1249system.iocache.WriteInvalidateReq_accesses::total 106664 # number of WriteInvalidateReq accesses(hits+misses) 1250system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses 1251system.iocache.demand_accesses::realview.ide 8839 # number of demand (read+write) accesses 1252system.iocache.demand_accesses::total 8879 # number of demand (read+write) accesses 1253system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses 1254system.iocache.overall_accesses::realview.ide 8839 # number of overall (read+write) accesses 1255system.iocache.overall_accesses::total 8879 # number of overall (read+write) accesses 1256system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 1257system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 1258system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1259system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 1260system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 1261system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses 1262system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses 1263system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses 1264system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 1265system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1266system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses 1267system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 1268system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 1269system.iocache.ReadReq_avg_miss_latency::realview.ethernet 148243.243243 # average ReadReq miss latency 1270system.iocache.ReadReq_avg_miss_latency::realview.ide 217732.589433 # average ReadReq miss latency 1271system.iocache.ReadReq_avg_miss_latency::total 217442.920009 # average ReadReq miss latency 1272system.iocache.WriteReq_avg_miss_latency::realview.ethernet 113000 # average WriteReq miss latency 1273system.iocache.WriteReq_avg_miss_latency::total 113000 # average WriteReq miss latency 1274system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 270485.675279 # average WriteInvalidateReq miss latency 1275system.iocache.WriteInvalidateReq_avg_miss_latency::total 270485.675279 # average WriteInvalidateReq miss latency 1276system.iocache.demand_avg_miss_latency::realview.ethernet 145600 # average overall miss latency 1277system.iocache.demand_avg_miss_latency::realview.ide 217732.589433 # average overall miss latency 1278system.iocache.demand_avg_miss_latency::total 217407.631265 # average overall miss latency 1279system.iocache.overall_avg_miss_latency::realview.ethernet 145600 # average overall miss latency 1280system.iocache.overall_avg_miss_latency::realview.ide 217732.589433 # average overall miss latency 1281system.iocache.overall_avg_miss_latency::total 217407.631265 # average overall miss latency 1282system.iocache.blocked_cycles::no_mshrs 225366 # number of cycles access was blocked 1283system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1284system.iocache.blocked::no_mshrs 27560 # number of cycles access was blocked 1285system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1286system.iocache.avg_blocked_cycles::no_mshrs 8.177286 # average number of cycles each access was blocked 1287system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1288system.iocache.fast_writes 0 # number of fast writes performed 1289system.iocache.cache_copies 0 # number of cache copies performed 1290system.iocache.writebacks::writebacks 106630 # number of writebacks 1291system.iocache.writebacks::total 106630 # number of writebacks 1292system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses 1293system.iocache.ReadReq_mshr_misses::realview.ide 8839 # number of ReadReq MSHR misses 1294system.iocache.ReadReq_mshr_misses::total 8876 # number of ReadReq MSHR misses 1295system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses 1296system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses 1297system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 106664 # number of WriteInvalidateReq MSHR misses 1298system.iocache.WriteInvalidateReq_mshr_misses::total 106664 # number of WriteInvalidateReq MSHR misses 1299system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses 1300system.iocache.demand_mshr_misses::realview.ide 8839 # number of demand (read+write) MSHR misses 1301system.iocache.demand_mshr_misses::total 8879 # number of demand (read+write) MSHR misses 1302system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses 1303system.iocache.overall_mshr_misses::realview.ide 8839 # number of overall MSHR misses 1304system.iocache.overall_mshr_misses::total 8879 # number of overall MSHR misses 1305system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3561000 # number of ReadReq MSHR miss cycles 1306system.iocache.ReadReq_mshr_miss_latency::realview.ide 1464798862 # number of ReadReq MSHR miss cycles 1307system.iocache.ReadReq_mshr_miss_latency::total 1468359862 # number of ReadReq MSHR miss cycles 1308system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 183000 # number of WriteReq MSHR miss cycles 1309system.iocache.WriteReq_mshr_miss_latency::total 183000 # number of WriteReq MSHR miss cycles 1310system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 23304534090 # number of WriteInvalidateReq MSHR miss cycles 1311system.iocache.WriteInvalidateReq_mshr_miss_latency::total 23304534090 # number of WriteInvalidateReq MSHR miss cycles 1312system.iocache.demand_mshr_miss_latency::realview.ethernet 3744000 # number of demand (read+write) MSHR miss cycles 1313system.iocache.demand_mshr_miss_latency::realview.ide 1464798862 # number of demand (read+write) MSHR miss cycles 1314system.iocache.demand_mshr_miss_latency::total 1468542862 # number of demand (read+write) MSHR miss cycles 1315system.iocache.overall_mshr_miss_latency::realview.ethernet 3744000 # number of overall MSHR miss cycles 1316system.iocache.overall_mshr_miss_latency::realview.ide 1464798862 # number of overall MSHR miss cycles 1317system.iocache.overall_mshr_miss_latency::total 1468542862 # number of overall MSHR miss cycles 1318system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses 1319system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 1320system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1321system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses 1322system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 1323system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses 1324system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses 1325system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses 1326system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 1327system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1328system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses 1329system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 1330system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 1331system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 96243.243243 # average ReadReq mshr miss latency 1332system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 165719.975337 # average ReadReq mshr miss latency 1333system.iocache.ReadReq_avg_mshr_miss_latency::total 165430.358495 # average ReadReq mshr miss latency 1334system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 61000 # average WriteReq mshr miss latency 1335system.iocache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency 1336system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 218485.469230 # average WriteInvalidateReq mshr miss latency 1337system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 218485.469230 # average WriteInvalidateReq mshr miss latency 1338system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 93600 # average overall mshr miss latency 1339system.iocache.demand_avg_mshr_miss_latency::realview.ide 165719.975337 # average overall mshr miss latency 1340system.iocache.demand_avg_mshr_miss_latency::total 165395.073995 # average overall mshr miss latency 1341system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 93600 # average overall mshr miss latency 1342system.iocache.overall_avg_mshr_miss_latency::realview.ide 165719.975337 # average overall mshr miss latency 1343system.iocache.overall_avg_mshr_miss_latency::total 165395.073995 # average overall mshr miss latency 1344system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1345system.membus.trans_dist::ReadReq 548979 # Transaction distribution 1346system.membus.trans_dist::ReadResp 548979 # Transaction distribution 1347system.membus.trans_dist::WriteReq 33870 # Transaction distribution 1348system.membus.trans_dist::WriteResp 33870 # Transaction distribution 1349system.membus.trans_dist::Writeback 1485997 # Transaction distribution 1350system.membus.trans_dist::WriteInvalidateReq 647215 # Transaction distribution 1351system.membus.trans_dist::WriteInvalidateResp 647215 # Transaction distribution 1352system.membus.trans_dist::UpgradeReq 39795 # Transaction distribution 1353system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution 1354system.membus.trans_dist::UpgradeResp 39797 # Transaction distribution 1355system.membus.trans_dist::ReadExReq 718688 # Transaction distribution 1356system.membus.trans_dist::ReadExResp 718688 # Transaction distribution 1357system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 123190 # Packet count per connected master and slave (bytes) 1358system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 32 # Packet count per connected master and slave (bytes) 1359system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6926 # Packet count per connected master and slave (bytes) 1360system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4994566 # Packet count per connected master and slave (bytes) 1361system.membus.pkt_count_system.cpu.l2cache.mem_side::total 5124714 # Packet count per connected master and slave (bytes) 1362system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 335466 # Packet count per connected master and slave (bytes) 1363system.membus.pkt_count_system.iocache.mem_side::total 335466 # Packet count per connected master and slave (bytes) 1364system.membus.pkt_count::total 5460180 # Packet count per connected master and slave (bytes) 1365system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 156320 # Cumulative packet size per connected master and slave (bytes) 1366system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 740 # Cumulative packet size per connected master and slave (bytes) 1367system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13852 # Cumulative packet size per connected master and slave (bytes) 1368system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 201253164 # Cumulative packet size per connected master and slave (bytes) 1369system.membus.pkt_size_system.cpu.l2cache.mem_side::total 201424076 # Cumulative packet size per connected master and slave (bytes) 1370system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14075072 # Cumulative packet size per connected master and slave (bytes) 1371system.membus.pkt_size_system.iocache.mem_side::total 14075072 # Cumulative packet size per connected master and slave (bytes) 1372system.membus.pkt_size::total 215499148 # Cumulative packet size per connected master and slave (bytes) 1373system.membus.snoops 2915 # Total snoops (count) 1374system.membus.snoop_fanout::samples 3354632 # Request fanout histogram 1375system.membus.snoop_fanout::mean 1 # Request fanout histogram 1376system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1377system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1378system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1379system.membus.snoop_fanout::1 3354632 100.00% 100.00% # Request fanout histogram 1380system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1381system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1382system.membus.snoop_fanout::min_value 1 # Request fanout histogram 1383system.membus.snoop_fanout::max_value 1 # Request fanout histogram 1384system.membus.snoop_fanout::total 3354632 # Request fanout histogram 1385system.membus.reqLayer0.occupancy 113785000 # Layer occupancy (ticks) 1386system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 1387system.membus.reqLayer1.occupancy 23328 # Layer occupancy (ticks) 1388system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 1389system.membus.reqLayer2.occupancy 5606499 # Layer occupancy (ticks) 1390system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 1391system.membus.reqLayer5.occupancy 21358745741 # Layer occupancy (ticks) 1392system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 1393system.membus.respLayer2.occupancy 12484485177 # Layer occupancy (ticks) 1394system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 1395system.membus.respLayer3.occupancy 186617737 # Layer occupancy (ticks) 1396system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 1397system.realview.ethernet.txBytes 966 # Bytes Transmitted 1398system.realview.ethernet.txPackets 3 # Number of Packets Transmitted 1399system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device 1400system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device 1401system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 1402system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1403system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1404system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 1405system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 1406system.realview.ethernet.totBandwidth 149 # Total Bandwidth (bits/s) 1407system.realview.ethernet.totPackets 3 # Total Packets 1408system.realview.ethernet.totBytes 966 # Total Bytes 1409system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) 1410system.realview.ethernet.txBandwidth 149 # Transmit Bandwidth (bits/s) 1411system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) 1412system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 1413system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post 1414system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 1415system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 1416system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post 1417system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 1418system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 1419system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post 1420system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 1421system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 1422system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post 1423system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 1424system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 1425system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post 1426system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 1427system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 1428system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post 1429system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 1430system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 1431system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 1432system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 1433system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 1434system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 1435system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 1436system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 1437system.realview.ethernet.postedInterrupts 13 # number of posts to CPU 1438system.realview.ethernet.droppedPackets 0 # number of packets dropped 1439 1440---------- End Simulation Statistics ---------- 1441