stats.txt revision 11570
110515SAli.Saidi@ARM.com 210515SAli.Saidi@ARM.com---------- Begin Simulation Statistics ---------- 311570SCurtis.Dunham@arm.comsim_seconds 47.445489 # Number of seconds simulated 411570SCurtis.Dunham@arm.comsim_ticks 47445489241000 # Number of ticks simulated 511570SCurtis.Dunham@arm.comfinal_tick 47445489241000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 610515SAli.Saidi@ARM.comsim_freq 1000000000000 # Frequency of simulated ticks 711570SCurtis.Dunham@arm.comhost_inst_rate 208966 # Simulator instruction rate (inst/s) 811570SCurtis.Dunham@arm.comhost_op_rate 245756 # Simulator op (including micro ops) rate (op/s) 911570SCurtis.Dunham@arm.comhost_tick_rate 10881126125 # Simulator tick rate (ticks/s) 1011570SCurtis.Dunham@arm.comhost_mem_usage 759660 # Number of bytes of host memory used 1111570SCurtis.Dunham@arm.comhost_seconds 4360.35 # Real time elapsed on the host 1211570SCurtis.Dunham@arm.comsim_insts 911162440 # Number of instructions simulated 1311570SCurtis.Dunham@arm.comsim_ops 1071583187 # Number of ops (including micro ops) simulated 1410515SAli.Saidi@ARM.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1510515SAli.Saidi@ARM.comsystem.clk_domain.clock 1000 # Clock period in ticks 1611570SCurtis.Dunham@arm.comsystem.physmem.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states 1711570SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu0.dtb.walker 163648 # Number of bytes read from this memory 1811570SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu0.itb.walker 157696 # Number of bytes read from this memory 1911570SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu0.inst 8375360 # Number of bytes read from this memory 2011570SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu0.data 16685256 # Number of bytes read from this memory 2111570SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu0.l2cache.prefetcher 18550592 # Number of bytes read from this memory 2211570SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu1.dtb.walker 100224 # Number of bytes read from this memory 2311570SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu1.itb.walker 74048 # Number of bytes read from this memory 2411570SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu1.inst 2844864 # Number of bytes read from this memory 2511570SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu1.data 7994832 # Number of bytes read from this memory 2611570SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu1.l2cache.prefetcher 10895744 # Number of bytes read from this memory 2711570SCurtis.Dunham@arm.comsystem.physmem.bytes_read::realview.ide 436800 # Number of bytes read from this memory 2811570SCurtis.Dunham@arm.comsystem.physmem.bytes_read::total 66279064 # Number of bytes read from this memory 2911570SCurtis.Dunham@arm.comsystem.physmem.bytes_inst_read::cpu0.inst 8375360 # Number of instructions bytes read from this memory 3011570SCurtis.Dunham@arm.comsystem.physmem.bytes_inst_read::cpu1.inst 2844864 # Number of instructions bytes read from this memory 3111570SCurtis.Dunham@arm.comsystem.physmem.bytes_inst_read::total 11220224 # Number of instructions bytes read from this memory 3211570SCurtis.Dunham@arm.comsystem.physmem.bytes_written::writebacks 78621824 # Number of bytes written to this memory 3310827Sandreas.hansson@arm.comsystem.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory 3410636Snilay@cs.wisc.edusystem.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory 3511570SCurtis.Dunham@arm.comsystem.physmem.bytes_written::total 78642408 # Number of bytes written to this memory 3611570SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu0.dtb.walker 2557 # Number of read requests responded to by this memory 3711570SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu0.itb.walker 2464 # Number of read requests responded to by this memory 3811570SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu0.inst 130865 # Number of read requests responded to by this memory 3911570SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu0.data 260720 # Number of read requests responded to by this memory 4011570SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu0.l2cache.prefetcher 289853 # Number of read requests responded to by this memory 4111570SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu1.dtb.walker 1566 # Number of read requests responded to by this memory 4211570SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu1.itb.walker 1157 # Number of read requests responded to by this memory 4311570SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu1.inst 44451 # Number of read requests responded to by this memory 4411570SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu1.data 124932 # Number of read requests responded to by this memory 4511570SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu1.l2cache.prefetcher 170246 # Number of read requests responded to by this memory 4611570SCurtis.Dunham@arm.comsystem.physmem.num_reads::realview.ide 6825 # Number of read requests responded to by this memory 4711570SCurtis.Dunham@arm.comsystem.physmem.num_reads::total 1035636 # Number of read requests responded to by this memory 4811570SCurtis.Dunham@arm.comsystem.physmem.num_writes::writebacks 1228466 # Number of write requests responded to by this memory 4910827Sandreas.hansson@arm.comsystem.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory 5010636Snilay@cs.wisc.edusystem.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory 5111570SCurtis.Dunham@arm.comsystem.physmem.num_writes::total 1231040 # Number of write requests responded to by this memory 5211570SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu0.dtb.walker 3449 # Total read bandwidth from this memory (bytes/s) 5311570SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu0.itb.walker 3324 # Total read bandwidth from this memory (bytes/s) 5411570SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu0.inst 176526 # Total read bandwidth from this memory (bytes/s) 5511570SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu0.data 351672 # Total read bandwidth from this memory (bytes/s) 5611570SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu0.l2cache.prefetcher 390987 # Total read bandwidth from this memory (bytes/s) 5711570SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu1.dtb.walker 2112 # Total read bandwidth from this memory (bytes/s) 5811570SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu1.itb.walker 1561 # Total read bandwidth from this memory (bytes/s) 5911570SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu1.inst 59961 # Total read bandwidth from this memory (bytes/s) 6011570SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu1.data 168506 # Total read bandwidth from this memory (bytes/s) 6111570SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu1.l2cache.prefetcher 229648 # Total read bandwidth from this memory (bytes/s) 6211570SCurtis.Dunham@arm.comsystem.physmem.bw_read::realview.ide 9206 # Total read bandwidth from this memory (bytes/s) 6311570SCurtis.Dunham@arm.comsystem.physmem.bw_read::total 1396952 # Total read bandwidth from this memory (bytes/s) 6411570SCurtis.Dunham@arm.comsystem.physmem.bw_inst_read::cpu0.inst 176526 # Instruction read bandwidth from this memory (bytes/s) 6511570SCurtis.Dunham@arm.comsystem.physmem.bw_inst_read::cpu1.inst 59961 # Instruction read bandwidth from this memory (bytes/s) 6611570SCurtis.Dunham@arm.comsystem.physmem.bw_inst_read::total 236487 # Instruction read bandwidth from this memory (bytes/s) 6711570SCurtis.Dunham@arm.comsystem.physmem.bw_write::writebacks 1657098 # Write bandwidth from this memory (bytes/s) 6811570SCurtis.Dunham@arm.comsystem.physmem.bw_write::cpu0.data 434 # Write bandwidth from this memory (bytes/s) 6910636Snilay@cs.wisc.edusystem.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) 7011570SCurtis.Dunham@arm.comsystem.physmem.bw_write::total 1657532 # Write bandwidth from this memory (bytes/s) 7111570SCurtis.Dunham@arm.comsystem.physmem.bw_total::writebacks 1657098 # Total bandwidth to/from this memory (bytes/s) 7211570SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu0.dtb.walker 3449 # Total bandwidth to/from this memory (bytes/s) 7311570SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu0.itb.walker 3324 # Total bandwidth to/from this memory (bytes/s) 7411570SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu0.inst 176526 # Total bandwidth to/from this memory (bytes/s) 7511570SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu0.data 352106 # Total bandwidth to/from this memory (bytes/s) 7611570SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu0.l2cache.prefetcher 390987 # Total bandwidth to/from this memory (bytes/s) 7711570SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu1.dtb.walker 2112 # Total bandwidth to/from this memory (bytes/s) 7811570SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu1.itb.walker 1561 # Total bandwidth to/from this memory (bytes/s) 7911570SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu1.inst 59961 # Total bandwidth to/from this memory (bytes/s) 8011570SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu1.data 168506 # Total bandwidth to/from this memory (bytes/s) 8111570SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu1.l2cache.prefetcher 229648 # Total bandwidth to/from this memory (bytes/s) 8211570SCurtis.Dunham@arm.comsystem.physmem.bw_total::realview.ide 9206 # Total bandwidth to/from this memory (bytes/s) 8311570SCurtis.Dunham@arm.comsystem.physmem.bw_total::total 3054484 # Total bandwidth to/from this memory (bytes/s) 8411570SCurtis.Dunham@arm.comsystem.physmem.readReqs 1035636 # Number of read requests accepted 8511570SCurtis.Dunham@arm.comsystem.physmem.writeReqs 1231040 # Number of write requests accepted 8611570SCurtis.Dunham@arm.comsystem.physmem.readBursts 1035636 # Number of DRAM read bursts, including those serviced by the write queue 8711570SCurtis.Dunham@arm.comsystem.physmem.writeBursts 1231040 # Number of DRAM write bursts, including those merged in the write queue 8811570SCurtis.Dunham@arm.comsystem.physmem.bytesReadDRAM 66252160 # Total number of bytes read from DRAM 8911570SCurtis.Dunham@arm.comsystem.physmem.bytesReadWrQ 28544 # Total number of bytes read from write queue 9011570SCurtis.Dunham@arm.comsystem.physmem.bytesWritten 78640192 # Total number of bytes written to DRAM 9111570SCurtis.Dunham@arm.comsystem.physmem.bytesReadSys 66279064 # Total read bytes from the system interface side 9211570SCurtis.Dunham@arm.comsystem.physmem.bytesWrittenSys 78642408 # Total written bytes from the system interface side 9311570SCurtis.Dunham@arm.comsystem.physmem.servicedByWrQ 446 # Number of DRAM read bursts serviced by the write queue 9411570SCurtis.Dunham@arm.comsystem.physmem.mergedWrBursts 2268 # Number of DRAM write bursts merged with an existing one 9511336Sandreas.hansson@arm.comsystem.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 9611570SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::0 59521 # Per bank write bursts 9711570SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::1 66808 # Per bank write bursts 9811570SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::2 62154 # Per bank write bursts 9911570SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::3 70128 # Per bank write bursts 10011570SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::4 60732 # Per bank write bursts 10111570SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::5 72109 # Per bank write bursts 10211570SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::6 58717 # Per bank write bursts 10311570SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::7 62140 # Per bank write bursts 10411570SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::8 50595 # Per bank write bursts 10511570SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::9 107916 # Per bank write bursts 10611570SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::10 54809 # Per bank write bursts 10711570SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::11 63010 # Per bank write bursts 10811570SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::12 57730 # Per bank write bursts 10911570SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::13 64314 # Per bank write bursts 11011570SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::14 61474 # Per bank write bursts 11111570SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::15 63033 # Per bank write bursts 11211570SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::0 75175 # Per bank write bursts 11311570SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::1 80913 # Per bank write bursts 11411570SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::2 75568 # Per bank write bursts 11511570SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::3 82272 # Per bank write bursts 11611570SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::4 75546 # Per bank write bursts 11711570SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::5 83102 # Per bank write bursts 11811570SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::6 75765 # Per bank write bursts 11911570SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::7 76740 # Per bank write bursts 12011570SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::8 69114 # Per bank write bursts 12111570SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::9 73138 # Per bank write bursts 12211570SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::10 71733 # Per bank write bursts 12311570SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::11 77960 # Per bank write bursts 12411570SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::12 74616 # Per bank write bursts 12511570SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::13 78881 # Per bank write bursts 12611570SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::14 78631 # Per bank write bursts 12711570SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::15 79599 # Per bank write bursts 12810515SAli.Saidi@ARM.comsystem.physmem.numRdRetry 0 # Number of times read queue was full causing retry 12911570SCurtis.Dunham@arm.comsystem.physmem.numWrRetry 48 # Number of times write queue was full causing retry 13011570SCurtis.Dunham@arm.comsystem.physmem.totGap 47445487151500 # Total gap between requests 13110515SAli.Saidi@ARM.comsystem.physmem.readPktSize::0 0 # Read request sizes (log2) 13210515SAli.Saidi@ARM.comsystem.physmem.readPktSize::1 0 # Read request sizes (log2) 13310515SAli.Saidi@ARM.comsystem.physmem.readPktSize::2 0 # Read request sizes (log2) 13410827Sandreas.hansson@arm.comsystem.physmem.readPktSize::3 25 # Read request sizes (log2) 13510515SAli.Saidi@ARM.comsystem.physmem.readPktSize::4 5 # Read request sizes (log2) 13610515SAli.Saidi@ARM.comsystem.physmem.readPktSize::5 0 # Read request sizes (log2) 13711570SCurtis.Dunham@arm.comsystem.physmem.readPktSize::6 1035606 # Read request sizes (log2) 13810515SAli.Saidi@ARM.comsystem.physmem.writePktSize::0 0 # Write request sizes (log2) 13910515SAli.Saidi@ARM.comsystem.physmem.writePktSize::1 0 # Write request sizes (log2) 14010515SAli.Saidi@ARM.comsystem.physmem.writePktSize::2 2 # Write request sizes (log2) 14110827Sandreas.hansson@arm.comsystem.physmem.writePktSize::3 2572 # Write request sizes (log2) 14210515SAli.Saidi@ARM.comsystem.physmem.writePktSize::4 0 # Write request sizes (log2) 14310515SAli.Saidi@ARM.comsystem.physmem.writePktSize::5 0 # Write request sizes (log2) 14411570SCurtis.Dunham@arm.comsystem.physmem.writePktSize::6 1228466 # Write request sizes (log2) 14511570SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::0 692790 # What read queue length does an incoming req see 14611570SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::1 121307 # What read queue length does an incoming req see 14711570SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::2 45775 # What read queue length does an incoming req see 14811570SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::3 35632 # What read queue length does an incoming req see 14911570SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::4 30940 # What read queue length does an incoming req see 15011570SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::5 28399 # What read queue length does an incoming req see 15111570SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::6 26620 # What read queue length does an incoming req see 15211570SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::7 23199 # What read queue length does an incoming req see 15311570SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::8 20889 # What read queue length does an incoming req see 15411570SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::9 3694 # What read queue length does an incoming req see 15511570SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::10 1663 # What read queue length does an incoming req see 15611570SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::11 1197 # What read queue length does an incoming req see 15711570SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::12 944 # What read queue length does an incoming req see 15811570SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::13 702 # What read queue length does an incoming req see 15911570SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::14 419 # What read queue length does an incoming req see 16011570SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::15 350 # What read queue length does an incoming req see 16111570SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::16 273 # What read queue length does an incoming req see 16211570SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::17 228 # What read queue length does an incoming req see 16311570SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::18 102 # What read queue length does an incoming req see 16411570SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::19 60 # What read queue length does an incoming req see 16511502SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::20 6 # What read queue length does an incoming req see 16611570SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see 16711353Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 16811353Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 16911353Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 17010515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 17110515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 17210515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 17310515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 17410515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 17510515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 17610515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 17710515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 17810515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 17910515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 18010515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 18110515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 18210515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 18310515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 18410515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 18510515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 18610515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 18710515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 18810515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 18910515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 19010515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 19110515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 19211570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::15 27376 # What write queue length does an incoming req see 19311570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::16 35697 # What write queue length does an incoming req see 19411570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::17 51705 # What write queue length does an incoming req see 19511570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::18 59824 # What write queue length does an incoming req see 19611570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::19 65779 # What write queue length does an incoming req see 19711570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::20 68512 # What write queue length does an incoming req see 19811570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::21 70877 # What write queue length does an incoming req see 19911570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::22 72860 # What write queue length does an incoming req see 20011570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::23 75714 # What write queue length does an incoming req see 20111570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::24 75511 # What write queue length does an incoming req see 20211570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::25 79365 # What write queue length does an incoming req see 20311570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::26 82384 # What write queue length does an incoming req see 20411570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::27 78677 # What write queue length does an incoming req see 20511570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::28 77306 # What write queue length does an incoming req see 20611570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::29 82372 # What write queue length does an incoming req see 20711570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::30 73265 # What write queue length does an incoming req see 20811570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::31 67472 # What write queue length does an incoming req see 20911570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::32 64363 # What write queue length does an incoming req see 21011570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::33 3236 # What write queue length does an incoming req see 21111570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::34 2482 # What write queue length does an incoming req see 21211570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::35 1926 # What write queue length does an incoming req see 21311570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::36 1455 # What write queue length does an incoming req see 21411570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::37 1166 # What write queue length does an incoming req see 21511570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::38 922 # What write queue length does an incoming req see 21611570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::39 878 # What write queue length does an incoming req see 21711570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::40 663 # What write queue length does an incoming req see 21811570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::41 558 # What write queue length does an incoming req see 21911570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::42 539 # What write queue length does an incoming req see 22011570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::43 435 # What write queue length does an incoming req see 22111570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::44 477 # What write queue length does an incoming req see 22211570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::45 423 # What write queue length does an incoming req see 22311570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::46 525 # What write queue length does an incoming req see 22411570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::47 457 # What write queue length does an incoming req see 22511570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::48 414 # What write queue length does an incoming req see 22611570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::49 431 # What write queue length does an incoming req see 22711570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::50 338 # What write queue length does an incoming req see 22811570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::51 283 # What write queue length does an incoming req see 22911570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::52 266 # What write queue length does an incoming req see 23011570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::53 273 # What write queue length does an incoming req see 23111570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::54 259 # What write queue length does an incoming req see 23211570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::55 245 # What write queue length does an incoming req see 23311570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::56 169 # What write queue length does an incoming req see 23411570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::57 155 # What write queue length does an incoming req see 23511570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::58 130 # What write queue length does an incoming req see 23611570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::59 138 # What write queue length does an incoming req see 23711570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::60 111 # What write queue length does an incoming req see 23811570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::61 131 # What write queue length does an incoming req see 23911570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::62 69 # What write queue length does an incoming req see 24011570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::63 144 # What write queue length does an incoming req see 24111570SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::samples 1012110 # Bytes accessed per row activation 24211570SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::mean 143.157878 # Bytes accessed per row activation 24311570SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::gmean 97.072288 # Bytes accessed per row activation 24411570SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::stdev 192.644368 # Bytes accessed per row activation 24511570SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::0-127 686114 67.79% 67.79% # Bytes accessed per row activation 24611570SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::128-255 195882 19.35% 87.14% # Bytes accessed per row activation 24711570SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::256-383 47037 4.65% 91.79% # Bytes accessed per row activation 24811570SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::384-511 20980 2.07% 93.86% # Bytes accessed per row activation 24911570SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::512-639 15295 1.51% 95.38% # Bytes accessed per row activation 25011570SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::640-767 9865 0.97% 96.35% # Bytes accessed per row activation 25111570SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::768-895 6724 0.66% 97.01% # Bytes accessed per row activation 25211570SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::896-1023 5499 0.54% 97.56% # Bytes accessed per row activation 25311570SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::1024-1151 24714 2.44% 100.00% # Bytes accessed per row activation 25411570SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::total 1012110 # Bytes accessed per row activation 25511570SCurtis.Dunham@arm.comsystem.physmem.rdPerTurnAround::samples 60277 # Reads before turning the bus around for writes 25611570SCurtis.Dunham@arm.comsystem.physmem.rdPerTurnAround::mean 17.173764 # Reads before turning the bus around for writes 25711570SCurtis.Dunham@arm.comsystem.physmem.rdPerTurnAround::stdev 160.670576 # Reads before turning the bus around for writes 25811570SCurtis.Dunham@arm.comsystem.physmem.rdPerTurnAround::0-1023 60274 100.00% 100.00% # Reads before turning the bus around for writes 25911502SCurtis.Dunham@arm.comsystem.physmem.rdPerTurnAround::1024-2047 1 0.00% 100.00% # Reads before turning the bus around for writes 26011353Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::25600-26623 1 0.00% 100.00% # Reads before turning the bus around for writes 26111353Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::29696-30719 1 0.00% 100.00% # Reads before turning the bus around for writes 26211570SCurtis.Dunham@arm.comsystem.physmem.rdPerTurnAround::total 60277 # Reads before turning the bus around for writes 26311570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::samples 60277 # Writes before turning the bus around for reads 26411570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::mean 20.385105 # Writes before turning the bus around for reads 26511570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::gmean 18.691366 # Writes before turning the bus around for reads 26611570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::stdev 13.394945 # Writes before turning the bus around for reads 26711570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::16-19 52026 86.31% 86.31% # Writes before turning the bus around for reads 26811570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::20-23 2335 3.87% 90.19% # Writes before turning the bus around for reads 26911570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::24-27 778 1.29% 91.48% # Writes before turning the bus around for reads 27011570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::28-31 614 1.02% 92.49% # Writes before turning the bus around for reads 27111570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::32-35 994 1.65% 94.14% # Writes before turning the bus around for reads 27211570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::36-39 490 0.81% 94.96% # Writes before turning the bus around for reads 27311570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::40-43 334 0.55% 95.51% # Writes before turning the bus around for reads 27411570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::44-47 282 0.47% 95.98% # Writes before turning the bus around for reads 27511570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::48-51 206 0.34% 96.32% # Writes before turning the bus around for reads 27611570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::52-55 170 0.28% 96.60% # Writes before turning the bus around for reads 27711570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::56-59 135 0.22% 96.83% # Writes before turning the bus around for reads 27811570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::60-63 158 0.26% 97.09% # Writes before turning the bus around for reads 27911570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::64-67 477 0.79% 97.88% # Writes before turning the bus around for reads 28011570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::68-71 137 0.23% 98.11% # Writes before turning the bus around for reads 28111570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::72-75 123 0.20% 98.31% # Writes before turning the bus around for reads 28211570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::76-79 110 0.18% 98.49% # Writes before turning the bus around for reads 28311570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::80-83 87 0.14% 98.64% # Writes before turning the bus around for reads 28411570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::84-87 84 0.14% 98.78% # Writes before turning the bus around for reads 28511570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::88-91 91 0.15% 98.93% # Writes before turning the bus around for reads 28611570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::92-95 102 0.17% 99.10% # Writes before turning the bus around for reads 28711570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::96-99 72 0.12% 99.22% # Writes before turning the bus around for reads 28811570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::100-103 71 0.12% 99.33% # Writes before turning the bus around for reads 28911570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::104-107 64 0.11% 99.44% # Writes before turning the bus around for reads 29011570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::108-111 59 0.10% 99.54% # Writes before turning the bus around for reads 29111570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::112-115 43 0.07% 99.61% # Writes before turning the bus around for reads 29211570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::116-119 45 0.07% 99.68% # Writes before turning the bus around for reads 29311570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::120-123 41 0.07% 99.75% # Writes before turning the bus around for reads 29411570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::124-127 40 0.07% 99.82% # Writes before turning the bus around for reads 29511570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::128-131 47 0.08% 99.90% # Writes before turning the bus around for reads 29611570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::132-135 20 0.03% 99.93% # Writes before turning the bus around for reads 29711570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::136-139 11 0.02% 99.95% # Writes before turning the bus around for reads 29811570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::140-143 5 0.01% 99.96% # Writes before turning the bus around for reads 29911570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::144-147 4 0.01% 99.96% # Writes before turning the bus around for reads 30011570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::148-151 1 0.00% 99.97% # Writes before turning the bus around for reads 30111502SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::152-155 2 0.00% 99.97% # Writes before turning the bus around for reads 30211570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::156-159 4 0.01% 99.98% # Writes before turning the bus around for reads 30311570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::160-163 8 0.01% 99.99% # Writes before turning the bus around for reads 30411570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::168-171 1 0.00% 99.99% # Writes before turning the bus around for reads 30511570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::172-175 4 0.01% 100.00% # Writes before turning the bus around for reads 30611570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::180-183 1 0.00% 100.00% # Writes before turning the bus around for reads 30711570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::184-187 1 0.00% 100.00% # Writes before turning the bus around for reads 30811570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::total 60277 # Writes before turning the bus around for reads 30911570SCurtis.Dunham@arm.comsystem.physmem.totQLat 35377622933 # Total ticks spent queuing 31011570SCurtis.Dunham@arm.comsystem.physmem.totMemAccLat 54787435433 # Total ticks spent from burst creation until serviced by the DRAM 31111570SCurtis.Dunham@arm.comsystem.physmem.totBusLat 5175950000 # Total ticks spent in databus transfers 31211570SCurtis.Dunham@arm.comsystem.physmem.avgQLat 34175.00 # Average queueing delay per DRAM burst 31310515SAli.Saidi@ARM.comsystem.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 31411570SCurtis.Dunham@arm.comsystem.physmem.avgMemAccLat 52925.00 # Average memory access latency per DRAM burst 31511570SCurtis.Dunham@arm.comsystem.physmem.avgRdBW 1.40 # Average DRAM read bandwidth in MiByte/s 31611570SCurtis.Dunham@arm.comsystem.physmem.avgWrBW 1.66 # Average achieved write bandwidth in MiByte/s 31711570SCurtis.Dunham@arm.comsystem.physmem.avgRdBWSys 1.40 # Average system read bandwidth in MiByte/s 31811570SCurtis.Dunham@arm.comsystem.physmem.avgWrBWSys 1.66 # Average system write bandwidth in MiByte/s 31910515SAli.Saidi@ARM.comsystem.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 32011441Sandreas.hansson@arm.comsystem.physmem.busUtil 0.02 # Data bus utilization in percentage 32111353Sandreas.hansson@arm.comsystem.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads 32211441Sandreas.hansson@arm.comsystem.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes 32311502SCurtis.Dunham@arm.comsystem.physmem.avgRdQLen 1.15 # Average read queue length when enqueuing 32411570SCurtis.Dunham@arm.comsystem.physmem.avgWrQLen 27.61 # Average write queue length when enqueuing 32511570SCurtis.Dunham@arm.comsystem.physmem.readRowHits 780044 # Number of row buffer hits during reads 32611570SCurtis.Dunham@arm.comsystem.physmem.writeRowHits 471783 # Number of row buffer hits during writes 32711570SCurtis.Dunham@arm.comsystem.physmem.readRowHitRate 75.35 # Row buffer hit rate for reads 32811570SCurtis.Dunham@arm.comsystem.physmem.writeRowHitRate 38.39 # Row buffer hit rate for writes 32911570SCurtis.Dunham@arm.comsystem.physmem.avgGap 20931746.38 # Average gap between requests 33011570SCurtis.Dunham@arm.comsystem.physmem.pageHitRate 55.29 # Row buffer hit rate, read and write combined 33111570SCurtis.Dunham@arm.comsystem.physmem_0.actEnergy 3937837680 # Energy for activate commands per rank (pJ) 33211570SCurtis.Dunham@arm.comsystem.physmem_0.preEnergy 2148621750 # Energy for precharge commands per rank (pJ) 33311570SCurtis.Dunham@arm.comsystem.physmem_0.readEnergy 3995955600 # Energy for read commands per rank (pJ) 33411570SCurtis.Dunham@arm.comsystem.physmem_0.writeEnergy 4050479520 # Energy for write commands per rank (pJ) 33511570SCurtis.Dunham@arm.comsystem.physmem_0.refreshEnergy 3098908325760 # Energy for refresh commands per rank (pJ) 33611570SCurtis.Dunham@arm.comsystem.physmem_0.actBackEnergy 1191842451045 # Energy for active background per rank (pJ) 33711570SCurtis.Dunham@arm.comsystem.physmem_0.preBackEnergy 27421814259750 # Energy for precharge background per rank (pJ) 33811570SCurtis.Dunham@arm.comsystem.physmem_0.totalEnergy 31726697931105 # Total energy per rank (pJ) 33911570SCurtis.Dunham@arm.comsystem.physmem_0.averagePower 668.697958 # Core power per rank (mW) 34011570SCurtis.Dunham@arm.comsystem.physmem_0.memoryStateTime::IDLE 45618359398995 # Time in different power states 34111570SCurtis.Dunham@arm.comsystem.physmem_0.memoryStateTime::REF 1584308960000 # Time in different power states 34210628Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 34311570SCurtis.Dunham@arm.comsystem.physmem_0.memoryStateTime::ACT 242820245005 # Time in different power states 34410628Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 34511570SCurtis.Dunham@arm.comsystem.physmem_1.actEnergy 3713615640 # Energy for activate commands per rank (pJ) 34611570SCurtis.Dunham@arm.comsystem.physmem_1.preEnergy 2026278375 # Energy for precharge commands per rank (pJ) 34711570SCurtis.Dunham@arm.comsystem.physmem_1.readEnergy 4078440600 # Energy for read commands per rank (pJ) 34811570SCurtis.Dunham@arm.comsystem.physmem_1.writeEnergy 3911723280 # Energy for write commands per rank (pJ) 34911570SCurtis.Dunham@arm.comsystem.physmem_1.refreshEnergy 3098908325760 # Energy for refresh commands per rank (pJ) 35011570SCurtis.Dunham@arm.comsystem.physmem_1.actBackEnergy 1186342158240 # Energy for active background per rank (pJ) 35111570SCurtis.Dunham@arm.comsystem.physmem_1.preBackEnergy 27426639078000 # Energy for precharge background per rank (pJ) 35211570SCurtis.Dunham@arm.comsystem.physmem_1.totalEnergy 31725619619895 # Total energy per rank (pJ) 35311570SCurtis.Dunham@arm.comsystem.physmem_1.averagePower 668.675231 # Core power per rank (mW) 35411570SCurtis.Dunham@arm.comsystem.physmem_1.memoryStateTime::IDLE 45626361005854 # Time in different power states 35511570SCurtis.Dunham@arm.comsystem.physmem_1.memoryStateTime::REF 1584308960000 # Time in different power states 35610628Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 35711570SCurtis.Dunham@arm.comsystem.physmem_1.memoryStateTime::ACT 234814164146 # Time in different power states 35810628Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 35911570SCurtis.Dunham@arm.comsystem.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states 36010636Snilay@cs.wisc.edusystem.realview.nvmem.bytes_read::cpu0.inst 704 # Number of bytes read from this memory 36110636Snilay@cs.wisc.edusystem.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory 36211570SCurtis.Dunham@arm.comsystem.realview.nvmem.bytes_read::cpu1.inst 640 # Number of bytes read from this memory 36310636Snilay@cs.wisc.edusystem.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory 36411570SCurtis.Dunham@arm.comsystem.realview.nvmem.bytes_read::total 1388 # Number of bytes read from this memory 36510515SAli.Saidi@ARM.comsystem.realview.nvmem.bytes_inst_read::cpu0.inst 704 # Number of instructions bytes read from this memory 36611570SCurtis.Dunham@arm.comsystem.realview.nvmem.bytes_inst_read::cpu1.inst 640 # Number of instructions bytes read from this memory 36711570SCurtis.Dunham@arm.comsystem.realview.nvmem.bytes_inst_read::total 1344 # Number of instructions bytes read from this memory 36810636Snilay@cs.wisc.edusystem.realview.nvmem.num_reads::cpu0.inst 11 # Number of read requests responded to by this memory 36910636Snilay@cs.wisc.edusystem.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory 37011570SCurtis.Dunham@arm.comsystem.realview.nvmem.num_reads::cpu1.inst 10 # Number of read requests responded to by this memory 37110636Snilay@cs.wisc.edusystem.realview.nvmem.num_reads::cpu1.data 1 # Number of read requests responded to by this memory 37211570SCurtis.Dunham@arm.comsystem.realview.nvmem.num_reads::total 27 # Number of read requests responded to by this memory 37310636Snilay@cs.wisc.edusystem.realview.nvmem.bw_read::cpu0.inst 15 # Total read bandwidth from this memory (bytes/s) 37410636Snilay@cs.wisc.edusystem.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s) 37511570SCurtis.Dunham@arm.comsystem.realview.nvmem.bw_read::cpu1.inst 13 # Total read bandwidth from this memory (bytes/s) 37610636Snilay@cs.wisc.edusystem.realview.nvmem.bw_read::cpu1.data 0 # Total read bandwidth from this memory (bytes/s) 37711570SCurtis.Dunham@arm.comsystem.realview.nvmem.bw_read::total 29 # Total read bandwidth from this memory (bytes/s) 37810515SAli.Saidi@ARM.comsystem.realview.nvmem.bw_inst_read::cpu0.inst 15 # Instruction read bandwidth from this memory (bytes/s) 37911570SCurtis.Dunham@arm.comsystem.realview.nvmem.bw_inst_read::cpu1.inst 13 # Instruction read bandwidth from this memory (bytes/s) 38011570SCurtis.Dunham@arm.comsystem.realview.nvmem.bw_inst_read::total 28 # Instruction read bandwidth from this memory (bytes/s) 38110636Snilay@cs.wisc.edusystem.realview.nvmem.bw_total::cpu0.inst 15 # Total bandwidth to/from this memory (bytes/s) 38210636Snilay@cs.wisc.edusystem.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s) 38311570SCurtis.Dunham@arm.comsystem.realview.nvmem.bw_total::cpu1.inst 13 # Total bandwidth to/from this memory (bytes/s) 38410636Snilay@cs.wisc.edusystem.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) 38511570SCurtis.Dunham@arm.comsystem.realview.nvmem.bw_total::total 29 # Total bandwidth to/from this memory (bytes/s) 38611570SCurtis.Dunham@arm.comsystem.realview.vram.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states 38711570SCurtis.Dunham@arm.comsystem.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states 38811570SCurtis.Dunham@arm.comsystem.bridge.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states 38910585Sandreas.hansson@arm.comsystem.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 39010585Sandreas.hansson@arm.comsystem.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 39110585Sandreas.hansson@arm.comsystem.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 39211570SCurtis.Dunham@arm.comsystem.cf0.dma_write_full_pages 1671 # Number of full page size DMA writes. 39311570SCurtis.Dunham@arm.comsystem.cf0.dma_write_bytes 6846976 # Number of bytes transfered via DMA writes. 39411570SCurtis.Dunham@arm.comsystem.cf0.dma_write_txs 1674 # Number of DMA write transactions. 39511570SCurtis.Dunham@arm.comsystem.cpu0.branchPred.lookups 160314756 # Number of BP lookups 39611570SCurtis.Dunham@arm.comsystem.cpu0.branchPred.condPredicted 112651620 # Number of conditional branches predicted 39711570SCurtis.Dunham@arm.comsystem.cpu0.branchPred.condIncorrect 7238532 # Number of conditional branches incorrect 39811570SCurtis.Dunham@arm.comsystem.cpu0.branchPred.BTBLookups 119384108 # Number of BTB lookups 39911570SCurtis.Dunham@arm.comsystem.cpu0.branchPred.BTBHits 83018284 # Number of BTB hits 40010585Sandreas.hansson@arm.comsystem.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 40111570SCurtis.Dunham@arm.comsystem.cpu0.branchPred.BTBHitPct 69.538807 # BTB Hit Percentage 40211570SCurtis.Dunham@arm.comsystem.cpu0.branchPred.usedRAS 19042266 # Number of times the RAS was used to get a target. 40311570SCurtis.Dunham@arm.comsystem.cpu0.branchPred.RASInCorrect 1248322 # Number of incorrect RAS predictions. 40411570SCurtis.Dunham@arm.comsystem.cpu0.branchPred.indirectLookups 4272460 # Number of indirect predictor lookups. 40511570SCurtis.Dunham@arm.comsystem.cpu0.branchPred.indirectHits 2939923 # Number of indirect target hits. 40611570SCurtis.Dunham@arm.comsystem.cpu0.branchPred.indirectMisses 1332537 # Number of indirect misses. 40711570SCurtis.Dunham@arm.comsystem.cpu0.branchPredindirectMispredicted 468796 # Number of mispredicted indirect branches. 40810515SAli.Saidi@ARM.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 40911570SCurtis.Dunham@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states 41010628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 41110628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 41210628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 41310628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 41410628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 41510628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 41610628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 41710628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 41810585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 41910585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 42010585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 42110585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 42210585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 42310585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 42410585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 42510585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 42610585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 42710585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 42810585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 42910585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 43010585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 43110585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 43210585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 43310585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 43410585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 43510585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 43610585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 43710585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 43810585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 43911570SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states 44011570SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walks 329365 # Table walker walks requested 44111570SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walksLong 329365 # Table walker walks initiated with long descriptors 44211570SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walksLongTerminationLevel::Level2 11619 # Level at which table walker walks with long descriptors terminate 44311570SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walksLongTerminationLevel::Level3 95372 # Level at which table walker walks with long descriptors terminate 44411570SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkWaitTime::samples 329365 # Table walker wait (enqueue to first request) latency 44511570SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkWaitTime::0 329365 100.00% 100.00% # Table walker wait (enqueue to first request) latency 44611570SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkWaitTime::total 329365 # Table walker wait (enqueue to first request) latency 44711570SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::samples 106991 # Table walker service (enqueue to completion) latency 44811570SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::mean 23090.091690 # Table walker service (enqueue to completion) latency 44911570SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::gmean 21491.120734 # Table walker service (enqueue to completion) latency 45011570SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::stdev 15706.739319 # Table walker service (enqueue to completion) latency 45111570SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::0-65535 105441 98.55% 98.55% # Table walker service (enqueue to completion) latency 45211570SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::65536-131071 1327 1.24% 99.79% # Table walker service (enqueue to completion) latency 45311570SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::131072-196607 42 0.04% 99.83% # Table walker service (enqueue to completion) latency 45411570SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::196608-262143 76 0.07% 99.90% # Table walker service (enqueue to completion) latency 45511570SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::262144-327679 69 0.06% 99.97% # Table walker service (enqueue to completion) latency 45611570SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::327680-393215 15 0.01% 99.98% # Table walker service (enqueue to completion) latency 45711570SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::393216-458751 14 0.01% 99.99% # Table walker service (enqueue to completion) latency 45811570SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::458752-524287 6 0.01% 100.00% # Table walker service (enqueue to completion) latency 45911502SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 46011570SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::total 106991 # Table walker service (enqueue to completion) latency 46111570SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walksPending::samples 734573704 # Table walker pending requests distribution 46211570SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walksPending::0 734573704 100.00% 100.00% # Table walker pending requests distribution 46311570SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walksPending::total 734573704 # Table walker pending requests distribution 46411570SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkPageSizes::4K 95372 89.14% 89.14% # Table walker page sizes translated 46511570SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkPageSizes::2M 11619 10.86% 100.00% # Table walker page sizes translated 46611570SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkPageSizes::total 106991 # Table walker page sizes translated 46711570SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 329365 # Table walker requests started/completed, data/inst 46810628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 46911570SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Requested::total 329365 # Table walker requests started/completed, data/inst 47011570SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 106991 # Table walker requests started/completed, data/inst 47110628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 47211570SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Completed::total 106991 # Table walker requests started/completed, data/inst 47311570SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin::total 436356 # Table walker requests started/completed, data/inst 47410585Sandreas.hansson@arm.comsystem.cpu0.dtb.inst_hits 0 # ITB inst hits 47510585Sandreas.hansson@arm.comsystem.cpu0.dtb.inst_misses 0 # ITB inst misses 47611570SCurtis.Dunham@arm.comsystem.cpu0.dtb.read_hits 103710651 # DTB read hits 47711570SCurtis.Dunham@arm.comsystem.cpu0.dtb.read_misses 276993 # DTB read misses 47811570SCurtis.Dunham@arm.comsystem.cpu0.dtb.write_hits 90811723 # DTB write hits 47911570SCurtis.Dunham@arm.comsystem.cpu0.dtb.write_misses 52372 # DTB write misses 48011441Sandreas.hansson@arm.comsystem.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed 48110585Sandreas.hansson@arm.comsystem.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 48211570SCurtis.Dunham@arm.comsystem.cpu0.dtb.flush_tlb_mva_asid 43240 # Number of times TLB was flushed by MVA & ASID 48311570SCurtis.Dunham@arm.comsystem.cpu0.dtb.flush_tlb_asid 1075 # Number of times TLB was flushed by ASID 48411570SCurtis.Dunham@arm.comsystem.cpu0.dtb.flush_entries 42132 # Number of entries that have been flushed from TLB 48511570SCurtis.Dunham@arm.comsystem.cpu0.dtb.align_faults 2205 # Number of TLB faults due to alignment restrictions 48611570SCurtis.Dunham@arm.comsystem.cpu0.dtb.prefetch_faults 11314 # Number of TLB faults due to prefetch 48710585Sandreas.hansson@arm.comsystem.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 48811570SCurtis.Dunham@arm.comsystem.cpu0.dtb.perms_faults 11590 # Number of TLB faults due to permissions restrictions 48911570SCurtis.Dunham@arm.comsystem.cpu0.dtb.read_accesses 103987644 # DTB read accesses 49011570SCurtis.Dunham@arm.comsystem.cpu0.dtb.write_accesses 90864095 # DTB write accesses 49110585Sandreas.hansson@arm.comsystem.cpu0.dtb.inst_accesses 0 # ITB inst accesses 49211570SCurtis.Dunham@arm.comsystem.cpu0.dtb.hits 194522374 # DTB hits 49311570SCurtis.Dunham@arm.comsystem.cpu0.dtb.misses 329365 # DTB misses 49411570SCurtis.Dunham@arm.comsystem.cpu0.dtb.accesses 194851739 # DTB accesses 49511570SCurtis.Dunham@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states 49610628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 49710628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 49810628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 49910628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 50010628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 50110628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 50210628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 50310628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 50410585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 50510585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 50610585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 50710585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 50810585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 50910585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 51010585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 51110585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 51210585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 51310585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 51410585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 51510585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 51610585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 51710585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 51810585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 51910585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 52010585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 52110585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 52210585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 52310585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 52410585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 52511570SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states 52611570SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walks 72209 # Table walker walks requested 52711570SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walksLong 72209 # Table walker walks initiated with long descriptors 52811570SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walksLongTerminationLevel::Level2 611 # Level at which table walker walks with long descriptors terminate 52911570SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walksLongTerminationLevel::Level3 59557 # Level at which table walker walks with long descriptors terminate 53011570SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkWaitTime::samples 72209 # Table walker wait (enqueue to first request) latency 53111570SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkWaitTime::0 72209 100.00% 100.00% # Table walker wait (enqueue to first request) latency 53211570SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkWaitTime::total 72209 # Table walker wait (enqueue to first request) latency 53311570SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkCompletionTime::samples 60168 # Table walker service (enqueue to completion) latency 53411570SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkCompletionTime::mean 25971.338585 # Table walker service (enqueue to completion) latency 53511570SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkCompletionTime::gmean 23756.230706 # Table walker service (enqueue to completion) latency 53611570SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkCompletionTime::stdev 17963.019846 # Table walker service (enqueue to completion) latency 53711570SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkCompletionTime::0-32767 55134 91.63% 91.63% # Table walker service (enqueue to completion) latency 53811570SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkCompletionTime::32768-65535 3439 5.72% 97.35% # Table walker service (enqueue to completion) latency 53911570SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkCompletionTime::65536-98303 6 0.01% 97.36% # Table walker service (enqueue to completion) latency 54011570SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkCompletionTime::98304-131071 1442 2.40% 99.76% # Table walker service (enqueue to completion) latency 54111570SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkCompletionTime::131072-163839 23 0.04% 99.79% # Table walker service (enqueue to completion) latency 54211570SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkCompletionTime::163840-196607 16 0.03% 99.82% # Table walker service (enqueue to completion) latency 54311570SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkCompletionTime::196608-229375 52 0.09% 99.91% # Table walker service (enqueue to completion) latency 54411570SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkCompletionTime::229376-262143 23 0.04% 99.95% # Table walker service (enqueue to completion) latency 54511570SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkCompletionTime::262144-294911 9 0.01% 99.96% # Table walker service (enqueue to completion) latency 54611570SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkCompletionTime::294912-327679 12 0.02% 99.98% # Table walker service (enqueue to completion) latency 54711570SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkCompletionTime::327680-360447 6 0.01% 99.99% # Table walker service (enqueue to completion) latency 54811570SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkCompletionTime::360448-393215 4 0.01% 100.00% # Table walker service (enqueue to completion) latency 54911570SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkCompletionTime::458752-491519 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 55011570SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkCompletionTime::total 60168 # Table walker service (enqueue to completion) latency 55111570SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walksPending::samples 733851204 # Table walker pending requests distribution 55211570SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walksPending::0 733851204 100.00% 100.00% # Table walker pending requests distribution 55311570SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walksPending::total 733851204 # Table walker pending requests distribution 55411570SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkPageSizes::4K 59557 98.98% 98.98% # Table walker page sizes translated 55511570SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkPageSizes::2M 611 1.02% 100.00% # Table walker page sizes translated 55611570SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkPageSizes::total 60168 # Table walker page sizes translated 55710628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 55811570SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 72209 # Table walker requests started/completed, data/inst 55911570SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Requested::total 72209 # Table walker requests started/completed, data/inst 56010628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 56111570SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 60168 # Table walker requests started/completed, data/inst 56211570SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Completed::total 60168 # Table walker requests started/completed, data/inst 56311570SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkRequestOrigin::total 132377 # Table walker requests started/completed, data/inst 56411570SCurtis.Dunham@arm.comsystem.cpu0.itb.inst_hits 285203366 # ITB inst hits 56511570SCurtis.Dunham@arm.comsystem.cpu0.itb.inst_misses 72209 # ITB inst misses 56610585Sandreas.hansson@arm.comsystem.cpu0.itb.read_hits 0 # DTB read hits 56710585Sandreas.hansson@arm.comsystem.cpu0.itb.read_misses 0 # DTB read misses 56810585Sandreas.hansson@arm.comsystem.cpu0.itb.write_hits 0 # DTB write hits 56910585Sandreas.hansson@arm.comsystem.cpu0.itb.write_misses 0 # DTB write misses 57011441Sandreas.hansson@arm.comsystem.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed 57110585Sandreas.hansson@arm.comsystem.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 57211570SCurtis.Dunham@arm.comsystem.cpu0.itb.flush_tlb_mva_asid 43240 # Number of times TLB was flushed by MVA & ASID 57311570SCurtis.Dunham@arm.comsystem.cpu0.itb.flush_tlb_asid 1075 # Number of times TLB was flushed by ASID 57411570SCurtis.Dunham@arm.comsystem.cpu0.itb.flush_entries 30424 # Number of entries that have been flushed from TLB 57510585Sandreas.hansson@arm.comsystem.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 57610585Sandreas.hansson@arm.comsystem.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 57710585Sandreas.hansson@arm.comsystem.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 57811570SCurtis.Dunham@arm.comsystem.cpu0.itb.perms_faults 190431 # Number of TLB faults due to permissions restrictions 57910585Sandreas.hansson@arm.comsystem.cpu0.itb.read_accesses 0 # DTB read accesses 58010585Sandreas.hansson@arm.comsystem.cpu0.itb.write_accesses 0 # DTB write accesses 58111570SCurtis.Dunham@arm.comsystem.cpu0.itb.inst_accesses 285275575 # ITB inst accesses 58211570SCurtis.Dunham@arm.comsystem.cpu0.itb.hits 285203366 # DTB hits 58311570SCurtis.Dunham@arm.comsystem.cpu0.itb.misses 72209 # DTB misses 58411570SCurtis.Dunham@arm.comsystem.cpu0.itb.accesses 285275575 # DTB accesses 58511570SCurtis.Dunham@arm.comsystem.cpu0.numPwrStateTransitions 26302 # Number of power state transitions 58611570SCurtis.Dunham@arm.comsystem.cpu0.pwrStateClkGateDist::samples 13151 # Distribution of time spent in the clock gated state 58711570SCurtis.Dunham@arm.comsystem.cpu0.pwrStateClkGateDist::mean 3564690271.200593 # Distribution of time spent in the clock gated state 58811570SCurtis.Dunham@arm.comsystem.cpu0.pwrStateClkGateDist::stdev 65409151988.663887 # Distribution of time spent in the clock gated state 58911570SCurtis.Dunham@arm.comsystem.cpu0.pwrStateClkGateDist::underflows 3759 28.58% 28.58% # Distribution of time spent in the clock gated state 59011570SCurtis.Dunham@arm.comsystem.cpu0.pwrStateClkGateDist::1000-5e+10 9361 71.18% 99.76% # Distribution of time spent in the clock gated state 59111570SCurtis.Dunham@arm.comsystem.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 1 0.01% 99.77% # Distribution of time spent in the clock gated state 59211570SCurtis.Dunham@arm.comsystem.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.01% 99.78% # Distribution of time spent in the clock gated state 59311570SCurtis.Dunham@arm.comsystem.cpu0.pwrStateClkGateDist::2e+11-2.5e+11 4 0.03% 99.81% # Distribution of time spent in the clock gated state 59411570SCurtis.Dunham@arm.comsystem.cpu0.pwrStateClkGateDist::2.5e+11-3e+11 1 0.01% 99.82% # Distribution of time spent in the clock gated state 59511570SCurtis.Dunham@arm.comsystem.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 1 0.01% 99.83% # Distribution of time spent in the clock gated state 59611570SCurtis.Dunham@arm.comsystem.cpu0.pwrStateClkGateDist::5e+11-5.5e+11 2 0.02% 99.84% # Distribution of time spent in the clock gated state 59711570SCurtis.Dunham@arm.comsystem.cpu0.pwrStateClkGateDist::6e+11-6.5e+11 1 0.01% 99.85% # Distribution of time spent in the clock gated state 59811570SCurtis.Dunham@arm.comsystem.cpu0.pwrStateClkGateDist::7e+11-7.5e+11 1 0.01% 99.86% # Distribution of time spent in the clock gated state 59911570SCurtis.Dunham@arm.comsystem.cpu0.pwrStateClkGateDist::8.5e+11-9e+11 1 0.01% 99.86% # Distribution of time spent in the clock gated state 60011570SCurtis.Dunham@arm.comsystem.cpu0.pwrStateClkGateDist::overflows 18 0.14% 100.00% # Distribution of time spent in the clock gated state 60111570SCurtis.Dunham@arm.comsystem.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state 60211570SCurtis.Dunham@arm.comsystem.cpu0.pwrStateClkGateDist::max_value 1988779311380 # Distribution of time spent in the clock gated state 60311570SCurtis.Dunham@arm.comsystem.cpu0.pwrStateClkGateDist::total 13151 # Distribution of time spent in the clock gated state 60411570SCurtis.Dunham@arm.comsystem.cpu0.pwrStateResidencyTicks::ON 566247484441 # Cumulative time (in ticks) in various power states 60511570SCurtis.Dunham@arm.comsystem.cpu0.pwrStateResidencyTicks::CLK_GATED 46879241756559 # Cumulative time (in ticks) in various power states 60611570SCurtis.Dunham@arm.comsystem.cpu0.numCycles 1132534446 # number of cpu cycles simulated 60710585Sandreas.hansson@arm.comsystem.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 60810585Sandreas.hansson@arm.comsystem.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 60911570SCurtis.Dunham@arm.comsystem.cpu0.committedInsts 532076805 # Number of instructions committed 61011570SCurtis.Dunham@arm.comsystem.cpu0.committedOps 624758290 # Number of ops (including micro ops) committed 61111570SCurtis.Dunham@arm.comsystem.cpu0.discardedOps 52154793 # Number of ops (including micro ops) which were discarded before commit 61211570SCurtis.Dunham@arm.comsystem.cpu0.numFetchSuspends 4664 # Number of times Execute suspended instruction fetching 61311570SCurtis.Dunham@arm.comsystem.cpu0.quiesceCycles 93759282538 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 61411570SCurtis.Dunham@arm.comsystem.cpu0.cpi 2.128517 # CPI: cycles per instruction 61511570SCurtis.Dunham@arm.comsystem.cpu0.ipc 0.469811 # IPC: instructions per cycle 61611570SCurtis.Dunham@arm.comsystem.cpu0.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 61711570SCurtis.Dunham@arm.comsystem.cpu0.op_class_0::IntAlu 432780145 69.27% 69.27% # Class of committed instruction 61811570SCurtis.Dunham@arm.comsystem.cpu0.op_class_0::IntMult 1412970 0.23% 69.50% # Class of committed instruction 61911570SCurtis.Dunham@arm.comsystem.cpu0.op_class_0::IntDiv 69899 0.01% 69.51% # Class of committed instruction 62011570SCurtis.Dunham@arm.comsystem.cpu0.op_class_0::FloatAdd 0 0.00% 69.51% # Class of committed instruction 62111570SCurtis.Dunham@arm.comsystem.cpu0.op_class_0::FloatCmp 0 0.00% 69.51% # Class of committed instruction 62211570SCurtis.Dunham@arm.comsystem.cpu0.op_class_0::FloatCvt 0 0.00% 69.51% # Class of committed instruction 62311570SCurtis.Dunham@arm.comsystem.cpu0.op_class_0::FloatMult 0 0.00% 69.51% # Class of committed instruction 62411570SCurtis.Dunham@arm.comsystem.cpu0.op_class_0::FloatDiv 0 0.00% 69.51% # Class of committed instruction 62511570SCurtis.Dunham@arm.comsystem.cpu0.op_class_0::FloatSqrt 0 0.00% 69.51% # Class of committed instruction 62611570SCurtis.Dunham@arm.comsystem.cpu0.op_class_0::SimdAdd 0 0.00% 69.51% # Class of committed instruction 62711570SCurtis.Dunham@arm.comsystem.cpu0.op_class_0::SimdAddAcc 0 0.00% 69.51% # Class of committed instruction 62811570SCurtis.Dunham@arm.comsystem.cpu0.op_class_0::SimdAlu 0 0.00% 69.51% # Class of committed instruction 62911570SCurtis.Dunham@arm.comsystem.cpu0.op_class_0::SimdCmp 0 0.00% 69.51% # Class of committed instruction 63011570SCurtis.Dunham@arm.comsystem.cpu0.op_class_0::SimdCvt 0 0.00% 69.51% # Class of committed instruction 63111570SCurtis.Dunham@arm.comsystem.cpu0.op_class_0::SimdMisc 0 0.00% 69.51% # Class of committed instruction 63211570SCurtis.Dunham@arm.comsystem.cpu0.op_class_0::SimdMult 0 0.00% 69.51% # Class of committed instruction 63311570SCurtis.Dunham@arm.comsystem.cpu0.op_class_0::SimdMultAcc 0 0.00% 69.51% # Class of committed instruction 63411570SCurtis.Dunham@arm.comsystem.cpu0.op_class_0::SimdShift 0 0.00% 69.51% # Class of committed instruction 63511570SCurtis.Dunham@arm.comsystem.cpu0.op_class_0::SimdShiftAcc 0 0.00% 69.51% # Class of committed instruction 63611570SCurtis.Dunham@arm.comsystem.cpu0.op_class_0::SimdSqrt 0 0.00% 69.51% # Class of committed instruction 63711570SCurtis.Dunham@arm.comsystem.cpu0.op_class_0::SimdFloatAdd 0 0.00% 69.51% # Class of committed instruction 63811570SCurtis.Dunham@arm.comsystem.cpu0.op_class_0::SimdFloatAlu 0 0.00% 69.51% # Class of committed instruction 63911570SCurtis.Dunham@arm.comsystem.cpu0.op_class_0::SimdFloatCmp 0 0.00% 69.51% # Class of committed instruction 64011570SCurtis.Dunham@arm.comsystem.cpu0.op_class_0::SimdFloatCvt 0 0.00% 69.51% # Class of committed instruction 64111570SCurtis.Dunham@arm.comsystem.cpu0.op_class_0::SimdFloatDiv 0 0.00% 69.51% # Class of committed instruction 64211570SCurtis.Dunham@arm.comsystem.cpu0.op_class_0::SimdFloatMisc 79522 0.01% 69.52% # Class of committed instruction 64311570SCurtis.Dunham@arm.comsystem.cpu0.op_class_0::SimdFloatMult 0 0.00% 69.52% # Class of committed instruction 64411570SCurtis.Dunham@arm.comsystem.cpu0.op_class_0::SimdFloatMultAcc 0 0.00% 69.52% # Class of committed instruction 64511570SCurtis.Dunham@arm.comsystem.cpu0.op_class_0::SimdFloatSqrt 0 0.00% 69.52% # Class of committed instruction 64611570SCurtis.Dunham@arm.comsystem.cpu0.op_class_0::MemRead 99981749 16.00% 85.52% # Class of committed instruction 64711570SCurtis.Dunham@arm.comsystem.cpu0.op_class_0::MemWrite 90434005 14.48% 100.00% # Class of committed instruction 64811441Sandreas.hansson@arm.comsystem.cpu0.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 64911441Sandreas.hansson@arm.comsystem.cpu0.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 65011570SCurtis.Dunham@arm.comsystem.cpu0.op_class_0::total 624758290 # Class of committed instruction 65110585Sandreas.hansson@arm.comsystem.cpu0.kern.inst.arm 0 # number of arm instructions executed 65211570SCurtis.Dunham@arm.comsystem.cpu0.kern.inst.quiesce 13151 # number of quiesce instructions executed 65311570SCurtis.Dunham@arm.comsystem.cpu0.tickCycles 847175236 # Number of cycles that the object actually ticked 65411570SCurtis.Dunham@arm.comsystem.cpu0.idleCycles 285359210 # Total number of cycles that the object has spent stopped 65511570SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states 65611570SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.replacements 6574289 # number of replacements 65711570SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.tagsinuse 508.066535 # Cycle average of tags in use 65811570SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.total_refs 184992173 # Total number of references to valid blocks. 65911570SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.sampled_refs 6574801 # Sample count of references to valid blocks. 66011570SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.avg_refs 28.136543 # Average number of references to valid blocks. 66111570SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.warmup_cycle 5039429000 # Cycle when the warmup percentage was hit. 66211570SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.occ_blocks::cpu0.data 508.066535 # Average occupied blocks per requestor 66311570SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.occ_percent::cpu0.data 0.992317 # Average percentage of cache occupancy 66411570SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.occ_percent::total 0.992317 # Average percentage of cache occupancy 66511336Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 66611570SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::0 211 # Occupied blocks per task id 66711570SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::1 229 # Occupied blocks per task id 66811570SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::2 72 # Occupied blocks per task id 66911336Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 67011570SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.tag_accesses 392594755 # Number of tag accesses 67111570SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.data_accesses 392594755 # Number of data accesses 67211570SCurtis.Dunham@arm.comsystem.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states 67311570SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_hits::cpu0.data 95401287 # number of ReadReq hits 67411570SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_hits::total 95401287 # number of ReadReq hits 67511570SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_hits::cpu0.data 84287466 # number of WriteReq hits 67611570SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_hits::total 84287466 # number of WriteReq hits 67711570SCurtis.Dunham@arm.comsystem.cpu0.dcache.SoftPFReq_hits::cpu0.data 321965 # number of SoftPFReq hits 67811570SCurtis.Dunham@arm.comsystem.cpu0.dcache.SoftPFReq_hits::total 321965 # number of SoftPFReq hits 67911570SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteLineReq_hits::cpu0.data 280846 # number of WriteLineReq hits 68011570SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteLineReq_hits::total 280846 # number of WriteLineReq hits 68111570SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_hits::cpu0.data 2060188 # number of LoadLockedReq hits 68211570SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_hits::total 2060188 # number of LoadLockedReq hits 68311570SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_hits::cpu0.data 2061125 # number of StoreCondReq hits 68411570SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_hits::total 2061125 # number of StoreCondReq hits 68511570SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_hits::cpu0.data 179969599 # number of demand (read+write) hits 68611570SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_hits::total 179969599 # number of demand (read+write) hits 68711570SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_hits::cpu0.data 180291564 # number of overall hits 68811570SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_hits::total 180291564 # number of overall hits 68911570SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_misses::cpu0.data 3840217 # number of ReadReq misses 69011570SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_misses::total 3840217 # number of ReadReq misses 69111570SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_misses::cpu0.data 2718306 # number of WriteReq misses 69211570SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_misses::total 2718306 # number of WriteReq misses 69311570SCurtis.Dunham@arm.comsystem.cpu0.dcache.SoftPFReq_misses::cpu0.data 733729 # number of SoftPFReq misses 69411570SCurtis.Dunham@arm.comsystem.cpu0.dcache.SoftPFReq_misses::total 733729 # number of SoftPFReq misses 69511570SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteLineReq_misses::cpu0.data 858022 # number of WriteLineReq misses 69611570SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteLineReq_misses::total 858022 # number of WriteLineReq misses 69711570SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_misses::cpu0.data 199658 # number of LoadLockedReq misses 69811570SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_misses::total 199658 # number of LoadLockedReq misses 69911570SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_misses::cpu0.data 197397 # number of StoreCondReq misses 70011570SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_misses::total 197397 # number of StoreCondReq misses 70111570SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_misses::cpu0.data 7416545 # number of demand (read+write) misses 70211570SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_misses::total 7416545 # number of demand (read+write) misses 70311570SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_misses::cpu0.data 8150274 # number of overall misses 70411570SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_misses::total 8150274 # number of overall misses 70511570SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_miss_latency::cpu0.data 59779296000 # number of ReadReq miss cycles 70611570SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_miss_latency::total 59779296000 # number of ReadReq miss cycles 70711570SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_miss_latency::cpu0.data 54754909500 # number of WriteReq miss cycles 70811570SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_miss_latency::total 54754909500 # number of WriteReq miss cycles 70911570SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 28457275000 # number of WriteLineReq miss cycles 71011570SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteLineReq_miss_latency::total 28457275000 # number of WriteLineReq miss cycles 71111570SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2995014000 # number of LoadLockedReq miss cycles 71211570SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_latency::total 2995014000 # number of LoadLockedReq miss cycles 71311570SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4953933500 # number of StoreCondReq miss cycles 71411570SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_miss_latency::total 4953933500 # number of StoreCondReq miss cycles 71511570SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 3818500 # number of StoreCondFailReq miss cycles 71611570SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondFailReq_miss_latency::total 3818500 # number of StoreCondFailReq miss cycles 71711570SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_miss_latency::cpu0.data 142991480500 # number of demand (read+write) miss cycles 71811570SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_miss_latency::total 142991480500 # number of demand (read+write) miss cycles 71911570SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_miss_latency::cpu0.data 142991480500 # number of overall miss cycles 72011570SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_miss_latency::total 142991480500 # number of overall miss cycles 72111570SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_accesses::cpu0.data 99241504 # number of ReadReq accesses(hits+misses) 72211570SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_accesses::total 99241504 # number of ReadReq accesses(hits+misses) 72311570SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_accesses::cpu0.data 87005772 # number of WriteReq accesses(hits+misses) 72411570SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_accesses::total 87005772 # number of WriteReq accesses(hits+misses) 72511570SCurtis.Dunham@arm.comsystem.cpu0.dcache.SoftPFReq_accesses::cpu0.data 1055694 # number of SoftPFReq accesses(hits+misses) 72611570SCurtis.Dunham@arm.comsystem.cpu0.dcache.SoftPFReq_accesses::total 1055694 # number of SoftPFReq accesses(hits+misses) 72711570SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1138868 # number of WriteLineReq accesses(hits+misses) 72811570SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteLineReq_accesses::total 1138868 # number of WriteLineReq accesses(hits+misses) 72911570SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2259846 # number of LoadLockedReq accesses(hits+misses) 73011570SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_accesses::total 2259846 # number of LoadLockedReq accesses(hits+misses) 73111570SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2258522 # number of StoreCondReq accesses(hits+misses) 73211570SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_accesses::total 2258522 # number of StoreCondReq accesses(hits+misses) 73311570SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_accesses::cpu0.data 187386144 # number of demand (read+write) accesses 73411570SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_accesses::total 187386144 # number of demand (read+write) accesses 73511570SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_accesses::cpu0.data 188441838 # number of overall (read+write) accesses 73611570SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_accesses::total 188441838 # number of overall (read+write) accesses 73711570SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.038696 # miss rate for ReadReq accesses 73811570SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_miss_rate::total 0.038696 # miss rate for ReadReq accesses 73911570SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.031243 # miss rate for WriteReq accesses 74011570SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_miss_rate::total 0.031243 # miss rate for WriteReq accesses 74111570SCurtis.Dunham@arm.comsystem.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.695021 # miss rate for SoftPFReq accesses 74211570SCurtis.Dunham@arm.comsystem.cpu0.dcache.SoftPFReq_miss_rate::total 0.695021 # miss rate for SoftPFReq accesses 74311570SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.753399 # miss rate for WriteLineReq accesses 74411570SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteLineReq_miss_rate::total 0.753399 # miss rate for WriteLineReq accesses 74511570SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.088350 # miss rate for LoadLockedReq accesses 74611570SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_rate::total 0.088350 # miss rate for LoadLockedReq accesses 74711570SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.087401 # miss rate for StoreCondReq accesses 74811570SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_miss_rate::total 0.087401 # miss rate for StoreCondReq accesses 74911570SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_miss_rate::cpu0.data 0.039579 # miss rate for demand accesses 75011570SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_miss_rate::total 0.039579 # miss rate for demand accesses 75111570SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_miss_rate::cpu0.data 0.043251 # miss rate for overall accesses 75211570SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_miss_rate::total 0.043251 # miss rate for overall accesses 75311570SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15566.645322 # average ReadReq miss latency 75411570SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_avg_miss_latency::total 15566.645322 # average ReadReq miss latency 75511570SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 20143.026392 # average WriteReq miss latency 75611570SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_avg_miss_latency::total 20143.026392 # average WriteReq miss latency 75711570SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 33166.136766 # average WriteLineReq miss latency 75811570SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteLineReq_avg_miss_latency::total 33166.136766 # average WriteLineReq miss latency 75911570SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15000.721233 # average LoadLockedReq miss latency 76011570SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15000.721233 # average LoadLockedReq miss latency 76111570SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 25096.295790 # average StoreCondReq miss latency 76211570SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_avg_miss_latency::total 25096.295790 # average StoreCondReq miss latency 76310636Snilay@cs.wisc.edusystem.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency 76410585Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 76511570SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19280.066460 # average overall miss latency 76611570SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_avg_miss_latency::total 19280.066460 # average overall miss latency 76711570SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_avg_miss_latency::cpu0.data 17544.377097 # average overall miss latency 76811570SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_avg_miss_latency::total 17544.377097 # average overall miss latency 76910585Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 77010585Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 77110585Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 77210585Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 77310585Sandreas.hansson@arm.comsystem.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 77410585Sandreas.hansson@arm.comsystem.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 77511570SCurtis.Dunham@arm.comsystem.cpu0.dcache.writebacks::writebacks 6574291 # number of writebacks 77611570SCurtis.Dunham@arm.comsystem.cpu0.dcache.writebacks::total 6574291 # number of writebacks 77711570SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 237792 # number of ReadReq MSHR hits 77811570SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_mshr_hits::total 237792 # number of ReadReq MSHR hits 77911570SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1117306 # number of WriteReq MSHR hits 78011570SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_mshr_hits::total 1117306 # number of WriteReq MSHR hits 78111570SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 90 # number of WriteLineReq MSHR hits 78211570SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_hits::total 90 # number of WriteLineReq MSHR hits 78311570SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 48445 # number of LoadLockedReq MSHR hits 78411570SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_hits::total 48445 # number of LoadLockedReq MSHR hits 78511570SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data 60 # number of StoreCondReq MSHR hits 78611570SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_hits::total 60 # number of StoreCondReq MSHR hits 78711570SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_mshr_hits::cpu0.data 1355188 # number of demand (read+write) MSHR hits 78811570SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_mshr_hits::total 1355188 # number of demand (read+write) MSHR hits 78911570SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_mshr_hits::cpu0.data 1355188 # number of overall MSHR hits 79011570SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_mshr_hits::total 1355188 # number of overall MSHR hits 79111570SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3602425 # number of ReadReq MSHR misses 79211570SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_mshr_misses::total 3602425 # number of ReadReq MSHR misses 79311570SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1601000 # number of WriteReq MSHR misses 79411570SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_mshr_misses::total 1601000 # number of WriteReq MSHR misses 79511570SCurtis.Dunham@arm.comsystem.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 732137 # number of SoftPFReq MSHR misses 79611570SCurtis.Dunham@arm.comsystem.cpu0.dcache.SoftPFReq_mshr_misses::total 732137 # number of SoftPFReq MSHR misses 79711570SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 857932 # number of WriteLineReq MSHR misses 79811570SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_misses::total 857932 # number of WriteLineReq MSHR misses 79911570SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 151213 # number of LoadLockedReq MSHR misses 80011570SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_misses::total 151213 # number of LoadLockedReq MSHR misses 80111570SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 197337 # number of StoreCondReq MSHR misses 80211570SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_misses::total 197337 # number of StoreCondReq MSHR misses 80311570SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_mshr_misses::cpu0.data 6061357 # number of demand (read+write) MSHR misses 80411570SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_mshr_misses::total 6061357 # number of demand (read+write) MSHR misses 80511570SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_mshr_misses::cpu0.data 6793494 # number of overall MSHR misses 80611570SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_mshr_misses::total 6793494 # number of overall MSHR misses 80711570SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 29793 # number of ReadReq MSHR uncacheable 80811570SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_mshr_uncacheable::total 29793 # number of ReadReq MSHR uncacheable 80911570SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 29400 # number of WriteReq MSHR uncacheable 81011570SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_mshr_uncacheable::total 29400 # number of WriteReq MSHR uncacheable 81111570SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 59193 # number of overall MSHR uncacheable misses 81211570SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_mshr_uncacheable_misses::total 59193 # number of overall MSHR uncacheable misses 81311570SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 50925119500 # number of ReadReq MSHR miss cycles 81411570SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_mshr_miss_latency::total 50925119500 # number of ReadReq MSHR miss cycles 81511570SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 31536308500 # number of WriteReq MSHR miss cycles 81611570SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_mshr_miss_latency::total 31536308500 # number of WriteReq MSHR miss cycles 81711570SCurtis.Dunham@arm.comsystem.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 16544300500 # number of SoftPFReq MSHR miss cycles 81811570SCurtis.Dunham@arm.comsystem.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 16544300500 # number of SoftPFReq MSHR miss cycles 81911570SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 27594364000 # number of WriteLineReq MSHR miss cycles 82011570SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 27594364000 # number of WriteLineReq MSHR miss cycles 82111570SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1964885000 # number of LoadLockedReq MSHR miss cycles 82211570SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1964885000 # number of LoadLockedReq MSHR miss cycles 82311570SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4754516500 # number of StoreCondReq MSHR miss cycles 82411570SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4754516500 # number of StoreCondReq MSHR miss cycles 82511570SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 3441500 # number of StoreCondFailReq MSHR miss cycles 82611570SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 3441500 # number of StoreCondFailReq MSHR miss cycles 82711570SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 110055792000 # number of demand (read+write) MSHR miss cycles 82811570SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_mshr_miss_latency::total 110055792000 # number of demand (read+write) MSHR miss cycles 82911570SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 126600092500 # number of overall MSHR miss cycles 83011570SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_mshr_miss_latency::total 126600092500 # number of overall MSHR miss cycles 83111570SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5675765000 # number of ReadReq MSHR uncacheable cycles 83211570SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5675765000 # number of ReadReq MSHR uncacheable cycles 83311570SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5675765000 # number of overall MSHR uncacheable cycles 83411570SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_mshr_uncacheable_latency::total 5675765000 # number of overall MSHR uncacheable cycles 83511570SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036300 # mshr miss rate for ReadReq accesses 83611570SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036300 # mshr miss rate for ReadReq accesses 83711570SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018401 # mshr miss rate for WriteReq accesses 83811570SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018401 # mshr miss rate for WriteReq accesses 83911570SCurtis.Dunham@arm.comsystem.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.693513 # mshr miss rate for SoftPFReq accesses 84011570SCurtis.Dunham@arm.comsystem.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.693513 # mshr miss rate for SoftPFReq accesses 84111570SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.753320 # mshr miss rate for WriteLineReq accesses 84211570SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.753320 # mshr miss rate for WriteLineReq accesses 84311570SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.066913 # mshr miss rate for LoadLockedReq accesses 84411570SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.066913 # mshr miss rate for LoadLockedReq accesses 84511570SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.087374 # mshr miss rate for StoreCondReq accesses 84611570SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.087374 # mshr miss rate for StoreCondReq accesses 84711570SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.032347 # mshr miss rate for demand accesses 84811570SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_mshr_miss_rate::total 0.032347 # mshr miss rate for demand accesses 84911570SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.036051 # mshr miss rate for overall accesses 85011570SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_mshr_miss_rate::total 0.036051 # mshr miss rate for overall accesses 85111570SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14136.344129 # average ReadReq mshr miss latency 85211570SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14136.344129 # average ReadReq mshr miss latency 85311570SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 19697.881636 # average WriteReq mshr miss latency 85411570SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 19697.881636 # average WriteReq mshr miss latency 85511570SCurtis.Dunham@arm.comsystem.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 22597.274144 # average SoftPFReq mshr miss latency 85611570SCurtis.Dunham@arm.comsystem.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 22597.274144 # average SoftPFReq mshr miss latency 85711570SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 32163.812517 # average WriteLineReq mshr miss latency 85811570SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 32163.812517 # average WriteLineReq mshr miss latency 85911570SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12994.153942 # average LoadLockedReq mshr miss latency 86011570SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12994.153942 # average LoadLockedReq mshr miss latency 86111570SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 24093.385934 # average StoreCondReq mshr miss latency 86211570SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 24093.385934 # average StoreCondReq mshr miss latency 86310636Snilay@cs.wisc.edusystem.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 86410585Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 86511570SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18156.955942 # average overall mshr miss latency 86611570SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_avg_mshr_miss_latency::total 18156.955942 # average overall mshr miss latency 86711570SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 18635.490441 # average overall mshr miss latency 86811570SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_avg_mshr_miss_latency::total 18635.490441 # average overall mshr miss latency 86911570SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 190506.662639 # average ReadReq mshr uncacheable latency 87011570SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 190506.662639 # average ReadReq mshr uncacheable latency 87111570SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 95885.746625 # average overall mshr uncacheable latency 87211570SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 95885.746625 # average overall mshr uncacheable latency 87311570SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states 87411570SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.replacements 10998491 # number of replacements 87511570SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.tagsinuse 511.932591 # Cycle average of tags in use 87611570SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.total_refs 274007938 # Total number of references to valid blocks. 87711570SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.sampled_refs 10999003 # Sample count of references to valid blocks. 87811570SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.avg_refs 24.912070 # Average number of references to valid blocks. 87911570SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.warmup_cycle 22037323000 # Cycle when the warmup percentage was hit. 88011570SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.occ_blocks::cpu0.inst 511.932591 # Average occupied blocks per requestor 88111502SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.occ_percent::cpu0.inst 0.999868 # Average percentage of cache occupancy 88211502SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.occ_percent::total 0.999868 # Average percentage of cache occupancy 88310585Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 88411570SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::0 207 # Occupied blocks per task id 88511570SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::1 273 # Occupied blocks per task id 88611570SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::2 32 # Occupied blocks per task id 88710585Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 88811570SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.tag_accesses 581012885 # Number of tag accesses 88911570SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.data_accesses 581012885 # Number of data accesses 89011570SCurtis.Dunham@arm.comsystem.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states 89111570SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_hits::cpu0.inst 274007938 # number of ReadReq hits 89211570SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_hits::total 274007938 # number of ReadReq hits 89311570SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_hits::cpu0.inst 274007938 # number of demand (read+write) hits 89411570SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_hits::total 274007938 # number of demand (read+write) hits 89511570SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_hits::cpu0.inst 274007938 # number of overall hits 89611570SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_hits::total 274007938 # number of overall hits 89711570SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_misses::cpu0.inst 10999003 # number of ReadReq misses 89811570SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_misses::total 10999003 # number of ReadReq misses 89911570SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_misses::cpu0.inst 10999003 # number of demand (read+write) misses 90011570SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_misses::total 10999003 # number of demand (read+write) misses 90111570SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_misses::cpu0.inst 10999003 # number of overall misses 90211570SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_misses::total 10999003 # number of overall misses 90311570SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_miss_latency::cpu0.inst 111429437000 # number of ReadReq miss cycles 90411570SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_miss_latency::total 111429437000 # number of ReadReq miss cycles 90511570SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_miss_latency::cpu0.inst 111429437000 # number of demand (read+write) miss cycles 90611570SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_miss_latency::total 111429437000 # number of demand (read+write) miss cycles 90711570SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_miss_latency::cpu0.inst 111429437000 # number of overall miss cycles 90811570SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_miss_latency::total 111429437000 # number of overall miss cycles 90911570SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_accesses::cpu0.inst 285006941 # number of ReadReq accesses(hits+misses) 91011570SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_accesses::total 285006941 # number of ReadReq accesses(hits+misses) 91111570SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_accesses::cpu0.inst 285006941 # number of demand (read+write) accesses 91211570SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_accesses::total 285006941 # number of demand (read+write) accesses 91311570SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_accesses::cpu0.inst 285006941 # number of overall (read+write) accesses 91411570SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_accesses::total 285006941 # number of overall (read+write) accesses 91511570SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.038592 # miss rate for ReadReq accesses 91611570SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_miss_rate::total 0.038592 # miss rate for ReadReq accesses 91711570SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_miss_rate::cpu0.inst 0.038592 # miss rate for demand accesses 91811570SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_miss_rate::total 0.038592 # miss rate for demand accesses 91911570SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_miss_rate::cpu0.inst 0.038592 # miss rate for overall accesses 92011570SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_miss_rate::total 0.038592 # miss rate for overall accesses 92111570SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10130.867043 # average ReadReq miss latency 92211570SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_avg_miss_latency::total 10130.867043 # average ReadReq miss latency 92311570SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10130.867043 # average overall miss latency 92411570SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_avg_miss_latency::total 10130.867043 # average overall miss latency 92511570SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10130.867043 # average overall miss latency 92611570SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_avg_miss_latency::total 10130.867043 # average overall miss latency 92710585Sandreas.hansson@arm.comsystem.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 92810585Sandreas.hansson@arm.comsystem.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 92910585Sandreas.hansson@arm.comsystem.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 93010585Sandreas.hansson@arm.comsystem.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 93110585Sandreas.hansson@arm.comsystem.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 93210585Sandreas.hansson@arm.comsystem.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 93311570SCurtis.Dunham@arm.comsystem.cpu0.icache.writebacks::writebacks 10998491 # number of writebacks 93411570SCurtis.Dunham@arm.comsystem.cpu0.icache.writebacks::total 10998491 # number of writebacks 93511570SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 10999003 # number of ReadReq MSHR misses 93611570SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_mshr_misses::total 10999003 # number of ReadReq MSHR misses 93711570SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_mshr_misses::cpu0.inst 10999003 # number of demand (read+write) MSHR misses 93811570SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_mshr_misses::total 10999003 # number of demand (read+write) MSHR misses 93911570SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_mshr_misses::cpu0.inst 10999003 # number of overall MSHR misses 94011570SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_mshr_misses::total 10999003 # number of overall MSHR misses 94111570SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 52300 # number of ReadReq MSHR uncacheable 94211570SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_mshr_uncacheable::total 52300 # number of ReadReq MSHR uncacheable 94311570SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 52300 # number of overall MSHR uncacheable misses 94411570SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_mshr_uncacheable_misses::total 52300 # number of overall MSHR uncacheable misses 94511570SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 105929935500 # number of ReadReq MSHR miss cycles 94611570SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_latency::total 105929935500 # number of ReadReq MSHR miss cycles 94711570SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 105929935500 # number of demand (read+write) MSHR miss cycles 94811570SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_mshr_miss_latency::total 105929935500 # number of demand (read+write) MSHR miss cycles 94911570SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 105929935500 # number of overall MSHR miss cycles 95011570SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_mshr_miss_latency::total 105929935500 # number of overall MSHR miss cycles 95111570SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 4836784500 # number of ReadReq MSHR uncacheable cycles 95211570SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 4836784500 # number of ReadReq MSHR uncacheable cycles 95311570SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 4836784500 # number of overall MSHR uncacheable cycles 95411570SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_mshr_uncacheable_latency::total 4836784500 # number of overall MSHR uncacheable cycles 95511570SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.038592 # mshr miss rate for ReadReq accesses 95611570SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_rate::total 0.038592 # mshr miss rate for ReadReq accesses 95711570SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.038592 # mshr miss rate for demand accesses 95811570SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_mshr_miss_rate::total 0.038592 # mshr miss rate for demand accesses 95911570SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.038592 # mshr miss rate for overall accesses 96011570SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_mshr_miss_rate::total 0.038592 # mshr miss rate for overall accesses 96111570SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9630.867043 # average ReadReq mshr miss latency 96211570SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9630.867043 # average ReadReq mshr miss latency 96311570SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9630.867043 # average overall mshr miss latency 96411570SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_avg_mshr_miss_latency::total 9630.867043 # average overall mshr miss latency 96511570SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9630.867043 # average overall mshr miss latency 96611570SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_avg_mshr_miss_latency::total 9630.867043 # average overall mshr miss latency 96711570SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 92481.539197 # average ReadReq mshr uncacheable latency 96811570SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 92481.539197 # average ReadReq mshr uncacheable latency 96911570SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 92481.539197 # average overall mshr uncacheable latency 97011570SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 92481.539197 # average overall mshr uncacheable latency 97111570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states 97211570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.prefetcher.num_hwpf_issued 8833822 # number of hwpf issued 97311570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.prefetcher.pfIdentified 8835143 # number of prefetch candidates identified 97411570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.prefetcher.pfBufferHit 1166 # number of redundant prefetches already in prefetch queue 97510628Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 97610628Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 97711570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.prefetcher.pfSpanPage 1192777 # number of prefetches not generated due to page crossing 97811570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states 97911570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.replacements 3147716 # number of replacements 98011570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.tagsinuse 16192.217188 # Cycle average of tags in use 98111570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.total_refs 27546589 # Total number of references to valid blocks. 98211570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.sampled_refs 3163437 # Sample count of references to valid blocks. 98311570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.avg_refs 8.707804 # Average number of references to valid blocks. 98411570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.warmup_cycle 5661168000 # Cycle when the warmup percentage was hit. 98511570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.occ_blocks::writebacks 15379.701531 # Average occupied blocks per requestor 98611570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 70.199902 # Average occupied blocks per requestor 98711570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 67.449935 # Average occupied blocks per requestor 98811570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 674.865820 # Average occupied blocks per requestor 98911570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.occ_percent::writebacks 0.938702 # Average percentage of cache occupancy 99011570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.004285 # Average percentage of cache occupancy 99111570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.004117 # Average percentage of cache occupancy 99211570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.041191 # Average percentage of cache occupancy 99311570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.occ_percent::total 0.988295 # Average percentage of cache occupancy 99411570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.occ_task_id_blocks::1022 1251 # Occupied blocks per task id 99511570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.occ_task_id_blocks::1023 80 # Occupied blocks per task id 99611570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.occ_task_id_blocks::1024 14390 # Occupied blocks per task id 99711570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1022::0 7 # Occupied blocks per task id 99811502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1022::1 16 # Occupied blocks per task id 99911570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1022::2 214 # Occupied blocks per task id 100011570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1022::3 985 # Occupied blocks per task id 100111570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1022::4 29 # Occupied blocks per task id 100211570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id 100311570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::2 13 # Occupied blocks per task id 100411570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::3 66 # Occupied blocks per task id 100511570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::0 230 # Occupied blocks per task id 100611570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::1 603 # Occupied blocks per task id 100711570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4671 # Occupied blocks per task id 100811570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::3 8629 # Occupied blocks per task id 100911570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::4 257 # Occupied blocks per task id 101011570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.occ_task_id_percent::1022 0.076355 # Percentage of cache occupancy per task id 101111570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.occ_task_id_percent::1023 0.004883 # Percentage of cache occupancy per task id 101211570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.occ_task_id_percent::1024 0.878296 # Percentage of cache occupancy per task id 101311570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.tag_accesses 591522987 # Number of tag accesses 101411570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.data_accesses 591522987 # Number of data accesses 101511570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states 101611570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 626255 # number of ReadReq hits 101711570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 186723 # number of ReadReq hits 101811570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_hits::total 812978 # number of ReadReq hits 101911570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.WritebackDirty_hits::writebacks 4288810 # number of WritebackDirty hits 102011570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.WritebackDirty_hits::total 4288810 # number of WritebackDirty hits 102111570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.WritebackClean_hits::writebacks 13280453 # number of WritebackClean hits 102211570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.WritebackClean_hits::total 13280453 # number of WritebackClean hits 102311570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.UpgradeReq_hits::cpu0.data 665 # number of UpgradeReq hits 102411570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.UpgradeReq_hits::total 665 # number of UpgradeReq hits 102511570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 1 # number of SCUpgradeReq hits 102611570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeReq_hits::total 1 # number of SCUpgradeReq hits 102711570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_hits::cpu0.data 1035920 # number of ReadExReq hits 102811570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_hits::total 1035920 # number of ReadExReq hits 102911570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 10174002 # number of ReadCleanReq hits 103011570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadCleanReq_hits::total 10174002 # number of ReadCleanReq hits 103111570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 3369103 # number of ReadSharedReq hits 103211570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_hits::total 3369103 # number of ReadSharedReq hits 103311570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.InvalidateReq_hits::cpu0.data 227555 # number of InvalidateReq hits 103411570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.InvalidateReq_hits::total 227555 # number of InvalidateReq hits 103511570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.dtb.walker 626255 # number of demand (read+write) hits 103611570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.itb.walker 186723 # number of demand (read+write) hits 103711570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.inst 10174002 # number of demand (read+write) hits 103811570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.data 4405023 # number of demand (read+write) hits 103911570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_hits::total 15392003 # number of demand (read+write) hits 104011570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.dtb.walker 626255 # number of overall hits 104111570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.itb.walker 186723 # number of overall hits 104211570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.inst 10174002 # number of overall hits 104311570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.data 4405023 # number of overall hits 104411570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_hits::total 15392003 # number of overall hits 104511570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 13618 # number of ReadReq misses 104611570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 9516 # number of ReadReq misses 104711570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_misses::total 23134 # number of ReadReq misses 104811570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.UpgradeReq_misses::cpu0.data 275991 # number of UpgradeReq misses 104911570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.UpgradeReq_misses::total 275991 # number of UpgradeReq misses 105011570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 197331 # number of SCUpgradeReq misses 105111570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeReq_misses::total 197331 # number of SCUpgradeReq misses 105211570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 5 # number of SCUpgradeFailReq misses 105311570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_misses::total 5 # number of SCUpgradeFailReq misses 105411570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_misses::cpu0.data 297475 # number of ReadExReq misses 105511570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_misses::total 297475 # number of ReadExReq misses 105611570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 825000 # number of ReadCleanReq misses 105711570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadCleanReq_misses::total 825000 # number of ReadCleanReq misses 105811570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 1116183 # number of ReadSharedReq misses 105911570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_misses::total 1116183 # number of ReadSharedReq misses 106011570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.InvalidateReq_misses::cpu0.data 628029 # number of InvalidateReq misses 106111570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.InvalidateReq_misses::total 628029 # number of InvalidateReq misses 106211570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.dtb.walker 13618 # number of demand (read+write) misses 106311570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.itb.walker 9516 # number of demand (read+write) misses 106411570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.inst 825000 # number of demand (read+write) misses 106511570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.data 1413658 # number of demand (read+write) misses 106611570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_misses::total 2261792 # number of demand (read+write) misses 106711570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.dtb.walker 13618 # number of overall misses 106811570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.itb.walker 9516 # number of overall misses 106911570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.inst 825000 # number of overall misses 107011570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.data 1413658 # number of overall misses 107111570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_misses::total 2261792 # number of overall misses 107211570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 516990000 # number of ReadReq miss cycles 107311570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 406929500 # number of ReadReq miss cycles 107411570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_miss_latency::total 923919500 # number of ReadReq miss cycles 107511570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 2174724500 # number of UpgradeReq miss cycles 107611570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.UpgradeReq_miss_latency::total 2174724500 # number of UpgradeReq miss cycles 107711570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 1540108000 # number of SCUpgradeReq miss cycles 107811570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeReq_miss_latency::total 1540108000 # number of SCUpgradeReq miss cycles 107911570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 3340999 # number of SCUpgradeFailReq miss cycles 108011570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 3340999 # number of SCUpgradeFailReq miss cycles 108111570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 14927255997 # number of ReadExReq miss cycles 108211570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_miss_latency::total 14927255997 # number of ReadExReq miss cycles 108311570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 27980842000 # number of ReadCleanReq miss cycles 108411570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadCleanReq_miss_latency::total 27980842000 # number of ReadCleanReq miss cycles 108511570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 40509457995 # number of ReadSharedReq miss cycles 108611570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_miss_latency::total 40509457995 # number of ReadSharedReq miss cycles 108711570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data 326706500 # number of InvalidateReq miss cycles 108811570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.InvalidateReq_miss_latency::total 326706500 # number of InvalidateReq miss cycles 108911570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 516990000 # number of demand (read+write) miss cycles 109011570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 406929500 # number of demand (read+write) miss cycles 109111570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_miss_latency::cpu0.inst 27980842000 # number of demand (read+write) miss cycles 109211570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_miss_latency::cpu0.data 55436713992 # number of demand (read+write) miss cycles 109311570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_miss_latency::total 84341475492 # number of demand (read+write) miss cycles 109411570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 516990000 # number of overall miss cycles 109511570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 406929500 # number of overall miss cycles 109611570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_miss_latency::cpu0.inst 27980842000 # number of overall miss cycles 109711570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_miss_latency::cpu0.data 55436713992 # number of overall miss cycles 109811570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_miss_latency::total 84341475492 # number of overall miss cycles 109911570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 639873 # number of ReadReq accesses(hits+misses) 110011570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 196239 # number of ReadReq accesses(hits+misses) 110111570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_accesses::total 836112 # number of ReadReq accesses(hits+misses) 110211570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.WritebackDirty_accesses::writebacks 4288810 # number of WritebackDirty accesses(hits+misses) 110311570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.WritebackDirty_accesses::total 4288810 # number of WritebackDirty accesses(hits+misses) 110411570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.WritebackClean_accesses::writebacks 13280453 # number of WritebackClean accesses(hits+misses) 110511570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.WritebackClean_accesses::total 13280453 # number of WritebackClean accesses(hits+misses) 110611570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 276656 # number of UpgradeReq accesses(hits+misses) 110711570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.UpgradeReq_accesses::total 276656 # number of UpgradeReq accesses(hits+misses) 110811570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 197332 # number of SCUpgradeReq accesses(hits+misses) 110911570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeReq_accesses::total 197332 # number of SCUpgradeReq accesses(hits+misses) 111011570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 5 # number of SCUpgradeFailReq accesses(hits+misses) 111111570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_accesses::total 5 # number of SCUpgradeFailReq accesses(hits+misses) 111211570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1333395 # number of ReadExReq accesses(hits+misses) 111311570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_accesses::total 1333395 # number of ReadExReq accesses(hits+misses) 111411570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 10999002 # number of ReadCleanReq accesses(hits+misses) 111511570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadCleanReq_accesses::total 10999002 # number of ReadCleanReq accesses(hits+misses) 111611570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 4485286 # number of ReadSharedReq accesses(hits+misses) 111711570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_accesses::total 4485286 # number of ReadSharedReq accesses(hits+misses) 111811570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 855584 # number of InvalidateReq accesses(hits+misses) 111911570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.InvalidateReq_accesses::total 855584 # number of InvalidateReq accesses(hits+misses) 112011570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 639873 # number of demand (read+write) accesses 112111570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.itb.walker 196239 # number of demand (read+write) accesses 112211570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.inst 10999002 # number of demand (read+write) accesses 112311570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.data 5818681 # number of demand (read+write) accesses 112411570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_accesses::total 17653795 # number of demand (read+write) accesses 112511570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 639873 # number of overall (read+write) accesses 112611570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.itb.walker 196239 # number of overall (read+write) accesses 112711570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.inst 10999002 # number of overall (read+write) accesses 112811570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.data 5818681 # number of overall (read+write) accesses 112911570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_accesses::total 17653795 # number of overall (read+write) accesses 113011570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.021282 # miss rate for ReadReq accesses 113111570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.048492 # miss rate for ReadReq accesses 113211570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::total 0.027669 # miss rate for ReadReq accesses 113311570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.997596 # miss rate for UpgradeReq accesses 113411570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.UpgradeReq_miss_rate::total 0.997596 # miss rate for UpgradeReq accesses 113511570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.999995 # miss rate for SCUpgradeReq accesses 113611570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.999995 # miss rate for SCUpgradeReq accesses 113710636Snilay@cs.wisc.edusystem.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses 113810585Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 113911570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.223096 # miss rate for ReadExReq accesses 114011570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_miss_rate::total 0.223096 # miss rate for ReadExReq accesses 114111570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.075007 # miss rate for ReadCleanReq accesses 114211570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.075007 # miss rate for ReadCleanReq accesses 114311570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.248854 # miss rate for ReadSharedReq accesses 114411570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.248854 # miss rate for ReadSharedReq accesses 114511570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.734035 # miss rate for InvalidateReq accesses 114611570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.InvalidateReq_miss_rate::total 0.734035 # miss rate for InvalidateReq accesses 114711570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.021282 # miss rate for demand accesses 114811570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.048492 # miss rate for demand accesses 114911570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.075007 # miss rate for demand accesses 115011570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.data 0.242952 # miss rate for demand accesses 115111570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_miss_rate::total 0.128119 # miss rate for demand accesses 115211570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.021282 # miss rate for overall accesses 115311570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.048492 # miss rate for overall accesses 115411570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.075007 # miss rate for overall accesses 115511570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.data 0.242952 # miss rate for overall accesses 115611570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_miss_rate::total 0.128119 # miss rate for overall accesses 115711570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 37963.724482 # average ReadReq miss latency 115811570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 42762.662884 # average ReadReq miss latency 115911570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_avg_miss_latency::total 39937.732342 # average ReadReq miss latency 116011570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 7879.693541 # average UpgradeReq miss latency 116111570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 7879.693541 # average UpgradeReq miss latency 116211570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 7804.693637 # average SCUpgradeReq miss latency 116311570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 7804.693637 # average SCUpgradeReq miss latency 116411570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 668199.800000 # average SCUpgradeFailReq miss latency 116511570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 668199.800000 # average SCUpgradeFailReq miss latency 116611570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 50179.867206 # average ReadExReq miss latency 116711570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_avg_miss_latency::total 50179.867206 # average ReadExReq miss latency 116811570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 33916.172121 # average ReadCleanReq miss latency 116911570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 33916.172121 # average ReadCleanReq miss latency 117011570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 36292.846240 # average ReadSharedReq miss latency 117111570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 36292.846240 # average ReadSharedReq miss latency 117211570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 520.209258 # average InvalidateReq miss latency 117311570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 520.209258 # average InvalidateReq miss latency 117411570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 37963.724482 # average overall miss latency 117511570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 42762.662884 # average overall miss latency 117611570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 33916.172121 # average overall miss latency 117711570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 39215.081718 # average overall miss latency 117811570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_avg_miss_latency::total 37289.669206 # average overall miss latency 117911570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 37963.724482 # average overall miss latency 118011570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 42762.662884 # average overall miss latency 118111570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 33916.172121 # average overall miss latency 118211570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 39215.081718 # average overall miss latency 118311570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_avg_miss_latency::total 37289.669206 # average overall miss latency 118411570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 118510585Sandreas.hansson@arm.comsystem.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 118611570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 118710585Sandreas.hansson@arm.comsystem.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 118811570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 118910585Sandreas.hansson@arm.comsystem.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 119011570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.unused_prefetches 56740 # number of HardPF blocks evicted w/o reference 119111570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.writebacks::writebacks 1791276 # number of writebacks 119211570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.writebacks::total 1791276 # number of writebacks 119311570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker 1 # number of ReadReq MSHR hits 119411570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 4 # number of ReadReq MSHR hits 119511570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_mshr_hits::total 5 # number of ReadReq MSHR hits 119611570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 10486 # number of ReadExReq MSHR hits 119711570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_hits::total 10486 # number of ReadExReq MSHR hits 119811570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 14 # number of ReadCleanReq MSHR hits 119911570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_hits::total 14 # number of ReadCleanReq MSHR hits 120011570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 1072 # number of ReadSharedReq MSHR hits 120111570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_hits::total 1072 # number of ReadSharedReq MSHR hits 120211570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_hits::cpu0.data 4 # number of InvalidateReq MSHR hits 120311570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_hits::total 4 # number of InvalidateReq MSHR hits 120411570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker 1 # number of demand (read+write) MSHR hits 120511570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 4 # number of demand (read+write) MSHR hits 120611570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_mshr_hits::cpu0.inst 14 # number of demand (read+write) MSHR hits 120711570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_mshr_hits::cpu0.data 11558 # number of demand (read+write) MSHR hits 120811570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_mshr_hits::total 11577 # number of demand (read+write) MSHR hits 120911570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker 1 # number of overall MSHR hits 121011570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 4 # number of overall MSHR hits 121111570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_mshr_hits::cpu0.inst 14 # number of overall MSHR hits 121211570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_mshr_hits::cpu0.data 11558 # number of overall MSHR hits 121311570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_mshr_hits::total 11577 # number of overall MSHR hits 121411570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 13617 # number of ReadReq MSHR misses 121511570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 9512 # number of ReadReq MSHR misses 121611570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_mshr_misses::total 23129 # number of ReadReq MSHR misses 121711570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 884711 # number of HardPFReq MSHR misses 121811570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.HardPFReq_mshr_misses::total 884711 # number of HardPFReq MSHR misses 121911570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 275991 # number of UpgradeReq MSHR misses 122011570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.UpgradeReq_mshr_misses::total 275991 # number of UpgradeReq MSHR misses 122111570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 197331 # number of SCUpgradeReq MSHR misses 122211570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 197331 # number of SCUpgradeReq MSHR misses 122311570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 5 # number of SCUpgradeFailReq MSHR misses 122411570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 5 # number of SCUpgradeFailReq MSHR misses 122511570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 286989 # number of ReadExReq MSHR misses 122611570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_misses::total 286989 # number of ReadExReq MSHR misses 122711570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 824986 # number of ReadCleanReq MSHR misses 122811570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_misses::total 824986 # number of ReadCleanReq MSHR misses 122911570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 1115111 # number of ReadSharedReq MSHR misses 123011570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_misses::total 1115111 # number of ReadSharedReq MSHR misses 123111570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data 628025 # number of InvalidateReq MSHR misses 123211570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_misses::total 628025 # number of InvalidateReq MSHR misses 123311570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 13617 # number of demand (read+write) MSHR misses 123411570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 9512 # number of demand (read+write) MSHR misses 123511570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_mshr_misses::cpu0.inst 824986 # number of demand (read+write) MSHR misses 123611570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_mshr_misses::cpu0.data 1402100 # number of demand (read+write) MSHR misses 123711570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_mshr_misses::total 2250215 # number of demand (read+write) MSHR misses 123811570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 13617 # number of overall MSHR misses 123911570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 9512 # number of overall MSHR misses 124011570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_mshr_misses::cpu0.inst 824986 # number of overall MSHR misses 124111570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_mshr_misses::cpu0.data 1402100 # number of overall MSHR misses 124211570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 884711 # number of overall MSHR misses 124311570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_mshr_misses::total 3134926 # number of overall MSHR misses 124411570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 52300 # number of ReadReq MSHR uncacheable 124511570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 29793 # number of ReadReq MSHR uncacheable 124611570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable::total 82093 # number of ReadReq MSHR uncacheable 124711570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 29400 # number of WriteReq MSHR uncacheable 124811570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.WriteReq_mshr_uncacheable::total 29400 # number of WriteReq MSHR uncacheable 124911570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 52300 # number of overall MSHR uncacheable misses 125011570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 59193 # number of overall MSHR uncacheable misses 125111570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_mshr_uncacheable_misses::total 111493 # number of overall MSHR uncacheable misses 125211570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 435264000 # number of ReadReq MSHR miss cycles 125311570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 349787000 # number of ReadReq MSHR miss cycles 125411570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_latency::total 785051000 # number of ReadReq MSHR miss cycles 125511570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 42685466504 # number of HardPFReq MSHR miss cycles 125611570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 42685466504 # number of HardPFReq MSHR miss cycles 125711570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 5679653996 # number of UpgradeReq MSHR miss cycles 125811570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 5679653996 # number of UpgradeReq MSHR miss cycles 125911570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 3269289499 # number of SCUpgradeReq MSHR miss cycles 126011570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 3269289499 # number of SCUpgradeReq MSHR miss cycles 126111570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 2944999 # number of SCUpgradeFailReq MSHR miss cycles 126211570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 2944999 # number of SCUpgradeFailReq MSHR miss cycles 126311570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 11923656997 # number of ReadExReq MSHR miss cycles 126411570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 11923656997 # number of ReadExReq MSHR miss cycles 126511570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 23030463500 # number of ReadCleanReq MSHR miss cycles 126611570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 23030463500 # number of ReadCleanReq MSHR miss cycles 126711570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 33712054495 # number of ReadSharedReq MSHR miss cycles 126811570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 33712054495 # number of ReadSharedReq MSHR miss cycles 126911570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 20896498500 # number of InvalidateReq MSHR miss cycles 127011570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 20896498500 # number of InvalidateReq MSHR miss cycles 127111570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 435264000 # number of demand (read+write) MSHR miss cycles 127211570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 349787000 # number of demand (read+write) MSHR miss cycles 127311570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 23030463500 # number of demand (read+write) MSHR miss cycles 127411570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 45635711492 # number of demand (read+write) MSHR miss cycles 127511570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_mshr_miss_latency::total 69451225992 # number of demand (read+write) MSHR miss cycles 127611570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 435264000 # number of overall MSHR miss cycles 127711570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 349787000 # number of overall MSHR miss cycles 127811570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 23030463500 # number of overall MSHR miss cycles 127911570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 45635711492 # number of overall MSHR miss cycles 128011570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 42685466504 # number of overall MSHR miss cycles 128111570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::total 112136692496 # number of overall MSHR miss cycles 128211570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 4418384500 # number of ReadReq MSHR uncacheable cycles 128311570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5437142000 # number of ReadReq MSHR uncacheable cycles 128411570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 9855526500 # number of ReadReq MSHR uncacheable cycles 128511570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 4418384500 # number of overall MSHR uncacheable cycles 128611570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 5437142000 # number of overall MSHR uncacheable cycles 128711570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_mshr_uncacheable_latency::total 9855526500 # number of overall MSHR uncacheable cycles 128811570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.021281 # mshr miss rate for ReadReq accesses 128911570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.048472 # mshr miss rate for ReadReq accesses 129011570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.027663 # mshr miss rate for ReadReq accesses 129110585Sandreas.hansson@arm.comsystem.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 129210585Sandreas.hansson@arm.comsystem.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 129311570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.997596 # mshr miss rate for UpgradeReq accesses 129411570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.997596 # mshr miss rate for UpgradeReq accesses 129511570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.999995 # mshr miss rate for SCUpgradeReq accesses 129611570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.999995 # mshr miss rate for SCUpgradeReq accesses 129710636Snilay@cs.wisc.edusystem.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses 129810585Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 129911570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.215232 # mshr miss rate for ReadExReq accesses 130011570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.215232 # mshr miss rate for ReadExReq accesses 130111570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.075006 # mshr miss rate for ReadCleanReq accesses 130211570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.075006 # mshr miss rate for ReadCleanReq accesses 130311570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.248615 # mshr miss rate for ReadSharedReq accesses 130411570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.248615 # mshr miss rate for ReadSharedReq accesses 130511570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.734031 # mshr miss rate for InvalidateReq accesses 130611570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.734031 # mshr miss rate for InvalidateReq accesses 130711570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.021281 # mshr miss rate for demand accesses 130811570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.048472 # mshr miss rate for demand accesses 130911570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.075006 # mshr miss rate for demand accesses 131011570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.240965 # mshr miss rate for demand accesses 131111570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_mshr_miss_rate::total 0.127464 # mshr miss rate for demand accesses 131211570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.021281 # mshr miss rate for overall accesses 131311570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.048472 # mshr miss rate for overall accesses 131411570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.075006 # mshr miss rate for overall accesses 131511570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.240965 # mshr miss rate for overall accesses 131610585Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses 131711570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_mshr_miss_rate::total 0.177578 # mshr miss rate for overall accesses 131811570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 31964.749945 # average ReadReq mshr miss latency 131911570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 36773.233810 # average ReadReq mshr miss latency 132011570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 33942.280254 # average ReadReq mshr miss latency 132111570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 48247.921077 # average HardPFReq mshr miss latency 132211570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 48247.921077 # average HardPFReq mshr miss latency 132311570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20579.127566 # average UpgradeReq mshr miss latency 132411570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20579.127566 # average UpgradeReq mshr miss latency 132511570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 16567.541334 # average SCUpgradeReq mshr miss latency 132611570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 16567.541334 # average SCUpgradeReq mshr miss latency 132711570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 588999.800000 # average SCUpgradeFailReq mshr miss latency 132811570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 588999.800000 # average SCUpgradeFailReq mshr miss latency 132911570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 41547.435606 # average ReadExReq mshr miss latency 133011570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 41547.435606 # average ReadExReq mshr miss latency 133111570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 27916.187063 # average ReadCleanReq mshr miss latency 133211570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 27916.187063 # average ReadCleanReq mshr miss latency 133311570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 30232.016808 # average ReadSharedReq mshr miss latency 133411570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 30232.016808 # average ReadSharedReq mshr miss latency 133511570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 33273.354564 # average InvalidateReq mshr miss latency 133611570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 33273.354564 # average InvalidateReq mshr miss latency 133711570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 31964.749945 # average overall mshr miss latency 133811570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 36773.233810 # average overall mshr miss latency 133911570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 27916.187063 # average overall mshr miss latency 134011570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 32548.114608 # average overall mshr miss latency 134111570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_avg_mshr_miss_latency::total 30864.262300 # average overall mshr miss latency 134211570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 31964.749945 # average overall mshr miss latency 134311570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 36773.233810 # average overall mshr miss latency 134411570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 27916.187063 # average overall mshr miss latency 134511570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 32548.114608 # average overall mshr miss latency 134611570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 48247.921077 # average overall mshr miss latency 134711570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::total 35770.124238 # average overall mshr miss latency 134811570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 84481.539197 # average ReadReq mshr uncacheable latency 134911570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182497.298023 # average ReadReq mshr uncacheable latency 135011570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 120053.189675 # average ReadReq mshr uncacheable latency 135111570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 84481.539197 # average overall mshr uncacheable latency 135211570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 91854.476036 # average overall mshr uncacheable latency 135311570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 88395.921717 # average overall mshr uncacheable latency 135411570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoop_filter.tot_requests 36072564 # Total number of requests made to the snoop filter. 135511570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoop_filter.hit_single_requests 18399437 # Number of requests hitting in the snoop filter with a single holder of the requested data. 135611570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoop_filter.hit_multi_requests 3515 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 135711570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoop_filter.tot_snoops 2427957 # Total number of snoops made to the snoop filter. 135811570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoop_filter.hit_single_snoops 2427386 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 135911570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 571 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 136011570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states 136111570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadReq 1003133 # Transaction distribution 136211570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadResp 16585926 # Transaction distribution 136311502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution 136411570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::WriteReq 29400 # Transaction distribution 136511570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::WriteResp 29400 # Transaction distribution 136611570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::WritebackDirty 6083435 # Transaction distribution 136711570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::WritebackClean 13283967 # Transaction distribution 136811570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::CleanEvict 3350152 # Transaction distribution 136911570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::HardPFReq 1133444 # Transaction distribution 137011570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution 137111570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::UpgradeReq 490495 # Transaction distribution 137211570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::SCUpgradeReq 347636 # Transaction distribution 137311570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::UpgradeResp 543136 # Transaction distribution 137411570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 77 # Transaction distribution 137511570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::UpgradeFailResp 138 # Transaction distribution 137611570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadExReq 1366077 # Transaction distribution 137711570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadExResp 1342549 # Transaction distribution 137811570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadCleanReq 10999003 # Transaction distribution 137911570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadSharedReq 5499511 # Transaction distribution 138011570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::InvalidateReq 903440 # Transaction distribution 138111570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::InvalidateResp 855584 # Transaction distribution 138211570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 33101096 # Packet count per connected master and slave (bytes) 138311570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 21166131 # Packet count per connected master and slave (bytes) 138411570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 412052 # Packet count per connected master and slave (bytes) 138511570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1345098 # Packet count per connected master and slave (bytes) 138611570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.pkt_count::total 56024377 # Packet count per connected master and slave (bytes) 138711570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 1411186752 # Cumulative packet size per connected master and slave (bytes) 138811570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 800229141 # Cumulative packet size per connected master and slave (bytes) 138911570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1569912 # Cumulative packet size per connected master and slave (bytes) 139011570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 5118984 # Cumulative packet size per connected master and slave (bytes) 139111570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.pkt_size::total 2218104789 # Cumulative packet size per connected master and slave (bytes) 139211570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoops 7999072 # Total snoops (count) 139311570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoopTraffic 122429440 # Total snoop traffic (bytes) 139411570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoop_fanout::samples 26916994 # Request fanout histogram 139511570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoop_fanout::mean 0.103450 # Request fanout histogram 139611570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoop_fanout::stdev 0.304616 # Request fanout histogram 139710585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 139811570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoop_fanout::0 24132997 89.66% 89.66% # Request fanout histogram 139911570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoop_fanout::1 2783426 10.34% 100.00% # Request fanout histogram 140011570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoop_fanout::2 571 0.00% 100.00% # Request fanout histogram 140110585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 140211138Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 140310827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 140411570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoop_fanout::total 26916994 # Request fanout histogram 140511570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.reqLayer0.occupancy 35963769502 # Layer occupancy (ticks) 140611201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 140711570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoopLayer0.occupancy 196401052 # Layer occupancy (ticks) 140810585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 140911570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.respLayer0.occupancy 16580139110 # Layer occupancy (ticks) 141010585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 141111570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.respLayer1.occupancy 9441182874 # Layer occupancy (ticks) 141210585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 141311570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.respLayer2.occupancy 215851922 # Layer occupancy (ticks) 141410585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 141511570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.respLayer3.occupancy 705346257 # Layer occupancy (ticks) 141610585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 141711570SCurtis.Dunham@arm.comsystem.cpu1.branchPred.lookups 118915951 # Number of BP lookups 141811570SCurtis.Dunham@arm.comsystem.cpu1.branchPred.condPredicted 85033049 # Number of conditional branches predicted 141911570SCurtis.Dunham@arm.comsystem.cpu1.branchPred.condIncorrect 5367569 # Number of conditional branches incorrect 142011570SCurtis.Dunham@arm.comsystem.cpu1.branchPred.BTBLookups 89750040 # Number of BTB lookups 142111570SCurtis.Dunham@arm.comsystem.cpu1.branchPred.BTBHits 63411692 # Number of BTB hits 142210585Sandreas.hansson@arm.comsystem.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 142311570SCurtis.Dunham@arm.comsystem.cpu1.branchPred.BTBHitPct 70.653664 # BTB Hit Percentage 142411570SCurtis.Dunham@arm.comsystem.cpu1.branchPred.usedRAS 13468810 # Number of times the RAS was used to get a target. 142511570SCurtis.Dunham@arm.comsystem.cpu1.branchPred.RASInCorrect 887929 # Number of incorrect RAS predictions. 142611570SCurtis.Dunham@arm.comsystem.cpu1.branchPred.indirectLookups 3084567 # Number of indirect predictor lookups. 142711570SCurtis.Dunham@arm.comsystem.cpu1.branchPred.indirectHits 1998882 # Number of indirect target hits. 142811570SCurtis.Dunham@arm.comsystem.cpu1.branchPred.indirectMisses 1085685 # Number of indirect misses. 142911570SCurtis.Dunham@arm.comsystem.cpu1.branchPredindirectMispredicted 396796 # Number of mispredicted indirect branches. 143011570SCurtis.Dunham@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states 143110628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 143210628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 143310628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 143410628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 143510628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 143610628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 143710628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 143810628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 143910585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 144010585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 144110585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 144210585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 144310585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 144410585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 144510585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 144610585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 144710585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 144810585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 144910585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 145010585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 145110585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 145210585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 145310585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 145410585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 145510585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 145610585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 145710585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 145810585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 145910585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 146011570SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states 146111570SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walks 246313 # Table walker walks requested 146211570SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walksLong 246313 # Table walker walks initiated with long descriptors 146311570SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walksLongTerminationLevel::Level2 8582 # Level at which table walker walks with long descriptors terminate 146411570SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walksLongTerminationLevel::Level3 75463 # Level at which table walker walks with long descriptors terminate 146511570SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkWaitTime::samples 246313 # Table walker wait (enqueue to first request) latency 146611570SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkWaitTime::0 246313 100.00% 100.00% # Table walker wait (enqueue to first request) latency 146711570SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkWaitTime::total 246313 # Table walker wait (enqueue to first request) latency 146811570SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::samples 84045 # Table walker service (enqueue to completion) latency 146911570SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::mean 22346.070557 # Table walker service (enqueue to completion) latency 147011570SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::gmean 21064.042846 # Table walker service (enqueue to completion) latency 147111570SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::stdev 12361.258067 # Table walker service (enqueue to completion) latency 147211570SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::0-32767 79296 94.35% 94.35% # Table walker service (enqueue to completion) latency 147311570SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::32768-65535 4004 4.76% 99.11% # Table walker service (enqueue to completion) latency 147411570SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::65536-98303 175 0.21% 99.32% # Table walker service (enqueue to completion) latency 147511570SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::98304-131071 458 0.54% 99.87% # Table walker service (enqueue to completion) latency 147611570SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::131072-163839 22 0.03% 99.89% # Table walker service (enqueue to completion) latency 147711570SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::163840-196607 12 0.01% 99.91% # Table walker service (enqueue to completion) latency 147811570SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::196608-229375 27 0.03% 99.94% # Table walker service (enqueue to completion) latency 147911570SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::229376-262143 10 0.01% 99.95% # Table walker service (enqueue to completion) latency 148011570SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::262144-294911 13 0.02% 99.97% # Table walker service (enqueue to completion) latency 148111570SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::294912-327679 13 0.02% 99.98% # Table walker service (enqueue to completion) latency 148211570SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::327680-360447 6 0.01% 99.99% # Table walker service (enqueue to completion) latency 148311570SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::360448-393215 3 0.00% 99.99% # Table walker service (enqueue to completion) latency 148411570SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::393216-425983 3 0.00% 100.00% # Table walker service (enqueue to completion) latency 148511570SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::458752-491519 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 148611570SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 148711570SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::total 84045 # Table walker service (enqueue to completion) latency 148811570SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walksPending::samples -766256056 # Table walker pending requests distribution 148911570SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walksPending::0 -766256056 100.00% 100.00% # Table walker pending requests distribution 149011570SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walksPending::total -766256056 # Table walker pending requests distribution 149111570SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkPageSizes::4K 75463 89.79% 89.79% # Table walker page sizes translated 149211570SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkPageSizes::2M 8582 10.21% 100.00% # Table walker page sizes translated 149311570SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkPageSizes::total 84045 # Table walker page sizes translated 149411570SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 246313 # Table walker requests started/completed, data/inst 149510628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 149611570SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Requested::total 246313 # Table walker requests started/completed, data/inst 149711570SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 84045 # Table walker requests started/completed, data/inst 149810628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 149911570SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Completed::total 84045 # Table walker requests started/completed, data/inst 150011570SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin::total 330358 # Table walker requests started/completed, data/inst 150110585Sandreas.hansson@arm.comsystem.cpu1.dtb.inst_hits 0 # ITB inst hits 150210585Sandreas.hansson@arm.comsystem.cpu1.dtb.inst_misses 0 # ITB inst misses 150311570SCurtis.Dunham@arm.comsystem.cpu1.dtb.read_hits 74020776 # DTB read hits 150411570SCurtis.Dunham@arm.comsystem.cpu1.dtb.read_misses 200548 # DTB read misses 150511570SCurtis.Dunham@arm.comsystem.cpu1.dtb.write_hits 65603987 # DTB write hits 150611570SCurtis.Dunham@arm.comsystem.cpu1.dtb.write_misses 45765 # DTB write misses 150711441Sandreas.hansson@arm.comsystem.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed 150810585Sandreas.hansson@arm.comsystem.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 150911570SCurtis.Dunham@arm.comsystem.cpu1.dtb.flush_tlb_mva_asid 43240 # Number of times TLB was flushed by MVA & ASID 151011570SCurtis.Dunham@arm.comsystem.cpu1.dtb.flush_tlb_asid 1075 # Number of times TLB was flushed by ASID 151111570SCurtis.Dunham@arm.comsystem.cpu1.dtb.flush_entries 34845 # Number of entries that have been flushed from TLB 151211570SCurtis.Dunham@arm.comsystem.cpu1.dtb.align_faults 889 # Number of TLB faults due to alignment restrictions 151311570SCurtis.Dunham@arm.comsystem.cpu1.dtb.prefetch_faults 6796 # Number of TLB faults due to prefetch 151410585Sandreas.hansson@arm.comsystem.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 151511570SCurtis.Dunham@arm.comsystem.cpu1.dtb.perms_faults 11277 # Number of TLB faults due to permissions restrictions 151611570SCurtis.Dunham@arm.comsystem.cpu1.dtb.read_accesses 74221324 # DTB read accesses 151711570SCurtis.Dunham@arm.comsystem.cpu1.dtb.write_accesses 65649752 # DTB write accesses 151810585Sandreas.hansson@arm.comsystem.cpu1.dtb.inst_accesses 0 # ITB inst accesses 151911570SCurtis.Dunham@arm.comsystem.cpu1.dtb.hits 139624763 # DTB hits 152011570SCurtis.Dunham@arm.comsystem.cpu1.dtb.misses 246313 # DTB misses 152111570SCurtis.Dunham@arm.comsystem.cpu1.dtb.accesses 139871076 # DTB accesses 152211570SCurtis.Dunham@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states 152310628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 152410628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 152510628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 152610628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 152710628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 152810628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 152910628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 153010628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 153110585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 153210585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 153310585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 153410585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 153510585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 153610585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 153710585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 153810585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 153910585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 154010585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 154110585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 154210585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 154310585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 154410585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 154510585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 154610585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 154710585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 154810585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 154910585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 155010585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 155110585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 155211570SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states 155311570SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walks 60327 # Table walker walks requested 155411570SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walksLong 60327 # Table walker walks initiated with long descriptors 155511570SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walksLongTerminationLevel::Level2 545 # Level at which table walker walks with long descriptors terminate 155611570SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walksLongTerminationLevel::Level3 52409 # Level at which table walker walks with long descriptors terminate 155711570SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkWaitTime::samples 60327 # Table walker wait (enqueue to first request) latency 155811570SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkWaitTime::0 60327 100.00% 100.00% # Table walker wait (enqueue to first request) latency 155911570SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkWaitTime::total 60327 # Table walker wait (enqueue to first request) latency 156011570SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkCompletionTime::samples 52954 # Table walker service (enqueue to completion) latency 156111570SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkCompletionTime::mean 24879.980738 # Table walker service (enqueue to completion) latency 156211570SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkCompletionTime::gmean 23402.458623 # Table walker service (enqueue to completion) latency 156311570SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkCompletionTime::stdev 13318.614145 # Table walker service (enqueue to completion) latency 156411570SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkCompletionTime::0-32767 48523 91.63% 91.63% # Table walker service (enqueue to completion) latency 156511570SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkCompletionTime::32768-65535 3764 7.11% 98.74% # Table walker service (enqueue to completion) latency 156611570SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkCompletionTime::65536-98303 13 0.02% 98.76% # Table walker service (enqueue to completion) latency 156711570SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkCompletionTime::98304-131071 577 1.09% 99.85% # Table walker service (enqueue to completion) latency 156811570SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkCompletionTime::131072-163839 18 0.03% 99.89% # Table walker service (enqueue to completion) latency 156911570SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkCompletionTime::163840-196607 8 0.02% 99.90% # Table walker service (enqueue to completion) latency 157011570SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkCompletionTime::196608-229375 20 0.04% 99.94% # Table walker service (enqueue to completion) latency 157111570SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkCompletionTime::229376-262143 20 0.04% 99.98% # Table walker service (enqueue to completion) latency 157211570SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkCompletionTime::262144-294911 3 0.01% 99.98% # Table walker service (enqueue to completion) latency 157311570SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkCompletionTime::294912-327679 4 0.01% 99.99% # Table walker service (enqueue to completion) latency 157411570SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkCompletionTime::327680-360447 1 0.00% 99.99% # Table walker service (enqueue to completion) latency 157511570SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkCompletionTime::360448-393215 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 157611570SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkCompletionTime::393216-425983 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 157711570SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 157811570SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkCompletionTime::total 52954 # Table walker service (enqueue to completion) latency 157911570SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walksPending::samples -766782556 # Table walker pending requests distribution 158011570SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walksPending::0 -766782556 100.00% 100.00% # Table walker pending requests distribution 158111570SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walksPending::total -766782556 # Table walker pending requests distribution 158211570SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkPageSizes::4K 52409 98.97% 98.97% # Table walker page sizes translated 158311570SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkPageSizes::2M 545 1.03% 100.00% # Table walker page sizes translated 158411570SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkPageSizes::total 52954 # Table walker page sizes translated 158510628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 158611570SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 60327 # Table walker requests started/completed, data/inst 158711570SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Requested::total 60327 # Table walker requests started/completed, data/inst 158810628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 158911570SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 52954 # Table walker requests started/completed, data/inst 159011570SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Completed::total 52954 # Table walker requests started/completed, data/inst 159111570SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkRequestOrigin::total 113281 # Table walker requests started/completed, data/inst 159211570SCurtis.Dunham@arm.comsystem.cpu1.itb.inst_hits 210682225 # ITB inst hits 159311570SCurtis.Dunham@arm.comsystem.cpu1.itb.inst_misses 60327 # ITB inst misses 159410585Sandreas.hansson@arm.comsystem.cpu1.itb.read_hits 0 # DTB read hits 159510585Sandreas.hansson@arm.comsystem.cpu1.itb.read_misses 0 # DTB read misses 159610585Sandreas.hansson@arm.comsystem.cpu1.itb.write_hits 0 # DTB write hits 159710585Sandreas.hansson@arm.comsystem.cpu1.itb.write_misses 0 # DTB write misses 159811441Sandreas.hansson@arm.comsystem.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed 159910585Sandreas.hansson@arm.comsystem.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 160011570SCurtis.Dunham@arm.comsystem.cpu1.itb.flush_tlb_mva_asid 43240 # Number of times TLB was flushed by MVA & ASID 160111570SCurtis.Dunham@arm.comsystem.cpu1.itb.flush_tlb_asid 1075 # Number of times TLB was flushed by ASID 160211570SCurtis.Dunham@arm.comsystem.cpu1.itb.flush_entries 24520 # Number of entries that have been flushed from TLB 160310585Sandreas.hansson@arm.comsystem.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 160410585Sandreas.hansson@arm.comsystem.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 160510585Sandreas.hansson@arm.comsystem.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 160611570SCurtis.Dunham@arm.comsystem.cpu1.itb.perms_faults 163777 # Number of TLB faults due to permissions restrictions 160710585Sandreas.hansson@arm.comsystem.cpu1.itb.read_accesses 0 # DTB read accesses 160810585Sandreas.hansson@arm.comsystem.cpu1.itb.write_accesses 0 # DTB write accesses 160911570SCurtis.Dunham@arm.comsystem.cpu1.itb.inst_accesses 210742552 # ITB inst accesses 161011570SCurtis.Dunham@arm.comsystem.cpu1.itb.hits 210682225 # DTB hits 161111570SCurtis.Dunham@arm.comsystem.cpu1.itb.misses 60327 # DTB misses 161211570SCurtis.Dunham@arm.comsystem.cpu1.itb.accesses 210742552 # DTB accesses 161311570SCurtis.Dunham@arm.comsystem.cpu1.numPwrStateTransitions 10392 # Number of power state transitions 161411570SCurtis.Dunham@arm.comsystem.cpu1.pwrStateClkGateDist::samples 5196 # Distribution of time spent in the clock gated state 161511570SCurtis.Dunham@arm.comsystem.cpu1.pwrStateClkGateDist::mean 9053828227.255966 # Distribution of time spent in the clock gated state 161611570SCurtis.Dunham@arm.comsystem.cpu1.pwrStateClkGateDist::stdev 188730440437.234528 # Distribution of time spent in the clock gated state 161711570SCurtis.Dunham@arm.comsystem.cpu1.pwrStateClkGateDist::underflows 3531 67.96% 67.96% # Distribution of time spent in the clock gated state 161811570SCurtis.Dunham@arm.comsystem.cpu1.pwrStateClkGateDist::1000-5e+10 1645 31.66% 99.62% # Distribution of time spent in the clock gated state 161911570SCurtis.Dunham@arm.comsystem.cpu1.pwrStateClkGateDist::5e+10-1e+11 9 0.17% 99.79% # Distribution of time spent in the clock gated state 162011570SCurtis.Dunham@arm.comsystem.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 1 0.02% 99.81% # Distribution of time spent in the clock gated state 162111570SCurtis.Dunham@arm.comsystem.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 1 0.02% 99.83% # Distribution of time spent in the clock gated state 162211570SCurtis.Dunham@arm.comsystem.cpu1.pwrStateClkGateDist::7.5e+11-8e+11 1 0.02% 99.85% # Distribution of time spent in the clock gated state 162311570SCurtis.Dunham@arm.comsystem.cpu1.pwrStateClkGateDist::9.5e+11-1e+12 1 0.02% 99.87% # Distribution of time spent in the clock gated state 162411570SCurtis.Dunham@arm.comsystem.cpu1.pwrStateClkGateDist::overflows 7 0.13% 100.00% # Distribution of time spent in the clock gated state 162511570SCurtis.Dunham@arm.comsystem.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state 162611570SCurtis.Dunham@arm.comsystem.cpu1.pwrStateClkGateDist::max_value 7351146453012 # Distribution of time spent in the clock gated state 162711570SCurtis.Dunham@arm.comsystem.cpu1.pwrStateClkGateDist::total 5196 # Distribution of time spent in the clock gated state 162811570SCurtis.Dunham@arm.comsystem.cpu1.pwrStateResidencyTicks::ON 401797772178 # Cumulative time (in ticks) in various power states 162911570SCurtis.Dunham@arm.comsystem.cpu1.pwrStateResidencyTicks::CLK_GATED 47043691468822 # Cumulative time (in ticks) in various power states 163011570SCurtis.Dunham@arm.comsystem.cpu1.numCycles 803603609 # number of cpu cycles simulated 163110585Sandreas.hansson@arm.comsystem.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 163210585Sandreas.hansson@arm.comsystem.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 163311570SCurtis.Dunham@arm.comsystem.cpu1.committedInsts 379085635 # Number of instructions committed 163411570SCurtis.Dunham@arm.comsystem.cpu1.committedOps 446824897 # Number of ops (including micro ops) committed 163511570SCurtis.Dunham@arm.comsystem.cpu1.discardedOps 44295367 # Number of ops (including micro ops) which were discarded before commit 163611570SCurtis.Dunham@arm.comsystem.cpu1.numFetchSuspends 4823 # Number of times Execute suspended instruction fetching 163711570SCurtis.Dunham@arm.comsystem.cpu1.quiesceCycles 94088042190 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 163811570SCurtis.Dunham@arm.comsystem.cpu1.cpi 2.119847 # CPI: cycles per instruction 163911570SCurtis.Dunham@arm.comsystem.cpu1.ipc 0.471732 # IPC: instructions per cycle 164011570SCurtis.Dunham@arm.comsystem.cpu1.op_class_0::No_OpClass 1 0.00% 0.00% # Class of committed instruction 164111570SCurtis.Dunham@arm.comsystem.cpu1.op_class_0::IntAlu 309274392 69.22% 69.22% # Class of committed instruction 164211570SCurtis.Dunham@arm.comsystem.cpu1.op_class_0::IntMult 866353 0.19% 69.41% # Class of committed instruction 164311570SCurtis.Dunham@arm.comsystem.cpu1.op_class_0::IntDiv 49212 0.01% 69.42% # Class of committed instruction 164411570SCurtis.Dunham@arm.comsystem.cpu1.op_class_0::FloatAdd 0 0.00% 69.42% # Class of committed instruction 164511570SCurtis.Dunham@arm.comsystem.cpu1.op_class_0::FloatCmp 0 0.00% 69.42% # Class of committed instruction 164611570SCurtis.Dunham@arm.comsystem.cpu1.op_class_0::FloatCvt 0 0.00% 69.42% # Class of committed instruction 164711570SCurtis.Dunham@arm.comsystem.cpu1.op_class_0::FloatMult 0 0.00% 69.42% # Class of committed instruction 164811570SCurtis.Dunham@arm.comsystem.cpu1.op_class_0::FloatDiv 0 0.00% 69.42% # Class of committed instruction 164911570SCurtis.Dunham@arm.comsystem.cpu1.op_class_0::FloatSqrt 0 0.00% 69.42% # Class of committed instruction 165011570SCurtis.Dunham@arm.comsystem.cpu1.op_class_0::SimdAdd 0 0.00% 69.42% # Class of committed instruction 165111570SCurtis.Dunham@arm.comsystem.cpu1.op_class_0::SimdAddAcc 0 0.00% 69.42% # Class of committed instruction 165211570SCurtis.Dunham@arm.comsystem.cpu1.op_class_0::SimdAlu 0 0.00% 69.42% # Class of committed instruction 165311570SCurtis.Dunham@arm.comsystem.cpu1.op_class_0::SimdCmp 0 0.00% 69.42% # Class of committed instruction 165411570SCurtis.Dunham@arm.comsystem.cpu1.op_class_0::SimdCvt 0 0.00% 69.42% # Class of committed instruction 165511570SCurtis.Dunham@arm.comsystem.cpu1.op_class_0::SimdMisc 0 0.00% 69.42% # Class of committed instruction 165611570SCurtis.Dunham@arm.comsystem.cpu1.op_class_0::SimdMult 0 0.00% 69.42% # Class of committed instruction 165711570SCurtis.Dunham@arm.comsystem.cpu1.op_class_0::SimdMultAcc 0 0.00% 69.42% # Class of committed instruction 165811570SCurtis.Dunham@arm.comsystem.cpu1.op_class_0::SimdShift 0 0.00% 69.42% # Class of committed instruction 165911570SCurtis.Dunham@arm.comsystem.cpu1.op_class_0::SimdShiftAcc 0 0.00% 69.42% # Class of committed instruction 166011570SCurtis.Dunham@arm.comsystem.cpu1.op_class_0::SimdSqrt 0 0.00% 69.42% # Class of committed instruction 166111570SCurtis.Dunham@arm.comsystem.cpu1.op_class_0::SimdFloatAdd 8 0.00% 69.42% # Class of committed instruction 166211570SCurtis.Dunham@arm.comsystem.cpu1.op_class_0::SimdFloatAlu 0 0.00% 69.42% # Class of committed instruction 166311570SCurtis.Dunham@arm.comsystem.cpu1.op_class_0::SimdFloatCmp 13 0.00% 69.42% # Class of committed instruction 166411570SCurtis.Dunham@arm.comsystem.cpu1.op_class_0::SimdFloatCvt 21 0.00% 69.42% # Class of committed instruction 166511570SCurtis.Dunham@arm.comsystem.cpu1.op_class_0::SimdFloatDiv 0 0.00% 69.42% # Class of committed instruction 166611570SCurtis.Dunham@arm.comsystem.cpu1.op_class_0::SimdFloatMisc 34424 0.01% 69.43% # Class of committed instruction 166711570SCurtis.Dunham@arm.comsystem.cpu1.op_class_0::SimdFloatMult 0 0.00% 69.43% # Class of committed instruction 166811570SCurtis.Dunham@arm.comsystem.cpu1.op_class_0::SimdFloatMultAcc 0 0.00% 69.43% # Class of committed instruction 166911570SCurtis.Dunham@arm.comsystem.cpu1.op_class_0::SimdFloatSqrt 0 0.00% 69.43% # Class of committed instruction 167011570SCurtis.Dunham@arm.comsystem.cpu1.op_class_0::MemRead 71272038 15.95% 85.38% # Class of committed instruction 167111570SCurtis.Dunham@arm.comsystem.cpu1.op_class_0::MemWrite 65328435 14.62% 100.00% # Class of committed instruction 167211441Sandreas.hansson@arm.comsystem.cpu1.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 167311441Sandreas.hansson@arm.comsystem.cpu1.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 167411570SCurtis.Dunham@arm.comsystem.cpu1.op_class_0::total 446824897 # Class of committed instruction 167510585Sandreas.hansson@arm.comsystem.cpu1.kern.inst.arm 0 # number of arm instructions executed 167611570SCurtis.Dunham@arm.comsystem.cpu1.kern.inst.quiesce 5196 # number of quiesce instructions executed 167711570SCurtis.Dunham@arm.comsystem.cpu1.tickCycles 627540865 # Number of cycles that the object actually ticked 167811570SCurtis.Dunham@arm.comsystem.cpu1.idleCycles 176062744 # Total number of cycles that the object has spent stopped 167911570SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states 168011570SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.replacements 4660684 # number of replacements 168111570SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.tagsinuse 434.489996 # Cycle average of tags in use 168211570SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.total_refs 132775101 # Total number of references to valid blocks. 168311570SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.sampled_refs 4661196 # Sample count of references to valid blocks. 168411570SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.avg_refs 28.485200 # Average number of references to valid blocks. 168511570SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.warmup_cycle 8377585211000 # Cycle when the warmup percentage was hit. 168611570SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.occ_blocks::cpu1.data 434.489996 # Average occupied blocks per requestor 168711570SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.occ_percent::cpu1.data 0.848613 # Average percentage of cache occupancy 168811570SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.occ_percent::total 0.848613 # Average percentage of cache occupancy 168911570SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 169011570SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::0 72 # Occupied blocks per task id 169111570SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::1 401 # Occupied blocks per task id 169211570SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::2 39 # Occupied blocks per task id 169311570SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 169411570SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.tag_accesses 281793929 # Number of tag accesses 169511570SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.data_accesses 281793929 # Number of data accesses 169611570SCurtis.Dunham@arm.comsystem.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states 169711570SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_hits::cpu1.data 67965873 # number of ReadReq hits 169811570SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_hits::total 67965873 # number of ReadReq hits 169911570SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_hits::cpu1.data 61015488 # number of WriteReq hits 170011570SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_hits::total 61015488 # number of WriteReq hits 170111570SCurtis.Dunham@arm.comsystem.cpu1.dcache.SoftPFReq_hits::cpu1.data 190971 # number of SoftPFReq hits 170211570SCurtis.Dunham@arm.comsystem.cpu1.dcache.SoftPFReq_hits::total 190971 # number of SoftPFReq hits 170311570SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteLineReq_hits::cpu1.data 44349 # number of WriteLineReq hits 170411570SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteLineReq_hits::total 44349 # number of WriteLineReq hits 170511570SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1561438 # number of LoadLockedReq hits 170611570SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_hits::total 1561438 # number of LoadLockedReq hits 170711570SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_hits::cpu1.data 1518539 # number of StoreCondReq hits 170811570SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_hits::total 1518539 # number of StoreCondReq hits 170911570SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_hits::cpu1.data 129025710 # number of demand (read+write) hits 171011570SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_hits::total 129025710 # number of demand (read+write) hits 171111570SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_hits::cpu1.data 129216681 # number of overall hits 171211570SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_hits::total 129216681 # number of overall hits 171311570SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_misses::cpu1.data 2729495 # number of ReadReq misses 171411570SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_misses::total 2729495 # number of ReadReq misses 171511570SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_misses::cpu1.data 2149690 # number of WriteReq misses 171611570SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_misses::total 2149690 # number of WriteReq misses 171711570SCurtis.Dunham@arm.comsystem.cpu1.dcache.SoftPFReq_misses::cpu1.data 616052 # number of SoftPFReq misses 171811570SCurtis.Dunham@arm.comsystem.cpu1.dcache.SoftPFReq_misses::total 616052 # number of SoftPFReq misses 171911570SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteLineReq_misses::cpu1.data 399927 # number of WriteLineReq misses 172011570SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteLineReq_misses::total 399927 # number of WriteLineReq misses 172111570SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_misses::cpu1.data 143085 # number of LoadLockedReq misses 172211570SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_misses::total 143085 # number of LoadLockedReq misses 172311570SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_misses::cpu1.data 184951 # number of StoreCondReq misses 172411570SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_misses::total 184951 # number of StoreCondReq misses 172511570SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_misses::cpu1.data 5279112 # number of demand (read+write) misses 172611570SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_misses::total 5279112 # number of demand (read+write) misses 172711570SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_misses::cpu1.data 5895164 # number of overall misses 172811570SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_misses::total 5895164 # number of overall misses 172911570SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_miss_latency::cpu1.data 39717227000 # number of ReadReq miss cycles 173011570SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_miss_latency::total 39717227000 # number of ReadReq miss cycles 173111570SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_miss_latency::cpu1.data 40094025500 # number of WriteReq miss cycles 173211570SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_miss_latency::total 40094025500 # number of WriteReq miss cycles 173311570SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 9755721000 # number of WriteLineReq miss cycles 173411570SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteLineReq_miss_latency::total 9755721000 # number of WriteLineReq miss cycles 173511570SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2101168500 # number of LoadLockedReq miss cycles 173611570SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_latency::total 2101168500 # number of LoadLockedReq miss cycles 173711570SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4571201000 # number of StoreCondReq miss cycles 173811570SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_miss_latency::total 4571201000 # number of StoreCondReq miss cycles 173911570SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 4144500 # number of StoreCondFailReq miss cycles 174011570SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondFailReq_miss_latency::total 4144500 # number of StoreCondFailReq miss cycles 174111570SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_miss_latency::cpu1.data 89566973500 # number of demand (read+write) miss cycles 174211570SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_miss_latency::total 89566973500 # number of demand (read+write) miss cycles 174311570SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_miss_latency::cpu1.data 89566973500 # number of overall miss cycles 174411570SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_miss_latency::total 89566973500 # number of overall miss cycles 174511570SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_accesses::cpu1.data 70695368 # number of ReadReq accesses(hits+misses) 174611570SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_accesses::total 70695368 # number of ReadReq accesses(hits+misses) 174711570SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_accesses::cpu1.data 63165178 # number of WriteReq accesses(hits+misses) 174811570SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_accesses::total 63165178 # number of WriteReq accesses(hits+misses) 174911570SCurtis.Dunham@arm.comsystem.cpu1.dcache.SoftPFReq_accesses::cpu1.data 807023 # number of SoftPFReq accesses(hits+misses) 175011570SCurtis.Dunham@arm.comsystem.cpu1.dcache.SoftPFReq_accesses::total 807023 # number of SoftPFReq accesses(hits+misses) 175111570SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteLineReq_accesses::cpu1.data 444276 # number of WriteLineReq accesses(hits+misses) 175211570SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteLineReq_accesses::total 444276 # number of WriteLineReq accesses(hits+misses) 175311570SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1704523 # number of LoadLockedReq accesses(hits+misses) 175411570SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_accesses::total 1704523 # number of LoadLockedReq accesses(hits+misses) 175511570SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1703490 # number of StoreCondReq accesses(hits+misses) 175611570SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_accesses::total 1703490 # number of StoreCondReq accesses(hits+misses) 175711570SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_accesses::cpu1.data 134304822 # number of demand (read+write) accesses 175811570SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_accesses::total 134304822 # number of demand (read+write) accesses 175911570SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_accesses::cpu1.data 135111845 # number of overall (read+write) accesses 176011570SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_accesses::total 135111845 # number of overall (read+write) accesses 176111570SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.038609 # miss rate for ReadReq accesses 176211570SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_miss_rate::total 0.038609 # miss rate for ReadReq accesses 176311570SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.034033 # miss rate for WriteReq accesses 176411570SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_miss_rate::total 0.034033 # miss rate for WriteReq accesses 176511570SCurtis.Dunham@arm.comsystem.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.763364 # miss rate for SoftPFReq accesses 176611570SCurtis.Dunham@arm.comsystem.cpu1.dcache.SoftPFReq_miss_rate::total 0.763364 # miss rate for SoftPFReq accesses 176711570SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.900177 # miss rate for WriteLineReq accesses 176811570SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteLineReq_miss_rate::total 0.900177 # miss rate for WriteLineReq accesses 176911570SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.083944 # miss rate for LoadLockedReq accesses 177011570SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_rate::total 0.083944 # miss rate for LoadLockedReq accesses 177111570SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.108572 # miss rate for StoreCondReq accesses 177211570SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_miss_rate::total 0.108572 # miss rate for StoreCondReq accesses 177311570SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_miss_rate::cpu1.data 0.039307 # miss rate for demand accesses 177411570SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_miss_rate::total 0.039307 # miss rate for demand accesses 177511570SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_miss_rate::cpu1.data 0.043632 # miss rate for overall accesses 177611570SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_miss_rate::total 0.043632 # miss rate for overall accesses 177711570SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14551.126490 # average ReadReq miss latency 177811570SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_avg_miss_latency::total 14551.126490 # average ReadReq miss latency 177911570SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18651.073178 # average WriteReq miss latency 178011570SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_avg_miss_latency::total 18651.073178 # average WriteReq miss latency 178111570SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 24393.754360 # average WriteLineReq miss latency 178211570SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteLineReq_avg_miss_latency::total 24393.754360 # average WriteLineReq miss latency 178311570SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14684.757312 # average LoadLockedReq miss latency 178411570SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14684.757312 # average LoadLockedReq miss latency 178511570SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 24715.740926 # average StoreCondReq miss latency 178611570SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_avg_miss_latency::total 24715.740926 # average StoreCondReq miss latency 178710636Snilay@cs.wisc.edusystem.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 178810585Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 178911570SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_avg_miss_latency::cpu1.data 16966.295373 # average overall miss latency 179011570SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_avg_miss_latency::total 16966.295373 # average overall miss latency 179111570SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15193.296319 # average overall miss latency 179211570SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_avg_miss_latency::total 15193.296319 # average overall miss latency 179310585Sandreas.hansson@arm.comsystem.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 179410585Sandreas.hansson@arm.comsystem.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 179510585Sandreas.hansson@arm.comsystem.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 179610585Sandreas.hansson@arm.comsystem.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 179710585Sandreas.hansson@arm.comsystem.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 179810585Sandreas.hansson@arm.comsystem.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 179911570SCurtis.Dunham@arm.comsystem.cpu1.dcache.writebacks::writebacks 4660691 # number of writebacks 180011570SCurtis.Dunham@arm.comsystem.cpu1.dcache.writebacks::total 4660691 # number of writebacks 180111570SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 132278 # number of ReadReq MSHR hits 180211570SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_mshr_hits::total 132278 # number of ReadReq MSHR hits 180311570SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 894898 # number of WriteReq MSHR hits 180411570SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_mshr_hits::total 894898 # number of WriteReq MSHR hits 180511570SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 69 # number of WriteLineReq MSHR hits 180611570SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_hits::total 69 # number of WriteLineReq MSHR hits 180711570SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 37558 # number of LoadLockedReq MSHR hits 180811570SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_hits::total 37558 # number of LoadLockedReq MSHR hits 180911570SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data 59 # number of StoreCondReq MSHR hits 181011570SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_hits::total 59 # number of StoreCondReq MSHR hits 181111570SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_mshr_hits::cpu1.data 1027245 # number of demand (read+write) MSHR hits 181211570SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_mshr_hits::total 1027245 # number of demand (read+write) MSHR hits 181311570SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_mshr_hits::cpu1.data 1027245 # number of overall MSHR hits 181411570SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_mshr_hits::total 1027245 # number of overall MSHR hits 181511570SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2597217 # number of ReadReq MSHR misses 181611570SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_mshr_misses::total 2597217 # number of ReadReq MSHR misses 181711570SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1254792 # number of WriteReq MSHR misses 181811570SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_mshr_misses::total 1254792 # number of WriteReq MSHR misses 181911570SCurtis.Dunham@arm.comsystem.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 615702 # number of SoftPFReq MSHR misses 182011570SCurtis.Dunham@arm.comsystem.cpu1.dcache.SoftPFReq_mshr_misses::total 615702 # number of SoftPFReq MSHR misses 182111570SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 399858 # number of WriteLineReq MSHR misses 182211570SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_misses::total 399858 # number of WriteLineReq MSHR misses 182311570SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 105527 # number of LoadLockedReq MSHR misses 182411570SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_misses::total 105527 # number of LoadLockedReq MSHR misses 182511570SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 184892 # number of StoreCondReq MSHR misses 182611570SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_misses::total 184892 # number of StoreCondReq MSHR misses 182711570SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_mshr_misses::cpu1.data 4251867 # number of demand (read+write) MSHR misses 182811570SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_mshr_misses::total 4251867 # number of demand (read+write) MSHR misses 182911570SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_mshr_misses::cpu1.data 4867569 # number of overall MSHR misses 183011570SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_mshr_misses::total 4867569 # number of overall MSHR misses 183111570SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 8793 # number of ReadReq MSHR uncacheable 183211570SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_mshr_uncacheable::total 8793 # number of ReadReq MSHR uncacheable 183311570SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 9091 # number of WriteReq MSHR uncacheable 183411570SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_mshr_uncacheable::total 9091 # number of WriteReq MSHR uncacheable 183511570SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 17884 # number of overall MSHR uncacheable misses 183611570SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_mshr_uncacheable_misses::total 17884 # number of overall MSHR uncacheable misses 183711570SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 34245614000 # number of ReadReq MSHR miss cycles 183811570SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_mshr_miss_latency::total 34245614000 # number of ReadReq MSHR miss cycles 183911570SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 22880344500 # number of WriteReq MSHR miss cycles 184011570SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_mshr_miss_latency::total 22880344500 # number of WriteReq MSHR miss cycles 184111570SCurtis.Dunham@arm.comsystem.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 13431113500 # number of SoftPFReq MSHR miss cycles 184211570SCurtis.Dunham@arm.comsystem.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 13431113500 # number of SoftPFReq MSHR miss cycles 184311570SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 9350661500 # number of WriteLineReq MSHR miss cycles 184411570SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 9350661500 # number of WriteLineReq MSHR miss cycles 184511570SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1405417000 # number of LoadLockedReq MSHR miss cycles 184611570SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1405417000 # number of LoadLockedReq MSHR miss cycles 184711570SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4384302500 # number of StoreCondReq MSHR miss cycles 184811570SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4384302500 # number of StoreCondReq MSHR miss cycles 184911570SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 3898500 # number of StoreCondFailReq MSHR miss cycles 185011570SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 3898500 # number of StoreCondFailReq MSHR miss cycles 185111570SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 66476620000 # number of demand (read+write) MSHR miss cycles 185211570SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_mshr_miss_latency::total 66476620000 # number of demand (read+write) MSHR miss cycles 185311570SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 79907733500 # number of overall MSHR miss cycles 185411570SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_mshr_miss_latency::total 79907733500 # number of overall MSHR miss cycles 185511570SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 1305175500 # number of ReadReq MSHR uncacheable cycles 185611570SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 1305175500 # number of ReadReq MSHR uncacheable cycles 185711570SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1305175500 # number of overall MSHR uncacheable cycles 185811570SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_mshr_uncacheable_latency::total 1305175500 # number of overall MSHR uncacheable cycles 185911570SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036738 # mshr miss rate for ReadReq accesses 186011570SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036738 # mshr miss rate for ReadReq accesses 186111570SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.019865 # mshr miss rate for WriteReq accesses 186211570SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.019865 # mshr miss rate for WriteReq accesses 186311570SCurtis.Dunham@arm.comsystem.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.762930 # mshr miss rate for SoftPFReq accesses 186411570SCurtis.Dunham@arm.comsystem.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.762930 # mshr miss rate for SoftPFReq accesses 186511570SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.900022 # mshr miss rate for WriteLineReq accesses 186611570SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.900022 # mshr miss rate for WriteLineReq accesses 186711570SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.061910 # mshr miss rate for LoadLockedReq accesses 186811570SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.061910 # mshr miss rate for LoadLockedReq accesses 186911570SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.108537 # mshr miss rate for StoreCondReq accesses 187011570SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.108537 # mshr miss rate for StoreCondReq accesses 187111570SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031658 # mshr miss rate for demand accesses 187211570SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_mshr_miss_rate::total 0.031658 # mshr miss rate for demand accesses 187311570SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.036026 # mshr miss rate for overall accesses 187411570SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_mshr_miss_rate::total 0.036026 # mshr miss rate for overall accesses 187511570SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13185.503560 # average ReadReq mshr miss latency 187611570SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13185.503560 # average ReadReq mshr miss latency 187711570SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 18234.372310 # average WriteReq mshr miss latency 187811570SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 18234.372310 # average WriteReq mshr miss latency 187911570SCurtis.Dunham@arm.comsystem.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 21814.308708 # average SoftPFReq mshr miss latency 188011570SCurtis.Dunham@arm.comsystem.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 21814.308708 # average SoftPFReq mshr miss latency 188111570SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 23384.955409 # average WriteLineReq mshr miss latency 188211570SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 23384.955409 # average WriteLineReq mshr miss latency 188311570SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13318.079733 # average LoadLockedReq mshr miss latency 188411570SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13318.079733 # average LoadLockedReq mshr miss latency 188511570SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 23712.775566 # average StoreCondReq mshr miss latency 188611570SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 23712.775566 # average StoreCondReq mshr miss latency 188710636Snilay@cs.wisc.edusystem.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 188810585Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 188911570SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15634.689420 # average overall mshr miss latency 189011570SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_avg_mshr_miss_latency::total 15634.689420 # average overall mshr miss latency 189111570SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16416.353523 # average overall mshr miss latency 189211570SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_avg_mshr_miss_latency::total 16416.353523 # average overall mshr miss latency 189311570SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 148433.469806 # average ReadReq mshr uncacheable latency 189411570SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 148433.469806 # average ReadReq mshr uncacheable latency 189511570SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 72980.065981 # average overall mshr uncacheable latency 189611570SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 72980.065981 # average overall mshr uncacheable latency 189711570SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states 189811570SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.replacements 8014386 # number of replacements 189911570SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.tagsinuse 507.062567 # Cycle average of tags in use 190011570SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.total_refs 202497896 # Total number of references to valid blocks. 190111570SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.sampled_refs 8014898 # Sample count of references to valid blocks. 190211570SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.avg_refs 25.265187 # Average number of references to valid blocks. 190311570SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.warmup_cycle 8368004575000 # Cycle when the warmup percentage was hit. 190411570SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.occ_blocks::cpu1.inst 507.062567 # Average occupied blocks per requestor 190511570SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.occ_percent::cpu1.inst 0.990357 # Average percentage of cache occupancy 190611570SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.occ_percent::total 0.990357 # Average percentage of cache occupancy 190710585Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 190811570SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::0 113 # Occupied blocks per task id 190911570SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::1 354 # Occupied blocks per task id 191011570SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::2 45 # Occupied blocks per task id 191110585Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 191211570SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.tag_accesses 429040515 # Number of tag accesses 191311570SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.data_accesses 429040515 # Number of data accesses 191411570SCurtis.Dunham@arm.comsystem.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states 191511570SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_hits::cpu1.inst 202497896 # number of ReadReq hits 191611570SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_hits::total 202497896 # number of ReadReq hits 191711570SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_hits::cpu1.inst 202497896 # number of demand (read+write) hits 191811570SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_hits::total 202497896 # number of demand (read+write) hits 191911570SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_hits::cpu1.inst 202497896 # number of overall hits 192011570SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_hits::total 202497896 # number of overall hits 192111570SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_misses::cpu1.inst 8014908 # number of ReadReq misses 192211570SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_misses::total 8014908 # number of ReadReq misses 192311570SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_misses::cpu1.inst 8014908 # number of demand (read+write) misses 192411570SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_misses::total 8014908 # number of demand (read+write) misses 192511570SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_misses::cpu1.inst 8014908 # number of overall misses 192611570SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_misses::total 8014908 # number of overall misses 192711570SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_miss_latency::cpu1.inst 81330977500 # number of ReadReq miss cycles 192811570SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_miss_latency::total 81330977500 # number of ReadReq miss cycles 192911570SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_miss_latency::cpu1.inst 81330977500 # number of demand (read+write) miss cycles 193011570SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_miss_latency::total 81330977500 # number of demand (read+write) miss cycles 193111570SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_miss_latency::cpu1.inst 81330977500 # number of overall miss cycles 193211570SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_miss_latency::total 81330977500 # number of overall miss cycles 193311570SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_accesses::cpu1.inst 210512804 # number of ReadReq accesses(hits+misses) 193411570SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_accesses::total 210512804 # number of ReadReq accesses(hits+misses) 193511570SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_accesses::cpu1.inst 210512804 # number of demand (read+write) accesses 193611570SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_accesses::total 210512804 # number of demand (read+write) accesses 193711570SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_accesses::cpu1.inst 210512804 # number of overall (read+write) accesses 193811570SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_accesses::total 210512804 # number of overall (read+write) accesses 193911570SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.038073 # miss rate for ReadReq accesses 194011570SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_miss_rate::total 0.038073 # miss rate for ReadReq accesses 194111570SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_miss_rate::cpu1.inst 0.038073 # miss rate for demand accesses 194211570SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_miss_rate::total 0.038073 # miss rate for demand accesses 194311570SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_miss_rate::cpu1.inst 0.038073 # miss rate for overall accesses 194411570SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_miss_rate::total 0.038073 # miss rate for overall accesses 194511570SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10147.462391 # average ReadReq miss latency 194611570SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_avg_miss_latency::total 10147.462391 # average ReadReq miss latency 194711570SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10147.462391 # average overall miss latency 194811570SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_avg_miss_latency::total 10147.462391 # average overall miss latency 194911570SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10147.462391 # average overall miss latency 195011570SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_avg_miss_latency::total 10147.462391 # average overall miss latency 195110585Sandreas.hansson@arm.comsystem.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 195210585Sandreas.hansson@arm.comsystem.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 195310585Sandreas.hansson@arm.comsystem.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 195410585Sandreas.hansson@arm.comsystem.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 195510585Sandreas.hansson@arm.comsystem.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 195610585Sandreas.hansson@arm.comsystem.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 195711570SCurtis.Dunham@arm.comsystem.cpu1.icache.writebacks::writebacks 8014386 # number of writebacks 195811570SCurtis.Dunham@arm.comsystem.cpu1.icache.writebacks::total 8014386 # number of writebacks 195911570SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 8014908 # number of ReadReq MSHR misses 196011570SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_mshr_misses::total 8014908 # number of ReadReq MSHR misses 196111570SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_mshr_misses::cpu1.inst 8014908 # number of demand (read+write) MSHR misses 196211570SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_mshr_misses::total 8014908 # number of demand (read+write) MSHR misses 196311570SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_mshr_misses::cpu1.inst 8014908 # number of overall MSHR misses 196411570SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_mshr_misses::total 8014908 # number of overall MSHR misses 196511570SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 95 # number of ReadReq MSHR uncacheable 196611570SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_mshr_uncacheable::total 95 # number of ReadReq MSHR uncacheable 196711570SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 95 # number of overall MSHR uncacheable misses 196811570SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_mshr_uncacheable_misses::total 95 # number of overall MSHR uncacheable misses 196911570SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 77323524000 # number of ReadReq MSHR miss cycles 197011570SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_latency::total 77323524000 # number of ReadReq MSHR miss cycles 197111570SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 77323524000 # number of demand (read+write) MSHR miss cycles 197211570SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_mshr_miss_latency::total 77323524000 # number of demand (read+write) MSHR miss cycles 197311570SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 77323524000 # number of overall MSHR miss cycles 197411570SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_mshr_miss_latency::total 77323524000 # number of overall MSHR miss cycles 197511570SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8766500 # number of ReadReq MSHR uncacheable cycles 197611570SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 8766500 # number of ReadReq MSHR uncacheable cycles 197711570SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 8766500 # number of overall MSHR uncacheable cycles 197811570SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_mshr_uncacheable_latency::total 8766500 # number of overall MSHR uncacheable cycles 197911570SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.038073 # mshr miss rate for ReadReq accesses 198011570SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_rate::total 0.038073 # mshr miss rate for ReadReq accesses 198111570SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.038073 # mshr miss rate for demand accesses 198211570SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_mshr_miss_rate::total 0.038073 # mshr miss rate for demand accesses 198311570SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.038073 # mshr miss rate for overall accesses 198411570SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_mshr_miss_rate::total 0.038073 # mshr miss rate for overall accesses 198511570SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 9647.462454 # average ReadReq mshr miss latency 198611570SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 9647.462454 # average ReadReq mshr miss latency 198711570SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 9647.462454 # average overall mshr miss latency 198811570SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_avg_mshr_miss_latency::total 9647.462454 # average overall mshr miss latency 198911570SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 9647.462454 # average overall mshr miss latency 199011570SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_avg_mshr_miss_latency::total 9647.462454 # average overall mshr miss latency 199111570SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 92278.947368 # average ReadReq mshr uncacheable latency 199211570SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 92278.947368 # average ReadReq mshr uncacheable latency 199311570SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 92278.947368 # average overall mshr uncacheable latency 199411570SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 92278.947368 # average overall mshr uncacheable latency 199511570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states 199611570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.prefetcher.num_hwpf_issued 6532358 # number of hwpf issued 199711570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.prefetcher.pfIdentified 6532555 # number of prefetch candidates identified 199811570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.prefetcher.pfBufferHit 172 # number of redundant prefetches already in prefetch queue 199910628Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 200010628Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 200111570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.prefetcher.pfSpanPage 799581 # number of prefetches not generated due to page crossing 200211570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states 200311570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.replacements 2133098 # number of replacements 200411570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.tagsinuse 13038.197584 # Cycle average of tags in use 200511570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.total_refs 20019506 # Total number of references to valid blocks. 200611570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.sampled_refs 2148887 # Sample count of references to valid blocks. 200711570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.avg_refs 9.316221 # Average number of references to valid blocks. 200811570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.warmup_cycle 9619713453000 # Cycle when the warmup percentage was hit. 200911570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.occ_blocks::writebacks 11987.780509 # Average occupied blocks per requestor 201011570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 23.994022 # Average occupied blocks per requestor 201111570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 12.035388 # Average occupied blocks per requestor 201211570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 1014.387665 # Average occupied blocks per requestor 201311570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.occ_percent::writebacks 0.731676 # Average percentage of cache occupancy 201411570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.001464 # Average percentage of cache occupancy 201511570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000735 # Average percentage of cache occupancy 201611570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.061913 # Average percentage of cache occupancy 201711570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.occ_percent::total 0.795788 # Average percentage of cache occupancy 201811570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.occ_task_id_blocks::1022 829 # Occupied blocks per task id 201911570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.occ_task_id_blocks::1023 65 # Occupied blocks per task id 202011570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.occ_task_id_blocks::1024 14895 # Occupied blocks per task id 202111570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1022::0 11 # Occupied blocks per task id 202211570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1022::1 17 # Occupied blocks per task id 202311570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1022::2 152 # Occupied blocks per task id 202411570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1022::3 567 # Occupied blocks per task id 202511570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1022::4 82 # Occupied blocks per task id 202611570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id 202711570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::2 8 # Occupied blocks per task id 202811570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::3 55 # Occupied blocks per task id 202911570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::4 1 # Occupied blocks per task id 203011570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::0 105 # Occupied blocks per task id 203111570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1161 # Occupied blocks per task id 203211570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5545 # Occupied blocks per task id 203311570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::3 7510 # Occupied blocks per task id 203411570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::4 574 # Occupied blocks per task id 203511570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.occ_task_id_percent::1022 0.050598 # Percentage of cache occupancy per task id 203611570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.occ_task_id_percent::1023 0.003967 # Percentage of cache occupancy per task id 203711570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.occ_task_id_percent::1024 0.909119 # Percentage of cache occupancy per task id 203811570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.tag_accesses 428778233 # Number of tag accesses 203911570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.data_accesses 428778233 # Number of data accesses 204011570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states 204111570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 473132 # number of ReadReq hits 204211570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 155315 # number of ReadReq hits 204311570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_hits::total 628447 # number of ReadReq hits 204411570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.WritebackDirty_hits::writebacks 2939776 # number of WritebackDirty hits 204511570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.WritebackDirty_hits::total 2939776 # number of WritebackDirty hits 204611570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.WritebackClean_hits::writebacks 9733319 # number of WritebackClean hits 204711570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.WritebackClean_hits::total 9733319 # number of WritebackClean hits 204811570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.UpgradeReq_hits::cpu1.data 413 # number of UpgradeReq hits 204911570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.UpgradeReq_hits::total 413 # number of UpgradeReq hits 205011570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadExReq_hits::cpu1.data 783674 # number of ReadExReq hits 205111570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadExReq_hits::total 783674 # number of ReadExReq hits 205211570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 7365861 # number of ReadCleanReq hits 205311570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadCleanReq_hits::total 7365861 # number of ReadCleanReq hits 205411570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 2414791 # number of ReadSharedReq hits 205511570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadSharedReq_hits::total 2414791 # number of ReadSharedReq hits 205611570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.InvalidateReq_hits::cpu1.data 165268 # number of InvalidateReq hits 205711570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.InvalidateReq_hits::total 165268 # number of InvalidateReq hits 205811570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.dtb.walker 473132 # number of demand (read+write) hits 205911570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.itb.walker 155315 # number of demand (read+write) hits 206011570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.inst 7365861 # number of demand (read+write) hits 206111570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.data 3198465 # number of demand (read+write) hits 206211570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_hits::total 11192773 # number of demand (read+write) hits 206311570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.dtb.walker 473132 # number of overall hits 206411570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.itb.walker 155315 # number of overall hits 206511570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.inst 7365861 # number of overall hits 206611570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.data 3198465 # number of overall hits 206711570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_hits::total 11192773 # number of overall hits 206811570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 11255 # number of ReadReq misses 206911570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 7950 # number of ReadReq misses 207011570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_misses::total 19205 # number of ReadReq misses 207111570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.UpgradeReq_misses::cpu1.data 218866 # number of UpgradeReq misses 207211570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.UpgradeReq_misses::total 218866 # number of UpgradeReq misses 207311570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 184883 # number of SCUpgradeReq misses 207411570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeReq_misses::total 184883 # number of SCUpgradeReq misses 207511570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 9 # number of SCUpgradeFailReq misses 207611570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_misses::total 9 # number of SCUpgradeFailReq misses 207711570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadExReq_misses::cpu1.data 254182 # number of ReadExReq misses 207811570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadExReq_misses::total 254182 # number of ReadExReq misses 207911570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 649047 # number of ReadCleanReq misses 208011570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadCleanReq_misses::total 649047 # number of ReadCleanReq misses 208111570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 903423 # number of ReadSharedReq misses 208211570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadSharedReq_misses::total 903423 # number of ReadSharedReq misses 208311570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.InvalidateReq_misses::cpu1.data 232791 # number of InvalidateReq misses 208411570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.InvalidateReq_misses::total 232791 # number of InvalidateReq misses 208511570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.dtb.walker 11255 # number of demand (read+write) misses 208611570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.itb.walker 7950 # number of demand (read+write) misses 208711570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.inst 649047 # number of demand (read+write) misses 208811570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.data 1157605 # number of demand (read+write) misses 208911570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_misses::total 1825857 # number of demand (read+write) misses 209011570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.dtb.walker 11255 # number of overall misses 209111570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.itb.walker 7950 # number of overall misses 209211570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.inst 649047 # number of overall misses 209311570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.data 1157605 # number of overall misses 209411570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_misses::total 1825857 # number of overall misses 209511570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 391701000 # number of ReadReq miss cycles 209611570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 275187000 # number of ReadReq miss cycles 209711570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_miss_latency::total 666888000 # number of ReadReq miss cycles 209811570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 1898630500 # number of UpgradeReq miss cycles 209911570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.UpgradeReq_miss_latency::total 1898630500 # number of UpgradeReq miss cycles 210011570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 1381240500 # number of SCUpgradeReq miss cycles 210111570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeReq_miss_latency::total 1381240500 # number of SCUpgradeReq miss cycles 210211570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 3788499 # number of SCUpgradeFailReq miss cycles 210311570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 3788499 # number of SCUpgradeFailReq miss cycles 210411570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 10033557499 # number of ReadExReq miss cycles 210511570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadExReq_miss_latency::total 10033557499 # number of ReadExReq miss cycles 210611570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 20842529000 # number of ReadCleanReq miss cycles 210711570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadCleanReq_miss_latency::total 20842529000 # number of ReadCleanReq miss cycles 210811570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 28170928990 # number of ReadSharedReq miss cycles 210911570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadSharedReq_miss_latency::total 28170928990 # number of ReadSharedReq miss cycles 211011570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 350412000 # number of InvalidateReq miss cycles 211111570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.InvalidateReq_miss_latency::total 350412000 # number of InvalidateReq miss cycles 211211570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 391701000 # number of demand (read+write) miss cycles 211311570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 275187000 # number of demand (read+write) miss cycles 211411570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_miss_latency::cpu1.inst 20842529000 # number of demand (read+write) miss cycles 211511570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_miss_latency::cpu1.data 38204486489 # number of demand (read+write) miss cycles 211611570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_miss_latency::total 59713903489 # number of demand (read+write) miss cycles 211711570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 391701000 # number of overall miss cycles 211811570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 275187000 # number of overall miss cycles 211911570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_miss_latency::cpu1.inst 20842529000 # number of overall miss cycles 212011570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_miss_latency::cpu1.data 38204486489 # number of overall miss cycles 212111570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_miss_latency::total 59713903489 # number of overall miss cycles 212211570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 484387 # number of ReadReq accesses(hits+misses) 212311570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 163265 # number of ReadReq accesses(hits+misses) 212411570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_accesses::total 647652 # number of ReadReq accesses(hits+misses) 212511570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.WritebackDirty_accesses::writebacks 2939776 # number of WritebackDirty accesses(hits+misses) 212611570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.WritebackDirty_accesses::total 2939776 # number of WritebackDirty accesses(hits+misses) 212711570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.WritebackClean_accesses::writebacks 9733319 # number of WritebackClean accesses(hits+misses) 212811570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.WritebackClean_accesses::total 9733319 # number of WritebackClean accesses(hits+misses) 212911570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 219279 # number of UpgradeReq accesses(hits+misses) 213011570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.UpgradeReq_accesses::total 219279 # number of UpgradeReq accesses(hits+misses) 213111570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 184883 # number of SCUpgradeReq accesses(hits+misses) 213211570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeReq_accesses::total 184883 # number of SCUpgradeReq accesses(hits+misses) 213311570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 9 # number of SCUpgradeFailReq accesses(hits+misses) 213411570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_accesses::total 9 # number of SCUpgradeFailReq accesses(hits+misses) 213511570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1037856 # number of ReadExReq accesses(hits+misses) 213611570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadExReq_accesses::total 1037856 # number of ReadExReq accesses(hits+misses) 213711570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 8014908 # number of ReadCleanReq accesses(hits+misses) 213811570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadCleanReq_accesses::total 8014908 # number of ReadCleanReq accesses(hits+misses) 213911570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 3318214 # number of ReadSharedReq accesses(hits+misses) 214011570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadSharedReq_accesses::total 3318214 # number of ReadSharedReq accesses(hits+misses) 214111570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 398059 # number of InvalidateReq accesses(hits+misses) 214211570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.InvalidateReq_accesses::total 398059 # number of InvalidateReq accesses(hits+misses) 214311570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 484387 # number of demand (read+write) accesses 214411570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.itb.walker 163265 # number of demand (read+write) accesses 214511570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.inst 8014908 # number of demand (read+write) accesses 214611570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.data 4356070 # number of demand (read+write) accesses 214711570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_accesses::total 13018630 # number of demand (read+write) accesses 214811570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 484387 # number of overall (read+write) accesses 214911570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.itb.walker 163265 # number of overall (read+write) accesses 215011570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.inst 8014908 # number of overall (read+write) accesses 215111570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.data 4356070 # number of overall (read+write) accesses 215211570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_accesses::total 13018630 # number of overall (read+write) accesses 215311570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.023236 # miss rate for ReadReq accesses 215411570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.048694 # miss rate for ReadReq accesses 215511570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::total 0.029653 # miss rate for ReadReq accesses 215611570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.998117 # miss rate for UpgradeReq accesses 215711570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.UpgradeReq_miss_rate::total 0.998117 # miss rate for UpgradeReq accesses 215811201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses 215911201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 216010636Snilay@cs.wisc.edusystem.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses 216110585Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 216211570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.244911 # miss rate for ReadExReq accesses 216311570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadExReq_miss_rate::total 0.244911 # miss rate for ReadExReq accesses 216411570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.080980 # miss rate for ReadCleanReq accesses 216511570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.080980 # miss rate for ReadCleanReq accesses 216611570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.272262 # miss rate for ReadSharedReq accesses 216711570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.272262 # miss rate for ReadSharedReq accesses 216811570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.584815 # miss rate for InvalidateReq accesses 216911570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.InvalidateReq_miss_rate::total 0.584815 # miss rate for InvalidateReq accesses 217011570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.023236 # miss rate for demand accesses 217111570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.048694 # miss rate for demand accesses 217211570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.080980 # miss rate for demand accesses 217311570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.data 0.265745 # miss rate for demand accesses 217411570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_miss_rate::total 0.140250 # miss rate for demand accesses 217511570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.023236 # miss rate for overall accesses 217611570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.048694 # miss rate for overall accesses 217711570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.080980 # miss rate for overall accesses 217811570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.data 0.265745 # miss rate for overall accesses 217911570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_miss_rate::total 0.140250 # miss rate for overall accesses 218011570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 34802.398934 # average ReadReq miss latency 218111570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 34614.716981 # average ReadReq miss latency 218211570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_avg_miss_latency::total 34724.707108 # average ReadReq miss latency 218311570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 8674.853563 # average UpgradeReq miss latency 218411570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 8674.853563 # average UpgradeReq miss latency 218511570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 7470.889698 # average SCUpgradeReq miss latency 218611570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 7470.889698 # average SCUpgradeReq miss latency 218711570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 420944.333333 # average SCUpgradeFailReq miss latency 218811570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 420944.333333 # average SCUpgradeFailReq miss latency 218911570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 39473.910422 # average ReadExReq miss latency 219011570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadExReq_avg_miss_latency::total 39473.910422 # average ReadExReq miss latency 219111570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 32112.511112 # average ReadCleanReq miss latency 219211570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 32112.511112 # average ReadCleanReq miss latency 219311570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 31182.435017 # average ReadSharedReq miss latency 219411570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 31182.435017 # average ReadSharedReq miss latency 219511570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 1505.264379 # average InvalidateReq miss latency 219611570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 1505.264379 # average InvalidateReq miss latency 219711570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 34802.398934 # average overall miss latency 219811570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 34614.716981 # average overall miss latency 219911570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 32112.511112 # average overall miss latency 220011570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 33003.042047 # average overall miss latency 220111570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_avg_miss_latency::total 32704.589400 # average overall miss latency 220211570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 34802.398934 # average overall miss latency 220311570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 34614.716981 # average overall miss latency 220411570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 32112.511112 # average overall miss latency 220511570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 33003.042047 # average overall miss latency 220611570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_avg_miss_latency::total 32704.589400 # average overall miss latency 220711441Sandreas.hansson@arm.comsystem.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 220810585Sandreas.hansson@arm.comsystem.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 220911441Sandreas.hansson@arm.comsystem.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 221010585Sandreas.hansson@arm.comsystem.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 221111441Sandreas.hansson@arm.comsystem.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 221210585Sandreas.hansson@arm.comsystem.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 221311570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.unused_prefetches 43626 # number of HardPF blocks evicted w/o reference 221411570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.writebacks::writebacks 1060166 # number of writebacks 221511570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.writebacks::total 1060166 # number of writebacks 221611502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker 1 # number of ReadReq MSHR hits 221711570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 5 # number of ReadReq MSHR hits 221811570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_mshr_hits::total 6 # number of ReadReq MSHR hits 221911570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 5457 # number of ReadExReq MSHR hits 222011570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_hits::total 5457 # number of ReadExReq MSHR hits 222111502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst 3 # number of ReadCleanReq MSHR hits 222211502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadCleanReq_mshr_hits::total 3 # number of ReadCleanReq MSHR hits 222311570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 376 # number of ReadSharedReq MSHR hits 222411570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_hits::total 376 # number of ReadSharedReq MSHR hits 222511570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_hits::cpu1.data 5 # number of InvalidateReq MSHR hits 222611570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_hits::total 5 # number of InvalidateReq MSHR hits 222711502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker 1 # number of demand (read+write) MSHR hits 222811570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 5 # number of demand (read+write) MSHR hits 222911502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_mshr_hits::cpu1.inst 3 # number of demand (read+write) MSHR hits 223011570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_mshr_hits::cpu1.data 5833 # number of demand (read+write) MSHR hits 223111570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_mshr_hits::total 5842 # number of demand (read+write) MSHR hits 223211502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker 1 # number of overall MSHR hits 223311570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 5 # number of overall MSHR hits 223411502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_mshr_hits::cpu1.inst 3 # number of overall MSHR hits 223511570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_mshr_hits::cpu1.data 5833 # number of overall MSHR hits 223611570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_mshr_hits::total 5842 # number of overall MSHR hits 223711570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 11254 # number of ReadReq MSHR misses 223811570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 7945 # number of ReadReq MSHR misses 223911570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_mshr_misses::total 19199 # number of ReadReq MSHR misses 224011570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 690270 # number of HardPFReq MSHR misses 224111570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.HardPFReq_mshr_misses::total 690270 # number of HardPFReq MSHR misses 224211570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 218866 # number of UpgradeReq MSHR misses 224311570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.UpgradeReq_mshr_misses::total 218866 # number of UpgradeReq MSHR misses 224411570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 184883 # number of SCUpgradeReq MSHR misses 224511570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 184883 # number of SCUpgradeReq MSHR misses 224611570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 9 # number of SCUpgradeFailReq MSHR misses 224711570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 9 # number of SCUpgradeFailReq MSHR misses 224811570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 248725 # number of ReadExReq MSHR misses 224911570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_misses::total 248725 # number of ReadExReq MSHR misses 225011570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 649044 # number of ReadCleanReq MSHR misses 225111570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadCleanReq_mshr_misses::total 649044 # number of ReadCleanReq MSHR misses 225211570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 903047 # number of ReadSharedReq MSHR misses 225311570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_misses::total 903047 # number of ReadSharedReq MSHR misses 225411570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data 232786 # number of InvalidateReq MSHR misses 225511570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_misses::total 232786 # number of InvalidateReq MSHR misses 225611570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 11254 # number of demand (read+write) MSHR misses 225711570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 7945 # number of demand (read+write) MSHR misses 225811570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_mshr_misses::cpu1.inst 649044 # number of demand (read+write) MSHR misses 225911570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_mshr_misses::cpu1.data 1151772 # number of demand (read+write) MSHR misses 226011570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_mshr_misses::total 1820015 # number of demand (read+write) MSHR misses 226111570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 11254 # number of overall MSHR misses 226211570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 7945 # number of overall MSHR misses 226311570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_mshr_misses::cpu1.inst 649044 # number of overall MSHR misses 226411570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_mshr_misses::cpu1.data 1151772 # number of overall MSHR misses 226511570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 690270 # number of overall MSHR misses 226611570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_mshr_misses::total 2510285 # number of overall MSHR misses 226711570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 95 # number of ReadReq MSHR uncacheable 226811570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 8793 # number of ReadReq MSHR uncacheable 226911570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable::total 8888 # number of ReadReq MSHR uncacheable 227011570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 9091 # number of WriteReq MSHR uncacheable 227111570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.WriteReq_mshr_uncacheable::total 9091 # number of WriteReq MSHR uncacheable 227211570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 95 # number of overall MSHR uncacheable misses 227311570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 17884 # number of overall MSHR uncacheable misses 227411570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_mshr_uncacheable_misses::total 17979 # number of overall MSHR uncacheable misses 227511570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 324079500 # number of ReadReq MSHR miss cycles 227611570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 227423500 # number of ReadReq MSHR miss cycles 227711570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_latency::total 551503000 # number of ReadReq MSHR miss cycles 227811570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 26884842389 # number of HardPFReq MSHR miss cycles 227911570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 26884842389 # number of HardPFReq MSHR miss cycles 228011570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 4561523494 # number of UpgradeReq MSHR miss cycles 228111570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 4561523494 # number of UpgradeReq MSHR miss cycles 228211570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 2993192497 # number of SCUpgradeReq MSHR miss cycles 228311570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 2993192497 # number of SCUpgradeReq MSHR miss cycles 228411570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 3356499 # number of SCUpgradeFailReq MSHR miss cycles 228511570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 3356499 # number of SCUpgradeFailReq MSHR miss cycles 228611570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 7853418999 # number of ReadExReq MSHR miss cycles 228711570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 7853418999 # number of ReadExReq MSHR miss cycles 228811570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 16948153000 # number of ReadCleanReq MSHR miss cycles 228911570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 16948153000 # number of ReadCleanReq MSHR miss cycles 229011570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 22723854990 # number of ReadSharedReq MSHR miss cycles 229111570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 22723854990 # number of ReadSharedReq MSHR miss cycles 229211570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 6164226500 # number of InvalidateReq MSHR miss cycles 229311570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 6164226500 # number of InvalidateReq MSHR miss cycles 229411570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 324079500 # number of demand (read+write) MSHR miss cycles 229511570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 227423500 # number of demand (read+write) MSHR miss cycles 229611570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 16948153000 # number of demand (read+write) MSHR miss cycles 229711570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 30577273989 # number of demand (read+write) MSHR miss cycles 229811570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_mshr_miss_latency::total 48076929989 # number of demand (read+write) MSHR miss cycles 229911570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 324079500 # number of overall MSHR miss cycles 230011570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 227423500 # number of overall MSHR miss cycles 230111570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 16948153000 # number of overall MSHR miss cycles 230211570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 30577273989 # number of overall MSHR miss cycles 230311570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 26884842389 # number of overall MSHR miss cycles 230411570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_mshr_miss_latency::total 74961772378 # number of overall MSHR miss cycles 230511570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8006500 # number of ReadReq MSHR uncacheable cycles 230611570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 1234720500 # number of ReadReq MSHR uncacheable cycles 230711570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 1242727000 # number of ReadReq MSHR uncacheable cycles 230811570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 8006500 # number of overall MSHR uncacheable cycles 230911570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 1234720500 # number of overall MSHR uncacheable cycles 231011570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_mshr_uncacheable_latency::total 1242727000 # number of overall MSHR uncacheable cycles 231111570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.023233 # mshr miss rate for ReadReq accesses 231211570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.048663 # mshr miss rate for ReadReq accesses 231311570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.029644 # mshr miss rate for ReadReq accesses 231410585Sandreas.hansson@arm.comsystem.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 231510585Sandreas.hansson@arm.comsystem.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 231611570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.998117 # mshr miss rate for UpgradeReq accesses 231711570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.998117 # mshr miss rate for UpgradeReq accesses 231811201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses 231911201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 232010636Snilay@cs.wisc.edusystem.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses 232110585Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 232211570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.239653 # mshr miss rate for ReadExReq accesses 232311570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.239653 # mshr miss rate for ReadExReq accesses 232411570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.080980 # mshr miss rate for ReadCleanReq accesses 232511570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.080980 # mshr miss rate for ReadCleanReq accesses 232611570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.272149 # mshr miss rate for ReadSharedReq accesses 232711570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.272149 # mshr miss rate for ReadSharedReq accesses 232811570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.584803 # mshr miss rate for InvalidateReq accesses 232911570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.584803 # mshr miss rate for InvalidateReq accesses 233011570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.023233 # mshr miss rate for demand accesses 233111570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.048663 # mshr miss rate for demand accesses 233211570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.080980 # mshr miss rate for demand accesses 233311570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.264406 # mshr miss rate for demand accesses 233411570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_mshr_miss_rate::total 0.139801 # mshr miss rate for demand accesses 233511570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.023233 # mshr miss rate for overall accesses 233611570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.048663 # mshr miss rate for overall accesses 233711570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.080980 # mshr miss rate for overall accesses 233811570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.264406 # mshr miss rate for overall accesses 233910585Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses 234011570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_mshr_miss_rate::total 0.192823 # mshr miss rate for overall accesses 234111570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 28796.827795 # average ReadReq mshr miss latency 234211570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 28624.732536 # average ReadReq mshr miss latency 234311570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 28725.610709 # average ReadReq mshr miss latency 234411570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 38948.299055 # average HardPFReq mshr miss latency 234511570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 38948.299055 # average HardPFReq mshr miss latency 234611570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20841.626813 # average UpgradeReq mshr miss latency 234711570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20841.626813 # average UpgradeReq mshr miss latency 234811570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 16189.657767 # average SCUpgradeReq mshr miss latency 234911570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 16189.657767 # average SCUpgradeReq mshr miss latency 235011570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 372944.333333 # average SCUpgradeFailReq mshr miss latency 235111570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 372944.333333 # average SCUpgradeFailReq mshr miss latency 235211570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 31574.707002 # average ReadExReq mshr miss latency 235311570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 31574.707002 # average ReadExReq mshr miss latency 235411570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 26112.486981 # average ReadCleanReq mshr miss latency 235511570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 26112.486981 # average ReadCleanReq mshr miss latency 235611570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 25163.535220 # average ReadSharedReq mshr miss latency 235711570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 25163.535220 # average ReadSharedReq mshr miss latency 235811570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 26480.228622 # average InvalidateReq mshr miss latency 235911570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 26480.228622 # average InvalidateReq mshr miss latency 236011570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 28796.827795 # average overall mshr miss latency 236111570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 28624.732536 # average overall mshr miss latency 236211570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 26112.486981 # average overall mshr miss latency 236311570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 26548.026857 # average overall mshr miss latency 236411570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_avg_mshr_miss_latency::total 26415.677887 # average overall mshr miss latency 236511570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 28796.827795 # average overall mshr miss latency 236611570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 28624.732536 # average overall mshr miss latency 236711570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 26112.486981 # average overall mshr miss latency 236811570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 26548.026857 # average overall mshr miss latency 236911570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 38948.299055 # average overall mshr miss latency 237011570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::total 29861.857270 # average overall mshr miss latency 237111570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 84278.947368 # average ReadReq mshr uncacheable latency 237211570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 140420.846128 # average ReadReq mshr uncacheable latency 237311570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 139820.769577 # average ReadReq mshr uncacheable latency 237411570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 84278.947368 # average overall mshr uncacheable latency 237511570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 69040.511071 # average overall mshr uncacheable latency 237611570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 69121.030091 # average overall mshr uncacheable latency 237711570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoop_filter.tot_requests 26150144 # Total number of requests made to the snoop filter. 237811570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoop_filter.hit_single_requests 13381244 # Number of requests hitting in the snoop filter with a single holder of the requested data. 237911570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoop_filter.hit_multi_requests 1981 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 238011570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoop_filter.tot_snoops 1969364 # Total number of snoops made to the snoop filter. 238111570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoop_filter.hit_single_snoops 1969026 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 238211570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 338 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 238311570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states 238411570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadReq 732517 # Transaction distribution 238511570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadResp 12156991 # Transaction distribution 238611570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::WriteReq 9091 # Transaction distribution 238711570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::WriteResp 9091 # Transaction distribution 238811570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::WritebackDirty 4007359 # Transaction distribution 238911570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::WritebackClean 9735300 # Transaction distribution 239011570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::CleanEvict 2694691 # Transaction distribution 239111570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::HardPFReq 886167 # Transaction distribution 239211570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::HardPFResp 3 # Transaction distribution 239311570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::UpgradeReq 430328 # Transaction distribution 239411570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::SCUpgradeReq 337223 # Transaction distribution 239511570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::UpgradeResp 468486 # Transaction distribution 239611570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 75 # Transaction distribution 239711570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::UpgradeFailResp 138 # Transaction distribution 239811570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadExReq 1067899 # Transaction distribution 239911570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadExResp 1044213 # Transaction distribution 240011570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadCleanReq 8014908 # Transaction distribution 240111570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadSharedReq 4433895 # Transaction distribution 240211570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::InvalidateReq 458319 # Transaction distribution 240311570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::InvalidateResp 398059 # Transaction distribution 240411570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 24044391 # Packet count per connected master and slave (bytes) 240511570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 15175224 # Packet count per connected master and slave (bytes) 240611570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 343569 # Packet count per connected master and slave (bytes) 240711570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1027712 # Packet count per connected master and slave (bytes) 240811570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.pkt_count::total 40590896 # Packet count per connected master and slave (bytes) 240911570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1025880832 # Cumulative packet size per connected master and slave (bytes) 241011570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 583383788 # Cumulative packet size per connected master and slave (bytes) 241111570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1306120 # Cumulative packet size per connected master and slave (bytes) 241211570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 3875096 # Cumulative packet size per connected master and slave (bytes) 241311570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.pkt_size::total 1614445836 # Cumulative packet size per connected master and slave (bytes) 241411570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoops 6456023 # Total snoops (count) 241511570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoopTraffic 75189768 # Total snoop traffic (bytes) 241611570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoop_fanout::samples 20132697 # Request fanout histogram 241711570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoop_fanout::mean 0.112928 # Request fanout histogram 241811570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoop_fanout::stdev 0.316558 # Request fanout histogram 241910585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 242011570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoop_fanout::0 17859482 88.71% 88.71% # Request fanout histogram 242111570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoop_fanout::1 2272877 11.29% 100.00% # Request fanout histogram 242211570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoop_fanout::2 338 0.00% 100.00% # Request fanout histogram 242310585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 242411138Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 242510827Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 242611570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoop_fanout::total 20132697 # Request fanout histogram 242711570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.reqLayer0.occupancy 25974578977 # Layer occupancy (ticks) 242811201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 242911570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoopLayer0.occupancy 179053447 # Layer occupancy (ticks) 243010585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 243111570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.respLayer0.occupancy 12025219550 # Layer occupancy (ticks) 243210585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 243311570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.respLayer1.occupancy 6952751265 # Layer occupancy (ticks) 243410585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 243511570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.respLayer2.occupancy 180351405 # Layer occupancy (ticks) 243610585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 243711570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.respLayer3.occupancy 543399850 # Layer occupancy (ticks) 243810585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 243911570SCurtis.Dunham@arm.comsystem.iobus.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states 244011570SCurtis.Dunham@arm.comsystem.iobus.trans_dist::ReadReq 40387 # Transaction distribution 244111570SCurtis.Dunham@arm.comsystem.iobus.trans_dist::ReadResp 40387 # Transaction distribution 244211570SCurtis.Dunham@arm.comsystem.iobus.trans_dist::WriteReq 136979 # Transaction distribution 244311570SCurtis.Dunham@arm.comsystem.iobus.trans_dist::WriteResp 136979 # Transaction distribution 244411570SCurtis.Dunham@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47808 # Packet count per connected master and slave (bytes) 244510585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 244611245Sandreas.sandberg@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 244710585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) 244810585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) 244910585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 245010585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 245110585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 245210585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 245310585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) 245410585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 245511570SCurtis.Dunham@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29808 # Packet count per connected master and slave (bytes) 245610585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) 245711570SCurtis.Dunham@arm.comsystem.iobus.pkt_count_system.bridge.master::total 122950 # Packet count per connected master and slave (bytes) 245811570SCurtis.Dunham@arm.comsystem.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231702 # Packet count per connected master and slave (bytes) 245911570SCurtis.Dunham@arm.comsystem.iobus.pkt_count_system.realview.ide.dma::total 231702 # Packet count per connected master and slave (bytes) 246010585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) 246110585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) 246211570SCurtis.Dunham@arm.comsystem.iobus.pkt_count::total 354732 # Packet count per connected master and slave (bytes) 246311570SCurtis.Dunham@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47828 # Cumulative packet size per connected master and slave (bytes) 246410585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) 246511245Sandreas.sandberg@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) 246610585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) 246710585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) 246810585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 246910585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 247010585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 247110585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 247210585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) 247310585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 247411570SCurtis.Dunham@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17703 # Cumulative packet size per connected master and slave (bytes) 247510585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) 247611570SCurtis.Dunham@arm.comsystem.iobus.pkt_size_system.bridge.master::total 155965 # Cumulative packet size per connected master and slave (bytes) 247711570SCurtis.Dunham@arm.comsystem.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7355160 # Cumulative packet size per connected master and slave (bytes) 247811570SCurtis.Dunham@arm.comsystem.iobus.pkt_size_system.realview.ide.dma::total 7355160 # Cumulative packet size per connected master and slave (bytes) 247910585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 248010585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) 248111570SCurtis.Dunham@arm.comsystem.iobus.pkt_size::total 7513211 # Cumulative packet size per connected master and slave (bytes) 248211570SCurtis.Dunham@arm.comsystem.iobus.reqLayer0.occupancy 42458502 # Layer occupancy (ticks) 248310585Sandreas.hansson@arm.comsystem.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 248411570SCurtis.Dunham@arm.comsystem.iobus.reqLayer1.occupancy 11500 # Layer occupancy (ticks) 248510585Sandreas.hansson@arm.comsystem.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 248611570SCurtis.Dunham@arm.comsystem.iobus.reqLayer2.occupancy 311001 # Layer occupancy (ticks) 248710585Sandreas.hansson@arm.comsystem.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 248811570SCurtis.Dunham@arm.comsystem.iobus.reqLayer3.occupancy 9000 # Layer occupancy (ticks) 248910585Sandreas.hansson@arm.comsystem.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 249011570SCurtis.Dunham@arm.comsystem.iobus.reqLayer4.occupancy 9000 # Layer occupancy (ticks) 249111245Sandreas.sandberg@arm.comsystem.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 249211570SCurtis.Dunham@arm.comsystem.iobus.reqLayer10.occupancy 9500 # Layer occupancy (ticks) 249310585Sandreas.hansson@arm.comsystem.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 249411570SCurtis.Dunham@arm.comsystem.iobus.reqLayer13.occupancy 10500 # Layer occupancy (ticks) 249510585Sandreas.hansson@arm.comsystem.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 249611570SCurtis.Dunham@arm.comsystem.iobus.reqLayer14.occupancy 10000 # Layer occupancy (ticks) 249710585Sandreas.hansson@arm.comsystem.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 249811570SCurtis.Dunham@arm.comsystem.iobus.reqLayer15.occupancy 9500 # Layer occupancy (ticks) 249910585Sandreas.hansson@arm.comsystem.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 250011570SCurtis.Dunham@arm.comsystem.iobus.reqLayer16.occupancy 15000 # Layer occupancy (ticks) 250110585Sandreas.hansson@arm.comsystem.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 250211570SCurtis.Dunham@arm.comsystem.iobus.reqLayer17.occupancy 9000 # Layer occupancy (ticks) 250310585Sandreas.hansson@arm.comsystem.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 250411570SCurtis.Dunham@arm.comsystem.iobus.reqLayer23.occupancy 26063002 # Layer occupancy (ticks) 250510585Sandreas.hansson@arm.comsystem.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 250611570SCurtis.Dunham@arm.comsystem.iobus.reqLayer24.occupancy 34444001 # Layer occupancy (ticks) 250710585Sandreas.hansson@arm.comsystem.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 250811570SCurtis.Dunham@arm.comsystem.iobus.reqLayer25.occupancy 570734934 # Layer occupancy (ticks) 250910585Sandreas.hansson@arm.comsystem.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 251011570SCurtis.Dunham@arm.comsystem.iobus.respLayer0.occupancy 92958000 # Layer occupancy (ticks) 251110585Sandreas.hansson@arm.comsystem.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 251211570SCurtis.Dunham@arm.comsystem.iobus.respLayer3.occupancy 148142000 # Layer occupancy (ticks) 251310585Sandreas.hansson@arm.comsystem.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 251410892Sandreas.hansson@arm.comsystem.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) 251510585Sandreas.hansson@arm.comsystem.iobus.respLayer4.utilization 0.0 # Layer utilization (%) 251611570SCurtis.Dunham@arm.comsystem.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states 251711570SCurtis.Dunham@arm.comsystem.iocache.tags.replacements 115832 # number of replacements 251811570SCurtis.Dunham@arm.comsystem.iocache.tags.tagsinuse 11.305903 # Cycle average of tags in use 251911336Sandreas.hansson@arm.comsystem.iocache.tags.total_refs 3 # Total number of references to valid blocks. 252011570SCurtis.Dunham@arm.comsystem.iocache.tags.sampled_refs 115848 # Sample count of references to valid blocks. 252111336Sandreas.hansson@arm.comsystem.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. 252211570SCurtis.Dunham@arm.comsystem.iocache.tags.warmup_cycle 9127528857000 # Cycle when the warmup percentage was hit. 252311570SCurtis.Dunham@arm.comsystem.iocache.tags.occ_blocks::realview.ethernet 3.833923 # Average occupied blocks per requestor 252411570SCurtis.Dunham@arm.comsystem.iocache.tags.occ_blocks::realview.ide 7.471980 # Average occupied blocks per requestor 252511570SCurtis.Dunham@arm.comsystem.iocache.tags.occ_percent::realview.ethernet 0.239620 # Average percentage of cache occupancy 252611570SCurtis.Dunham@arm.comsystem.iocache.tags.occ_percent::realview.ide 0.466999 # Average percentage of cache occupancy 252711570SCurtis.Dunham@arm.comsystem.iocache.tags.occ_percent::total 0.706619 # Average percentage of cache occupancy 252810585Sandreas.hansson@arm.comsystem.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 252910827Sandreas.hansson@arm.comsystem.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 253010585Sandreas.hansson@arm.comsystem.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 253111570SCurtis.Dunham@arm.comsystem.iocache.tags.tag_accesses 1043016 # Number of tag accesses 253211570SCurtis.Dunham@arm.comsystem.iocache.tags.data_accesses 1043016 # Number of data accesses 253311570SCurtis.Dunham@arm.comsystem.iocache.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states 253410585Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses 253511570SCurtis.Dunham@arm.comsystem.iocache.ReadReq_misses::realview.ide 8867 # number of ReadReq misses 253611570SCurtis.Dunham@arm.comsystem.iocache.ReadReq_misses::total 8904 # number of ReadReq misses 253710585Sandreas.hansson@arm.comsystem.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 253810585Sandreas.hansson@arm.comsystem.iocache.WriteReq_misses::total 3 # number of WriteReq misses 253911570SCurtis.Dunham@arm.comsystem.iocache.WriteLineReq_misses::realview.ide 106984 # number of WriteLineReq misses 254011570SCurtis.Dunham@arm.comsystem.iocache.WriteLineReq_misses::total 106984 # number of WriteLineReq misses 254110585Sandreas.hansson@arm.comsystem.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses 254211570SCurtis.Dunham@arm.comsystem.iocache.demand_misses::realview.ide 115851 # number of demand (read+write) misses 254311570SCurtis.Dunham@arm.comsystem.iocache.demand_misses::total 115891 # number of demand (read+write) misses 254410585Sandreas.hansson@arm.comsystem.iocache.overall_misses::realview.ethernet 40 # number of overall misses 254511570SCurtis.Dunham@arm.comsystem.iocache.overall_misses::realview.ide 115851 # number of overall misses 254611570SCurtis.Dunham@arm.comsystem.iocache.overall_misses::total 115891 # number of overall misses 254711502SCurtis.Dunham@arm.comsystem.iocache.ReadReq_miss_latency::realview.ethernet 5198000 # number of ReadReq miss cycles 254811570SCurtis.Dunham@arm.comsystem.iocache.ReadReq_miss_latency::realview.ide 1647274031 # number of ReadReq miss cycles 254911570SCurtis.Dunham@arm.comsystem.iocache.ReadReq_miss_latency::total 1652472031 # number of ReadReq miss cycles 255010726Sandreas.hansson@arm.comsystem.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles 255110726Sandreas.hansson@arm.comsystem.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles 255211570SCurtis.Dunham@arm.comsystem.iocache.WriteLineReq_miss_latency::realview.ide 12886794903 # number of WriteLineReq miss cycles 255311570SCurtis.Dunham@arm.comsystem.iocache.WriteLineReq_miss_latency::total 12886794903 # number of WriteLineReq miss cycles 255411502SCurtis.Dunham@arm.comsystem.iocache.demand_miss_latency::realview.ethernet 5567000 # number of demand (read+write) miss cycles 255511570SCurtis.Dunham@arm.comsystem.iocache.demand_miss_latency::realview.ide 14534068934 # number of demand (read+write) miss cycles 255611570SCurtis.Dunham@arm.comsystem.iocache.demand_miss_latency::total 14539635934 # number of demand (read+write) miss cycles 255711502SCurtis.Dunham@arm.comsystem.iocache.overall_miss_latency::realview.ethernet 5567000 # number of overall miss cycles 255811570SCurtis.Dunham@arm.comsystem.iocache.overall_miss_latency::realview.ide 14534068934 # number of overall miss cycles 255911570SCurtis.Dunham@arm.comsystem.iocache.overall_miss_latency::total 14539635934 # number of overall miss cycles 256010585Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) 256111570SCurtis.Dunham@arm.comsystem.iocache.ReadReq_accesses::realview.ide 8867 # number of ReadReq accesses(hits+misses) 256211570SCurtis.Dunham@arm.comsystem.iocache.ReadReq_accesses::total 8904 # number of ReadReq accesses(hits+misses) 256310585Sandreas.hansson@arm.comsystem.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 256410585Sandreas.hansson@arm.comsystem.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 256511570SCurtis.Dunham@arm.comsystem.iocache.WriteLineReq_accesses::realview.ide 106984 # number of WriteLineReq accesses(hits+misses) 256611570SCurtis.Dunham@arm.comsystem.iocache.WriteLineReq_accesses::total 106984 # number of WriteLineReq accesses(hits+misses) 256710585Sandreas.hansson@arm.comsystem.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses 256811570SCurtis.Dunham@arm.comsystem.iocache.demand_accesses::realview.ide 115851 # number of demand (read+write) accesses 256911570SCurtis.Dunham@arm.comsystem.iocache.demand_accesses::total 115891 # number of demand (read+write) accesses 257010585Sandreas.hansson@arm.comsystem.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses 257111570SCurtis.Dunham@arm.comsystem.iocache.overall_accesses::realview.ide 115851 # number of overall (read+write) accesses 257211570SCurtis.Dunham@arm.comsystem.iocache.overall_accesses::total 115891 # number of overall (read+write) accesses 257310585Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 257410585Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 257510585Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 257610585Sandreas.hansson@arm.comsystem.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 257710585Sandreas.hansson@arm.comsystem.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 257811336Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 257911336Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 258010585Sandreas.hansson@arm.comsystem.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses 258110585Sandreas.hansson@arm.comsystem.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 258210585Sandreas.hansson@arm.comsystem.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 258310585Sandreas.hansson@arm.comsystem.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses 258410585Sandreas.hansson@arm.comsystem.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 258510585Sandreas.hansson@arm.comsystem.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 258611502SCurtis.Dunham@arm.comsystem.iocache.ReadReq_avg_miss_latency::realview.ethernet 140486.486486 # average ReadReq miss latency 258711570SCurtis.Dunham@arm.comsystem.iocache.ReadReq_avg_miss_latency::realview.ide 185775.801398 # average ReadReq miss latency 258811570SCurtis.Dunham@arm.comsystem.iocache.ReadReq_avg_miss_latency::total 185587.604560 # average ReadReq miss latency 258910726Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency 259010726Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency 259111570SCurtis.Dunham@arm.comsystem.iocache.WriteLineReq_avg_miss_latency::realview.ide 120455.347557 # average WriteLineReq miss latency 259211570SCurtis.Dunham@arm.comsystem.iocache.WriteLineReq_avg_miss_latency::total 120455.347557 # average WriteLineReq miss latency 259311502SCurtis.Dunham@arm.comsystem.iocache.demand_avg_miss_latency::realview.ethernet 139175 # average overall miss latency 259411570SCurtis.Dunham@arm.comsystem.iocache.demand_avg_miss_latency::realview.ide 125454.842289 # average overall miss latency 259511570SCurtis.Dunham@arm.comsystem.iocache.demand_avg_miss_latency::total 125459.577827 # average overall miss latency 259611502SCurtis.Dunham@arm.comsystem.iocache.overall_avg_miss_latency::realview.ethernet 139175 # average overall miss latency 259711570SCurtis.Dunham@arm.comsystem.iocache.overall_avg_miss_latency::realview.ide 125454.842289 # average overall miss latency 259811570SCurtis.Dunham@arm.comsystem.iocache.overall_avg_miss_latency::total 125459.577827 # average overall miss latency 259911570SCurtis.Dunham@arm.comsystem.iocache.blocked_cycles::no_mshrs 32243 # number of cycles access was blocked 260010585Sandreas.hansson@arm.comsystem.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 260111570SCurtis.Dunham@arm.comsystem.iocache.blocked::no_mshrs 3515 # number of cycles access was blocked 260210585Sandreas.hansson@arm.comsystem.iocache.blocked::no_targets 0 # number of cycles access was blocked 260311570SCurtis.Dunham@arm.comsystem.iocache.avg_blocked_cycles::no_mshrs 9.172973 # average number of cycles each access was blocked 260410585Sandreas.hansson@arm.comsystem.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 260511570SCurtis.Dunham@arm.comsystem.iocache.writebacks::writebacks 106950 # number of writebacks 260611570SCurtis.Dunham@arm.comsystem.iocache.writebacks::total 106950 # number of writebacks 260710585Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses 260811570SCurtis.Dunham@arm.comsystem.iocache.ReadReq_mshr_misses::realview.ide 8867 # number of ReadReq MSHR misses 260911570SCurtis.Dunham@arm.comsystem.iocache.ReadReq_mshr_misses::total 8904 # number of ReadReq MSHR misses 261010585Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses 261110585Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses 261211570SCurtis.Dunham@arm.comsystem.iocache.WriteLineReq_mshr_misses::realview.ide 106984 # number of WriteLineReq MSHR misses 261311570SCurtis.Dunham@arm.comsystem.iocache.WriteLineReq_mshr_misses::total 106984 # number of WriteLineReq MSHR misses 261410585Sandreas.hansson@arm.comsystem.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses 261511570SCurtis.Dunham@arm.comsystem.iocache.demand_mshr_misses::realview.ide 115851 # number of demand (read+write) MSHR misses 261611570SCurtis.Dunham@arm.comsystem.iocache.demand_mshr_misses::total 115891 # number of demand (read+write) MSHR misses 261710585Sandreas.hansson@arm.comsystem.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses 261811570SCurtis.Dunham@arm.comsystem.iocache.overall_mshr_misses::realview.ide 115851 # number of overall MSHR misses 261911570SCurtis.Dunham@arm.comsystem.iocache.overall_mshr_misses::total 115891 # number of overall MSHR misses 262011502SCurtis.Dunham@arm.comsystem.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3348000 # number of ReadReq MSHR miss cycles 262111570SCurtis.Dunham@arm.comsystem.iocache.ReadReq_mshr_miss_latency::realview.ide 1203924031 # number of ReadReq MSHR miss cycles 262211570SCurtis.Dunham@arm.comsystem.iocache.ReadReq_mshr_miss_latency::total 1207272031 # number of ReadReq MSHR miss cycles 262310892Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles 262410892Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles 262511570SCurtis.Dunham@arm.comsystem.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7528956843 # number of WriteLineReq MSHR miss cycles 262611570SCurtis.Dunham@arm.comsystem.iocache.WriteLineReq_mshr_miss_latency::total 7528956843 # number of WriteLineReq MSHR miss cycles 262711502SCurtis.Dunham@arm.comsystem.iocache.demand_mshr_miss_latency::realview.ethernet 3567000 # number of demand (read+write) MSHR miss cycles 262811570SCurtis.Dunham@arm.comsystem.iocache.demand_mshr_miss_latency::realview.ide 8732880874 # number of demand (read+write) MSHR miss cycles 262911570SCurtis.Dunham@arm.comsystem.iocache.demand_mshr_miss_latency::total 8736447874 # number of demand (read+write) MSHR miss cycles 263011502SCurtis.Dunham@arm.comsystem.iocache.overall_mshr_miss_latency::realview.ethernet 3567000 # number of overall MSHR miss cycles 263111570SCurtis.Dunham@arm.comsystem.iocache.overall_mshr_miss_latency::realview.ide 8732880874 # number of overall MSHR miss cycles 263211570SCurtis.Dunham@arm.comsystem.iocache.overall_mshr_miss_latency::total 8736447874 # number of overall MSHR miss cycles 263310585Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses 263410585Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 263510585Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 263610585Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses 263710585Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 263811336Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 263911336Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 264010585Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses 264110585Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 264210585Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 264310585Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses 264410585Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 264510585Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 264611502SCurtis.Dunham@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90486.486486 # average ReadReq mshr miss latency 264711570SCurtis.Dunham@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 135775.801398 # average ReadReq mshr miss latency 264811570SCurtis.Dunham@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::total 135587.604560 # average ReadReq mshr miss latency 264910892Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency 265010892Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency 265111570SCurtis.Dunham@arm.comsystem.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70374.605950 # average WriteLineReq mshr miss latency 265211570SCurtis.Dunham@arm.comsystem.iocache.WriteLineReq_avg_mshr_miss_latency::total 70374.605950 # average WriteLineReq mshr miss latency 265311502SCurtis.Dunham@arm.comsystem.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89175 # average overall mshr miss latency 265411570SCurtis.Dunham@arm.comsystem.iocache.demand_avg_mshr_miss_latency::realview.ide 75380.280481 # average overall mshr miss latency 265511570SCurtis.Dunham@arm.comsystem.iocache.demand_avg_mshr_miss_latency::total 75385.041755 # average overall mshr miss latency 265611502SCurtis.Dunham@arm.comsystem.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89175 # average overall mshr miss latency 265711570SCurtis.Dunham@arm.comsystem.iocache.overall_avg_mshr_miss_latency::realview.ide 75380.280481 # average overall mshr miss latency 265811570SCurtis.Dunham@arm.comsystem.iocache.overall_avg_mshr_miss_latency::total 75385.041755 # average overall mshr miss latency 265911570SCurtis.Dunham@arm.comsystem.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states 266011570SCurtis.Dunham@arm.comsystem.l2c.tags.replacements 1436798 # number of replacements 266111570SCurtis.Dunham@arm.comsystem.l2c.tags.tagsinuse 63641.257392 # Cycle average of tags in use 266211570SCurtis.Dunham@arm.comsystem.l2c.tags.total_refs 6808742 # Total number of references to valid blocks. 266311570SCurtis.Dunham@arm.comsystem.l2c.tags.sampled_refs 1497176 # Sample count of references to valid blocks. 266411570SCurtis.Dunham@arm.comsystem.l2c.tags.avg_refs 4.547723 # Average number of references to valid blocks. 266511570SCurtis.Dunham@arm.comsystem.l2c.tags.warmup_cycle 8050623000 # Cycle when the warmup percentage was hit. 266611570SCurtis.Dunham@arm.comsystem.l2c.tags.occ_blocks::writebacks 20256.980304 # Average occupied blocks per requestor 266711570SCurtis.Dunham@arm.comsystem.l2c.tags.occ_blocks::cpu0.dtb.walker 307.265586 # Average occupied blocks per requestor 266811570SCurtis.Dunham@arm.comsystem.l2c.tags.occ_blocks::cpu0.itb.walker 477.600666 # Average occupied blocks per requestor 266911570SCurtis.Dunham@arm.comsystem.l2c.tags.occ_blocks::cpu0.inst 6075.269789 # Average occupied blocks per requestor 267011570SCurtis.Dunham@arm.comsystem.l2c.tags.occ_blocks::cpu0.data 12531.509900 # Average occupied blocks per requestor 267111570SCurtis.Dunham@arm.comsystem.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 19419.437449 # Average occupied blocks per requestor 267211570SCurtis.Dunham@arm.comsystem.l2c.tags.occ_blocks::cpu1.dtb.walker 11.305032 # Average occupied blocks per requestor 267311570SCurtis.Dunham@arm.comsystem.l2c.tags.occ_blocks::cpu1.itb.walker 4.128844 # Average occupied blocks per requestor 267411570SCurtis.Dunham@arm.comsystem.l2c.tags.occ_blocks::cpu1.inst 2389.320183 # Average occupied blocks per requestor 267511570SCurtis.Dunham@arm.comsystem.l2c.tags.occ_blocks::cpu1.data 1436.582929 # Average occupied blocks per requestor 267611570SCurtis.Dunham@arm.comsystem.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 731.856711 # Average occupied blocks per requestor 267711570SCurtis.Dunham@arm.comsystem.l2c.tags.occ_percent::writebacks 0.309097 # Average percentage of cache occupancy 267811570SCurtis.Dunham@arm.comsystem.l2c.tags.occ_percent::cpu0.dtb.walker 0.004689 # Average percentage of cache occupancy 267911570SCurtis.Dunham@arm.comsystem.l2c.tags.occ_percent::cpu0.itb.walker 0.007288 # Average percentage of cache occupancy 268011570SCurtis.Dunham@arm.comsystem.l2c.tags.occ_percent::cpu0.inst 0.092701 # Average percentage of cache occupancy 268111570SCurtis.Dunham@arm.comsystem.l2c.tags.occ_percent::cpu0.data 0.191216 # Average percentage of cache occupancy 268211570SCurtis.Dunham@arm.comsystem.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.296317 # Average percentage of cache occupancy 268311570SCurtis.Dunham@arm.comsystem.l2c.tags.occ_percent::cpu1.dtb.walker 0.000173 # Average percentage of cache occupancy 268411570SCurtis.Dunham@arm.comsystem.l2c.tags.occ_percent::cpu1.itb.walker 0.000063 # Average percentage of cache occupancy 268511570SCurtis.Dunham@arm.comsystem.l2c.tags.occ_percent::cpu1.inst 0.036458 # Average percentage of cache occupancy 268611570SCurtis.Dunham@arm.comsystem.l2c.tags.occ_percent::cpu1.data 0.021921 # Average percentage of cache occupancy 268711570SCurtis.Dunham@arm.comsystem.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.011167 # Average percentage of cache occupancy 268811570SCurtis.Dunham@arm.comsystem.l2c.tags.occ_percent::total 0.971089 # Average percentage of cache occupancy 268911570SCurtis.Dunham@arm.comsystem.l2c.tags.occ_task_id_blocks::1022 10768 # Occupied blocks per task id 269011570SCurtis.Dunham@arm.comsystem.l2c.tags.occ_task_id_blocks::1023 197 # Occupied blocks per task id 269111570SCurtis.Dunham@arm.comsystem.l2c.tags.occ_task_id_blocks::1024 49413 # Occupied blocks per task id 269211570SCurtis.Dunham@arm.comsystem.l2c.tags.age_task_id_blocks_1022::1 9 # Occupied blocks per task id 269311570SCurtis.Dunham@arm.comsystem.l2c.tags.age_task_id_blocks_1022::2 162 # Occupied blocks per task id 269411570SCurtis.Dunham@arm.comsystem.l2c.tags.age_task_id_blocks_1022::3 3598 # Occupied blocks per task id 269511570SCurtis.Dunham@arm.comsystem.l2c.tags.age_task_id_blocks_1022::4 6999 # Occupied blocks per task id 269611570SCurtis.Dunham@arm.comsystem.l2c.tags.age_task_id_blocks_1023::3 18 # Occupied blocks per task id 269711570SCurtis.Dunham@arm.comsystem.l2c.tags.age_task_id_blocks_1023::4 179 # Occupied blocks per task id 269811570SCurtis.Dunham@arm.comsystem.l2c.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id 269911570SCurtis.Dunham@arm.comsystem.l2c.tags.age_task_id_blocks_1024::1 298 # Occupied blocks per task id 270011570SCurtis.Dunham@arm.comsystem.l2c.tags.age_task_id_blocks_1024::2 2209 # Occupied blocks per task id 270111570SCurtis.Dunham@arm.comsystem.l2c.tags.age_task_id_blocks_1024::3 15374 # Occupied blocks per task id 270211570SCurtis.Dunham@arm.comsystem.l2c.tags.age_task_id_blocks_1024::4 31482 # Occupied blocks per task id 270311570SCurtis.Dunham@arm.comsystem.l2c.tags.occ_task_id_percent::1022 0.164307 # Percentage of cache occupancy per task id 270411570SCurtis.Dunham@arm.comsystem.l2c.tags.occ_task_id_percent::1023 0.003006 # Percentage of cache occupancy per task id 270511570SCurtis.Dunham@arm.comsystem.l2c.tags.occ_task_id_percent::1024 0.753983 # Percentage of cache occupancy per task id 270611570SCurtis.Dunham@arm.comsystem.l2c.tags.tag_accesses 82887108 # Number of tag accesses 270711570SCurtis.Dunham@arm.comsystem.l2c.tags.data_accesses 82887108 # Number of data accesses 270811570SCurtis.Dunham@arm.comsystem.l2c.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states 270911570SCurtis.Dunham@arm.comsystem.l2c.WritebackDirty_hits::writebacks 2851442 # number of WritebackDirty hits 271011570SCurtis.Dunham@arm.comsystem.l2c.WritebackDirty_hits::total 2851442 # number of WritebackDirty hits 271111570SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_hits::cpu0.data 184675 # number of UpgradeReq hits 271211570SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_hits::cpu1.data 129782 # number of UpgradeReq hits 271311570SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_hits::total 314457 # number of UpgradeReq hits 271411570SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_hits::cpu0.data 47164 # number of SCUpgradeReq hits 271511570SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_hits::cpu1.data 36238 # number of SCUpgradeReq hits 271611570SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_hits::total 83402 # number of SCUpgradeReq hits 271711570SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_hits::cpu0.data 58975 # number of ReadExReq hits 271811570SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_hits::cpu1.data 57393 # number of ReadExReq hits 271911570SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_hits::total 116368 # number of ReadExReq hits 272011570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.dtb.walker 7045 # number of ReadSharedReq hits 272111570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.itb.walker 4376 # number of ReadSharedReq hits 272211570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.inst 746247 # number of ReadSharedReq hits 272311570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.data 677498 # number of ReadSharedReq hits 272411570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 343450 # number of ReadSharedReq hits 272511570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.dtb.walker 6710 # number of ReadSharedReq hits 272611570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.itb.walker 4818 # number of ReadSharedReq hits 272711570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.inst 604538 # number of ReadSharedReq hits 272811570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.data 564393 # number of ReadSharedReq hits 272911570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 306025 # number of ReadSharedReq hits 273011570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_hits::total 3265100 # number of ReadSharedReq hits 273111570SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_hits::cpu0.data 138219 # number of InvalidateReq hits 273211570SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_hits::cpu1.data 125546 # number of InvalidateReq hits 273311570SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_hits::total 263765 # number of InvalidateReq hits 273411570SCurtis.Dunham@arm.comsystem.l2c.demand_hits::cpu0.dtb.walker 7045 # number of demand (read+write) hits 273511570SCurtis.Dunham@arm.comsystem.l2c.demand_hits::cpu0.itb.walker 4376 # number of demand (read+write) hits 273611570SCurtis.Dunham@arm.comsystem.l2c.demand_hits::cpu0.inst 746247 # number of demand (read+write) hits 273711570SCurtis.Dunham@arm.comsystem.l2c.demand_hits::cpu0.data 736473 # number of demand (read+write) hits 273811570SCurtis.Dunham@arm.comsystem.l2c.demand_hits::cpu0.l2cache.prefetcher 343450 # number of demand (read+write) hits 273911570SCurtis.Dunham@arm.comsystem.l2c.demand_hits::cpu1.dtb.walker 6710 # number of demand (read+write) hits 274011570SCurtis.Dunham@arm.comsystem.l2c.demand_hits::cpu1.itb.walker 4818 # number of demand (read+write) hits 274111570SCurtis.Dunham@arm.comsystem.l2c.demand_hits::cpu1.inst 604538 # number of demand (read+write) hits 274211570SCurtis.Dunham@arm.comsystem.l2c.demand_hits::cpu1.data 621786 # number of demand (read+write) hits 274311570SCurtis.Dunham@arm.comsystem.l2c.demand_hits::cpu1.l2cache.prefetcher 306025 # number of demand (read+write) hits 274411570SCurtis.Dunham@arm.comsystem.l2c.demand_hits::total 3381468 # number of demand (read+write) hits 274511570SCurtis.Dunham@arm.comsystem.l2c.overall_hits::cpu0.dtb.walker 7045 # number of overall hits 274611570SCurtis.Dunham@arm.comsystem.l2c.overall_hits::cpu0.itb.walker 4376 # number of overall hits 274711570SCurtis.Dunham@arm.comsystem.l2c.overall_hits::cpu0.inst 746247 # number of overall hits 274811570SCurtis.Dunham@arm.comsystem.l2c.overall_hits::cpu0.data 736473 # number of overall hits 274911570SCurtis.Dunham@arm.comsystem.l2c.overall_hits::cpu0.l2cache.prefetcher 343450 # number of overall hits 275011570SCurtis.Dunham@arm.comsystem.l2c.overall_hits::cpu1.dtb.walker 6710 # number of overall hits 275111570SCurtis.Dunham@arm.comsystem.l2c.overall_hits::cpu1.itb.walker 4818 # number of overall hits 275211570SCurtis.Dunham@arm.comsystem.l2c.overall_hits::cpu1.inst 604538 # number of overall hits 275311570SCurtis.Dunham@arm.comsystem.l2c.overall_hits::cpu1.data 621786 # number of overall hits 275411570SCurtis.Dunham@arm.comsystem.l2c.overall_hits::cpu1.l2cache.prefetcher 306025 # number of overall hits 275511570SCurtis.Dunham@arm.comsystem.l2c.overall_hits::total 3381468 # number of overall hits 275611570SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_misses::cpu0.data 65595 # number of UpgradeReq misses 275711570SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_misses::cpu1.data 60730 # number of UpgradeReq misses 275811570SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_misses::total 126325 # number of UpgradeReq misses 275911570SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_misses::cpu0.data 12636 # number of SCUpgradeReq misses 276011570SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_misses::cpu1.data 10558 # number of SCUpgradeReq misses 276111570SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_misses::total 23194 # number of SCUpgradeReq misses 276211570SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_misses::cpu0.data 86809 # number of ReadExReq misses 276311570SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_misses::cpu1.data 47256 # number of ReadExReq misses 276411570SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_misses::total 134065 # number of ReadExReq misses 276511570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.dtb.walker 2557 # number of ReadSharedReq misses 276611570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.itb.walker 2464 # number of ReadSharedReq misses 276711570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.inst 78739 # number of ReadSharedReq misses 276811570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.data 176748 # number of ReadSharedReq misses 276911570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 289930 # number of ReadSharedReq misses 277011570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.dtb.walker 1566 # number of ReadSharedReq misses 277111570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.itb.walker 1157 # number of ReadSharedReq misses 277211570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.inst 44505 # number of ReadSharedReq misses 277311570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.data 80821 # number of ReadSharedReq misses 277411570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 170404 # number of ReadSharedReq misses 277511570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_misses::total 848891 # number of ReadSharedReq misses 277611570SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_misses::cpu0.data 477170 # number of InvalidateReq misses 277711570SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_misses::cpu1.data 94656 # number of InvalidateReq misses 277811570SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_misses::total 571826 # number of InvalidateReq misses 277911570SCurtis.Dunham@arm.comsystem.l2c.demand_misses::cpu0.dtb.walker 2557 # number of demand (read+write) misses 278011570SCurtis.Dunham@arm.comsystem.l2c.demand_misses::cpu0.itb.walker 2464 # number of demand (read+write) misses 278111570SCurtis.Dunham@arm.comsystem.l2c.demand_misses::cpu0.inst 78739 # number of demand (read+write) misses 278211570SCurtis.Dunham@arm.comsystem.l2c.demand_misses::cpu0.data 263557 # number of demand (read+write) misses 278311570SCurtis.Dunham@arm.comsystem.l2c.demand_misses::cpu0.l2cache.prefetcher 289930 # number of demand (read+write) misses 278411570SCurtis.Dunham@arm.comsystem.l2c.demand_misses::cpu1.dtb.walker 1566 # number of demand (read+write) misses 278511570SCurtis.Dunham@arm.comsystem.l2c.demand_misses::cpu1.itb.walker 1157 # number of demand (read+write) misses 278611570SCurtis.Dunham@arm.comsystem.l2c.demand_misses::cpu1.inst 44505 # number of demand (read+write) misses 278711570SCurtis.Dunham@arm.comsystem.l2c.demand_misses::cpu1.data 128077 # number of demand (read+write) misses 278811570SCurtis.Dunham@arm.comsystem.l2c.demand_misses::cpu1.l2cache.prefetcher 170404 # number of demand (read+write) misses 278911570SCurtis.Dunham@arm.comsystem.l2c.demand_misses::total 982956 # number of demand (read+write) misses 279011570SCurtis.Dunham@arm.comsystem.l2c.overall_misses::cpu0.dtb.walker 2557 # number of overall misses 279111570SCurtis.Dunham@arm.comsystem.l2c.overall_misses::cpu0.itb.walker 2464 # number of overall misses 279211570SCurtis.Dunham@arm.comsystem.l2c.overall_misses::cpu0.inst 78739 # number of overall misses 279311570SCurtis.Dunham@arm.comsystem.l2c.overall_misses::cpu0.data 263557 # number of overall misses 279411570SCurtis.Dunham@arm.comsystem.l2c.overall_misses::cpu0.l2cache.prefetcher 289930 # number of overall misses 279511570SCurtis.Dunham@arm.comsystem.l2c.overall_misses::cpu1.dtb.walker 1566 # number of overall misses 279611570SCurtis.Dunham@arm.comsystem.l2c.overall_misses::cpu1.itb.walker 1157 # number of overall misses 279711570SCurtis.Dunham@arm.comsystem.l2c.overall_misses::cpu1.inst 44505 # number of overall misses 279811570SCurtis.Dunham@arm.comsystem.l2c.overall_misses::cpu1.data 128077 # number of overall misses 279911570SCurtis.Dunham@arm.comsystem.l2c.overall_misses::cpu1.l2cache.prefetcher 170404 # number of overall misses 280011570SCurtis.Dunham@arm.comsystem.l2c.overall_misses::total 982956 # number of overall misses 280111570SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_miss_latency::cpu0.data 456935000 # number of UpgradeReq miss cycles 280211570SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_miss_latency::cpu1.data 428124500 # number of UpgradeReq miss cycles 280311570SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_miss_latency::total 885059500 # number of UpgradeReq miss cycles 280411570SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_miss_latency::cpu0.data 88094500 # number of SCUpgradeReq miss cycles 280511570SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_miss_latency::cpu1.data 70625000 # number of SCUpgradeReq miss cycles 280611570SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_miss_latency::total 158719500 # number of SCUpgradeReq miss cycles 280711570SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_miss_latency::cpu0.data 7719270500 # number of ReadExReq miss cycles 280811570SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_miss_latency::cpu1.data 3911139500 # number of ReadExReq miss cycles 280911570SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_miss_latency::total 11630410000 # number of ReadExReq miss cycles 281011570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 226838000 # number of ReadSharedReq miss cycles 281111570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 219007500 # number of ReadSharedReq miss cycles 281211570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu0.inst 6705086500 # number of ReadSharedReq miss cycles 281311570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu0.data 15776824000 # number of ReadSharedReq miss cycles 281411570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 36609242451 # number of ReadSharedReq miss cycles 281511570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 145187000 # number of ReadSharedReq miss cycles 281611570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 107589500 # number of ReadSharedReq miss cycles 281711570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu1.inst 3760779000 # number of ReadSharedReq miss cycles 281811570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu1.data 7519043500 # number of ReadSharedReq miss cycles 281911570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 21421936717 # number of ReadSharedReq miss cycles 282011570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_latency::total 92491534168 # number of ReadSharedReq miss cycles 282111570SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_miss_latency::cpu0.data 63068500 # number of InvalidateReq miss cycles 282211570SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_miss_latency::cpu1.data 48974000 # number of InvalidateReq miss cycles 282311570SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_miss_latency::total 112042500 # number of InvalidateReq miss cycles 282411570SCurtis.Dunham@arm.comsystem.l2c.demand_miss_latency::cpu0.dtb.walker 226838000 # number of demand (read+write) miss cycles 282511570SCurtis.Dunham@arm.comsystem.l2c.demand_miss_latency::cpu0.itb.walker 219007500 # number of demand (read+write) miss cycles 282611570SCurtis.Dunham@arm.comsystem.l2c.demand_miss_latency::cpu0.inst 6705086500 # number of demand (read+write) miss cycles 282711570SCurtis.Dunham@arm.comsystem.l2c.demand_miss_latency::cpu0.data 23496094500 # number of demand (read+write) miss cycles 282811570SCurtis.Dunham@arm.comsystem.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 36609242451 # number of demand (read+write) miss cycles 282911570SCurtis.Dunham@arm.comsystem.l2c.demand_miss_latency::cpu1.dtb.walker 145187000 # number of demand (read+write) miss cycles 283011570SCurtis.Dunham@arm.comsystem.l2c.demand_miss_latency::cpu1.itb.walker 107589500 # number of demand (read+write) miss cycles 283111570SCurtis.Dunham@arm.comsystem.l2c.demand_miss_latency::cpu1.inst 3760779000 # number of demand (read+write) miss cycles 283211570SCurtis.Dunham@arm.comsystem.l2c.demand_miss_latency::cpu1.data 11430183000 # number of demand (read+write) miss cycles 283311570SCurtis.Dunham@arm.comsystem.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 21421936717 # number of demand (read+write) miss cycles 283411570SCurtis.Dunham@arm.comsystem.l2c.demand_miss_latency::total 104121944168 # number of demand (read+write) miss cycles 283511570SCurtis.Dunham@arm.comsystem.l2c.overall_miss_latency::cpu0.dtb.walker 226838000 # number of overall miss cycles 283611570SCurtis.Dunham@arm.comsystem.l2c.overall_miss_latency::cpu0.itb.walker 219007500 # number of overall miss cycles 283711570SCurtis.Dunham@arm.comsystem.l2c.overall_miss_latency::cpu0.inst 6705086500 # number of overall miss cycles 283811570SCurtis.Dunham@arm.comsystem.l2c.overall_miss_latency::cpu0.data 23496094500 # number of overall miss cycles 283911570SCurtis.Dunham@arm.comsystem.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 36609242451 # number of overall miss cycles 284011570SCurtis.Dunham@arm.comsystem.l2c.overall_miss_latency::cpu1.dtb.walker 145187000 # number of overall miss cycles 284111570SCurtis.Dunham@arm.comsystem.l2c.overall_miss_latency::cpu1.itb.walker 107589500 # number of overall miss cycles 284211570SCurtis.Dunham@arm.comsystem.l2c.overall_miss_latency::cpu1.inst 3760779000 # number of overall miss cycles 284311570SCurtis.Dunham@arm.comsystem.l2c.overall_miss_latency::cpu1.data 11430183000 # number of overall miss cycles 284411570SCurtis.Dunham@arm.comsystem.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 21421936717 # number of overall miss cycles 284511570SCurtis.Dunham@arm.comsystem.l2c.overall_miss_latency::total 104121944168 # number of overall miss cycles 284611570SCurtis.Dunham@arm.comsystem.l2c.WritebackDirty_accesses::writebacks 2851442 # number of WritebackDirty accesses(hits+misses) 284711570SCurtis.Dunham@arm.comsystem.l2c.WritebackDirty_accesses::total 2851442 # number of WritebackDirty accesses(hits+misses) 284811570SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_accesses::cpu0.data 250270 # number of UpgradeReq accesses(hits+misses) 284911570SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_accesses::cpu1.data 190512 # number of UpgradeReq accesses(hits+misses) 285011570SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_accesses::total 440782 # number of UpgradeReq accesses(hits+misses) 285111570SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_accesses::cpu0.data 59800 # number of SCUpgradeReq accesses(hits+misses) 285211570SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_accesses::cpu1.data 46796 # number of SCUpgradeReq accesses(hits+misses) 285311570SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_accesses::total 106596 # number of SCUpgradeReq accesses(hits+misses) 285411570SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_accesses::cpu0.data 145784 # number of ReadExReq accesses(hits+misses) 285511570SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_accesses::cpu1.data 104649 # number of ReadExReq accesses(hits+misses) 285611570SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_accesses::total 250433 # number of ReadExReq accesses(hits+misses) 285711570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 9602 # number of ReadSharedReq accesses(hits+misses) 285811570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.itb.walker 6840 # number of ReadSharedReq accesses(hits+misses) 285911570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.inst 824986 # number of ReadSharedReq accesses(hits+misses) 286011570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.data 854246 # number of ReadSharedReq accesses(hits+misses) 286111570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 633380 # number of ReadSharedReq accesses(hits+misses) 286211570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 8276 # number of ReadSharedReq accesses(hits+misses) 286311570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.itb.walker 5975 # number of ReadSharedReq accesses(hits+misses) 286411570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.inst 649043 # number of ReadSharedReq accesses(hits+misses) 286511570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.data 645214 # number of ReadSharedReq accesses(hits+misses) 286611570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 476429 # number of ReadSharedReq accesses(hits+misses) 286711570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_accesses::total 4113991 # number of ReadSharedReq accesses(hits+misses) 286811570SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_accesses::cpu0.data 615389 # number of InvalidateReq accesses(hits+misses) 286911570SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_accesses::cpu1.data 220202 # number of InvalidateReq accesses(hits+misses) 287011570SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_accesses::total 835591 # number of InvalidateReq accesses(hits+misses) 287111570SCurtis.Dunham@arm.comsystem.l2c.demand_accesses::cpu0.dtb.walker 9602 # number of demand (read+write) accesses 287211570SCurtis.Dunham@arm.comsystem.l2c.demand_accesses::cpu0.itb.walker 6840 # number of demand (read+write) accesses 287311570SCurtis.Dunham@arm.comsystem.l2c.demand_accesses::cpu0.inst 824986 # number of demand (read+write) accesses 287411570SCurtis.Dunham@arm.comsystem.l2c.demand_accesses::cpu0.data 1000030 # number of demand (read+write) accesses 287511570SCurtis.Dunham@arm.comsystem.l2c.demand_accesses::cpu0.l2cache.prefetcher 633380 # number of demand (read+write) accesses 287611570SCurtis.Dunham@arm.comsystem.l2c.demand_accesses::cpu1.dtb.walker 8276 # number of demand (read+write) accesses 287711570SCurtis.Dunham@arm.comsystem.l2c.demand_accesses::cpu1.itb.walker 5975 # number of demand (read+write) accesses 287811570SCurtis.Dunham@arm.comsystem.l2c.demand_accesses::cpu1.inst 649043 # number of demand (read+write) accesses 287911570SCurtis.Dunham@arm.comsystem.l2c.demand_accesses::cpu1.data 749863 # number of demand (read+write) accesses 288011570SCurtis.Dunham@arm.comsystem.l2c.demand_accesses::cpu1.l2cache.prefetcher 476429 # number of demand (read+write) accesses 288111570SCurtis.Dunham@arm.comsystem.l2c.demand_accesses::total 4364424 # number of demand (read+write) accesses 288211570SCurtis.Dunham@arm.comsystem.l2c.overall_accesses::cpu0.dtb.walker 9602 # number of overall (read+write) accesses 288311570SCurtis.Dunham@arm.comsystem.l2c.overall_accesses::cpu0.itb.walker 6840 # number of overall (read+write) accesses 288411570SCurtis.Dunham@arm.comsystem.l2c.overall_accesses::cpu0.inst 824986 # number of overall (read+write) accesses 288511570SCurtis.Dunham@arm.comsystem.l2c.overall_accesses::cpu0.data 1000030 # number of overall (read+write) accesses 288611570SCurtis.Dunham@arm.comsystem.l2c.overall_accesses::cpu0.l2cache.prefetcher 633380 # number of overall (read+write) accesses 288711570SCurtis.Dunham@arm.comsystem.l2c.overall_accesses::cpu1.dtb.walker 8276 # number of overall (read+write) accesses 288811570SCurtis.Dunham@arm.comsystem.l2c.overall_accesses::cpu1.itb.walker 5975 # number of overall (read+write) accesses 288911570SCurtis.Dunham@arm.comsystem.l2c.overall_accesses::cpu1.inst 649043 # number of overall (read+write) accesses 289011570SCurtis.Dunham@arm.comsystem.l2c.overall_accesses::cpu1.data 749863 # number of overall (read+write) accesses 289111570SCurtis.Dunham@arm.comsystem.l2c.overall_accesses::cpu1.l2cache.prefetcher 476429 # number of overall (read+write) accesses 289211570SCurtis.Dunham@arm.comsystem.l2c.overall_accesses::total 4364424 # number of overall (read+write) accesses 289311570SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_miss_rate::cpu0.data 0.262097 # miss rate for UpgradeReq accesses 289411570SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_miss_rate::cpu1.data 0.318773 # miss rate for UpgradeReq accesses 289511570SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_miss_rate::total 0.286593 # miss rate for UpgradeReq accesses 289611570SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.211304 # miss rate for SCUpgradeReq accesses 289711570SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.225618 # miss rate for SCUpgradeReq accesses 289811570SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_miss_rate::total 0.217588 # miss rate for SCUpgradeReq accesses 289911570SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_miss_rate::cpu0.data 0.595463 # miss rate for ReadExReq accesses 290011570SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_miss_rate::cpu1.data 0.451567 # miss rate for ReadExReq accesses 290111570SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_miss_rate::total 0.535333 # miss rate for ReadExReq accesses 290211570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.266299 # miss rate for ReadSharedReq accesses 290311570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.360234 # miss rate for ReadSharedReq accesses 290411570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.095443 # miss rate for ReadSharedReq accesses 290511570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.data 0.206905 # miss rate for ReadSharedReq accesses 290611570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.457750 # miss rate for ReadSharedReq accesses 290711570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.189222 # miss rate for ReadSharedReq accesses 290811570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.193640 # miss rate for ReadSharedReq accesses 290911570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.068570 # miss rate for ReadSharedReq accesses 291011570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.data 0.125262 # miss rate for ReadSharedReq accesses 291111570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.357669 # miss rate for ReadSharedReq accesses 291211570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_rate::total 0.206342 # miss rate for ReadSharedReq accesses 291311570SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_miss_rate::cpu0.data 0.775396 # miss rate for InvalidateReq accesses 291411570SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_miss_rate::cpu1.data 0.429860 # miss rate for InvalidateReq accesses 291511570SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_miss_rate::total 0.684337 # miss rate for InvalidateReq accesses 291611570SCurtis.Dunham@arm.comsystem.l2c.demand_miss_rate::cpu0.dtb.walker 0.266299 # miss rate for demand accesses 291711570SCurtis.Dunham@arm.comsystem.l2c.demand_miss_rate::cpu0.itb.walker 0.360234 # miss rate for demand accesses 291811570SCurtis.Dunham@arm.comsystem.l2c.demand_miss_rate::cpu0.inst 0.095443 # miss rate for demand accesses 291911570SCurtis.Dunham@arm.comsystem.l2c.demand_miss_rate::cpu0.data 0.263549 # miss rate for demand accesses 292011570SCurtis.Dunham@arm.comsystem.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.457750 # miss rate for demand accesses 292111570SCurtis.Dunham@arm.comsystem.l2c.demand_miss_rate::cpu1.dtb.walker 0.189222 # miss rate for demand accesses 292211570SCurtis.Dunham@arm.comsystem.l2c.demand_miss_rate::cpu1.itb.walker 0.193640 # miss rate for demand accesses 292311570SCurtis.Dunham@arm.comsystem.l2c.demand_miss_rate::cpu1.inst 0.068570 # miss rate for demand accesses 292411570SCurtis.Dunham@arm.comsystem.l2c.demand_miss_rate::cpu1.data 0.170801 # miss rate for demand accesses 292511570SCurtis.Dunham@arm.comsystem.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.357669 # miss rate for demand accesses 292611570SCurtis.Dunham@arm.comsystem.l2c.demand_miss_rate::total 0.225220 # miss rate for demand accesses 292711570SCurtis.Dunham@arm.comsystem.l2c.overall_miss_rate::cpu0.dtb.walker 0.266299 # miss rate for overall accesses 292811570SCurtis.Dunham@arm.comsystem.l2c.overall_miss_rate::cpu0.itb.walker 0.360234 # miss rate for overall accesses 292911570SCurtis.Dunham@arm.comsystem.l2c.overall_miss_rate::cpu0.inst 0.095443 # miss rate for overall accesses 293011570SCurtis.Dunham@arm.comsystem.l2c.overall_miss_rate::cpu0.data 0.263549 # miss rate for overall accesses 293111570SCurtis.Dunham@arm.comsystem.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.457750 # miss rate for overall accesses 293211570SCurtis.Dunham@arm.comsystem.l2c.overall_miss_rate::cpu1.dtb.walker 0.189222 # miss rate for overall accesses 293311570SCurtis.Dunham@arm.comsystem.l2c.overall_miss_rate::cpu1.itb.walker 0.193640 # miss rate for overall accesses 293411570SCurtis.Dunham@arm.comsystem.l2c.overall_miss_rate::cpu1.inst 0.068570 # miss rate for overall accesses 293511570SCurtis.Dunham@arm.comsystem.l2c.overall_miss_rate::cpu1.data 0.170801 # miss rate for overall accesses 293611570SCurtis.Dunham@arm.comsystem.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.357669 # miss rate for overall accesses 293711570SCurtis.Dunham@arm.comsystem.l2c.overall_miss_rate::total 0.225220 # miss rate for overall accesses 293811570SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_avg_miss_latency::cpu0.data 6966.003506 # average UpgradeReq miss latency 293911570SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_avg_miss_latency::cpu1.data 7049.637741 # average UpgradeReq miss latency 294011570SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_avg_miss_latency::total 7006.210172 # average UpgradeReq miss latency 294111570SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 6971.707819 # average SCUpgradeReq miss latency 294211570SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 6689.240386 # average SCUpgradeReq miss latency 294311570SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_avg_miss_latency::total 6843.127533 # average SCUpgradeReq miss latency 294411570SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_avg_miss_latency::cpu0.data 88922.467716 # average ReadExReq miss latency 294511570SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_avg_miss_latency::cpu1.data 82764.929321 # average ReadExReq miss latency 294611570SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_avg_miss_latency::total 86752.023272 # average ReadExReq miss latency 294711570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 88712.553774 # average ReadSharedReq miss latency 294811570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 88882.913961 # average ReadSharedReq miss latency 294911570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 85155.850341 # average ReadSharedReq miss latency 295011570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 89261.683301 # average ReadSharedReq miss latency 295111570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 126269.245856 # average ReadSharedReq miss latency 295211570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 92712.005109 # average ReadSharedReq miss latency 295311570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 92990.060501 # average ReadSharedReq miss latency 295411570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 84502.392990 # average ReadSharedReq miss latency 295511570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 93033.289615 # average ReadSharedReq miss latency 295611570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 125712.640061 # average ReadSharedReq miss latency 295711570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::total 108955.724784 # average ReadSharedReq miss latency 295811570SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_avg_miss_latency::cpu0.data 132.171972 # average InvalidateReq miss latency 295911570SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_avg_miss_latency::cpu1.data 517.389283 # average InvalidateReq miss latency 296011570SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_avg_miss_latency::total 195.938100 # average InvalidateReq miss latency 296111570SCurtis.Dunham@arm.comsystem.l2c.demand_avg_miss_latency::cpu0.dtb.walker 88712.553774 # average overall miss latency 296211570SCurtis.Dunham@arm.comsystem.l2c.demand_avg_miss_latency::cpu0.itb.walker 88882.913961 # average overall miss latency 296311570SCurtis.Dunham@arm.comsystem.l2c.demand_avg_miss_latency::cpu0.inst 85155.850341 # average overall miss latency 296411570SCurtis.Dunham@arm.comsystem.l2c.demand_avg_miss_latency::cpu0.data 89149.954279 # average overall miss latency 296511570SCurtis.Dunham@arm.comsystem.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 126269.245856 # average overall miss latency 296611570SCurtis.Dunham@arm.comsystem.l2c.demand_avg_miss_latency::cpu1.dtb.walker 92712.005109 # average overall miss latency 296711570SCurtis.Dunham@arm.comsystem.l2c.demand_avg_miss_latency::cpu1.itb.walker 92990.060501 # average overall miss latency 296811570SCurtis.Dunham@arm.comsystem.l2c.demand_avg_miss_latency::cpu1.inst 84502.392990 # average overall miss latency 296911570SCurtis.Dunham@arm.comsystem.l2c.demand_avg_miss_latency::cpu1.data 89244.618472 # average overall miss latency 297011570SCurtis.Dunham@arm.comsystem.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 125712.640061 # average overall miss latency 297111570SCurtis.Dunham@arm.comsystem.l2c.demand_avg_miss_latency::total 105927.370267 # average overall miss latency 297211570SCurtis.Dunham@arm.comsystem.l2c.overall_avg_miss_latency::cpu0.dtb.walker 88712.553774 # average overall miss latency 297311570SCurtis.Dunham@arm.comsystem.l2c.overall_avg_miss_latency::cpu0.itb.walker 88882.913961 # average overall miss latency 297411570SCurtis.Dunham@arm.comsystem.l2c.overall_avg_miss_latency::cpu0.inst 85155.850341 # average overall miss latency 297511570SCurtis.Dunham@arm.comsystem.l2c.overall_avg_miss_latency::cpu0.data 89149.954279 # average overall miss latency 297611570SCurtis.Dunham@arm.comsystem.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 126269.245856 # average overall miss latency 297711570SCurtis.Dunham@arm.comsystem.l2c.overall_avg_miss_latency::cpu1.dtb.walker 92712.005109 # average overall miss latency 297811570SCurtis.Dunham@arm.comsystem.l2c.overall_avg_miss_latency::cpu1.itb.walker 92990.060501 # average overall miss latency 297911570SCurtis.Dunham@arm.comsystem.l2c.overall_avg_miss_latency::cpu1.inst 84502.392990 # average overall miss latency 298011570SCurtis.Dunham@arm.comsystem.l2c.overall_avg_miss_latency::cpu1.data 89244.618472 # average overall miss latency 298111570SCurtis.Dunham@arm.comsystem.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 125712.640061 # average overall miss latency 298211570SCurtis.Dunham@arm.comsystem.l2c.overall_avg_miss_latency::total 105927.370267 # average overall miss latency 298311570SCurtis.Dunham@arm.comsystem.l2c.blocked_cycles::no_mshrs 198 # number of cycles access was blocked 298410515SAli.Saidi@ARM.comsystem.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 298511570SCurtis.Dunham@arm.comsystem.l2c.blocked::no_mshrs 3 # number of cycles access was blocked 298610515SAli.Saidi@ARM.comsystem.l2c.blocked::no_targets 0 # number of cycles access was blocked 298711570SCurtis.Dunham@arm.comsystem.l2c.avg_blocked_cycles::no_mshrs 66 # average number of cycles each access was blocked 298810515SAli.Saidi@ARM.comsystem.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 298911570SCurtis.Dunham@arm.comsystem.l2c.writebacks::writebacks 1121516 # number of writebacks 299011570SCurtis.Dunham@arm.comsystem.l2c.writebacks::total 1121516 # number of writebacks 299111570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_hits::cpu0.inst 148 # number of ReadSharedReq MSHR hits 299211570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_hits::cpu0.data 11 # number of ReadSharedReq MSHR hits 299311570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_hits::cpu1.inst 139 # number of ReadSharedReq MSHR hits 299411502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_hits::cpu1.data 17 # number of ReadSharedReq MSHR hits 299511570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_hits::total 315 # number of ReadSharedReq MSHR hits 299611570SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_hits::cpu0.inst 148 # number of demand (read+write) MSHR hits 299711570SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_hits::cpu0.data 11 # number of demand (read+write) MSHR hits 299811570SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_hits::cpu1.inst 139 # number of demand (read+write) MSHR hits 299911502SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_hits::cpu1.data 17 # number of demand (read+write) MSHR hits 300011570SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_hits::total 315 # number of demand (read+write) MSHR hits 300111570SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_hits::cpu0.inst 148 # number of overall MSHR hits 300211570SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_hits::cpu0.data 11 # number of overall MSHR hits 300311570SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_hits::cpu1.inst 139 # number of overall MSHR hits 300411502SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_hits::cpu1.data 17 # number of overall MSHR hits 300511570SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_hits::total 315 # number of overall MSHR hits 300611570SCurtis.Dunham@arm.comsystem.l2c.CleanEvict_mshr_misses::writebacks 53239 # number of CleanEvict MSHR misses 300711570SCurtis.Dunham@arm.comsystem.l2c.CleanEvict_mshr_misses::total 53239 # number of CleanEvict MSHR misses 300811570SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_mshr_misses::cpu0.data 65595 # number of UpgradeReq MSHR misses 300911570SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_mshr_misses::cpu1.data 60730 # number of UpgradeReq MSHR misses 301011570SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_mshr_misses::total 126325 # number of UpgradeReq MSHR misses 301111570SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_mshr_misses::cpu0.data 12636 # number of SCUpgradeReq MSHR misses 301211570SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_mshr_misses::cpu1.data 10558 # number of SCUpgradeReq MSHR misses 301311570SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_mshr_misses::total 23194 # number of SCUpgradeReq MSHR misses 301411570SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_mshr_misses::cpu0.data 86809 # number of ReadExReq MSHR misses 301511570SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_mshr_misses::cpu1.data 47256 # number of ReadExReq MSHR misses 301611570SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_mshr_misses::total 134065 # number of ReadExReq MSHR misses 301711570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 2557 # number of ReadSharedReq MSHR misses 301811570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 2464 # number of ReadSharedReq MSHR misses 301911570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu0.inst 78591 # number of ReadSharedReq MSHR misses 302011570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu0.data 176737 # number of ReadSharedReq MSHR misses 302111570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 289930 # number of ReadSharedReq MSHR misses 302211570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 1566 # number of ReadSharedReq MSHR misses 302311570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker 1157 # number of ReadSharedReq MSHR misses 302411570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu1.inst 44366 # number of ReadSharedReq MSHR misses 302511570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu1.data 80804 # number of ReadSharedReq MSHR misses 302611570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 170404 # number of ReadSharedReq MSHR misses 302711570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_misses::total 848576 # number of ReadSharedReq MSHR misses 302811570SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_mshr_misses::cpu0.data 477170 # number of InvalidateReq MSHR misses 302911570SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_mshr_misses::cpu1.data 94656 # number of InvalidateReq MSHR misses 303011570SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_mshr_misses::total 571826 # number of InvalidateReq MSHR misses 303111570SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_misses::cpu0.dtb.walker 2557 # number of demand (read+write) MSHR misses 303211570SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_misses::cpu0.itb.walker 2464 # number of demand (read+write) MSHR misses 303311570SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_misses::cpu0.inst 78591 # number of demand (read+write) MSHR misses 303411570SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_misses::cpu0.data 263546 # number of demand (read+write) MSHR misses 303511570SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 289930 # number of demand (read+write) MSHR misses 303611570SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_misses::cpu1.dtb.walker 1566 # number of demand (read+write) MSHR misses 303711570SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_misses::cpu1.itb.walker 1157 # number of demand (read+write) MSHR misses 303811570SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_misses::cpu1.inst 44366 # number of demand (read+write) MSHR misses 303911570SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_misses::cpu1.data 128060 # number of demand (read+write) MSHR misses 304011570SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 170404 # number of demand (read+write) MSHR misses 304111570SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_misses::total 982641 # number of demand (read+write) MSHR misses 304211570SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_misses::cpu0.dtb.walker 2557 # number of overall MSHR misses 304311570SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_misses::cpu0.itb.walker 2464 # number of overall MSHR misses 304411570SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_misses::cpu0.inst 78591 # number of overall MSHR misses 304511570SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_misses::cpu0.data 263546 # number of overall MSHR misses 304611570SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 289930 # number of overall MSHR misses 304711570SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_misses::cpu1.dtb.walker 1566 # number of overall MSHR misses 304811570SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_misses::cpu1.itb.walker 1157 # number of overall MSHR misses 304911570SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_misses::cpu1.inst 44366 # number of overall MSHR misses 305011570SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_misses::cpu1.data 128060 # number of overall MSHR misses 305111570SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 170404 # number of overall MSHR misses 305211570SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_misses::total 982641 # number of overall MSHR misses 305311570SCurtis.Dunham@arm.comsystem.l2c.ReadReq_mshr_uncacheable::cpu0.inst 52300 # number of ReadReq MSHR uncacheable 305411570SCurtis.Dunham@arm.comsystem.l2c.ReadReq_mshr_uncacheable::cpu0.data 29793 # number of ReadReq MSHR uncacheable 305511570SCurtis.Dunham@arm.comsystem.l2c.ReadReq_mshr_uncacheable::cpu1.inst 95 # number of ReadReq MSHR uncacheable 305611570SCurtis.Dunham@arm.comsystem.l2c.ReadReq_mshr_uncacheable::cpu1.data 8791 # number of ReadReq MSHR uncacheable 305711570SCurtis.Dunham@arm.comsystem.l2c.ReadReq_mshr_uncacheable::total 90979 # number of ReadReq MSHR uncacheable 305811570SCurtis.Dunham@arm.comsystem.l2c.WriteReq_mshr_uncacheable::cpu0.data 29400 # number of WriteReq MSHR uncacheable 305911570SCurtis.Dunham@arm.comsystem.l2c.WriteReq_mshr_uncacheable::cpu1.data 9091 # number of WriteReq MSHR uncacheable 306011570SCurtis.Dunham@arm.comsystem.l2c.WriteReq_mshr_uncacheable::total 38491 # number of WriteReq MSHR uncacheable 306111570SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_uncacheable_misses::cpu0.inst 52300 # number of overall MSHR uncacheable misses 306211570SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_uncacheable_misses::cpu0.data 59193 # number of overall MSHR uncacheable misses 306311570SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_uncacheable_misses::cpu1.inst 95 # number of overall MSHR uncacheable misses 306411570SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_uncacheable_misses::cpu1.data 17882 # number of overall MSHR uncacheable misses 306511570SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_uncacheable_misses::total 129470 # number of overall MSHR uncacheable misses 306611570SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 1410582996 # number of UpgradeReq MSHR miss cycles 306711570SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 1311057994 # number of UpgradeReq MSHR miss cycles 306811570SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_mshr_miss_latency::total 2721640990 # number of UpgradeReq MSHR miss cycles 306911570SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 310816999 # number of SCUpgradeReq MSHR miss cycles 307011570SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 259803998 # number of SCUpgradeReq MSHR miss cycles 307111570SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_mshr_miss_latency::total 570620997 # number of SCUpgradeReq MSHR miss cycles 307211570SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_mshr_miss_latency::cpu0.data 6851145073 # number of ReadExReq MSHR miss cycles 307311570SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3438526610 # number of ReadExReq MSHR miss cycles 307411570SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_mshr_miss_latency::total 10289671683 # number of ReadExReq MSHR miss cycles 307511570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 201267501 # number of ReadSharedReq MSHR miss cycles 307611570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 194366502 # number of ReadSharedReq MSHR miss cycles 307711570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 5908962562 # number of ReadSharedReq MSHR miss cycles 307811570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 14008544736 # number of ReadSharedReq MSHR miss cycles 307911570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 33709734391 # number of ReadSharedReq MSHR miss cycles 308011570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 129525503 # number of ReadSharedReq MSHR miss cycles 308111570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 96018502 # number of ReadSharedReq MSHR miss cycles 308211570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 3307546077 # number of ReadSharedReq MSHR miss cycles 308311570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 6709739262 # number of ReadSharedReq MSHR miss cycles 308411570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 19717611814 # number of ReadSharedReq MSHR miss cycles 308511570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_latency::total 83983316850 # number of ReadSharedReq MSHR miss cycles 308611570SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_mshr_miss_latency::cpu0.data 9978148501 # number of InvalidateReq MSHR miss cycles 308711570SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_mshr_miss_latency::cpu1.data 1974697000 # number of InvalidateReq MSHR miss cycles 308811570SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_mshr_miss_latency::total 11952845501 # number of InvalidateReq MSHR miss cycles 308911570SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 201267501 # number of demand (read+write) MSHR miss cycles 309011570SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_latency::cpu0.itb.walker 194366502 # number of demand (read+write) MSHR miss cycles 309111570SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_latency::cpu0.inst 5908962562 # number of demand (read+write) MSHR miss cycles 309211570SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_latency::cpu0.data 20859689809 # number of demand (read+write) MSHR miss cycles 309311570SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 33709734391 # number of demand (read+write) MSHR miss cycles 309411570SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 129525503 # number of demand (read+write) MSHR miss cycles 309511570SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_latency::cpu1.itb.walker 96018502 # number of demand (read+write) MSHR miss cycles 309611570SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_latency::cpu1.inst 3307546077 # number of demand (read+write) MSHR miss cycles 309711570SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_latency::cpu1.data 10148265872 # number of demand (read+write) MSHR miss cycles 309811570SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 19717611814 # number of demand (read+write) MSHR miss cycles 309911570SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_latency::total 94272988533 # number of demand (read+write) MSHR miss cycles 310011570SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 201267501 # number of overall MSHR miss cycles 310111570SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_latency::cpu0.itb.walker 194366502 # number of overall MSHR miss cycles 310211570SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_latency::cpu0.inst 5908962562 # number of overall MSHR miss cycles 310311570SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_latency::cpu0.data 20859689809 # number of overall MSHR miss cycles 310411570SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 33709734391 # number of overall MSHR miss cycles 310511570SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 129525503 # number of overall MSHR miss cycles 310611570SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_latency::cpu1.itb.walker 96018502 # number of overall MSHR miss cycles 310711570SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_latency::cpu1.inst 3307546077 # number of overall MSHR miss cycles 310811570SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_latency::cpu1.data 10148265872 # number of overall MSHR miss cycles 310911570SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 19717611814 # number of overall MSHR miss cycles 311011570SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_latency::total 94272988533 # number of overall MSHR miss cycles 311111570SCurtis.Dunham@arm.comsystem.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 3320084000 # number of ReadReq MSHR uncacheable cycles 311211570SCurtis.Dunham@arm.comsystem.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 4900695009 # number of ReadReq MSHR uncacheable cycles 311311570SCurtis.Dunham@arm.comsystem.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 6011000 # number of ReadReq MSHR uncacheable cycles 311411570SCurtis.Dunham@arm.comsystem.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 1076346004 # number of ReadReq MSHR uncacheable cycles 311511570SCurtis.Dunham@arm.comsystem.l2c.ReadReq_mshr_uncacheable_latency::total 9303136013 # number of ReadReq MSHR uncacheable cycles 311611570SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_uncacheable_latency::cpu0.inst 3320084000 # number of overall MSHR uncacheable cycles 311711570SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_uncacheable_latency::cpu0.data 4900695009 # number of overall MSHR uncacheable cycles 311811570SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_uncacheable_latency::cpu1.inst 6011000 # number of overall MSHR uncacheable cycles 311911570SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_uncacheable_latency::cpu1.data 1076346004 # number of overall MSHR uncacheable cycles 312011570SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_uncacheable_latency::total 9303136013 # number of overall MSHR uncacheable cycles 312110892Sandreas.hansson@arm.comsystem.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 312210892Sandreas.hansson@arm.comsystem.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 312311570SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.262097 # mshr miss rate for UpgradeReq accesses 312411570SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.318773 # mshr miss rate for UpgradeReq accesses 312511570SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_mshr_miss_rate::total 0.286593 # mshr miss rate for UpgradeReq accesses 312611570SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.211304 # mshr miss rate for SCUpgradeReq accesses 312711570SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.225618 # mshr miss rate for SCUpgradeReq accesses 312811570SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_mshr_miss_rate::total 0.217588 # mshr miss rate for SCUpgradeReq accesses 312911570SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.595463 # mshr miss rate for ReadExReq accesses 313011570SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.451567 # mshr miss rate for ReadExReq accesses 313111570SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_mshr_miss_rate::total 0.535333 # mshr miss rate for ReadExReq accesses 313211570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.266299 # mshr miss rate for ReadSharedReq accesses 313311570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.360234 # mshr miss rate for ReadSharedReq accesses 313411570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.095263 # mshr miss rate for ReadSharedReq accesses 313511570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.206892 # mshr miss rate for ReadSharedReq accesses 313611570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.457750 # mshr miss rate for ReadSharedReq accesses 313711570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.189222 # mshr miss rate for ReadSharedReq accesses 313811570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.193640 # mshr miss rate for ReadSharedReq accesses 313911570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.068356 # mshr miss rate for ReadSharedReq accesses 314011570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.125236 # mshr miss rate for ReadSharedReq accesses 314111570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.357669 # mshr miss rate for ReadSharedReq accesses 314211570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::total 0.206266 # mshr miss rate for ReadSharedReq accesses 314311570SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_mshr_miss_rate::cpu0.data 0.775396 # mshr miss rate for InvalidateReq accesses 314411570SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.429860 # mshr miss rate for InvalidateReq accesses 314511570SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_mshr_miss_rate::total 0.684337 # mshr miss rate for InvalidateReq accesses 314611570SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.266299 # mshr miss rate for demand accesses 314711570SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.360234 # mshr miss rate for demand accesses 314811570SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_rate::cpu0.inst 0.095263 # mshr miss rate for demand accesses 314911570SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_rate::cpu0.data 0.263538 # mshr miss rate for demand accesses 315011570SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.457750 # mshr miss rate for demand accesses 315111570SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.189222 # mshr miss rate for demand accesses 315211570SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.193640 # mshr miss rate for demand accesses 315311570SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_rate::cpu1.inst 0.068356 # mshr miss rate for demand accesses 315411570SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_rate::cpu1.data 0.170778 # mshr miss rate for demand accesses 315511570SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.357669 # mshr miss rate for demand accesses 315611570SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_rate::total 0.225148 # mshr miss rate for demand accesses 315711570SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.266299 # mshr miss rate for overall accesses 315811570SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.360234 # mshr miss rate for overall accesses 315911570SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_rate::cpu0.inst 0.095263 # mshr miss rate for overall accesses 316011570SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_rate::cpu0.data 0.263538 # mshr miss rate for overall accesses 316111570SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.457750 # mshr miss rate for overall accesses 316211570SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.189222 # mshr miss rate for overall accesses 316311570SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.193640 # mshr miss rate for overall accesses 316411570SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_rate::cpu1.inst 0.068356 # mshr miss rate for overall accesses 316511570SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_rate::cpu1.data 0.170778 # mshr miss rate for overall accesses 316611570SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.357669 # mshr miss rate for overall accesses 316711570SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_rate::total 0.225148 # mshr miss rate for overall accesses 316811570SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 21504.428630 # average UpgradeReq mshr miss latency 316911570SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 21588.308809 # average UpgradeReq mshr miss latency 317011570SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_avg_mshr_miss_latency::total 21544.753533 # average UpgradeReq mshr miss latency 317111570SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 24597.736546 # average SCUpgradeReq mshr miss latency 317211570SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24607.311801 # average SCUpgradeReq mshr miss latency 317311570SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 24602.095240 # average SCUpgradeReq mshr miss latency 317411570SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 78922.059614 # average ReadExReq mshr miss latency 317511570SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 72763.810098 # average ReadExReq mshr miss latency 317611570SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_avg_mshr_miss_latency::total 76751.364510 # average ReadExReq mshr miss latency 317711570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 78712.358623 # average ReadSharedReq mshr miss latency 317811570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 78882.508929 # average ReadSharedReq mshr miss latency 317911570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 75186.249850 # average ReadSharedReq mshr miss latency 318011570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 79262.094163 # average ReadSharedReq mshr miss latency 318111570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 116268.528234 # average ReadSharedReq mshr miss latency 318211570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 82711.049170 # average ReadSharedReq mshr miss latency 318311570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 82989.197926 # average ReadSharedReq mshr miss latency 318411570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 74551.369900 # average ReadSharedReq mshr miss latency 318511570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 83037.216747 # average ReadSharedReq mshr miss latency 318611570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 115710.968135 # average ReadSharedReq mshr miss latency 318711570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::total 98969.705542 # average ReadSharedReq mshr miss latency 318811570SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 20911.097724 # average InvalidateReq mshr miss latency 318911570SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 20861.825980 # average InvalidateReq mshr miss latency 319011570SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_avg_mshr_miss_latency::total 20902.941631 # average InvalidateReq mshr miss latency 319111570SCurtis.Dunham@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 78712.358623 # average overall mshr miss latency 319211570SCurtis.Dunham@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 78882.508929 # average overall mshr miss latency 319311570SCurtis.Dunham@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.inst 75186.249850 # average overall mshr miss latency 319411570SCurtis.Dunham@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.data 79150.090720 # average overall mshr miss latency 319511570SCurtis.Dunham@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 116268.528234 # average overall mshr miss latency 319611570SCurtis.Dunham@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 82711.049170 # average overall mshr miss latency 319711570SCurtis.Dunham@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 82989.197926 # average overall mshr miss latency 319811570SCurtis.Dunham@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.inst 74551.369900 # average overall mshr miss latency 319911570SCurtis.Dunham@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.data 79246.180478 # average overall mshr miss latency 320011570SCurtis.Dunham@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 115710.968135 # average overall mshr miss latency 320111570SCurtis.Dunham@arm.comsystem.l2c.demand_avg_mshr_miss_latency::total 95938.382922 # average overall mshr miss latency 320211570SCurtis.Dunham@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 78712.358623 # average overall mshr miss latency 320311570SCurtis.Dunham@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 78882.508929 # average overall mshr miss latency 320411570SCurtis.Dunham@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.inst 75186.249850 # average overall mshr miss latency 320511570SCurtis.Dunham@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.data 79150.090720 # average overall mshr miss latency 320611570SCurtis.Dunham@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 116268.528234 # average overall mshr miss latency 320711570SCurtis.Dunham@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 82711.049170 # average overall mshr miss latency 320811570SCurtis.Dunham@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 82989.197926 # average overall mshr miss latency 320911570SCurtis.Dunham@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.inst 74551.369900 # average overall mshr miss latency 321011570SCurtis.Dunham@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.data 79246.180478 # average overall mshr miss latency 321111570SCurtis.Dunham@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 115710.968135 # average overall mshr miss latency 321211570SCurtis.Dunham@arm.comsystem.l2c.overall_avg_mshr_miss_latency::total 95938.382922 # average overall mshr miss latency 321311570SCurtis.Dunham@arm.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 63481.529637 # average ReadReq mshr uncacheable latency 321411570SCurtis.Dunham@arm.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 164491.491592 # average ReadReq mshr uncacheable latency 321511570SCurtis.Dunham@arm.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 63273.684211 # average ReadReq mshr uncacheable latency 321611570SCurtis.Dunham@arm.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 122437.265840 # average ReadReq mshr uncacheable latency 321711570SCurtis.Dunham@arm.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::total 102255.861386 # average ReadReq mshr uncacheable latency 321811570SCurtis.Dunham@arm.comsystem.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 63481.529637 # average overall mshr uncacheable latency 321911570SCurtis.Dunham@arm.comsystem.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 82791.799858 # average overall mshr uncacheable latency 322011570SCurtis.Dunham@arm.comsystem.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 63273.684211 # average overall mshr uncacheable latency 322111570SCurtis.Dunham@arm.comsystem.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 60191.589531 # average overall mshr uncacheable latency 322211570SCurtis.Dunham@arm.comsystem.l2c.overall_avg_mshr_uncacheable_latency::total 71855.534201 # average overall mshr uncacheable latency 322311570SCurtis.Dunham@arm.comsystem.membus.snoop_filter.tot_requests 3914348 # Total number of requests made to the snoop filter. 322411570SCurtis.Dunham@arm.comsystem.membus.snoop_filter.hit_single_requests 2362357 # Number of requests hitting in the snoop filter with a single holder of the requested data. 322511570SCurtis.Dunham@arm.comsystem.membus.snoop_filter.hit_multi_requests 2871 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 322611502SCurtis.Dunham@arm.comsystem.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 322711502SCurtis.Dunham@arm.comsystem.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 322811502SCurtis.Dunham@arm.comsystem.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 322911570SCurtis.Dunham@arm.comsystem.membus.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states 323011570SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadReq 90979 # Transaction distribution 323111570SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadResp 948459 # Transaction distribution 323211570SCurtis.Dunham@arm.comsystem.membus.trans_dist::WriteReq 38491 # Transaction distribution 323311570SCurtis.Dunham@arm.comsystem.membus.trans_dist::WriteResp 38491 # Transaction distribution 323411570SCurtis.Dunham@arm.comsystem.membus.trans_dist::WritebackDirty 1228466 # Transaction distribution 323511570SCurtis.Dunham@arm.comsystem.membus.trans_dist::CleanEvict 265252 # Transaction distribution 323611570SCurtis.Dunham@arm.comsystem.membus.trans_dist::UpgradeReq 443986 # Transaction distribution 323711570SCurtis.Dunham@arm.comsystem.membus.trans_dist::SCUpgradeReq 298688 # Transaction distribution 323811570SCurtis.Dunham@arm.comsystem.membus.trans_dist::UpgradeResp 23 # Transaction distribution 323911441Sandreas.hansson@arm.comsystem.membus.trans_dist::SCUpgradeFailReq 2 # Transaction distribution 324011570SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadExReq 145286 # Transaction distribution 324111570SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadExResp 128554 # Transaction distribution 324211570SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadSharedReq 857480 # Transaction distribution 324311570SCurtis.Dunham@arm.comsystem.membus.trans_dist::InvalidateReq 675140 # Transaction distribution 324411570SCurtis.Dunham@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122950 # Packet count per connected master and slave (bytes) 324511570SCurtis.Dunham@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 54 # Packet count per connected master and slave (bytes) 324611570SCurtis.Dunham@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 25980 # Packet count per connected master and slave (bytes) 324711570SCurtis.Dunham@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4768940 # Packet count per connected master and slave (bytes) 324811570SCurtis.Dunham@arm.comsystem.membus.pkt_count_system.l2c.mem_side::total 4917924 # Packet count per connected master and slave (bytes) 324911570SCurtis.Dunham@arm.comsystem.membus.pkt_count_system.iocache.mem_side::system.physmem.port 238548 # Packet count per connected master and slave (bytes) 325011570SCurtis.Dunham@arm.comsystem.membus.pkt_count_system.iocache.mem_side::total 238548 # Packet count per connected master and slave (bytes) 325111570SCurtis.Dunham@arm.comsystem.membus.pkt_count::total 5156472 # Packet count per connected master and slave (bytes) 325211570SCurtis.Dunham@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155965 # Cumulative packet size per connected master and slave (bytes) 325311570SCurtis.Dunham@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1388 # Cumulative packet size per connected master and slave (bytes) 325411570SCurtis.Dunham@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 51960 # Cumulative packet size per connected master and slave (bytes) 325511570SCurtis.Dunham@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.physmem.port 137639872 # Cumulative packet size per connected master and slave (bytes) 325611570SCurtis.Dunham@arm.comsystem.membus.pkt_size_system.l2c.mem_side::total 137849185 # Cumulative packet size per connected master and slave (bytes) 325711570SCurtis.Dunham@arm.comsystem.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7281600 # Cumulative packet size per connected master and slave (bytes) 325811570SCurtis.Dunham@arm.comsystem.membus.pkt_size_system.iocache.mem_side::total 7281600 # Cumulative packet size per connected master and slave (bytes) 325911570SCurtis.Dunham@arm.comsystem.membus.pkt_size::total 145130785 # Cumulative packet size per connected master and slave (bytes) 326011570SCurtis.Dunham@arm.comsystem.membus.snoops 603530 # Total snoops (count) 326111570SCurtis.Dunham@arm.comsystem.membus.snoopTraffic 179328 # Total snoop traffic (bytes) 326211570SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::samples 2550056 # Request fanout histogram 326311570SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::mean 0.011955 # Request fanout histogram 326411570SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::stdev 0.108685 # Request fanout histogram 326510585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 326611570SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::0 2519569 98.80% 98.80% # Request fanout histogram 326711570SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::1 30487 1.20% 100.00% # Request fanout histogram 326810585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 326910585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 327011502SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::min_value 0 # Request fanout histogram 327110585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::max_value 1 # Request fanout histogram 327211570SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::total 2550056 # Request fanout histogram 327311570SCurtis.Dunham@arm.comsystem.membus.reqLayer0.occupancy 103375494 # Layer occupancy (ticks) 327410585Sandreas.hansson@arm.comsystem.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 327511570SCurtis.Dunham@arm.comsystem.membus.reqLayer1.occupancy 34812 # Layer occupancy (ticks) 327610585Sandreas.hansson@arm.comsystem.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 327711570SCurtis.Dunham@arm.comsystem.membus.reqLayer2.occupancy 21768496 # Layer occupancy (ticks) 327810585Sandreas.hansson@arm.comsystem.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 327911570SCurtis.Dunham@arm.comsystem.membus.reqLayer5.occupancy 8632891321 # Layer occupancy (ticks) 328010585Sandreas.hansson@arm.comsystem.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 328111570SCurtis.Dunham@arm.comsystem.membus.respLayer2.occupancy 5537724663 # Layer occupancy (ticks) 328210585Sandreas.hansson@arm.comsystem.membus.respLayer2.utilization 0.0 # Layer utilization (%) 328311570SCurtis.Dunham@arm.comsystem.membus.respLayer3.occupancy 45395946 # Layer occupancy (ticks) 328410585Sandreas.hansson@arm.comsystem.membus.respLayer3.utilization 0.0 # Layer utilization (%) 328511570SCurtis.Dunham@arm.comsystem.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states 328611570SCurtis.Dunham@arm.comsystem.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states 328711570SCurtis.Dunham@arm.comsystem.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states 328811570SCurtis.Dunham@arm.comsystem.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states 328911570SCurtis.Dunham@arm.comsystem.realview.gic.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states 329011570SCurtis.Dunham@arm.comsystem.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states 329111570SCurtis.Dunham@arm.comsystem.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states 329211239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 329311239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 329411239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 329511239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 329611239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 329711239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_sys.clock 16667 # Clock period in ticks 329811570SCurtis.Dunham@arm.comsystem.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states 329911570SCurtis.Dunham@arm.comsystem.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states 330010515SAli.Saidi@ARM.comsystem.realview.ethernet.txBytes 966 # Bytes Transmitted 330110515SAli.Saidi@ARM.comsystem.realview.ethernet.txPackets 3 # Number of Packets Transmitted 330210515SAli.Saidi@ARM.comsystem.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device 330310515SAli.Saidi@ARM.comsystem.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device 330410515SAli.Saidi@ARM.comsystem.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 330510515SAli.Saidi@ARM.comsystem.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 330610515SAli.Saidi@ARM.comsystem.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 330710515SAli.Saidi@ARM.comsystem.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 330810515SAli.Saidi@ARM.comsystem.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 330911201Sandreas.hansson@arm.comsystem.realview.ethernet.totBandwidth 163 # Total Bandwidth (bits/s) 331010515SAli.Saidi@ARM.comsystem.realview.ethernet.totPackets 3 # Total Packets 331110515SAli.Saidi@ARM.comsystem.realview.ethernet.totBytes 966 # Total Bytes 331210515SAli.Saidi@ARM.comsystem.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) 331311201Sandreas.hansson@arm.comsystem.realview.ethernet.txBandwidth 163 # Transmit Bandwidth (bits/s) 331410515SAli.Saidi@ARM.comsystem.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) 331510515SAli.Saidi@ARM.comsystem.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 331610515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post 331710515SAli.Saidi@ARM.comsystem.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 331810515SAli.Saidi@ARM.comsystem.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 331910515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post 332010515SAli.Saidi@ARM.comsystem.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 332110515SAli.Saidi@ARM.comsystem.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 332210515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post 332310515SAli.Saidi@ARM.comsystem.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 332410515SAli.Saidi@ARM.comsystem.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 332510515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post 332610515SAli.Saidi@ARM.comsystem.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 332710515SAli.Saidi@ARM.comsystem.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 332810515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post 332910515SAli.Saidi@ARM.comsystem.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 333010515SAli.Saidi@ARM.comsystem.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 333110515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post 333210515SAli.Saidi@ARM.comsystem.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 333310515SAli.Saidi@ARM.comsystem.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 333410515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 333510515SAli.Saidi@ARM.comsystem.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 333610515SAli.Saidi@ARM.comsystem.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 333710515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 333810515SAli.Saidi@ARM.comsystem.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 333910515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 334010515SAli.Saidi@ARM.comsystem.realview.ethernet.postedInterrupts 13 # number of posts to CPU 334110515SAli.Saidi@ARM.comsystem.realview.ethernet.droppedPackets 0 # number of packets dropped 334211570SCurtis.Dunham@arm.comsystem.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states 334311570SCurtis.Dunham@arm.comsystem.realview.ide.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states 334411570SCurtis.Dunham@arm.comsystem.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states 334511570SCurtis.Dunham@arm.comsystem.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states 334611570SCurtis.Dunham@arm.comsystem.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states 334711570SCurtis.Dunham@arm.comsystem.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states 334811570SCurtis.Dunham@arm.comsystem.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states 334911239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 335011239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 335111239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 335211239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks 335311570SCurtis.Dunham@arm.comsystem.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states 335411570SCurtis.Dunham@arm.comsystem.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states 335511570SCurtis.Dunham@arm.comsystem.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states 335611570SCurtis.Dunham@arm.comsystem.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states 335711570SCurtis.Dunham@arm.comsystem.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states 335811570SCurtis.Dunham@arm.comsystem.realview.uart.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states 335911570SCurtis.Dunham@arm.comsystem.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states 336011570SCurtis.Dunham@arm.comsystem.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states 336111570SCurtis.Dunham@arm.comsystem.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states 336211570SCurtis.Dunham@arm.comsystem.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states 336311570SCurtis.Dunham@arm.comsystem.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states 336411570SCurtis.Dunham@arm.comsystem.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states 336511570SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_filter.tot_requests 12809826 # Total number of requests made to the snoop filter. 336611570SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_filter.hit_single_requests 6934559 # Number of requests hitting in the snoop filter with a single holder of the requested data. 336711570SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_filter.hit_multi_requests 2124865 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 336811570SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_filter.tot_snoops 137043 # Total number of snoops made to the snoop filter. 336911570SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_filter.hit_single_snoops 124917 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 337011570SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_filter.hit_multi_snoops 12126 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 337111570SCurtis.Dunham@arm.comsystem.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states 337211570SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::ReadReq 90981 # Transaction distribution 337311570SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::ReadResp 4987806 # Transaction distribution 337411570SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::WriteReq 38491 # Transaction distribution 337511570SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::WriteResp 38491 # Transaction distribution 337611570SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::WritebackDirty 3972958 # Transaction distribution 337711570SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::CleanEvict 3104635 # Transaction distribution 337811570SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::UpgradeReq 749262 # Transaction distribution 337911570SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::SCUpgradeReq 382090 # Transaction distribution 338011570SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::UpgradeResp 1131352 # Transaction distribution 338111570SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::SCUpgradeFailReq 138 # Transaction distribution 338211570SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::UpgradeFailResp 138 # Transaction distribution 338311570SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::ReadExReq 306540 # Transaction distribution 338411570SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::ReadExResp 306540 # Transaction distribution 338511570SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::ReadSharedReq 4897318 # Transaction distribution 338611570SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::InvalidateReq 863164 # Transaction distribution 338711570SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::InvalidateResp 835591 # Transaction distribution 338811570SCurtis.Dunham@arm.comsystem.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 11082342 # Packet count per connected master and slave (bytes) 338911570SCurtis.Dunham@arm.comsystem.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7735233 # Packet count per connected master and slave (bytes) 339011570SCurtis.Dunham@arm.comsystem.toL2Bus.pkt_count::total 18817575 # Packet count per connected master and slave (bytes) 339111570SCurtis.Dunham@arm.comsystem.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 276628165 # Cumulative packet size per connected master and slave (bytes) 339211570SCurtis.Dunham@arm.comsystem.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 188875292 # Cumulative packet size per connected master and slave (bytes) 339311570SCurtis.Dunham@arm.comsystem.toL2Bus.pkt_size::total 465503457 # Cumulative packet size per connected master and slave (bytes) 339411570SCurtis.Dunham@arm.comsystem.toL2Bus.snoops 2889580 # Total snoops (count) 339511570SCurtis.Dunham@arm.comsystem.toL2Bus.snoopTraffic 125478224 # Total snoop traffic (bytes) 339611570SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::samples 8764836 # Request fanout histogram 339711570SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::mean 0.360858 # Request fanout histogram 339811570SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::stdev 0.483121 # Request fanout histogram 339910515SAli.Saidi@ARM.comsystem.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 340011570SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::0 5614105 64.05% 64.05% # Request fanout histogram 340111570SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::1 3138605 35.81% 99.86% # Request fanout histogram 340211570SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::2 12126 0.14% 100.00% # Request fanout histogram 340310515SAli.Saidi@ARM.comsystem.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 340411138Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 340510515SAli.Saidi@ARM.comsystem.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 340611570SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::total 8764836 # Request fanout histogram 340711570SCurtis.Dunham@arm.comsystem.toL2Bus.reqLayer0.occupancy 9763497454 # Layer occupancy (ticks) 340810515SAli.Saidi@ARM.comsystem.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 340911570SCurtis.Dunham@arm.comsystem.toL2Bus.snoopLayer0.occupancy 2559907 # Layer occupancy (ticks) 341010515SAli.Saidi@ARM.comsystem.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 341111570SCurtis.Dunham@arm.comsystem.toL2Bus.respLayer0.occupancy 5082599079 # Layer occupancy (ticks) 341210515SAli.Saidi@ARM.comsystem.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 341311570SCurtis.Dunham@arm.comsystem.toL2Bus.respLayer1.occupancy 3859782501 # Layer occupancy (ticks) 341410515SAli.Saidi@ARM.comsystem.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 341510515SAli.Saidi@ARM.com 341610515SAli.Saidi@ARM.com---------- End Simulation Statistics ---------- 3417