stats.txt revision 11570
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 47.445489 # Number of seconds simulated 4sim_ticks 47445489241000 # Number of ticks simulated 5final_tick 47445489241000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 208966 # Simulator instruction rate (inst/s) 8host_op_rate 245756 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 10881126125 # Simulator tick rate (ticks/s) 10host_mem_usage 759660 # Number of bytes of host memory used 11host_seconds 4360.35 # Real time elapsed on the host 12sim_insts 911162440 # Number of instructions simulated 13sim_ops 1071583187 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu0.dtb.walker 163648 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.itb.walker 157696 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.inst 8375360 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu0.data 16685256 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu0.l2cache.prefetcher 18550592 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.dtb.walker 100224 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu1.itb.walker 74048 # Number of bytes read from this memory 24system.physmem.bytes_read::cpu1.inst 2844864 # Number of bytes read from this memory 25system.physmem.bytes_read::cpu1.data 7994832 # Number of bytes read from this memory 26system.physmem.bytes_read::cpu1.l2cache.prefetcher 10895744 # Number of bytes read from this memory 27system.physmem.bytes_read::realview.ide 436800 # Number of bytes read from this memory 28system.physmem.bytes_read::total 66279064 # Number of bytes read from this memory 29system.physmem.bytes_inst_read::cpu0.inst 8375360 # Number of instructions bytes read from this memory 30system.physmem.bytes_inst_read::cpu1.inst 2844864 # Number of instructions bytes read from this memory 31system.physmem.bytes_inst_read::total 11220224 # Number of instructions bytes read from this memory 32system.physmem.bytes_written::writebacks 78621824 # Number of bytes written to this memory 33system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory 34system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory 35system.physmem.bytes_written::total 78642408 # Number of bytes written to this memory 36system.physmem.num_reads::cpu0.dtb.walker 2557 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu0.itb.walker 2464 # Number of read requests responded to by this memory 38system.physmem.num_reads::cpu0.inst 130865 # Number of read requests responded to by this memory 39system.physmem.num_reads::cpu0.data 260720 # Number of read requests responded to by this memory 40system.physmem.num_reads::cpu0.l2cache.prefetcher 289853 # Number of read requests responded to by this memory 41system.physmem.num_reads::cpu1.dtb.walker 1566 # Number of read requests responded to by this memory 42system.physmem.num_reads::cpu1.itb.walker 1157 # Number of read requests responded to by this memory 43system.physmem.num_reads::cpu1.inst 44451 # Number of read requests responded to by this memory 44system.physmem.num_reads::cpu1.data 124932 # Number of read requests responded to by this memory 45system.physmem.num_reads::cpu1.l2cache.prefetcher 170246 # Number of read requests responded to by this memory 46system.physmem.num_reads::realview.ide 6825 # Number of read requests responded to by this memory 47system.physmem.num_reads::total 1035636 # Number of read requests responded to by this memory 48system.physmem.num_writes::writebacks 1228466 # Number of write requests responded to by this memory 49system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory 50system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory 51system.physmem.num_writes::total 1231040 # Number of write requests responded to by this memory 52system.physmem.bw_read::cpu0.dtb.walker 3449 # Total read bandwidth from this memory (bytes/s) 53system.physmem.bw_read::cpu0.itb.walker 3324 # Total read bandwidth from this memory (bytes/s) 54system.physmem.bw_read::cpu0.inst 176526 # Total read bandwidth from this memory (bytes/s) 55system.physmem.bw_read::cpu0.data 351672 # Total read bandwidth from this memory (bytes/s) 56system.physmem.bw_read::cpu0.l2cache.prefetcher 390987 # Total read bandwidth from this memory (bytes/s) 57system.physmem.bw_read::cpu1.dtb.walker 2112 # Total read bandwidth from this memory (bytes/s) 58system.physmem.bw_read::cpu1.itb.walker 1561 # Total read bandwidth from this memory (bytes/s) 59system.physmem.bw_read::cpu1.inst 59961 # Total read bandwidth from this memory (bytes/s) 60system.physmem.bw_read::cpu1.data 168506 # Total read bandwidth from this memory (bytes/s) 61system.physmem.bw_read::cpu1.l2cache.prefetcher 229648 # Total read bandwidth from this memory (bytes/s) 62system.physmem.bw_read::realview.ide 9206 # Total read bandwidth from this memory (bytes/s) 63system.physmem.bw_read::total 1396952 # Total read bandwidth from this memory (bytes/s) 64system.physmem.bw_inst_read::cpu0.inst 176526 # Instruction read bandwidth from this memory (bytes/s) 65system.physmem.bw_inst_read::cpu1.inst 59961 # Instruction read bandwidth from this memory (bytes/s) 66system.physmem.bw_inst_read::total 236487 # Instruction read bandwidth from this memory (bytes/s) 67system.physmem.bw_write::writebacks 1657098 # Write bandwidth from this memory (bytes/s) 68system.physmem.bw_write::cpu0.data 434 # Write bandwidth from this memory (bytes/s) 69system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) 70system.physmem.bw_write::total 1657532 # Write bandwidth from this memory (bytes/s) 71system.physmem.bw_total::writebacks 1657098 # Total bandwidth to/from this memory (bytes/s) 72system.physmem.bw_total::cpu0.dtb.walker 3449 # Total bandwidth to/from this memory (bytes/s) 73system.physmem.bw_total::cpu0.itb.walker 3324 # Total bandwidth to/from this memory (bytes/s) 74system.physmem.bw_total::cpu0.inst 176526 # Total bandwidth to/from this memory (bytes/s) 75system.physmem.bw_total::cpu0.data 352106 # Total bandwidth to/from this memory (bytes/s) 76system.physmem.bw_total::cpu0.l2cache.prefetcher 390987 # Total bandwidth to/from this memory (bytes/s) 77system.physmem.bw_total::cpu1.dtb.walker 2112 # Total bandwidth to/from this memory (bytes/s) 78system.physmem.bw_total::cpu1.itb.walker 1561 # Total bandwidth to/from this memory (bytes/s) 79system.physmem.bw_total::cpu1.inst 59961 # Total bandwidth to/from this memory (bytes/s) 80system.physmem.bw_total::cpu1.data 168506 # Total bandwidth to/from this memory (bytes/s) 81system.physmem.bw_total::cpu1.l2cache.prefetcher 229648 # Total bandwidth to/from this memory (bytes/s) 82system.physmem.bw_total::realview.ide 9206 # Total bandwidth to/from this memory (bytes/s) 83system.physmem.bw_total::total 3054484 # Total bandwidth to/from this memory (bytes/s) 84system.physmem.readReqs 1035636 # Number of read requests accepted 85system.physmem.writeReqs 1231040 # Number of write requests accepted 86system.physmem.readBursts 1035636 # Number of DRAM read bursts, including those serviced by the write queue 87system.physmem.writeBursts 1231040 # Number of DRAM write bursts, including those merged in the write queue 88system.physmem.bytesReadDRAM 66252160 # Total number of bytes read from DRAM 89system.physmem.bytesReadWrQ 28544 # Total number of bytes read from write queue 90system.physmem.bytesWritten 78640192 # Total number of bytes written to DRAM 91system.physmem.bytesReadSys 66279064 # Total read bytes from the system interface side 92system.physmem.bytesWrittenSys 78642408 # Total written bytes from the system interface side 93system.physmem.servicedByWrQ 446 # Number of DRAM read bursts serviced by the write queue 94system.physmem.mergedWrBursts 2268 # Number of DRAM write bursts merged with an existing one 95system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 96system.physmem.perBankRdBursts::0 59521 # Per bank write bursts 97system.physmem.perBankRdBursts::1 66808 # Per bank write bursts 98system.physmem.perBankRdBursts::2 62154 # Per bank write bursts 99system.physmem.perBankRdBursts::3 70128 # Per bank write bursts 100system.physmem.perBankRdBursts::4 60732 # Per bank write bursts 101system.physmem.perBankRdBursts::5 72109 # Per bank write bursts 102system.physmem.perBankRdBursts::6 58717 # Per bank write bursts 103system.physmem.perBankRdBursts::7 62140 # Per bank write bursts 104system.physmem.perBankRdBursts::8 50595 # Per bank write bursts 105system.physmem.perBankRdBursts::9 107916 # Per bank write bursts 106system.physmem.perBankRdBursts::10 54809 # Per bank write bursts 107system.physmem.perBankRdBursts::11 63010 # Per bank write bursts 108system.physmem.perBankRdBursts::12 57730 # Per bank write bursts 109system.physmem.perBankRdBursts::13 64314 # Per bank write bursts 110system.physmem.perBankRdBursts::14 61474 # Per bank write bursts 111system.physmem.perBankRdBursts::15 63033 # Per bank write bursts 112system.physmem.perBankWrBursts::0 75175 # Per bank write bursts 113system.physmem.perBankWrBursts::1 80913 # Per bank write bursts 114system.physmem.perBankWrBursts::2 75568 # Per bank write bursts 115system.physmem.perBankWrBursts::3 82272 # Per bank write bursts 116system.physmem.perBankWrBursts::4 75546 # Per bank write bursts 117system.physmem.perBankWrBursts::5 83102 # Per bank write bursts 118system.physmem.perBankWrBursts::6 75765 # Per bank write bursts 119system.physmem.perBankWrBursts::7 76740 # Per bank write bursts 120system.physmem.perBankWrBursts::8 69114 # Per bank write bursts 121system.physmem.perBankWrBursts::9 73138 # Per bank write bursts 122system.physmem.perBankWrBursts::10 71733 # Per bank write bursts 123system.physmem.perBankWrBursts::11 77960 # Per bank write bursts 124system.physmem.perBankWrBursts::12 74616 # Per bank write bursts 125system.physmem.perBankWrBursts::13 78881 # Per bank write bursts 126system.physmem.perBankWrBursts::14 78631 # Per bank write bursts 127system.physmem.perBankWrBursts::15 79599 # Per bank write bursts 128system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 129system.physmem.numWrRetry 48 # Number of times write queue was full causing retry 130system.physmem.totGap 47445487151500 # Total gap between requests 131system.physmem.readPktSize::0 0 # Read request sizes (log2) 132system.physmem.readPktSize::1 0 # Read request sizes (log2) 133system.physmem.readPktSize::2 0 # Read request sizes (log2) 134system.physmem.readPktSize::3 25 # Read request sizes (log2) 135system.physmem.readPktSize::4 5 # Read request sizes (log2) 136system.physmem.readPktSize::5 0 # Read request sizes (log2) 137system.physmem.readPktSize::6 1035606 # Read request sizes (log2) 138system.physmem.writePktSize::0 0 # Write request sizes (log2) 139system.physmem.writePktSize::1 0 # Write request sizes (log2) 140system.physmem.writePktSize::2 2 # Write request sizes (log2) 141system.physmem.writePktSize::3 2572 # Write request sizes (log2) 142system.physmem.writePktSize::4 0 # Write request sizes (log2) 143system.physmem.writePktSize::5 0 # Write request sizes (log2) 144system.physmem.writePktSize::6 1228466 # Write request sizes (log2) 145system.physmem.rdQLenPdf::0 692790 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::1 121307 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::2 45775 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::3 35632 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::4 30940 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::5 28399 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::6 26620 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::7 23199 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::8 20889 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::9 3694 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::10 1663 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::11 1197 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::12 944 # What read queue length does an incoming req see 158system.physmem.rdQLenPdf::13 702 # What read queue length does an incoming req see 159system.physmem.rdQLenPdf::14 419 # What read queue length does an incoming req see 160system.physmem.rdQLenPdf::15 350 # What read queue length does an incoming req see 161system.physmem.rdQLenPdf::16 273 # What read queue length does an incoming req see 162system.physmem.rdQLenPdf::17 228 # What read queue length does an incoming req see 163system.physmem.rdQLenPdf::18 102 # What read queue length does an incoming req see 164system.physmem.rdQLenPdf::19 60 # What read queue length does an incoming req see 165system.physmem.rdQLenPdf::20 6 # What read queue length does an incoming req see 166system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see 167system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 168system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 169system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 170system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 171system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 172system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 173system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 174system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 175system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 176system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 177system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::15 27376 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::16 35697 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::17 51705 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::18 59824 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::19 65779 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::20 68512 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::21 70877 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::22 72860 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::23 75714 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::24 75511 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::25 79365 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::26 82384 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::27 78677 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::28 77306 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::29 82372 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::30 73265 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::31 67472 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::32 64363 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::33 3236 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::34 2482 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::35 1926 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::36 1455 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::37 1166 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::38 922 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::39 878 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::40 663 # What write queue length does an incoming req see 218system.physmem.wrQLenPdf::41 558 # What write queue length does an incoming req see 219system.physmem.wrQLenPdf::42 539 # What write queue length does an incoming req see 220system.physmem.wrQLenPdf::43 435 # What write queue length does an incoming req see 221system.physmem.wrQLenPdf::44 477 # What write queue length does an incoming req see 222system.physmem.wrQLenPdf::45 423 # What write queue length does an incoming req see 223system.physmem.wrQLenPdf::46 525 # What write queue length does an incoming req see 224system.physmem.wrQLenPdf::47 457 # What write queue length does an incoming req see 225system.physmem.wrQLenPdf::48 414 # What write queue length does an incoming req see 226system.physmem.wrQLenPdf::49 431 # What write queue length does an incoming req see 227system.physmem.wrQLenPdf::50 338 # What write queue length does an incoming req see 228system.physmem.wrQLenPdf::51 283 # What write queue length does an incoming req see 229system.physmem.wrQLenPdf::52 266 # What write queue length does an incoming req see 230system.physmem.wrQLenPdf::53 273 # What write queue length does an incoming req see 231system.physmem.wrQLenPdf::54 259 # What write queue length does an incoming req see 232system.physmem.wrQLenPdf::55 245 # What write queue length does an incoming req see 233system.physmem.wrQLenPdf::56 169 # What write queue length does an incoming req see 234system.physmem.wrQLenPdf::57 155 # What write queue length does an incoming req see 235system.physmem.wrQLenPdf::58 130 # What write queue length does an incoming req see 236system.physmem.wrQLenPdf::59 138 # What write queue length does an incoming req see 237system.physmem.wrQLenPdf::60 111 # What write queue length does an incoming req see 238system.physmem.wrQLenPdf::61 131 # What write queue length does an incoming req see 239system.physmem.wrQLenPdf::62 69 # What write queue length does an incoming req see 240system.physmem.wrQLenPdf::63 144 # What write queue length does an incoming req see 241system.physmem.bytesPerActivate::samples 1012110 # Bytes accessed per row activation 242system.physmem.bytesPerActivate::mean 143.157878 # Bytes accessed per row activation 243system.physmem.bytesPerActivate::gmean 97.072288 # Bytes accessed per row activation 244system.physmem.bytesPerActivate::stdev 192.644368 # Bytes accessed per row activation 245system.physmem.bytesPerActivate::0-127 686114 67.79% 67.79% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::128-255 195882 19.35% 87.14% # Bytes accessed per row activation 247system.physmem.bytesPerActivate::256-383 47037 4.65% 91.79% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::384-511 20980 2.07% 93.86% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::512-639 15295 1.51% 95.38% # Bytes accessed per row activation 250system.physmem.bytesPerActivate::640-767 9865 0.97% 96.35% # Bytes accessed per row activation 251system.physmem.bytesPerActivate::768-895 6724 0.66% 97.01% # Bytes accessed per row activation 252system.physmem.bytesPerActivate::896-1023 5499 0.54% 97.56% # Bytes accessed per row activation 253system.physmem.bytesPerActivate::1024-1151 24714 2.44% 100.00% # Bytes accessed per row activation 254system.physmem.bytesPerActivate::total 1012110 # Bytes accessed per row activation 255system.physmem.rdPerTurnAround::samples 60277 # Reads before turning the bus around for writes 256system.physmem.rdPerTurnAround::mean 17.173764 # Reads before turning the bus around for writes 257system.physmem.rdPerTurnAround::stdev 160.670576 # Reads before turning the bus around for writes 258system.physmem.rdPerTurnAround::0-1023 60274 100.00% 100.00% # Reads before turning the bus around for writes 259system.physmem.rdPerTurnAround::1024-2047 1 0.00% 100.00% # Reads before turning the bus around for writes 260system.physmem.rdPerTurnAround::25600-26623 1 0.00% 100.00% # Reads before turning the bus around for writes 261system.physmem.rdPerTurnAround::29696-30719 1 0.00% 100.00% # Reads before turning the bus around for writes 262system.physmem.rdPerTurnAround::total 60277 # Reads before turning the bus around for writes 263system.physmem.wrPerTurnAround::samples 60277 # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::mean 20.385105 # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::gmean 18.691366 # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::stdev 13.394945 # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::16-19 52026 86.31% 86.31% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::20-23 2335 3.87% 90.19% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::24-27 778 1.29% 91.48% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::28-31 614 1.02% 92.49% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::32-35 994 1.65% 94.14% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::36-39 490 0.81% 94.96% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::40-43 334 0.55% 95.51% # Writes before turning the bus around for reads 274system.physmem.wrPerTurnAround::44-47 282 0.47% 95.98% # Writes before turning the bus around for reads 275system.physmem.wrPerTurnAround::48-51 206 0.34% 96.32% # Writes before turning the bus around for reads 276system.physmem.wrPerTurnAround::52-55 170 0.28% 96.60% # Writes before turning the bus around for reads 277system.physmem.wrPerTurnAround::56-59 135 0.22% 96.83% # Writes before turning the bus around for reads 278system.physmem.wrPerTurnAround::60-63 158 0.26% 97.09% # Writes before turning the bus around for reads 279system.physmem.wrPerTurnAround::64-67 477 0.79% 97.88% # Writes before turning the bus around for reads 280system.physmem.wrPerTurnAround::68-71 137 0.23% 98.11% # Writes before turning the bus around for reads 281system.physmem.wrPerTurnAround::72-75 123 0.20% 98.31% # Writes before turning the bus around for reads 282system.physmem.wrPerTurnAround::76-79 110 0.18% 98.49% # Writes before turning the bus around for reads 283system.physmem.wrPerTurnAround::80-83 87 0.14% 98.64% # Writes before turning the bus around for reads 284system.physmem.wrPerTurnAround::84-87 84 0.14% 98.78% # Writes before turning the bus around for reads 285system.physmem.wrPerTurnAround::88-91 91 0.15% 98.93% # Writes before turning the bus around for reads 286system.physmem.wrPerTurnAround::92-95 102 0.17% 99.10% # Writes before turning the bus around for reads 287system.physmem.wrPerTurnAround::96-99 72 0.12% 99.22% # Writes before turning the bus around for reads 288system.physmem.wrPerTurnAround::100-103 71 0.12% 99.33% # Writes before turning the bus around for reads 289system.physmem.wrPerTurnAround::104-107 64 0.11% 99.44% # Writes before turning the bus around for reads 290system.physmem.wrPerTurnAround::108-111 59 0.10% 99.54% # Writes before turning the bus around for reads 291system.physmem.wrPerTurnAround::112-115 43 0.07% 99.61% # Writes before turning the bus around for reads 292system.physmem.wrPerTurnAround::116-119 45 0.07% 99.68% # Writes before turning the bus around for reads 293system.physmem.wrPerTurnAround::120-123 41 0.07% 99.75% # Writes before turning the bus around for reads 294system.physmem.wrPerTurnAround::124-127 40 0.07% 99.82% # Writes before turning the bus around for reads 295system.physmem.wrPerTurnAround::128-131 47 0.08% 99.90% # Writes before turning the bus around for reads 296system.physmem.wrPerTurnAround::132-135 20 0.03% 99.93% # Writes before turning the bus around for reads 297system.physmem.wrPerTurnAround::136-139 11 0.02% 99.95% # Writes before turning the bus around for reads 298system.physmem.wrPerTurnAround::140-143 5 0.01% 99.96% # Writes before turning the bus around for reads 299system.physmem.wrPerTurnAround::144-147 4 0.01% 99.96% # Writes before turning the bus around for reads 300system.physmem.wrPerTurnAround::148-151 1 0.00% 99.97% # Writes before turning the bus around for reads 301system.physmem.wrPerTurnAround::152-155 2 0.00% 99.97% # Writes before turning the bus around for reads 302system.physmem.wrPerTurnAround::156-159 4 0.01% 99.98% # Writes before turning the bus around for reads 303system.physmem.wrPerTurnAround::160-163 8 0.01% 99.99% # Writes before turning the bus around for reads 304system.physmem.wrPerTurnAround::168-171 1 0.00% 99.99% # Writes before turning the bus around for reads 305system.physmem.wrPerTurnAround::172-175 4 0.01% 100.00% # Writes before turning the bus around for reads 306system.physmem.wrPerTurnAround::180-183 1 0.00% 100.00% # Writes before turning the bus around for reads 307system.physmem.wrPerTurnAround::184-187 1 0.00% 100.00% # Writes before turning the bus around for reads 308system.physmem.wrPerTurnAround::total 60277 # Writes before turning the bus around for reads 309system.physmem.totQLat 35377622933 # Total ticks spent queuing 310system.physmem.totMemAccLat 54787435433 # Total ticks spent from burst creation until serviced by the DRAM 311system.physmem.totBusLat 5175950000 # Total ticks spent in databus transfers 312system.physmem.avgQLat 34175.00 # Average queueing delay per DRAM burst 313system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 314system.physmem.avgMemAccLat 52925.00 # Average memory access latency per DRAM burst 315system.physmem.avgRdBW 1.40 # Average DRAM read bandwidth in MiByte/s 316system.physmem.avgWrBW 1.66 # Average achieved write bandwidth in MiByte/s 317system.physmem.avgRdBWSys 1.40 # Average system read bandwidth in MiByte/s 318system.physmem.avgWrBWSys 1.66 # Average system write bandwidth in MiByte/s 319system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 320system.physmem.busUtil 0.02 # Data bus utilization in percentage 321system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads 322system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes 323system.physmem.avgRdQLen 1.15 # Average read queue length when enqueuing 324system.physmem.avgWrQLen 27.61 # Average write queue length when enqueuing 325system.physmem.readRowHits 780044 # Number of row buffer hits during reads 326system.physmem.writeRowHits 471783 # Number of row buffer hits during writes 327system.physmem.readRowHitRate 75.35 # Row buffer hit rate for reads 328system.physmem.writeRowHitRate 38.39 # Row buffer hit rate for writes 329system.physmem.avgGap 20931746.38 # Average gap between requests 330system.physmem.pageHitRate 55.29 # Row buffer hit rate, read and write combined 331system.physmem_0.actEnergy 3937837680 # Energy for activate commands per rank (pJ) 332system.physmem_0.preEnergy 2148621750 # Energy for precharge commands per rank (pJ) 333system.physmem_0.readEnergy 3995955600 # Energy for read commands per rank (pJ) 334system.physmem_0.writeEnergy 4050479520 # Energy for write commands per rank (pJ) 335system.physmem_0.refreshEnergy 3098908325760 # Energy for refresh commands per rank (pJ) 336system.physmem_0.actBackEnergy 1191842451045 # Energy for active background per rank (pJ) 337system.physmem_0.preBackEnergy 27421814259750 # Energy for precharge background per rank (pJ) 338system.physmem_0.totalEnergy 31726697931105 # Total energy per rank (pJ) 339system.physmem_0.averagePower 668.697958 # Core power per rank (mW) 340system.physmem_0.memoryStateTime::IDLE 45618359398995 # Time in different power states 341system.physmem_0.memoryStateTime::REF 1584308960000 # Time in different power states 342system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 343system.physmem_0.memoryStateTime::ACT 242820245005 # Time in different power states 344system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 345system.physmem_1.actEnergy 3713615640 # Energy for activate commands per rank (pJ) 346system.physmem_1.preEnergy 2026278375 # Energy for precharge commands per rank (pJ) 347system.physmem_1.readEnergy 4078440600 # Energy for read commands per rank (pJ) 348system.physmem_1.writeEnergy 3911723280 # Energy for write commands per rank (pJ) 349system.physmem_1.refreshEnergy 3098908325760 # Energy for refresh commands per rank (pJ) 350system.physmem_1.actBackEnergy 1186342158240 # Energy for active background per rank (pJ) 351system.physmem_1.preBackEnergy 27426639078000 # Energy for precharge background per rank (pJ) 352system.physmem_1.totalEnergy 31725619619895 # Total energy per rank (pJ) 353system.physmem_1.averagePower 668.675231 # Core power per rank (mW) 354system.physmem_1.memoryStateTime::IDLE 45626361005854 # Time in different power states 355system.physmem_1.memoryStateTime::REF 1584308960000 # Time in different power states 356system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 357system.physmem_1.memoryStateTime::ACT 234814164146 # Time in different power states 358system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 359system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states 360system.realview.nvmem.bytes_read::cpu0.inst 704 # Number of bytes read from this memory 361system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory 362system.realview.nvmem.bytes_read::cpu1.inst 640 # Number of bytes read from this memory 363system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory 364system.realview.nvmem.bytes_read::total 1388 # Number of bytes read from this memory 365system.realview.nvmem.bytes_inst_read::cpu0.inst 704 # Number of instructions bytes read from this memory 366system.realview.nvmem.bytes_inst_read::cpu1.inst 640 # Number of instructions bytes read from this memory 367system.realview.nvmem.bytes_inst_read::total 1344 # Number of instructions bytes read from this memory 368system.realview.nvmem.num_reads::cpu0.inst 11 # Number of read requests responded to by this memory 369system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory 370system.realview.nvmem.num_reads::cpu1.inst 10 # Number of read requests responded to by this memory 371system.realview.nvmem.num_reads::cpu1.data 1 # Number of read requests responded to by this memory 372system.realview.nvmem.num_reads::total 27 # Number of read requests responded to by this memory 373system.realview.nvmem.bw_read::cpu0.inst 15 # Total read bandwidth from this memory (bytes/s) 374system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s) 375system.realview.nvmem.bw_read::cpu1.inst 13 # Total read bandwidth from this memory (bytes/s) 376system.realview.nvmem.bw_read::cpu1.data 0 # Total read bandwidth from this memory (bytes/s) 377system.realview.nvmem.bw_read::total 29 # Total read bandwidth from this memory (bytes/s) 378system.realview.nvmem.bw_inst_read::cpu0.inst 15 # Instruction read bandwidth from this memory (bytes/s) 379system.realview.nvmem.bw_inst_read::cpu1.inst 13 # Instruction read bandwidth from this memory (bytes/s) 380system.realview.nvmem.bw_inst_read::total 28 # Instruction read bandwidth from this memory (bytes/s) 381system.realview.nvmem.bw_total::cpu0.inst 15 # Total bandwidth to/from this memory (bytes/s) 382system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s) 383system.realview.nvmem.bw_total::cpu1.inst 13 # Total bandwidth to/from this memory (bytes/s) 384system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) 385system.realview.nvmem.bw_total::total 29 # Total bandwidth to/from this memory (bytes/s) 386system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states 387system.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states 388system.bridge.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states 389system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 390system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 391system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 392system.cf0.dma_write_full_pages 1671 # Number of full page size DMA writes. 393system.cf0.dma_write_bytes 6846976 # Number of bytes transfered via DMA writes. 394system.cf0.dma_write_txs 1674 # Number of DMA write transactions. 395system.cpu0.branchPred.lookups 160314756 # Number of BP lookups 396system.cpu0.branchPred.condPredicted 112651620 # Number of conditional branches predicted 397system.cpu0.branchPred.condIncorrect 7238532 # Number of conditional branches incorrect 398system.cpu0.branchPred.BTBLookups 119384108 # Number of BTB lookups 399system.cpu0.branchPred.BTBHits 83018284 # Number of BTB hits 400system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 401system.cpu0.branchPred.BTBHitPct 69.538807 # BTB Hit Percentage 402system.cpu0.branchPred.usedRAS 19042266 # Number of times the RAS was used to get a target. 403system.cpu0.branchPred.RASInCorrect 1248322 # Number of incorrect RAS predictions. 404system.cpu0.branchPred.indirectLookups 4272460 # Number of indirect predictor lookups. 405system.cpu0.branchPred.indirectHits 2939923 # Number of indirect target hits. 406system.cpu0.branchPred.indirectMisses 1332537 # Number of indirect misses. 407system.cpu0.branchPredindirectMispredicted 468796 # Number of mispredicted indirect branches. 408system.cpu_clk_domain.clock 500 # Clock period in ticks 409system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states 410system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 411system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 412system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 413system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 414system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 415system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 416system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 417system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 418system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 419system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 420system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 421system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 422system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 423system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 424system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 425system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 426system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 427system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 428system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 429system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 430system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 431system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 432system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 433system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 434system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 435system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 436system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 437system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 438system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 439system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states 440system.cpu0.dtb.walker.walks 329365 # Table walker walks requested 441system.cpu0.dtb.walker.walksLong 329365 # Table walker walks initiated with long descriptors 442system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 11619 # Level at which table walker walks with long descriptors terminate 443system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 95372 # Level at which table walker walks with long descriptors terminate 444system.cpu0.dtb.walker.walkWaitTime::samples 329365 # Table walker wait (enqueue to first request) latency 445system.cpu0.dtb.walker.walkWaitTime::0 329365 100.00% 100.00% # Table walker wait (enqueue to first request) latency 446system.cpu0.dtb.walker.walkWaitTime::total 329365 # Table walker wait (enqueue to first request) latency 447system.cpu0.dtb.walker.walkCompletionTime::samples 106991 # Table walker service (enqueue to completion) latency 448system.cpu0.dtb.walker.walkCompletionTime::mean 23090.091690 # Table walker service (enqueue to completion) latency 449system.cpu0.dtb.walker.walkCompletionTime::gmean 21491.120734 # Table walker service (enqueue to completion) latency 450system.cpu0.dtb.walker.walkCompletionTime::stdev 15706.739319 # Table walker service (enqueue to completion) latency 451system.cpu0.dtb.walker.walkCompletionTime::0-65535 105441 98.55% 98.55% # Table walker service (enqueue to completion) latency 452system.cpu0.dtb.walker.walkCompletionTime::65536-131071 1327 1.24% 99.79% # Table walker service (enqueue to completion) latency 453system.cpu0.dtb.walker.walkCompletionTime::131072-196607 42 0.04% 99.83% # Table walker service (enqueue to completion) latency 454system.cpu0.dtb.walker.walkCompletionTime::196608-262143 76 0.07% 99.90% # Table walker service (enqueue to completion) latency 455system.cpu0.dtb.walker.walkCompletionTime::262144-327679 69 0.06% 99.97% # Table walker service (enqueue to completion) latency 456system.cpu0.dtb.walker.walkCompletionTime::327680-393215 15 0.01% 99.98% # Table walker service (enqueue to completion) latency 457system.cpu0.dtb.walker.walkCompletionTime::393216-458751 14 0.01% 99.99% # Table walker service (enqueue to completion) latency 458system.cpu0.dtb.walker.walkCompletionTime::458752-524287 6 0.01% 100.00% # Table walker service (enqueue to completion) latency 459system.cpu0.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 460system.cpu0.dtb.walker.walkCompletionTime::total 106991 # Table walker service (enqueue to completion) latency 461system.cpu0.dtb.walker.walksPending::samples 734573704 # Table walker pending requests distribution 462system.cpu0.dtb.walker.walksPending::0 734573704 100.00% 100.00% # Table walker pending requests distribution 463system.cpu0.dtb.walker.walksPending::total 734573704 # Table walker pending requests distribution 464system.cpu0.dtb.walker.walkPageSizes::4K 95372 89.14% 89.14% # Table walker page sizes translated 465system.cpu0.dtb.walker.walkPageSizes::2M 11619 10.86% 100.00% # Table walker page sizes translated 466system.cpu0.dtb.walker.walkPageSizes::total 106991 # Table walker page sizes translated 467system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 329365 # Table walker requests started/completed, data/inst 468system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 469system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 329365 # Table walker requests started/completed, data/inst 470system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 106991 # Table walker requests started/completed, data/inst 471system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 472system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 106991 # Table walker requests started/completed, data/inst 473system.cpu0.dtb.walker.walkRequestOrigin::total 436356 # Table walker requests started/completed, data/inst 474system.cpu0.dtb.inst_hits 0 # ITB inst hits 475system.cpu0.dtb.inst_misses 0 # ITB inst misses 476system.cpu0.dtb.read_hits 103710651 # DTB read hits 477system.cpu0.dtb.read_misses 276993 # DTB read misses 478system.cpu0.dtb.write_hits 90811723 # DTB write hits 479system.cpu0.dtb.write_misses 52372 # DTB write misses 480system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed 481system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 482system.cpu0.dtb.flush_tlb_mva_asid 43240 # Number of times TLB was flushed by MVA & ASID 483system.cpu0.dtb.flush_tlb_asid 1075 # Number of times TLB was flushed by ASID 484system.cpu0.dtb.flush_entries 42132 # Number of entries that have been flushed from TLB 485system.cpu0.dtb.align_faults 2205 # Number of TLB faults due to alignment restrictions 486system.cpu0.dtb.prefetch_faults 11314 # Number of TLB faults due to prefetch 487system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 488system.cpu0.dtb.perms_faults 11590 # Number of TLB faults due to permissions restrictions 489system.cpu0.dtb.read_accesses 103987644 # DTB read accesses 490system.cpu0.dtb.write_accesses 90864095 # DTB write accesses 491system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 492system.cpu0.dtb.hits 194522374 # DTB hits 493system.cpu0.dtb.misses 329365 # DTB misses 494system.cpu0.dtb.accesses 194851739 # DTB accesses 495system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states 496system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 497system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 498system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 499system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 500system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 501system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 502system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 503system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 504system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 505system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 506system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 507system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 508system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 509system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 510system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 511system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 512system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 513system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 514system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 515system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 516system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 517system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 518system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 519system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 520system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 521system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 522system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 523system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 524system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 525system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states 526system.cpu0.itb.walker.walks 72209 # Table walker walks requested 527system.cpu0.itb.walker.walksLong 72209 # Table walker walks initiated with long descriptors 528system.cpu0.itb.walker.walksLongTerminationLevel::Level2 611 # Level at which table walker walks with long descriptors terminate 529system.cpu0.itb.walker.walksLongTerminationLevel::Level3 59557 # Level at which table walker walks with long descriptors terminate 530system.cpu0.itb.walker.walkWaitTime::samples 72209 # Table walker wait (enqueue to first request) latency 531system.cpu0.itb.walker.walkWaitTime::0 72209 100.00% 100.00% # Table walker wait (enqueue to first request) latency 532system.cpu0.itb.walker.walkWaitTime::total 72209 # Table walker wait (enqueue to first request) latency 533system.cpu0.itb.walker.walkCompletionTime::samples 60168 # Table walker service (enqueue to completion) latency 534system.cpu0.itb.walker.walkCompletionTime::mean 25971.338585 # Table walker service (enqueue to completion) latency 535system.cpu0.itb.walker.walkCompletionTime::gmean 23756.230706 # Table walker service (enqueue to completion) latency 536system.cpu0.itb.walker.walkCompletionTime::stdev 17963.019846 # Table walker service (enqueue to completion) latency 537system.cpu0.itb.walker.walkCompletionTime::0-32767 55134 91.63% 91.63% # Table walker service (enqueue to completion) latency 538system.cpu0.itb.walker.walkCompletionTime::32768-65535 3439 5.72% 97.35% # Table walker service (enqueue to completion) latency 539system.cpu0.itb.walker.walkCompletionTime::65536-98303 6 0.01% 97.36% # Table walker service (enqueue to completion) latency 540system.cpu0.itb.walker.walkCompletionTime::98304-131071 1442 2.40% 99.76% # Table walker service (enqueue to completion) latency 541system.cpu0.itb.walker.walkCompletionTime::131072-163839 23 0.04% 99.79% # Table walker service (enqueue to completion) latency 542system.cpu0.itb.walker.walkCompletionTime::163840-196607 16 0.03% 99.82% # Table walker service (enqueue to completion) latency 543system.cpu0.itb.walker.walkCompletionTime::196608-229375 52 0.09% 99.91% # Table walker service (enqueue to completion) latency 544system.cpu0.itb.walker.walkCompletionTime::229376-262143 23 0.04% 99.95% # Table walker service (enqueue to completion) latency 545system.cpu0.itb.walker.walkCompletionTime::262144-294911 9 0.01% 99.96% # Table walker service (enqueue to completion) latency 546system.cpu0.itb.walker.walkCompletionTime::294912-327679 12 0.02% 99.98% # Table walker service (enqueue to completion) latency 547system.cpu0.itb.walker.walkCompletionTime::327680-360447 6 0.01% 99.99% # Table walker service (enqueue to completion) latency 548system.cpu0.itb.walker.walkCompletionTime::360448-393215 4 0.01% 100.00% # Table walker service (enqueue to completion) latency 549system.cpu0.itb.walker.walkCompletionTime::458752-491519 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 550system.cpu0.itb.walker.walkCompletionTime::total 60168 # Table walker service (enqueue to completion) latency 551system.cpu0.itb.walker.walksPending::samples 733851204 # Table walker pending requests distribution 552system.cpu0.itb.walker.walksPending::0 733851204 100.00% 100.00% # Table walker pending requests distribution 553system.cpu0.itb.walker.walksPending::total 733851204 # Table walker pending requests distribution 554system.cpu0.itb.walker.walkPageSizes::4K 59557 98.98% 98.98% # Table walker page sizes translated 555system.cpu0.itb.walker.walkPageSizes::2M 611 1.02% 100.00% # Table walker page sizes translated 556system.cpu0.itb.walker.walkPageSizes::total 60168 # Table walker page sizes translated 557system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 558system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 72209 # Table walker requests started/completed, data/inst 559system.cpu0.itb.walker.walkRequestOrigin_Requested::total 72209 # Table walker requests started/completed, data/inst 560system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 561system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 60168 # Table walker requests started/completed, data/inst 562system.cpu0.itb.walker.walkRequestOrigin_Completed::total 60168 # Table walker requests started/completed, data/inst 563system.cpu0.itb.walker.walkRequestOrigin::total 132377 # Table walker requests started/completed, data/inst 564system.cpu0.itb.inst_hits 285203366 # ITB inst hits 565system.cpu0.itb.inst_misses 72209 # ITB inst misses 566system.cpu0.itb.read_hits 0 # DTB read hits 567system.cpu0.itb.read_misses 0 # DTB read misses 568system.cpu0.itb.write_hits 0 # DTB write hits 569system.cpu0.itb.write_misses 0 # DTB write misses 570system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed 571system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 572system.cpu0.itb.flush_tlb_mva_asid 43240 # Number of times TLB was flushed by MVA & ASID 573system.cpu0.itb.flush_tlb_asid 1075 # Number of times TLB was flushed by ASID 574system.cpu0.itb.flush_entries 30424 # Number of entries that have been flushed from TLB 575system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 576system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 577system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 578system.cpu0.itb.perms_faults 190431 # Number of TLB faults due to permissions restrictions 579system.cpu0.itb.read_accesses 0 # DTB read accesses 580system.cpu0.itb.write_accesses 0 # DTB write accesses 581system.cpu0.itb.inst_accesses 285275575 # ITB inst accesses 582system.cpu0.itb.hits 285203366 # DTB hits 583system.cpu0.itb.misses 72209 # DTB misses 584system.cpu0.itb.accesses 285275575 # DTB accesses 585system.cpu0.numPwrStateTransitions 26302 # Number of power state transitions 586system.cpu0.pwrStateClkGateDist::samples 13151 # Distribution of time spent in the clock gated state 587system.cpu0.pwrStateClkGateDist::mean 3564690271.200593 # Distribution of time spent in the clock gated state 588system.cpu0.pwrStateClkGateDist::stdev 65409151988.663887 # Distribution of time spent in the clock gated state 589system.cpu0.pwrStateClkGateDist::underflows 3759 28.58% 28.58% # Distribution of time spent in the clock gated state 590system.cpu0.pwrStateClkGateDist::1000-5e+10 9361 71.18% 99.76% # Distribution of time spent in the clock gated state 591system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 1 0.01% 99.77% # Distribution of time spent in the clock gated state 592system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.01% 99.78% # Distribution of time spent in the clock gated state 593system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11 4 0.03% 99.81% # Distribution of time spent in the clock gated state 594system.cpu0.pwrStateClkGateDist::2.5e+11-3e+11 1 0.01% 99.82% # Distribution of time spent in the clock gated state 595system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 1 0.01% 99.83% # Distribution of time spent in the clock gated state 596system.cpu0.pwrStateClkGateDist::5e+11-5.5e+11 2 0.02% 99.84% # Distribution of time spent in the clock gated state 597system.cpu0.pwrStateClkGateDist::6e+11-6.5e+11 1 0.01% 99.85% # Distribution of time spent in the clock gated state 598system.cpu0.pwrStateClkGateDist::7e+11-7.5e+11 1 0.01% 99.86% # Distribution of time spent in the clock gated state 599system.cpu0.pwrStateClkGateDist::8.5e+11-9e+11 1 0.01% 99.86% # Distribution of time spent in the clock gated state 600system.cpu0.pwrStateClkGateDist::overflows 18 0.14% 100.00% # Distribution of time spent in the clock gated state 601system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state 602system.cpu0.pwrStateClkGateDist::max_value 1988779311380 # Distribution of time spent in the clock gated state 603system.cpu0.pwrStateClkGateDist::total 13151 # Distribution of time spent in the clock gated state 604system.cpu0.pwrStateResidencyTicks::ON 566247484441 # Cumulative time (in ticks) in various power states 605system.cpu0.pwrStateResidencyTicks::CLK_GATED 46879241756559 # Cumulative time (in ticks) in various power states 606system.cpu0.numCycles 1132534446 # number of cpu cycles simulated 607system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 608system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 609system.cpu0.committedInsts 532076805 # Number of instructions committed 610system.cpu0.committedOps 624758290 # Number of ops (including micro ops) committed 611system.cpu0.discardedOps 52154793 # Number of ops (including micro ops) which were discarded before commit 612system.cpu0.numFetchSuspends 4664 # Number of times Execute suspended instruction fetching 613system.cpu0.quiesceCycles 93759282538 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 614system.cpu0.cpi 2.128517 # CPI: cycles per instruction 615system.cpu0.ipc 0.469811 # IPC: instructions per cycle 616system.cpu0.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 617system.cpu0.op_class_0::IntAlu 432780145 69.27% 69.27% # Class of committed instruction 618system.cpu0.op_class_0::IntMult 1412970 0.23% 69.50% # Class of committed instruction 619system.cpu0.op_class_0::IntDiv 69899 0.01% 69.51% # Class of committed instruction 620system.cpu0.op_class_0::FloatAdd 0 0.00% 69.51% # Class of committed instruction 621system.cpu0.op_class_0::FloatCmp 0 0.00% 69.51% # Class of committed instruction 622system.cpu0.op_class_0::FloatCvt 0 0.00% 69.51% # Class of committed instruction 623system.cpu0.op_class_0::FloatMult 0 0.00% 69.51% # Class of committed instruction 624system.cpu0.op_class_0::FloatDiv 0 0.00% 69.51% # Class of committed instruction 625system.cpu0.op_class_0::FloatSqrt 0 0.00% 69.51% # Class of committed instruction 626system.cpu0.op_class_0::SimdAdd 0 0.00% 69.51% # Class of committed instruction 627system.cpu0.op_class_0::SimdAddAcc 0 0.00% 69.51% # Class of committed instruction 628system.cpu0.op_class_0::SimdAlu 0 0.00% 69.51% # Class of committed instruction 629system.cpu0.op_class_0::SimdCmp 0 0.00% 69.51% # Class of committed instruction 630system.cpu0.op_class_0::SimdCvt 0 0.00% 69.51% # Class of committed instruction 631system.cpu0.op_class_0::SimdMisc 0 0.00% 69.51% # Class of committed instruction 632system.cpu0.op_class_0::SimdMult 0 0.00% 69.51% # Class of committed instruction 633system.cpu0.op_class_0::SimdMultAcc 0 0.00% 69.51% # Class of committed instruction 634system.cpu0.op_class_0::SimdShift 0 0.00% 69.51% # Class of committed instruction 635system.cpu0.op_class_0::SimdShiftAcc 0 0.00% 69.51% # Class of committed instruction 636system.cpu0.op_class_0::SimdSqrt 0 0.00% 69.51% # Class of committed instruction 637system.cpu0.op_class_0::SimdFloatAdd 0 0.00% 69.51% # Class of committed instruction 638system.cpu0.op_class_0::SimdFloatAlu 0 0.00% 69.51% # Class of committed instruction 639system.cpu0.op_class_0::SimdFloatCmp 0 0.00% 69.51% # Class of committed instruction 640system.cpu0.op_class_0::SimdFloatCvt 0 0.00% 69.51% # Class of committed instruction 641system.cpu0.op_class_0::SimdFloatDiv 0 0.00% 69.51% # Class of committed instruction 642system.cpu0.op_class_0::SimdFloatMisc 79522 0.01% 69.52% # Class of committed instruction 643system.cpu0.op_class_0::SimdFloatMult 0 0.00% 69.52% # Class of committed instruction 644system.cpu0.op_class_0::SimdFloatMultAcc 0 0.00% 69.52% # Class of committed instruction 645system.cpu0.op_class_0::SimdFloatSqrt 0 0.00% 69.52% # Class of committed instruction 646system.cpu0.op_class_0::MemRead 99981749 16.00% 85.52% # Class of committed instruction 647system.cpu0.op_class_0::MemWrite 90434005 14.48% 100.00% # Class of committed instruction 648system.cpu0.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 649system.cpu0.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 650system.cpu0.op_class_0::total 624758290 # Class of committed instruction 651system.cpu0.kern.inst.arm 0 # number of arm instructions executed 652system.cpu0.kern.inst.quiesce 13151 # number of quiesce instructions executed 653system.cpu0.tickCycles 847175236 # Number of cycles that the object actually ticked 654system.cpu0.idleCycles 285359210 # Total number of cycles that the object has spent stopped 655system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states 656system.cpu0.dcache.tags.replacements 6574289 # number of replacements 657system.cpu0.dcache.tags.tagsinuse 508.066535 # Cycle average of tags in use 658system.cpu0.dcache.tags.total_refs 184992173 # Total number of references to valid blocks. 659system.cpu0.dcache.tags.sampled_refs 6574801 # Sample count of references to valid blocks. 660system.cpu0.dcache.tags.avg_refs 28.136543 # Average number of references to valid blocks. 661system.cpu0.dcache.tags.warmup_cycle 5039429000 # Cycle when the warmup percentage was hit. 662system.cpu0.dcache.tags.occ_blocks::cpu0.data 508.066535 # Average occupied blocks per requestor 663system.cpu0.dcache.tags.occ_percent::cpu0.data 0.992317 # Average percentage of cache occupancy 664system.cpu0.dcache.tags.occ_percent::total 0.992317 # Average percentage of cache occupancy 665system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 666system.cpu0.dcache.tags.age_task_id_blocks_1024::0 211 # Occupied blocks per task id 667system.cpu0.dcache.tags.age_task_id_blocks_1024::1 229 # Occupied blocks per task id 668system.cpu0.dcache.tags.age_task_id_blocks_1024::2 72 # Occupied blocks per task id 669system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 670system.cpu0.dcache.tags.tag_accesses 392594755 # Number of tag accesses 671system.cpu0.dcache.tags.data_accesses 392594755 # Number of data accesses 672system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states 673system.cpu0.dcache.ReadReq_hits::cpu0.data 95401287 # number of ReadReq hits 674system.cpu0.dcache.ReadReq_hits::total 95401287 # number of ReadReq hits 675system.cpu0.dcache.WriteReq_hits::cpu0.data 84287466 # number of WriteReq hits 676system.cpu0.dcache.WriteReq_hits::total 84287466 # number of WriteReq hits 677system.cpu0.dcache.SoftPFReq_hits::cpu0.data 321965 # number of SoftPFReq hits 678system.cpu0.dcache.SoftPFReq_hits::total 321965 # number of SoftPFReq hits 679system.cpu0.dcache.WriteLineReq_hits::cpu0.data 280846 # number of WriteLineReq hits 680system.cpu0.dcache.WriteLineReq_hits::total 280846 # number of WriteLineReq hits 681system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 2060188 # number of LoadLockedReq hits 682system.cpu0.dcache.LoadLockedReq_hits::total 2060188 # number of LoadLockedReq hits 683system.cpu0.dcache.StoreCondReq_hits::cpu0.data 2061125 # number of StoreCondReq hits 684system.cpu0.dcache.StoreCondReq_hits::total 2061125 # number of StoreCondReq hits 685system.cpu0.dcache.demand_hits::cpu0.data 179969599 # number of demand (read+write) hits 686system.cpu0.dcache.demand_hits::total 179969599 # number of demand (read+write) hits 687system.cpu0.dcache.overall_hits::cpu0.data 180291564 # number of overall hits 688system.cpu0.dcache.overall_hits::total 180291564 # number of overall hits 689system.cpu0.dcache.ReadReq_misses::cpu0.data 3840217 # number of ReadReq misses 690system.cpu0.dcache.ReadReq_misses::total 3840217 # number of ReadReq misses 691system.cpu0.dcache.WriteReq_misses::cpu0.data 2718306 # number of WriteReq misses 692system.cpu0.dcache.WriteReq_misses::total 2718306 # number of WriteReq misses 693system.cpu0.dcache.SoftPFReq_misses::cpu0.data 733729 # number of SoftPFReq misses 694system.cpu0.dcache.SoftPFReq_misses::total 733729 # number of SoftPFReq misses 695system.cpu0.dcache.WriteLineReq_misses::cpu0.data 858022 # number of WriteLineReq misses 696system.cpu0.dcache.WriteLineReq_misses::total 858022 # number of WriteLineReq misses 697system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 199658 # number of LoadLockedReq misses 698system.cpu0.dcache.LoadLockedReq_misses::total 199658 # number of LoadLockedReq misses 699system.cpu0.dcache.StoreCondReq_misses::cpu0.data 197397 # number of StoreCondReq misses 700system.cpu0.dcache.StoreCondReq_misses::total 197397 # number of StoreCondReq misses 701system.cpu0.dcache.demand_misses::cpu0.data 7416545 # number of demand (read+write) misses 702system.cpu0.dcache.demand_misses::total 7416545 # number of demand (read+write) misses 703system.cpu0.dcache.overall_misses::cpu0.data 8150274 # number of overall misses 704system.cpu0.dcache.overall_misses::total 8150274 # number of overall misses 705system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 59779296000 # number of ReadReq miss cycles 706system.cpu0.dcache.ReadReq_miss_latency::total 59779296000 # number of ReadReq miss cycles 707system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 54754909500 # number of WriteReq miss cycles 708system.cpu0.dcache.WriteReq_miss_latency::total 54754909500 # number of WriteReq miss cycles 709system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 28457275000 # number of WriteLineReq miss cycles 710system.cpu0.dcache.WriteLineReq_miss_latency::total 28457275000 # number of WriteLineReq miss cycles 711system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2995014000 # number of LoadLockedReq miss cycles 712system.cpu0.dcache.LoadLockedReq_miss_latency::total 2995014000 # number of LoadLockedReq miss cycles 713system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4953933500 # number of StoreCondReq miss cycles 714system.cpu0.dcache.StoreCondReq_miss_latency::total 4953933500 # number of StoreCondReq miss cycles 715system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 3818500 # number of StoreCondFailReq miss cycles 716system.cpu0.dcache.StoreCondFailReq_miss_latency::total 3818500 # number of StoreCondFailReq miss cycles 717system.cpu0.dcache.demand_miss_latency::cpu0.data 142991480500 # number of demand (read+write) miss cycles 718system.cpu0.dcache.demand_miss_latency::total 142991480500 # number of demand (read+write) miss cycles 719system.cpu0.dcache.overall_miss_latency::cpu0.data 142991480500 # number of overall miss cycles 720system.cpu0.dcache.overall_miss_latency::total 142991480500 # number of overall miss cycles 721system.cpu0.dcache.ReadReq_accesses::cpu0.data 99241504 # number of ReadReq accesses(hits+misses) 722system.cpu0.dcache.ReadReq_accesses::total 99241504 # number of ReadReq accesses(hits+misses) 723system.cpu0.dcache.WriteReq_accesses::cpu0.data 87005772 # number of WriteReq accesses(hits+misses) 724system.cpu0.dcache.WriteReq_accesses::total 87005772 # number of WriteReq accesses(hits+misses) 725system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 1055694 # number of SoftPFReq accesses(hits+misses) 726system.cpu0.dcache.SoftPFReq_accesses::total 1055694 # number of SoftPFReq accesses(hits+misses) 727system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1138868 # number of WriteLineReq accesses(hits+misses) 728system.cpu0.dcache.WriteLineReq_accesses::total 1138868 # number of WriteLineReq accesses(hits+misses) 729system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2259846 # number of LoadLockedReq accesses(hits+misses) 730system.cpu0.dcache.LoadLockedReq_accesses::total 2259846 # number of LoadLockedReq accesses(hits+misses) 731system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2258522 # number of StoreCondReq accesses(hits+misses) 732system.cpu0.dcache.StoreCondReq_accesses::total 2258522 # number of StoreCondReq accesses(hits+misses) 733system.cpu0.dcache.demand_accesses::cpu0.data 187386144 # number of demand (read+write) accesses 734system.cpu0.dcache.demand_accesses::total 187386144 # number of demand (read+write) accesses 735system.cpu0.dcache.overall_accesses::cpu0.data 188441838 # number of overall (read+write) accesses 736system.cpu0.dcache.overall_accesses::total 188441838 # number of overall (read+write) accesses 737system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.038696 # miss rate for ReadReq accesses 738system.cpu0.dcache.ReadReq_miss_rate::total 0.038696 # miss rate for ReadReq accesses 739system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.031243 # miss rate for WriteReq accesses 740system.cpu0.dcache.WriteReq_miss_rate::total 0.031243 # miss rate for WriteReq accesses 741system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.695021 # miss rate for SoftPFReq accesses 742system.cpu0.dcache.SoftPFReq_miss_rate::total 0.695021 # miss rate for SoftPFReq accesses 743system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.753399 # miss rate for WriteLineReq accesses 744system.cpu0.dcache.WriteLineReq_miss_rate::total 0.753399 # miss rate for WriteLineReq accesses 745system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.088350 # miss rate for LoadLockedReq accesses 746system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.088350 # miss rate for LoadLockedReq accesses 747system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.087401 # miss rate for StoreCondReq accesses 748system.cpu0.dcache.StoreCondReq_miss_rate::total 0.087401 # miss rate for StoreCondReq accesses 749system.cpu0.dcache.demand_miss_rate::cpu0.data 0.039579 # miss rate for demand accesses 750system.cpu0.dcache.demand_miss_rate::total 0.039579 # miss rate for demand accesses 751system.cpu0.dcache.overall_miss_rate::cpu0.data 0.043251 # miss rate for overall accesses 752system.cpu0.dcache.overall_miss_rate::total 0.043251 # miss rate for overall accesses 753system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15566.645322 # average ReadReq miss latency 754system.cpu0.dcache.ReadReq_avg_miss_latency::total 15566.645322 # average ReadReq miss latency 755system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 20143.026392 # average WriteReq miss latency 756system.cpu0.dcache.WriteReq_avg_miss_latency::total 20143.026392 # average WriteReq miss latency 757system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 33166.136766 # average WriteLineReq miss latency 758system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 33166.136766 # average WriteLineReq miss latency 759system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15000.721233 # average LoadLockedReq miss latency 760system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15000.721233 # average LoadLockedReq miss latency 761system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 25096.295790 # average StoreCondReq miss latency 762system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 25096.295790 # average StoreCondReq miss latency 763system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency 764system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 765system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19280.066460 # average overall miss latency 766system.cpu0.dcache.demand_avg_miss_latency::total 19280.066460 # average overall miss latency 767system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 17544.377097 # average overall miss latency 768system.cpu0.dcache.overall_avg_miss_latency::total 17544.377097 # average overall miss latency 769system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 770system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 771system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 772system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 773system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 774system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 775system.cpu0.dcache.writebacks::writebacks 6574291 # number of writebacks 776system.cpu0.dcache.writebacks::total 6574291 # number of writebacks 777system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 237792 # number of ReadReq MSHR hits 778system.cpu0.dcache.ReadReq_mshr_hits::total 237792 # number of ReadReq MSHR hits 779system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1117306 # number of WriteReq MSHR hits 780system.cpu0.dcache.WriteReq_mshr_hits::total 1117306 # number of WriteReq MSHR hits 781system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 90 # number of WriteLineReq MSHR hits 782system.cpu0.dcache.WriteLineReq_mshr_hits::total 90 # number of WriteLineReq MSHR hits 783system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 48445 # number of LoadLockedReq MSHR hits 784system.cpu0.dcache.LoadLockedReq_mshr_hits::total 48445 # number of LoadLockedReq MSHR hits 785system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data 60 # number of StoreCondReq MSHR hits 786system.cpu0.dcache.StoreCondReq_mshr_hits::total 60 # number of StoreCondReq MSHR hits 787system.cpu0.dcache.demand_mshr_hits::cpu0.data 1355188 # number of demand (read+write) MSHR hits 788system.cpu0.dcache.demand_mshr_hits::total 1355188 # number of demand (read+write) MSHR hits 789system.cpu0.dcache.overall_mshr_hits::cpu0.data 1355188 # number of overall MSHR hits 790system.cpu0.dcache.overall_mshr_hits::total 1355188 # number of overall MSHR hits 791system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3602425 # number of ReadReq MSHR misses 792system.cpu0.dcache.ReadReq_mshr_misses::total 3602425 # number of ReadReq MSHR misses 793system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1601000 # number of WriteReq MSHR misses 794system.cpu0.dcache.WriteReq_mshr_misses::total 1601000 # number of WriteReq MSHR misses 795system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 732137 # number of SoftPFReq MSHR misses 796system.cpu0.dcache.SoftPFReq_mshr_misses::total 732137 # number of SoftPFReq MSHR misses 797system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 857932 # number of WriteLineReq MSHR misses 798system.cpu0.dcache.WriteLineReq_mshr_misses::total 857932 # number of WriteLineReq MSHR misses 799system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 151213 # number of LoadLockedReq MSHR misses 800system.cpu0.dcache.LoadLockedReq_mshr_misses::total 151213 # number of LoadLockedReq MSHR misses 801system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 197337 # number of StoreCondReq MSHR misses 802system.cpu0.dcache.StoreCondReq_mshr_misses::total 197337 # number of StoreCondReq MSHR misses 803system.cpu0.dcache.demand_mshr_misses::cpu0.data 6061357 # number of demand (read+write) MSHR misses 804system.cpu0.dcache.demand_mshr_misses::total 6061357 # number of demand (read+write) MSHR misses 805system.cpu0.dcache.overall_mshr_misses::cpu0.data 6793494 # number of overall MSHR misses 806system.cpu0.dcache.overall_mshr_misses::total 6793494 # number of overall MSHR misses 807system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 29793 # number of ReadReq MSHR uncacheable 808system.cpu0.dcache.ReadReq_mshr_uncacheable::total 29793 # number of ReadReq MSHR uncacheable 809system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 29400 # number of WriteReq MSHR uncacheable 810system.cpu0.dcache.WriteReq_mshr_uncacheable::total 29400 # number of WriteReq MSHR uncacheable 811system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 59193 # number of overall MSHR uncacheable misses 812system.cpu0.dcache.overall_mshr_uncacheable_misses::total 59193 # number of overall MSHR uncacheable misses 813system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 50925119500 # number of ReadReq MSHR miss cycles 814system.cpu0.dcache.ReadReq_mshr_miss_latency::total 50925119500 # number of ReadReq MSHR miss cycles 815system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 31536308500 # number of WriteReq MSHR miss cycles 816system.cpu0.dcache.WriteReq_mshr_miss_latency::total 31536308500 # number of WriteReq MSHR miss cycles 817system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 16544300500 # number of SoftPFReq MSHR miss cycles 818system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 16544300500 # number of SoftPFReq MSHR miss cycles 819system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 27594364000 # number of WriteLineReq MSHR miss cycles 820system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 27594364000 # number of WriteLineReq MSHR miss cycles 821system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1964885000 # number of LoadLockedReq MSHR miss cycles 822system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1964885000 # number of LoadLockedReq MSHR miss cycles 823system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4754516500 # number of StoreCondReq MSHR miss cycles 824system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4754516500 # number of StoreCondReq MSHR miss cycles 825system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 3441500 # number of StoreCondFailReq MSHR miss cycles 826system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 3441500 # number of StoreCondFailReq MSHR miss cycles 827system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 110055792000 # number of demand (read+write) MSHR miss cycles 828system.cpu0.dcache.demand_mshr_miss_latency::total 110055792000 # number of demand (read+write) MSHR miss cycles 829system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 126600092500 # number of overall MSHR miss cycles 830system.cpu0.dcache.overall_mshr_miss_latency::total 126600092500 # number of overall MSHR miss cycles 831system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5675765000 # number of ReadReq MSHR uncacheable cycles 832system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5675765000 # number of ReadReq MSHR uncacheable cycles 833system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5675765000 # number of overall MSHR uncacheable cycles 834system.cpu0.dcache.overall_mshr_uncacheable_latency::total 5675765000 # number of overall MSHR uncacheable cycles 835system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036300 # mshr miss rate for ReadReq accesses 836system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036300 # mshr miss rate for ReadReq accesses 837system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018401 # mshr miss rate for WriteReq accesses 838system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018401 # mshr miss rate for WriteReq accesses 839system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.693513 # mshr miss rate for SoftPFReq accesses 840system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.693513 # mshr miss rate for SoftPFReq accesses 841system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.753320 # mshr miss rate for WriteLineReq accesses 842system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.753320 # mshr miss rate for WriteLineReq accesses 843system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.066913 # mshr miss rate for LoadLockedReq accesses 844system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.066913 # mshr miss rate for LoadLockedReq accesses 845system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.087374 # mshr miss rate for StoreCondReq accesses 846system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.087374 # mshr miss rate for StoreCondReq accesses 847system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.032347 # mshr miss rate for demand accesses 848system.cpu0.dcache.demand_mshr_miss_rate::total 0.032347 # mshr miss rate for demand accesses 849system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.036051 # mshr miss rate for overall accesses 850system.cpu0.dcache.overall_mshr_miss_rate::total 0.036051 # mshr miss rate for overall accesses 851system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14136.344129 # average ReadReq mshr miss latency 852system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14136.344129 # average ReadReq mshr miss latency 853system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 19697.881636 # average WriteReq mshr miss latency 854system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 19697.881636 # average WriteReq mshr miss latency 855system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 22597.274144 # average SoftPFReq mshr miss latency 856system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 22597.274144 # average SoftPFReq mshr miss latency 857system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 32163.812517 # average WriteLineReq mshr miss latency 858system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 32163.812517 # average WriteLineReq mshr miss latency 859system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12994.153942 # average LoadLockedReq mshr miss latency 860system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12994.153942 # average LoadLockedReq mshr miss latency 861system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 24093.385934 # average StoreCondReq mshr miss latency 862system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 24093.385934 # average StoreCondReq mshr miss latency 863system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 864system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 865system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18156.955942 # average overall mshr miss latency 866system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18156.955942 # average overall mshr miss latency 867system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 18635.490441 # average overall mshr miss latency 868system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18635.490441 # average overall mshr miss latency 869system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 190506.662639 # average ReadReq mshr uncacheable latency 870system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 190506.662639 # average ReadReq mshr uncacheable latency 871system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 95885.746625 # average overall mshr uncacheable latency 872system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 95885.746625 # average overall mshr uncacheable latency 873system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states 874system.cpu0.icache.tags.replacements 10998491 # number of replacements 875system.cpu0.icache.tags.tagsinuse 511.932591 # Cycle average of tags in use 876system.cpu0.icache.tags.total_refs 274007938 # Total number of references to valid blocks. 877system.cpu0.icache.tags.sampled_refs 10999003 # Sample count of references to valid blocks. 878system.cpu0.icache.tags.avg_refs 24.912070 # Average number of references to valid blocks. 879system.cpu0.icache.tags.warmup_cycle 22037323000 # Cycle when the warmup percentage was hit. 880system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.932591 # Average occupied blocks per requestor 881system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999868 # Average percentage of cache occupancy 882system.cpu0.icache.tags.occ_percent::total 0.999868 # Average percentage of cache occupancy 883system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 884system.cpu0.icache.tags.age_task_id_blocks_1024::0 207 # Occupied blocks per task id 885system.cpu0.icache.tags.age_task_id_blocks_1024::1 273 # Occupied blocks per task id 886system.cpu0.icache.tags.age_task_id_blocks_1024::2 32 # Occupied blocks per task id 887system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 888system.cpu0.icache.tags.tag_accesses 581012885 # Number of tag accesses 889system.cpu0.icache.tags.data_accesses 581012885 # Number of data accesses 890system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states 891system.cpu0.icache.ReadReq_hits::cpu0.inst 274007938 # number of ReadReq hits 892system.cpu0.icache.ReadReq_hits::total 274007938 # number of ReadReq hits 893system.cpu0.icache.demand_hits::cpu0.inst 274007938 # number of demand (read+write) hits 894system.cpu0.icache.demand_hits::total 274007938 # number of demand (read+write) hits 895system.cpu0.icache.overall_hits::cpu0.inst 274007938 # number of overall hits 896system.cpu0.icache.overall_hits::total 274007938 # number of overall hits 897system.cpu0.icache.ReadReq_misses::cpu0.inst 10999003 # number of ReadReq misses 898system.cpu0.icache.ReadReq_misses::total 10999003 # number of ReadReq misses 899system.cpu0.icache.demand_misses::cpu0.inst 10999003 # number of demand (read+write) misses 900system.cpu0.icache.demand_misses::total 10999003 # number of demand (read+write) misses 901system.cpu0.icache.overall_misses::cpu0.inst 10999003 # number of overall misses 902system.cpu0.icache.overall_misses::total 10999003 # number of overall misses 903system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 111429437000 # number of ReadReq miss cycles 904system.cpu0.icache.ReadReq_miss_latency::total 111429437000 # number of ReadReq miss cycles 905system.cpu0.icache.demand_miss_latency::cpu0.inst 111429437000 # number of demand (read+write) miss cycles 906system.cpu0.icache.demand_miss_latency::total 111429437000 # number of demand (read+write) miss cycles 907system.cpu0.icache.overall_miss_latency::cpu0.inst 111429437000 # number of overall miss cycles 908system.cpu0.icache.overall_miss_latency::total 111429437000 # number of overall miss cycles 909system.cpu0.icache.ReadReq_accesses::cpu0.inst 285006941 # number of ReadReq accesses(hits+misses) 910system.cpu0.icache.ReadReq_accesses::total 285006941 # number of ReadReq accesses(hits+misses) 911system.cpu0.icache.demand_accesses::cpu0.inst 285006941 # number of demand (read+write) accesses 912system.cpu0.icache.demand_accesses::total 285006941 # number of demand (read+write) accesses 913system.cpu0.icache.overall_accesses::cpu0.inst 285006941 # number of overall (read+write) accesses 914system.cpu0.icache.overall_accesses::total 285006941 # number of overall (read+write) accesses 915system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.038592 # miss rate for ReadReq accesses 916system.cpu0.icache.ReadReq_miss_rate::total 0.038592 # miss rate for ReadReq accesses 917system.cpu0.icache.demand_miss_rate::cpu0.inst 0.038592 # miss rate for demand accesses 918system.cpu0.icache.demand_miss_rate::total 0.038592 # miss rate for demand accesses 919system.cpu0.icache.overall_miss_rate::cpu0.inst 0.038592 # miss rate for overall accesses 920system.cpu0.icache.overall_miss_rate::total 0.038592 # miss rate for overall accesses 921system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10130.867043 # average ReadReq miss latency 922system.cpu0.icache.ReadReq_avg_miss_latency::total 10130.867043 # average ReadReq miss latency 923system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10130.867043 # average overall miss latency 924system.cpu0.icache.demand_avg_miss_latency::total 10130.867043 # average overall miss latency 925system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10130.867043 # average overall miss latency 926system.cpu0.icache.overall_avg_miss_latency::total 10130.867043 # average overall miss latency 927system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 928system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 929system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 930system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 931system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 932system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 933system.cpu0.icache.writebacks::writebacks 10998491 # number of writebacks 934system.cpu0.icache.writebacks::total 10998491 # number of writebacks 935system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 10999003 # number of ReadReq MSHR misses 936system.cpu0.icache.ReadReq_mshr_misses::total 10999003 # number of ReadReq MSHR misses 937system.cpu0.icache.demand_mshr_misses::cpu0.inst 10999003 # number of demand (read+write) MSHR misses 938system.cpu0.icache.demand_mshr_misses::total 10999003 # number of demand (read+write) MSHR misses 939system.cpu0.icache.overall_mshr_misses::cpu0.inst 10999003 # number of overall MSHR misses 940system.cpu0.icache.overall_mshr_misses::total 10999003 # number of overall MSHR misses 941system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 52300 # number of ReadReq MSHR uncacheable 942system.cpu0.icache.ReadReq_mshr_uncacheable::total 52300 # number of ReadReq MSHR uncacheable 943system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 52300 # number of overall MSHR uncacheable misses 944system.cpu0.icache.overall_mshr_uncacheable_misses::total 52300 # number of overall MSHR uncacheable misses 945system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 105929935500 # number of ReadReq MSHR miss cycles 946system.cpu0.icache.ReadReq_mshr_miss_latency::total 105929935500 # number of ReadReq MSHR miss cycles 947system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 105929935500 # number of demand (read+write) MSHR miss cycles 948system.cpu0.icache.demand_mshr_miss_latency::total 105929935500 # number of demand (read+write) MSHR miss cycles 949system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 105929935500 # number of overall MSHR miss cycles 950system.cpu0.icache.overall_mshr_miss_latency::total 105929935500 # number of overall MSHR miss cycles 951system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 4836784500 # number of ReadReq MSHR uncacheable cycles 952system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 4836784500 # number of ReadReq MSHR uncacheable cycles 953system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 4836784500 # number of overall MSHR uncacheable cycles 954system.cpu0.icache.overall_mshr_uncacheable_latency::total 4836784500 # number of overall MSHR uncacheable cycles 955system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.038592 # mshr miss rate for ReadReq accesses 956system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.038592 # mshr miss rate for ReadReq accesses 957system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.038592 # mshr miss rate for demand accesses 958system.cpu0.icache.demand_mshr_miss_rate::total 0.038592 # mshr miss rate for demand accesses 959system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.038592 # mshr miss rate for overall accesses 960system.cpu0.icache.overall_mshr_miss_rate::total 0.038592 # mshr miss rate for overall accesses 961system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9630.867043 # average ReadReq mshr miss latency 962system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9630.867043 # average ReadReq mshr miss latency 963system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9630.867043 # average overall mshr miss latency 964system.cpu0.icache.demand_avg_mshr_miss_latency::total 9630.867043 # average overall mshr miss latency 965system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9630.867043 # average overall mshr miss latency 966system.cpu0.icache.overall_avg_mshr_miss_latency::total 9630.867043 # average overall mshr miss latency 967system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 92481.539197 # average ReadReq mshr uncacheable latency 968system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 92481.539197 # average ReadReq mshr uncacheable latency 969system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 92481.539197 # average overall mshr uncacheable latency 970system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 92481.539197 # average overall mshr uncacheable latency 971system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states 972system.cpu0.l2cache.prefetcher.num_hwpf_issued 8833822 # number of hwpf issued 973system.cpu0.l2cache.prefetcher.pfIdentified 8835143 # number of prefetch candidates identified 974system.cpu0.l2cache.prefetcher.pfBufferHit 1166 # number of redundant prefetches already in prefetch queue 975system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 976system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 977system.cpu0.l2cache.prefetcher.pfSpanPage 1192777 # number of prefetches not generated due to page crossing 978system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states 979system.cpu0.l2cache.tags.replacements 3147716 # number of replacements 980system.cpu0.l2cache.tags.tagsinuse 16192.217188 # Cycle average of tags in use 981system.cpu0.l2cache.tags.total_refs 27546589 # Total number of references to valid blocks. 982system.cpu0.l2cache.tags.sampled_refs 3163437 # Sample count of references to valid blocks. 983system.cpu0.l2cache.tags.avg_refs 8.707804 # Average number of references to valid blocks. 984system.cpu0.l2cache.tags.warmup_cycle 5661168000 # Cycle when the warmup percentage was hit. 985system.cpu0.l2cache.tags.occ_blocks::writebacks 15379.701531 # Average occupied blocks per requestor 986system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 70.199902 # Average occupied blocks per requestor 987system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 67.449935 # Average occupied blocks per requestor 988system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 674.865820 # Average occupied blocks per requestor 989system.cpu0.l2cache.tags.occ_percent::writebacks 0.938702 # Average percentage of cache occupancy 990system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.004285 # Average percentage of cache occupancy 991system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.004117 # Average percentage of cache occupancy 992system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.041191 # Average percentage of cache occupancy 993system.cpu0.l2cache.tags.occ_percent::total 0.988295 # Average percentage of cache occupancy 994system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1251 # Occupied blocks per task id 995system.cpu0.l2cache.tags.occ_task_id_blocks::1023 80 # Occupied blocks per task id 996system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14390 # Occupied blocks per task id 997system.cpu0.l2cache.tags.age_task_id_blocks_1022::0 7 # Occupied blocks per task id 998system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 16 # Occupied blocks per task id 999system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 214 # Occupied blocks per task id 1000system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 985 # Occupied blocks per task id 1001system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 29 # Occupied blocks per task id 1002system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id 1003system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 13 # Occupied blocks per task id 1004system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 66 # Occupied blocks per task id 1005system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 230 # Occupied blocks per task id 1006system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 603 # Occupied blocks per task id 1007system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4671 # Occupied blocks per task id 1008system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 8629 # Occupied blocks per task id 1009system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 257 # Occupied blocks per task id 1010system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.076355 # Percentage of cache occupancy per task id 1011system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.004883 # Percentage of cache occupancy per task id 1012system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.878296 # Percentage of cache occupancy per task id 1013system.cpu0.l2cache.tags.tag_accesses 591522987 # Number of tag accesses 1014system.cpu0.l2cache.tags.data_accesses 591522987 # Number of data accesses 1015system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states 1016system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 626255 # number of ReadReq hits 1017system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 186723 # number of ReadReq hits 1018system.cpu0.l2cache.ReadReq_hits::total 812978 # number of ReadReq hits 1019system.cpu0.l2cache.WritebackDirty_hits::writebacks 4288810 # number of WritebackDirty hits 1020system.cpu0.l2cache.WritebackDirty_hits::total 4288810 # number of WritebackDirty hits 1021system.cpu0.l2cache.WritebackClean_hits::writebacks 13280453 # number of WritebackClean hits 1022system.cpu0.l2cache.WritebackClean_hits::total 13280453 # number of WritebackClean hits 1023system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 665 # number of UpgradeReq hits 1024system.cpu0.l2cache.UpgradeReq_hits::total 665 # number of UpgradeReq hits 1025system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 1 # number of SCUpgradeReq hits 1026system.cpu0.l2cache.SCUpgradeReq_hits::total 1 # number of SCUpgradeReq hits 1027system.cpu0.l2cache.ReadExReq_hits::cpu0.data 1035920 # number of ReadExReq hits 1028system.cpu0.l2cache.ReadExReq_hits::total 1035920 # number of ReadExReq hits 1029system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 10174002 # number of ReadCleanReq hits 1030system.cpu0.l2cache.ReadCleanReq_hits::total 10174002 # number of ReadCleanReq hits 1031system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 3369103 # number of ReadSharedReq hits 1032system.cpu0.l2cache.ReadSharedReq_hits::total 3369103 # number of ReadSharedReq hits 1033system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 227555 # number of InvalidateReq hits 1034system.cpu0.l2cache.InvalidateReq_hits::total 227555 # number of InvalidateReq hits 1035system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 626255 # number of demand (read+write) hits 1036system.cpu0.l2cache.demand_hits::cpu0.itb.walker 186723 # number of demand (read+write) hits 1037system.cpu0.l2cache.demand_hits::cpu0.inst 10174002 # number of demand (read+write) hits 1038system.cpu0.l2cache.demand_hits::cpu0.data 4405023 # number of demand (read+write) hits 1039system.cpu0.l2cache.demand_hits::total 15392003 # number of demand (read+write) hits 1040system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 626255 # number of overall hits 1041system.cpu0.l2cache.overall_hits::cpu0.itb.walker 186723 # number of overall hits 1042system.cpu0.l2cache.overall_hits::cpu0.inst 10174002 # number of overall hits 1043system.cpu0.l2cache.overall_hits::cpu0.data 4405023 # number of overall hits 1044system.cpu0.l2cache.overall_hits::total 15392003 # number of overall hits 1045system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 13618 # number of ReadReq misses 1046system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 9516 # number of ReadReq misses 1047system.cpu0.l2cache.ReadReq_misses::total 23134 # number of ReadReq misses 1048system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 275991 # number of UpgradeReq misses 1049system.cpu0.l2cache.UpgradeReq_misses::total 275991 # number of UpgradeReq misses 1050system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 197331 # number of SCUpgradeReq misses 1051system.cpu0.l2cache.SCUpgradeReq_misses::total 197331 # number of SCUpgradeReq misses 1052system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 5 # number of SCUpgradeFailReq misses 1053system.cpu0.l2cache.SCUpgradeFailReq_misses::total 5 # number of SCUpgradeFailReq misses 1054system.cpu0.l2cache.ReadExReq_misses::cpu0.data 297475 # number of ReadExReq misses 1055system.cpu0.l2cache.ReadExReq_misses::total 297475 # number of ReadExReq misses 1056system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 825000 # number of ReadCleanReq misses 1057system.cpu0.l2cache.ReadCleanReq_misses::total 825000 # number of ReadCleanReq misses 1058system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 1116183 # number of ReadSharedReq misses 1059system.cpu0.l2cache.ReadSharedReq_misses::total 1116183 # number of ReadSharedReq misses 1060system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 628029 # number of InvalidateReq misses 1061system.cpu0.l2cache.InvalidateReq_misses::total 628029 # number of InvalidateReq misses 1062system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 13618 # number of demand (read+write) misses 1063system.cpu0.l2cache.demand_misses::cpu0.itb.walker 9516 # number of demand (read+write) misses 1064system.cpu0.l2cache.demand_misses::cpu0.inst 825000 # number of demand (read+write) misses 1065system.cpu0.l2cache.demand_misses::cpu0.data 1413658 # number of demand (read+write) misses 1066system.cpu0.l2cache.demand_misses::total 2261792 # number of demand (read+write) misses 1067system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 13618 # number of overall misses 1068system.cpu0.l2cache.overall_misses::cpu0.itb.walker 9516 # number of overall misses 1069system.cpu0.l2cache.overall_misses::cpu0.inst 825000 # number of overall misses 1070system.cpu0.l2cache.overall_misses::cpu0.data 1413658 # number of overall misses 1071system.cpu0.l2cache.overall_misses::total 2261792 # number of overall misses 1072system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 516990000 # number of ReadReq miss cycles 1073system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 406929500 # number of ReadReq miss cycles 1074system.cpu0.l2cache.ReadReq_miss_latency::total 923919500 # number of ReadReq miss cycles 1075system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 2174724500 # number of UpgradeReq miss cycles 1076system.cpu0.l2cache.UpgradeReq_miss_latency::total 2174724500 # number of UpgradeReq miss cycles 1077system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 1540108000 # number of SCUpgradeReq miss cycles 1078system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 1540108000 # number of SCUpgradeReq miss cycles 1079system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 3340999 # number of SCUpgradeFailReq miss cycles 1080system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 3340999 # number of SCUpgradeFailReq miss cycles 1081system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 14927255997 # number of ReadExReq miss cycles 1082system.cpu0.l2cache.ReadExReq_miss_latency::total 14927255997 # number of ReadExReq miss cycles 1083system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 27980842000 # number of ReadCleanReq miss cycles 1084system.cpu0.l2cache.ReadCleanReq_miss_latency::total 27980842000 # number of ReadCleanReq miss cycles 1085system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 40509457995 # number of ReadSharedReq miss cycles 1086system.cpu0.l2cache.ReadSharedReq_miss_latency::total 40509457995 # number of ReadSharedReq miss cycles 1087system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data 326706500 # number of InvalidateReq miss cycles 1088system.cpu0.l2cache.InvalidateReq_miss_latency::total 326706500 # number of InvalidateReq miss cycles 1089system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 516990000 # number of demand (read+write) miss cycles 1090system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 406929500 # number of demand (read+write) miss cycles 1091system.cpu0.l2cache.demand_miss_latency::cpu0.inst 27980842000 # number of demand (read+write) miss cycles 1092system.cpu0.l2cache.demand_miss_latency::cpu0.data 55436713992 # number of demand (read+write) miss cycles 1093system.cpu0.l2cache.demand_miss_latency::total 84341475492 # number of demand (read+write) miss cycles 1094system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 516990000 # number of overall miss cycles 1095system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 406929500 # number of overall miss cycles 1096system.cpu0.l2cache.overall_miss_latency::cpu0.inst 27980842000 # number of overall miss cycles 1097system.cpu0.l2cache.overall_miss_latency::cpu0.data 55436713992 # number of overall miss cycles 1098system.cpu0.l2cache.overall_miss_latency::total 84341475492 # number of overall miss cycles 1099system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 639873 # number of ReadReq accesses(hits+misses) 1100system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 196239 # number of ReadReq accesses(hits+misses) 1101system.cpu0.l2cache.ReadReq_accesses::total 836112 # number of ReadReq accesses(hits+misses) 1102system.cpu0.l2cache.WritebackDirty_accesses::writebacks 4288810 # number of WritebackDirty accesses(hits+misses) 1103system.cpu0.l2cache.WritebackDirty_accesses::total 4288810 # number of WritebackDirty accesses(hits+misses) 1104system.cpu0.l2cache.WritebackClean_accesses::writebacks 13280453 # number of WritebackClean accesses(hits+misses) 1105system.cpu0.l2cache.WritebackClean_accesses::total 13280453 # number of WritebackClean accesses(hits+misses) 1106system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 276656 # number of UpgradeReq accesses(hits+misses) 1107system.cpu0.l2cache.UpgradeReq_accesses::total 276656 # number of UpgradeReq accesses(hits+misses) 1108system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 197332 # number of SCUpgradeReq accesses(hits+misses) 1109system.cpu0.l2cache.SCUpgradeReq_accesses::total 197332 # number of SCUpgradeReq accesses(hits+misses) 1110system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 5 # number of SCUpgradeFailReq accesses(hits+misses) 1111system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 5 # number of SCUpgradeFailReq accesses(hits+misses) 1112system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1333395 # number of ReadExReq accesses(hits+misses) 1113system.cpu0.l2cache.ReadExReq_accesses::total 1333395 # number of ReadExReq accesses(hits+misses) 1114system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 10999002 # number of ReadCleanReq accesses(hits+misses) 1115system.cpu0.l2cache.ReadCleanReq_accesses::total 10999002 # number of ReadCleanReq accesses(hits+misses) 1116system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 4485286 # number of ReadSharedReq accesses(hits+misses) 1117system.cpu0.l2cache.ReadSharedReq_accesses::total 4485286 # number of ReadSharedReq accesses(hits+misses) 1118system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 855584 # number of InvalidateReq accesses(hits+misses) 1119system.cpu0.l2cache.InvalidateReq_accesses::total 855584 # number of InvalidateReq accesses(hits+misses) 1120system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 639873 # number of demand (read+write) accesses 1121system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 196239 # number of demand (read+write) accesses 1122system.cpu0.l2cache.demand_accesses::cpu0.inst 10999002 # number of demand (read+write) accesses 1123system.cpu0.l2cache.demand_accesses::cpu0.data 5818681 # number of demand (read+write) accesses 1124system.cpu0.l2cache.demand_accesses::total 17653795 # number of demand (read+write) accesses 1125system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 639873 # number of overall (read+write) accesses 1126system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 196239 # number of overall (read+write) accesses 1127system.cpu0.l2cache.overall_accesses::cpu0.inst 10999002 # number of overall (read+write) accesses 1128system.cpu0.l2cache.overall_accesses::cpu0.data 5818681 # number of overall (read+write) accesses 1129system.cpu0.l2cache.overall_accesses::total 17653795 # number of overall (read+write) accesses 1130system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.021282 # miss rate for ReadReq accesses 1131system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.048492 # miss rate for ReadReq accesses 1132system.cpu0.l2cache.ReadReq_miss_rate::total 0.027669 # miss rate for ReadReq accesses 1133system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.997596 # miss rate for UpgradeReq accesses 1134system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.997596 # miss rate for UpgradeReq accesses 1135system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.999995 # miss rate for SCUpgradeReq accesses 1136system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.999995 # miss rate for SCUpgradeReq accesses 1137system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses 1138system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 1139system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.223096 # miss rate for ReadExReq accesses 1140system.cpu0.l2cache.ReadExReq_miss_rate::total 0.223096 # miss rate for ReadExReq accesses 1141system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.075007 # miss rate for ReadCleanReq accesses 1142system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.075007 # miss rate for ReadCleanReq accesses 1143system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.248854 # miss rate for ReadSharedReq accesses 1144system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.248854 # miss rate for ReadSharedReq accesses 1145system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.734035 # miss rate for InvalidateReq accesses 1146system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.734035 # miss rate for InvalidateReq accesses 1147system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.021282 # miss rate for demand accesses 1148system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.048492 # miss rate for demand accesses 1149system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.075007 # miss rate for demand accesses 1150system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.242952 # miss rate for demand accesses 1151system.cpu0.l2cache.demand_miss_rate::total 0.128119 # miss rate for demand accesses 1152system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.021282 # miss rate for overall accesses 1153system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.048492 # miss rate for overall accesses 1154system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.075007 # miss rate for overall accesses 1155system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.242952 # miss rate for overall accesses 1156system.cpu0.l2cache.overall_miss_rate::total 0.128119 # miss rate for overall accesses 1157system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 37963.724482 # average ReadReq miss latency 1158system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 42762.662884 # average ReadReq miss latency 1159system.cpu0.l2cache.ReadReq_avg_miss_latency::total 39937.732342 # average ReadReq miss latency 1160system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 7879.693541 # average UpgradeReq miss latency 1161system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 7879.693541 # average UpgradeReq miss latency 1162system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 7804.693637 # average SCUpgradeReq miss latency 1163system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 7804.693637 # average SCUpgradeReq miss latency 1164system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 668199.800000 # average SCUpgradeFailReq miss latency 1165system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 668199.800000 # average SCUpgradeFailReq miss latency 1166system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 50179.867206 # average ReadExReq miss latency 1167system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 50179.867206 # average ReadExReq miss latency 1168system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 33916.172121 # average ReadCleanReq miss latency 1169system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 33916.172121 # average ReadCleanReq miss latency 1170system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 36292.846240 # average ReadSharedReq miss latency 1171system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 36292.846240 # average ReadSharedReq miss latency 1172system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 520.209258 # average InvalidateReq miss latency 1173system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 520.209258 # average InvalidateReq miss latency 1174system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 37963.724482 # average overall miss latency 1175system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 42762.662884 # average overall miss latency 1176system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 33916.172121 # average overall miss latency 1177system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 39215.081718 # average overall miss latency 1178system.cpu0.l2cache.demand_avg_miss_latency::total 37289.669206 # average overall miss latency 1179system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 37963.724482 # average overall miss latency 1180system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 42762.662884 # average overall miss latency 1181system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 33916.172121 # average overall miss latency 1182system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 39215.081718 # average overall miss latency 1183system.cpu0.l2cache.overall_avg_miss_latency::total 37289.669206 # average overall miss latency 1184system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1185system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1186system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1187system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1188system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1189system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1190system.cpu0.l2cache.unused_prefetches 56740 # number of HardPF blocks evicted w/o reference 1191system.cpu0.l2cache.writebacks::writebacks 1791276 # number of writebacks 1192system.cpu0.l2cache.writebacks::total 1791276 # number of writebacks 1193system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker 1 # number of ReadReq MSHR hits 1194system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 4 # number of ReadReq MSHR hits 1195system.cpu0.l2cache.ReadReq_mshr_hits::total 5 # number of ReadReq MSHR hits 1196system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 10486 # number of ReadExReq MSHR hits 1197system.cpu0.l2cache.ReadExReq_mshr_hits::total 10486 # number of ReadExReq MSHR hits 1198system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 14 # number of ReadCleanReq MSHR hits 1199system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 14 # number of ReadCleanReq MSHR hits 1200system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 1072 # number of ReadSharedReq MSHR hits 1201system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 1072 # number of ReadSharedReq MSHR hits 1202system.cpu0.l2cache.InvalidateReq_mshr_hits::cpu0.data 4 # number of InvalidateReq MSHR hits 1203system.cpu0.l2cache.InvalidateReq_mshr_hits::total 4 # number of InvalidateReq MSHR hits 1204system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker 1 # number of demand (read+write) MSHR hits 1205system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 4 # number of demand (read+write) MSHR hits 1206system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 14 # number of demand (read+write) MSHR hits 1207system.cpu0.l2cache.demand_mshr_hits::cpu0.data 11558 # number of demand (read+write) MSHR hits 1208system.cpu0.l2cache.demand_mshr_hits::total 11577 # number of demand (read+write) MSHR hits 1209system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker 1 # number of overall MSHR hits 1210system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 4 # number of overall MSHR hits 1211system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 14 # number of overall MSHR hits 1212system.cpu0.l2cache.overall_mshr_hits::cpu0.data 11558 # number of overall MSHR hits 1213system.cpu0.l2cache.overall_mshr_hits::total 11577 # number of overall MSHR hits 1214system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 13617 # number of ReadReq MSHR misses 1215system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 9512 # number of ReadReq MSHR misses 1216system.cpu0.l2cache.ReadReq_mshr_misses::total 23129 # number of ReadReq MSHR misses 1217system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 884711 # number of HardPFReq MSHR misses 1218system.cpu0.l2cache.HardPFReq_mshr_misses::total 884711 # number of HardPFReq MSHR misses 1219system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 275991 # number of UpgradeReq MSHR misses 1220system.cpu0.l2cache.UpgradeReq_mshr_misses::total 275991 # number of UpgradeReq MSHR misses 1221system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 197331 # number of SCUpgradeReq MSHR misses 1222system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 197331 # number of SCUpgradeReq MSHR misses 1223system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 5 # number of SCUpgradeFailReq MSHR misses 1224system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 5 # number of SCUpgradeFailReq MSHR misses 1225system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 286989 # number of ReadExReq MSHR misses 1226system.cpu0.l2cache.ReadExReq_mshr_misses::total 286989 # number of ReadExReq MSHR misses 1227system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 824986 # number of ReadCleanReq MSHR misses 1228system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 824986 # number of ReadCleanReq MSHR misses 1229system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 1115111 # number of ReadSharedReq MSHR misses 1230system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 1115111 # number of ReadSharedReq MSHR misses 1231system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data 628025 # number of InvalidateReq MSHR misses 1232system.cpu0.l2cache.InvalidateReq_mshr_misses::total 628025 # number of InvalidateReq MSHR misses 1233system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 13617 # number of demand (read+write) MSHR misses 1234system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 9512 # number of demand (read+write) MSHR misses 1235system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 824986 # number of demand (read+write) MSHR misses 1236system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1402100 # number of demand (read+write) MSHR misses 1237system.cpu0.l2cache.demand_mshr_misses::total 2250215 # number of demand (read+write) MSHR misses 1238system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 13617 # number of overall MSHR misses 1239system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 9512 # number of overall MSHR misses 1240system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 824986 # number of overall MSHR misses 1241system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1402100 # number of overall MSHR misses 1242system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 884711 # number of overall MSHR misses 1243system.cpu0.l2cache.overall_mshr_misses::total 3134926 # number of overall MSHR misses 1244system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 52300 # number of ReadReq MSHR uncacheable 1245system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 29793 # number of ReadReq MSHR uncacheable 1246system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 82093 # number of ReadReq MSHR uncacheable 1247system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 29400 # number of WriteReq MSHR uncacheable 1248system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 29400 # number of WriteReq MSHR uncacheable 1249system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 52300 # number of overall MSHR uncacheable misses 1250system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 59193 # number of overall MSHR uncacheable misses 1251system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 111493 # number of overall MSHR uncacheable misses 1252system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 435264000 # number of ReadReq MSHR miss cycles 1253system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 349787000 # number of ReadReq MSHR miss cycles 1254system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 785051000 # number of ReadReq MSHR miss cycles 1255system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 42685466504 # number of HardPFReq MSHR miss cycles 1256system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 42685466504 # number of HardPFReq MSHR miss cycles 1257system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 5679653996 # number of UpgradeReq MSHR miss cycles 1258system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 5679653996 # number of UpgradeReq MSHR miss cycles 1259system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 3269289499 # number of SCUpgradeReq MSHR miss cycles 1260system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 3269289499 # number of SCUpgradeReq MSHR miss cycles 1261system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 2944999 # number of SCUpgradeFailReq MSHR miss cycles 1262system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 2944999 # number of SCUpgradeFailReq MSHR miss cycles 1263system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 11923656997 # number of ReadExReq MSHR miss cycles 1264system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 11923656997 # number of ReadExReq MSHR miss cycles 1265system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 23030463500 # number of ReadCleanReq MSHR miss cycles 1266system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 23030463500 # number of ReadCleanReq MSHR miss cycles 1267system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 33712054495 # number of ReadSharedReq MSHR miss cycles 1268system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 33712054495 # number of ReadSharedReq MSHR miss cycles 1269system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 20896498500 # number of InvalidateReq MSHR miss cycles 1270system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 20896498500 # number of InvalidateReq MSHR miss cycles 1271system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 435264000 # number of demand (read+write) MSHR miss cycles 1272system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 349787000 # number of demand (read+write) MSHR miss cycles 1273system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 23030463500 # number of demand (read+write) MSHR miss cycles 1274system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 45635711492 # number of demand (read+write) MSHR miss cycles 1275system.cpu0.l2cache.demand_mshr_miss_latency::total 69451225992 # number of demand (read+write) MSHR miss cycles 1276system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 435264000 # number of overall MSHR miss cycles 1277system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 349787000 # number of overall MSHR miss cycles 1278system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 23030463500 # number of overall MSHR miss cycles 1279system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 45635711492 # number of overall MSHR miss cycles 1280system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 42685466504 # number of overall MSHR miss cycles 1281system.cpu0.l2cache.overall_mshr_miss_latency::total 112136692496 # number of overall MSHR miss cycles 1282system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 4418384500 # number of ReadReq MSHR uncacheable cycles 1283system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5437142000 # number of ReadReq MSHR uncacheable cycles 1284system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 9855526500 # number of ReadReq MSHR uncacheable cycles 1285system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 4418384500 # number of overall MSHR uncacheable cycles 1286system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 5437142000 # number of overall MSHR uncacheable cycles 1287system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 9855526500 # number of overall MSHR uncacheable cycles 1288system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.021281 # mshr miss rate for ReadReq accesses 1289system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.048472 # mshr miss rate for ReadReq accesses 1290system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.027663 # mshr miss rate for ReadReq accesses 1291system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1292system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 1293system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.997596 # mshr miss rate for UpgradeReq accesses 1294system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.997596 # mshr miss rate for UpgradeReq accesses 1295system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.999995 # mshr miss rate for SCUpgradeReq accesses 1296system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.999995 # mshr miss rate for SCUpgradeReq accesses 1297system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses 1298system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 1299system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.215232 # mshr miss rate for ReadExReq accesses 1300system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.215232 # mshr miss rate for ReadExReq accesses 1301system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.075006 # mshr miss rate for ReadCleanReq accesses 1302system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.075006 # mshr miss rate for ReadCleanReq accesses 1303system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.248615 # mshr miss rate for ReadSharedReq accesses 1304system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.248615 # mshr miss rate for ReadSharedReq accesses 1305system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.734031 # mshr miss rate for InvalidateReq accesses 1306system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.734031 # mshr miss rate for InvalidateReq accesses 1307system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.021281 # mshr miss rate for demand accesses 1308system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.048472 # mshr miss rate for demand accesses 1309system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.075006 # mshr miss rate for demand accesses 1310system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.240965 # mshr miss rate for demand accesses 1311system.cpu0.l2cache.demand_mshr_miss_rate::total 0.127464 # mshr miss rate for demand accesses 1312system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.021281 # mshr miss rate for overall accesses 1313system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.048472 # mshr miss rate for overall accesses 1314system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.075006 # mshr miss rate for overall accesses 1315system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.240965 # mshr miss rate for overall accesses 1316system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses 1317system.cpu0.l2cache.overall_mshr_miss_rate::total 0.177578 # mshr miss rate for overall accesses 1318system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 31964.749945 # average ReadReq mshr miss latency 1319system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 36773.233810 # average ReadReq mshr miss latency 1320system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 33942.280254 # average ReadReq mshr miss latency 1321system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 48247.921077 # average HardPFReq mshr miss latency 1322system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 48247.921077 # average HardPFReq mshr miss latency 1323system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20579.127566 # average UpgradeReq mshr miss latency 1324system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20579.127566 # average UpgradeReq mshr miss latency 1325system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 16567.541334 # average SCUpgradeReq mshr miss latency 1326system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 16567.541334 # average SCUpgradeReq mshr miss latency 1327system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 588999.800000 # average SCUpgradeFailReq mshr miss latency 1328system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 588999.800000 # average SCUpgradeFailReq mshr miss latency 1329system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 41547.435606 # average ReadExReq mshr miss latency 1330system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 41547.435606 # average ReadExReq mshr miss latency 1331system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 27916.187063 # average ReadCleanReq mshr miss latency 1332system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 27916.187063 # average ReadCleanReq mshr miss latency 1333system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 30232.016808 # average ReadSharedReq mshr miss latency 1334system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 30232.016808 # average ReadSharedReq mshr miss latency 1335system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 33273.354564 # average InvalidateReq mshr miss latency 1336system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 33273.354564 # average InvalidateReq mshr miss latency 1337system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 31964.749945 # average overall mshr miss latency 1338system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 36773.233810 # average overall mshr miss latency 1339system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 27916.187063 # average overall mshr miss latency 1340system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 32548.114608 # average overall mshr miss latency 1341system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 30864.262300 # average overall mshr miss latency 1342system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 31964.749945 # average overall mshr miss latency 1343system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 36773.233810 # average overall mshr miss latency 1344system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 27916.187063 # average overall mshr miss latency 1345system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 32548.114608 # average overall mshr miss latency 1346system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 48247.921077 # average overall mshr miss latency 1347system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 35770.124238 # average overall mshr miss latency 1348system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 84481.539197 # average ReadReq mshr uncacheable latency 1349system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182497.298023 # average ReadReq mshr uncacheable latency 1350system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 120053.189675 # average ReadReq mshr uncacheable latency 1351system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 84481.539197 # average overall mshr uncacheable latency 1352system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 91854.476036 # average overall mshr uncacheable latency 1353system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 88395.921717 # average overall mshr uncacheable latency 1354system.cpu0.toL2Bus.snoop_filter.tot_requests 36072564 # Total number of requests made to the snoop filter. 1355system.cpu0.toL2Bus.snoop_filter.hit_single_requests 18399437 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1356system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 3515 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1357system.cpu0.toL2Bus.snoop_filter.tot_snoops 2427957 # Total number of snoops made to the snoop filter. 1358system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 2427386 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1359system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 571 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1360system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states 1361system.cpu0.toL2Bus.trans_dist::ReadReq 1003133 # Transaction distribution 1362system.cpu0.toL2Bus.trans_dist::ReadResp 16585926 # Transaction distribution 1363system.cpu0.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution 1364system.cpu0.toL2Bus.trans_dist::WriteReq 29400 # Transaction distribution 1365system.cpu0.toL2Bus.trans_dist::WriteResp 29400 # Transaction distribution 1366system.cpu0.toL2Bus.trans_dist::WritebackDirty 6083435 # Transaction distribution 1367system.cpu0.toL2Bus.trans_dist::WritebackClean 13283967 # Transaction distribution 1368system.cpu0.toL2Bus.trans_dist::CleanEvict 3350152 # Transaction distribution 1369system.cpu0.toL2Bus.trans_dist::HardPFReq 1133444 # Transaction distribution 1370system.cpu0.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution 1371system.cpu0.toL2Bus.trans_dist::UpgradeReq 490495 # Transaction distribution 1372system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 347636 # Transaction distribution 1373system.cpu0.toL2Bus.trans_dist::UpgradeResp 543136 # Transaction distribution 1374system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 77 # Transaction distribution 1375system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 138 # Transaction distribution 1376system.cpu0.toL2Bus.trans_dist::ReadExReq 1366077 # Transaction distribution 1377system.cpu0.toL2Bus.trans_dist::ReadExResp 1342549 # Transaction distribution 1378system.cpu0.toL2Bus.trans_dist::ReadCleanReq 10999003 # Transaction distribution 1379system.cpu0.toL2Bus.trans_dist::ReadSharedReq 5499511 # Transaction distribution 1380system.cpu0.toL2Bus.trans_dist::InvalidateReq 903440 # Transaction distribution 1381system.cpu0.toL2Bus.trans_dist::InvalidateResp 855584 # Transaction distribution 1382system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 33101096 # Packet count per connected master and slave (bytes) 1383system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 21166131 # Packet count per connected master and slave (bytes) 1384system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 412052 # Packet count per connected master and slave (bytes) 1385system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1345098 # Packet count per connected master and slave (bytes) 1386system.cpu0.toL2Bus.pkt_count::total 56024377 # Packet count per connected master and slave (bytes) 1387system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 1411186752 # Cumulative packet size per connected master and slave (bytes) 1388system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 800229141 # Cumulative packet size per connected master and slave (bytes) 1389system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1569912 # Cumulative packet size per connected master and slave (bytes) 1390system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 5118984 # Cumulative packet size per connected master and slave (bytes) 1391system.cpu0.toL2Bus.pkt_size::total 2218104789 # Cumulative packet size per connected master and slave (bytes) 1392system.cpu0.toL2Bus.snoops 7999072 # Total snoops (count) 1393system.cpu0.toL2Bus.snoopTraffic 122429440 # Total snoop traffic (bytes) 1394system.cpu0.toL2Bus.snoop_fanout::samples 26916994 # Request fanout histogram 1395system.cpu0.toL2Bus.snoop_fanout::mean 0.103450 # Request fanout histogram 1396system.cpu0.toL2Bus.snoop_fanout::stdev 0.304616 # Request fanout histogram 1397system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1398system.cpu0.toL2Bus.snoop_fanout::0 24132997 89.66% 89.66% # Request fanout histogram 1399system.cpu0.toL2Bus.snoop_fanout::1 2783426 10.34% 100.00% # Request fanout histogram 1400system.cpu0.toL2Bus.snoop_fanout::2 571 0.00% 100.00% # Request fanout histogram 1401system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1402system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1403system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 1404system.cpu0.toL2Bus.snoop_fanout::total 26916994 # Request fanout histogram 1405system.cpu0.toL2Bus.reqLayer0.occupancy 35963769502 # Layer occupancy (ticks) 1406system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 1407system.cpu0.toL2Bus.snoopLayer0.occupancy 196401052 # Layer occupancy (ticks) 1408system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1409system.cpu0.toL2Bus.respLayer0.occupancy 16580139110 # Layer occupancy (ticks) 1410system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 1411system.cpu0.toL2Bus.respLayer1.occupancy 9441182874 # Layer occupancy (ticks) 1412system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 1413system.cpu0.toL2Bus.respLayer2.occupancy 215851922 # Layer occupancy (ticks) 1414system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1415system.cpu0.toL2Bus.respLayer3.occupancy 705346257 # Layer occupancy (ticks) 1416system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1417system.cpu1.branchPred.lookups 118915951 # Number of BP lookups 1418system.cpu1.branchPred.condPredicted 85033049 # Number of conditional branches predicted 1419system.cpu1.branchPred.condIncorrect 5367569 # Number of conditional branches incorrect 1420system.cpu1.branchPred.BTBLookups 89750040 # Number of BTB lookups 1421system.cpu1.branchPred.BTBHits 63411692 # Number of BTB hits 1422system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 1423system.cpu1.branchPred.BTBHitPct 70.653664 # BTB Hit Percentage 1424system.cpu1.branchPred.usedRAS 13468810 # Number of times the RAS was used to get a target. 1425system.cpu1.branchPred.RASInCorrect 887929 # Number of incorrect RAS predictions. 1426system.cpu1.branchPred.indirectLookups 3084567 # Number of indirect predictor lookups. 1427system.cpu1.branchPred.indirectHits 1998882 # Number of indirect target hits. 1428system.cpu1.branchPred.indirectMisses 1085685 # Number of indirect misses. 1429system.cpu1.branchPredindirectMispredicted 396796 # Number of mispredicted indirect branches. 1430system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states 1431system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1432system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1433system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1434system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1435system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1436system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1437system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1438system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 1439system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1440system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1441system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1442system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1443system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1444system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1445system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1446system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1447system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1448system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1449system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1450system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1451system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1452system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1453system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1454system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1455system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1456system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1457system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1458system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1459system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1460system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states 1461system.cpu1.dtb.walker.walks 246313 # Table walker walks requested 1462system.cpu1.dtb.walker.walksLong 246313 # Table walker walks initiated with long descriptors 1463system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 8582 # Level at which table walker walks with long descriptors terminate 1464system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 75463 # Level at which table walker walks with long descriptors terminate 1465system.cpu1.dtb.walker.walkWaitTime::samples 246313 # Table walker wait (enqueue to first request) latency 1466system.cpu1.dtb.walker.walkWaitTime::0 246313 100.00% 100.00% # Table walker wait (enqueue to first request) latency 1467system.cpu1.dtb.walker.walkWaitTime::total 246313 # Table walker wait (enqueue to first request) latency 1468system.cpu1.dtb.walker.walkCompletionTime::samples 84045 # Table walker service (enqueue to completion) latency 1469system.cpu1.dtb.walker.walkCompletionTime::mean 22346.070557 # Table walker service (enqueue to completion) latency 1470system.cpu1.dtb.walker.walkCompletionTime::gmean 21064.042846 # Table walker service (enqueue to completion) latency 1471system.cpu1.dtb.walker.walkCompletionTime::stdev 12361.258067 # Table walker service (enqueue to completion) latency 1472system.cpu1.dtb.walker.walkCompletionTime::0-32767 79296 94.35% 94.35% # Table walker service (enqueue to completion) latency 1473system.cpu1.dtb.walker.walkCompletionTime::32768-65535 4004 4.76% 99.11% # Table walker service (enqueue to completion) latency 1474system.cpu1.dtb.walker.walkCompletionTime::65536-98303 175 0.21% 99.32% # Table walker service (enqueue to completion) latency 1475system.cpu1.dtb.walker.walkCompletionTime::98304-131071 458 0.54% 99.87% # Table walker service (enqueue to completion) latency 1476system.cpu1.dtb.walker.walkCompletionTime::131072-163839 22 0.03% 99.89% # Table walker service (enqueue to completion) latency 1477system.cpu1.dtb.walker.walkCompletionTime::163840-196607 12 0.01% 99.91% # Table walker service (enqueue to completion) latency 1478system.cpu1.dtb.walker.walkCompletionTime::196608-229375 27 0.03% 99.94% # Table walker service (enqueue to completion) latency 1479system.cpu1.dtb.walker.walkCompletionTime::229376-262143 10 0.01% 99.95% # Table walker service (enqueue to completion) latency 1480system.cpu1.dtb.walker.walkCompletionTime::262144-294911 13 0.02% 99.97% # Table walker service (enqueue to completion) latency 1481system.cpu1.dtb.walker.walkCompletionTime::294912-327679 13 0.02% 99.98% # Table walker service (enqueue to completion) latency 1482system.cpu1.dtb.walker.walkCompletionTime::327680-360447 6 0.01% 99.99% # Table walker service (enqueue to completion) latency 1483system.cpu1.dtb.walker.walkCompletionTime::360448-393215 3 0.00% 99.99% # Table walker service (enqueue to completion) latency 1484system.cpu1.dtb.walker.walkCompletionTime::393216-425983 3 0.00% 100.00% # Table walker service (enqueue to completion) latency 1485system.cpu1.dtb.walker.walkCompletionTime::458752-491519 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 1486system.cpu1.dtb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 1487system.cpu1.dtb.walker.walkCompletionTime::total 84045 # Table walker service (enqueue to completion) latency 1488system.cpu1.dtb.walker.walksPending::samples -766256056 # Table walker pending requests distribution 1489system.cpu1.dtb.walker.walksPending::0 -766256056 100.00% 100.00% # Table walker pending requests distribution 1490system.cpu1.dtb.walker.walksPending::total -766256056 # Table walker pending requests distribution 1491system.cpu1.dtb.walker.walkPageSizes::4K 75463 89.79% 89.79% # Table walker page sizes translated 1492system.cpu1.dtb.walker.walkPageSizes::2M 8582 10.21% 100.00% # Table walker page sizes translated 1493system.cpu1.dtb.walker.walkPageSizes::total 84045 # Table walker page sizes translated 1494system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 246313 # Table walker requests started/completed, data/inst 1495system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1496system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 246313 # Table walker requests started/completed, data/inst 1497system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 84045 # Table walker requests started/completed, data/inst 1498system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1499system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 84045 # Table walker requests started/completed, data/inst 1500system.cpu1.dtb.walker.walkRequestOrigin::total 330358 # Table walker requests started/completed, data/inst 1501system.cpu1.dtb.inst_hits 0 # ITB inst hits 1502system.cpu1.dtb.inst_misses 0 # ITB inst misses 1503system.cpu1.dtb.read_hits 74020776 # DTB read hits 1504system.cpu1.dtb.read_misses 200548 # DTB read misses 1505system.cpu1.dtb.write_hits 65603987 # DTB write hits 1506system.cpu1.dtb.write_misses 45765 # DTB write misses 1507system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed 1508system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1509system.cpu1.dtb.flush_tlb_mva_asid 43240 # Number of times TLB was flushed by MVA & ASID 1510system.cpu1.dtb.flush_tlb_asid 1075 # Number of times TLB was flushed by ASID 1511system.cpu1.dtb.flush_entries 34845 # Number of entries that have been flushed from TLB 1512system.cpu1.dtb.align_faults 889 # Number of TLB faults due to alignment restrictions 1513system.cpu1.dtb.prefetch_faults 6796 # Number of TLB faults due to prefetch 1514system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 1515system.cpu1.dtb.perms_faults 11277 # Number of TLB faults due to permissions restrictions 1516system.cpu1.dtb.read_accesses 74221324 # DTB read accesses 1517system.cpu1.dtb.write_accesses 65649752 # DTB write accesses 1518system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 1519system.cpu1.dtb.hits 139624763 # DTB hits 1520system.cpu1.dtb.misses 246313 # DTB misses 1521system.cpu1.dtb.accesses 139871076 # DTB accesses 1522system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states 1523system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1524system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1525system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1526system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1527system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1528system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1529system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1530system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 1531system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1532system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1533system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1534system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1535system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1536system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1537system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1538system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1539system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1540system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1541system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1542system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1543system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1544system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1545system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1546system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1547system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1548system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1549system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1550system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1551system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1552system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states 1553system.cpu1.itb.walker.walks 60327 # Table walker walks requested 1554system.cpu1.itb.walker.walksLong 60327 # Table walker walks initiated with long descriptors 1555system.cpu1.itb.walker.walksLongTerminationLevel::Level2 545 # Level at which table walker walks with long descriptors terminate 1556system.cpu1.itb.walker.walksLongTerminationLevel::Level3 52409 # Level at which table walker walks with long descriptors terminate 1557system.cpu1.itb.walker.walkWaitTime::samples 60327 # Table walker wait (enqueue to first request) latency 1558system.cpu1.itb.walker.walkWaitTime::0 60327 100.00% 100.00% # Table walker wait (enqueue to first request) latency 1559system.cpu1.itb.walker.walkWaitTime::total 60327 # Table walker wait (enqueue to first request) latency 1560system.cpu1.itb.walker.walkCompletionTime::samples 52954 # Table walker service (enqueue to completion) latency 1561system.cpu1.itb.walker.walkCompletionTime::mean 24879.980738 # Table walker service (enqueue to completion) latency 1562system.cpu1.itb.walker.walkCompletionTime::gmean 23402.458623 # Table walker service (enqueue to completion) latency 1563system.cpu1.itb.walker.walkCompletionTime::stdev 13318.614145 # Table walker service (enqueue to completion) latency 1564system.cpu1.itb.walker.walkCompletionTime::0-32767 48523 91.63% 91.63% # Table walker service (enqueue to completion) latency 1565system.cpu1.itb.walker.walkCompletionTime::32768-65535 3764 7.11% 98.74% # Table walker service (enqueue to completion) latency 1566system.cpu1.itb.walker.walkCompletionTime::65536-98303 13 0.02% 98.76% # Table walker service (enqueue to completion) latency 1567system.cpu1.itb.walker.walkCompletionTime::98304-131071 577 1.09% 99.85% # Table walker service (enqueue to completion) latency 1568system.cpu1.itb.walker.walkCompletionTime::131072-163839 18 0.03% 99.89% # Table walker service (enqueue to completion) latency 1569system.cpu1.itb.walker.walkCompletionTime::163840-196607 8 0.02% 99.90% # Table walker service (enqueue to completion) latency 1570system.cpu1.itb.walker.walkCompletionTime::196608-229375 20 0.04% 99.94% # Table walker service (enqueue to completion) latency 1571system.cpu1.itb.walker.walkCompletionTime::229376-262143 20 0.04% 99.98% # Table walker service (enqueue to completion) latency 1572system.cpu1.itb.walker.walkCompletionTime::262144-294911 3 0.01% 99.98% # Table walker service (enqueue to completion) latency 1573system.cpu1.itb.walker.walkCompletionTime::294912-327679 4 0.01% 99.99% # Table walker service (enqueue to completion) latency 1574system.cpu1.itb.walker.walkCompletionTime::327680-360447 1 0.00% 99.99% # Table walker service (enqueue to completion) latency 1575system.cpu1.itb.walker.walkCompletionTime::360448-393215 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 1576system.cpu1.itb.walker.walkCompletionTime::393216-425983 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 1577system.cpu1.itb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 1578system.cpu1.itb.walker.walkCompletionTime::total 52954 # Table walker service (enqueue to completion) latency 1579system.cpu1.itb.walker.walksPending::samples -766782556 # Table walker pending requests distribution 1580system.cpu1.itb.walker.walksPending::0 -766782556 100.00% 100.00% # Table walker pending requests distribution 1581system.cpu1.itb.walker.walksPending::total -766782556 # Table walker pending requests distribution 1582system.cpu1.itb.walker.walkPageSizes::4K 52409 98.97% 98.97% # Table walker page sizes translated 1583system.cpu1.itb.walker.walkPageSizes::2M 545 1.03% 100.00% # Table walker page sizes translated 1584system.cpu1.itb.walker.walkPageSizes::total 52954 # Table walker page sizes translated 1585system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1586system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 60327 # Table walker requests started/completed, data/inst 1587system.cpu1.itb.walker.walkRequestOrigin_Requested::total 60327 # Table walker requests started/completed, data/inst 1588system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1589system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 52954 # Table walker requests started/completed, data/inst 1590system.cpu1.itb.walker.walkRequestOrigin_Completed::total 52954 # Table walker requests started/completed, data/inst 1591system.cpu1.itb.walker.walkRequestOrigin::total 113281 # Table walker requests started/completed, data/inst 1592system.cpu1.itb.inst_hits 210682225 # ITB inst hits 1593system.cpu1.itb.inst_misses 60327 # ITB inst misses 1594system.cpu1.itb.read_hits 0 # DTB read hits 1595system.cpu1.itb.read_misses 0 # DTB read misses 1596system.cpu1.itb.write_hits 0 # DTB write hits 1597system.cpu1.itb.write_misses 0 # DTB write misses 1598system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed 1599system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1600system.cpu1.itb.flush_tlb_mva_asid 43240 # Number of times TLB was flushed by MVA & ASID 1601system.cpu1.itb.flush_tlb_asid 1075 # Number of times TLB was flushed by ASID 1602system.cpu1.itb.flush_entries 24520 # Number of entries that have been flushed from TLB 1603system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1604system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1605system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1606system.cpu1.itb.perms_faults 163777 # Number of TLB faults due to permissions restrictions 1607system.cpu1.itb.read_accesses 0 # DTB read accesses 1608system.cpu1.itb.write_accesses 0 # DTB write accesses 1609system.cpu1.itb.inst_accesses 210742552 # ITB inst accesses 1610system.cpu1.itb.hits 210682225 # DTB hits 1611system.cpu1.itb.misses 60327 # DTB misses 1612system.cpu1.itb.accesses 210742552 # DTB accesses 1613system.cpu1.numPwrStateTransitions 10392 # Number of power state transitions 1614system.cpu1.pwrStateClkGateDist::samples 5196 # Distribution of time spent in the clock gated state 1615system.cpu1.pwrStateClkGateDist::mean 9053828227.255966 # Distribution of time spent in the clock gated state 1616system.cpu1.pwrStateClkGateDist::stdev 188730440437.234528 # Distribution of time spent in the clock gated state 1617system.cpu1.pwrStateClkGateDist::underflows 3531 67.96% 67.96% # Distribution of time spent in the clock gated state 1618system.cpu1.pwrStateClkGateDist::1000-5e+10 1645 31.66% 99.62% # Distribution of time spent in the clock gated state 1619system.cpu1.pwrStateClkGateDist::5e+10-1e+11 9 0.17% 99.79% # Distribution of time spent in the clock gated state 1620system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 1 0.02% 99.81% # Distribution of time spent in the clock gated state 1621system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 1 0.02% 99.83% # Distribution of time spent in the clock gated state 1622system.cpu1.pwrStateClkGateDist::7.5e+11-8e+11 1 0.02% 99.85% # Distribution of time spent in the clock gated state 1623system.cpu1.pwrStateClkGateDist::9.5e+11-1e+12 1 0.02% 99.87% # Distribution of time spent in the clock gated state 1624system.cpu1.pwrStateClkGateDist::overflows 7 0.13% 100.00% # Distribution of time spent in the clock gated state 1625system.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state 1626system.cpu1.pwrStateClkGateDist::max_value 7351146453012 # Distribution of time spent in the clock gated state 1627system.cpu1.pwrStateClkGateDist::total 5196 # Distribution of time spent in the clock gated state 1628system.cpu1.pwrStateResidencyTicks::ON 401797772178 # Cumulative time (in ticks) in various power states 1629system.cpu1.pwrStateResidencyTicks::CLK_GATED 47043691468822 # Cumulative time (in ticks) in various power states 1630system.cpu1.numCycles 803603609 # number of cpu cycles simulated 1631system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1632system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 1633system.cpu1.committedInsts 379085635 # Number of instructions committed 1634system.cpu1.committedOps 446824897 # Number of ops (including micro ops) committed 1635system.cpu1.discardedOps 44295367 # Number of ops (including micro ops) which were discarded before commit 1636system.cpu1.numFetchSuspends 4823 # Number of times Execute suspended instruction fetching 1637system.cpu1.quiesceCycles 94088042190 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1638system.cpu1.cpi 2.119847 # CPI: cycles per instruction 1639system.cpu1.ipc 0.471732 # IPC: instructions per cycle 1640system.cpu1.op_class_0::No_OpClass 1 0.00% 0.00% # Class of committed instruction 1641system.cpu1.op_class_0::IntAlu 309274392 69.22% 69.22% # Class of committed instruction 1642system.cpu1.op_class_0::IntMult 866353 0.19% 69.41% # Class of committed instruction 1643system.cpu1.op_class_0::IntDiv 49212 0.01% 69.42% # Class of committed instruction 1644system.cpu1.op_class_0::FloatAdd 0 0.00% 69.42% # Class of committed instruction 1645system.cpu1.op_class_0::FloatCmp 0 0.00% 69.42% # Class of committed instruction 1646system.cpu1.op_class_0::FloatCvt 0 0.00% 69.42% # Class of committed instruction 1647system.cpu1.op_class_0::FloatMult 0 0.00% 69.42% # Class of committed instruction 1648system.cpu1.op_class_0::FloatDiv 0 0.00% 69.42% # Class of committed instruction 1649system.cpu1.op_class_0::FloatSqrt 0 0.00% 69.42% # Class of committed instruction 1650system.cpu1.op_class_0::SimdAdd 0 0.00% 69.42% # Class of committed instruction 1651system.cpu1.op_class_0::SimdAddAcc 0 0.00% 69.42% # Class of committed instruction 1652system.cpu1.op_class_0::SimdAlu 0 0.00% 69.42% # Class of committed instruction 1653system.cpu1.op_class_0::SimdCmp 0 0.00% 69.42% # Class of committed instruction 1654system.cpu1.op_class_0::SimdCvt 0 0.00% 69.42% # Class of committed instruction 1655system.cpu1.op_class_0::SimdMisc 0 0.00% 69.42% # Class of committed instruction 1656system.cpu1.op_class_0::SimdMult 0 0.00% 69.42% # Class of committed instruction 1657system.cpu1.op_class_0::SimdMultAcc 0 0.00% 69.42% # Class of committed instruction 1658system.cpu1.op_class_0::SimdShift 0 0.00% 69.42% # Class of committed instruction 1659system.cpu1.op_class_0::SimdShiftAcc 0 0.00% 69.42% # Class of committed instruction 1660system.cpu1.op_class_0::SimdSqrt 0 0.00% 69.42% # Class of committed instruction 1661system.cpu1.op_class_0::SimdFloatAdd 8 0.00% 69.42% # Class of committed instruction 1662system.cpu1.op_class_0::SimdFloatAlu 0 0.00% 69.42% # Class of committed instruction 1663system.cpu1.op_class_0::SimdFloatCmp 13 0.00% 69.42% # Class of committed instruction 1664system.cpu1.op_class_0::SimdFloatCvt 21 0.00% 69.42% # Class of committed instruction 1665system.cpu1.op_class_0::SimdFloatDiv 0 0.00% 69.42% # Class of committed instruction 1666system.cpu1.op_class_0::SimdFloatMisc 34424 0.01% 69.43% # Class of committed instruction 1667system.cpu1.op_class_0::SimdFloatMult 0 0.00% 69.43% # Class of committed instruction 1668system.cpu1.op_class_0::SimdFloatMultAcc 0 0.00% 69.43% # Class of committed instruction 1669system.cpu1.op_class_0::SimdFloatSqrt 0 0.00% 69.43% # Class of committed instruction 1670system.cpu1.op_class_0::MemRead 71272038 15.95% 85.38% # Class of committed instruction 1671system.cpu1.op_class_0::MemWrite 65328435 14.62% 100.00% # Class of committed instruction 1672system.cpu1.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 1673system.cpu1.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 1674system.cpu1.op_class_0::total 446824897 # Class of committed instruction 1675system.cpu1.kern.inst.arm 0 # number of arm instructions executed 1676system.cpu1.kern.inst.quiesce 5196 # number of quiesce instructions executed 1677system.cpu1.tickCycles 627540865 # Number of cycles that the object actually ticked 1678system.cpu1.idleCycles 176062744 # Total number of cycles that the object has spent stopped 1679system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states 1680system.cpu1.dcache.tags.replacements 4660684 # number of replacements 1681system.cpu1.dcache.tags.tagsinuse 434.489996 # Cycle average of tags in use 1682system.cpu1.dcache.tags.total_refs 132775101 # Total number of references to valid blocks. 1683system.cpu1.dcache.tags.sampled_refs 4661196 # Sample count of references to valid blocks. 1684system.cpu1.dcache.tags.avg_refs 28.485200 # Average number of references to valid blocks. 1685system.cpu1.dcache.tags.warmup_cycle 8377585211000 # Cycle when the warmup percentage was hit. 1686system.cpu1.dcache.tags.occ_blocks::cpu1.data 434.489996 # Average occupied blocks per requestor 1687system.cpu1.dcache.tags.occ_percent::cpu1.data 0.848613 # Average percentage of cache occupancy 1688system.cpu1.dcache.tags.occ_percent::total 0.848613 # Average percentage of cache occupancy 1689system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1690system.cpu1.dcache.tags.age_task_id_blocks_1024::0 72 # Occupied blocks per task id 1691system.cpu1.dcache.tags.age_task_id_blocks_1024::1 401 # Occupied blocks per task id 1692system.cpu1.dcache.tags.age_task_id_blocks_1024::2 39 # Occupied blocks per task id 1693system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1694system.cpu1.dcache.tags.tag_accesses 281793929 # Number of tag accesses 1695system.cpu1.dcache.tags.data_accesses 281793929 # Number of data accesses 1696system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states 1697system.cpu1.dcache.ReadReq_hits::cpu1.data 67965873 # number of ReadReq hits 1698system.cpu1.dcache.ReadReq_hits::total 67965873 # number of ReadReq hits 1699system.cpu1.dcache.WriteReq_hits::cpu1.data 61015488 # number of WriteReq hits 1700system.cpu1.dcache.WriteReq_hits::total 61015488 # number of WriteReq hits 1701system.cpu1.dcache.SoftPFReq_hits::cpu1.data 190971 # number of SoftPFReq hits 1702system.cpu1.dcache.SoftPFReq_hits::total 190971 # number of SoftPFReq hits 1703system.cpu1.dcache.WriteLineReq_hits::cpu1.data 44349 # number of WriteLineReq hits 1704system.cpu1.dcache.WriteLineReq_hits::total 44349 # number of WriteLineReq hits 1705system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1561438 # number of LoadLockedReq hits 1706system.cpu1.dcache.LoadLockedReq_hits::total 1561438 # number of LoadLockedReq hits 1707system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1518539 # number of StoreCondReq hits 1708system.cpu1.dcache.StoreCondReq_hits::total 1518539 # number of StoreCondReq hits 1709system.cpu1.dcache.demand_hits::cpu1.data 129025710 # number of demand (read+write) hits 1710system.cpu1.dcache.demand_hits::total 129025710 # number of demand (read+write) hits 1711system.cpu1.dcache.overall_hits::cpu1.data 129216681 # number of overall hits 1712system.cpu1.dcache.overall_hits::total 129216681 # number of overall hits 1713system.cpu1.dcache.ReadReq_misses::cpu1.data 2729495 # number of ReadReq misses 1714system.cpu1.dcache.ReadReq_misses::total 2729495 # number of ReadReq misses 1715system.cpu1.dcache.WriteReq_misses::cpu1.data 2149690 # number of WriteReq misses 1716system.cpu1.dcache.WriteReq_misses::total 2149690 # number of WriteReq misses 1717system.cpu1.dcache.SoftPFReq_misses::cpu1.data 616052 # number of SoftPFReq misses 1718system.cpu1.dcache.SoftPFReq_misses::total 616052 # number of SoftPFReq misses 1719system.cpu1.dcache.WriteLineReq_misses::cpu1.data 399927 # number of WriteLineReq misses 1720system.cpu1.dcache.WriteLineReq_misses::total 399927 # number of WriteLineReq misses 1721system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 143085 # number of LoadLockedReq misses 1722system.cpu1.dcache.LoadLockedReq_misses::total 143085 # number of LoadLockedReq misses 1723system.cpu1.dcache.StoreCondReq_misses::cpu1.data 184951 # number of StoreCondReq misses 1724system.cpu1.dcache.StoreCondReq_misses::total 184951 # number of StoreCondReq misses 1725system.cpu1.dcache.demand_misses::cpu1.data 5279112 # number of demand (read+write) misses 1726system.cpu1.dcache.demand_misses::total 5279112 # number of demand (read+write) misses 1727system.cpu1.dcache.overall_misses::cpu1.data 5895164 # number of overall misses 1728system.cpu1.dcache.overall_misses::total 5895164 # number of overall misses 1729system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 39717227000 # number of ReadReq miss cycles 1730system.cpu1.dcache.ReadReq_miss_latency::total 39717227000 # number of ReadReq miss cycles 1731system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 40094025500 # number of WriteReq miss cycles 1732system.cpu1.dcache.WriteReq_miss_latency::total 40094025500 # number of WriteReq miss cycles 1733system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 9755721000 # number of WriteLineReq miss cycles 1734system.cpu1.dcache.WriteLineReq_miss_latency::total 9755721000 # number of WriteLineReq miss cycles 1735system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2101168500 # number of LoadLockedReq miss cycles 1736system.cpu1.dcache.LoadLockedReq_miss_latency::total 2101168500 # number of LoadLockedReq miss cycles 1737system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4571201000 # number of StoreCondReq miss cycles 1738system.cpu1.dcache.StoreCondReq_miss_latency::total 4571201000 # number of StoreCondReq miss cycles 1739system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 4144500 # number of StoreCondFailReq miss cycles 1740system.cpu1.dcache.StoreCondFailReq_miss_latency::total 4144500 # number of StoreCondFailReq miss cycles 1741system.cpu1.dcache.demand_miss_latency::cpu1.data 89566973500 # number of demand (read+write) miss cycles 1742system.cpu1.dcache.demand_miss_latency::total 89566973500 # number of demand (read+write) miss cycles 1743system.cpu1.dcache.overall_miss_latency::cpu1.data 89566973500 # number of overall miss cycles 1744system.cpu1.dcache.overall_miss_latency::total 89566973500 # number of overall miss cycles 1745system.cpu1.dcache.ReadReq_accesses::cpu1.data 70695368 # number of ReadReq accesses(hits+misses) 1746system.cpu1.dcache.ReadReq_accesses::total 70695368 # number of ReadReq accesses(hits+misses) 1747system.cpu1.dcache.WriteReq_accesses::cpu1.data 63165178 # number of WriteReq accesses(hits+misses) 1748system.cpu1.dcache.WriteReq_accesses::total 63165178 # number of WriteReq accesses(hits+misses) 1749system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 807023 # number of SoftPFReq accesses(hits+misses) 1750system.cpu1.dcache.SoftPFReq_accesses::total 807023 # number of SoftPFReq accesses(hits+misses) 1751system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 444276 # number of WriteLineReq accesses(hits+misses) 1752system.cpu1.dcache.WriteLineReq_accesses::total 444276 # number of WriteLineReq accesses(hits+misses) 1753system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1704523 # number of LoadLockedReq accesses(hits+misses) 1754system.cpu1.dcache.LoadLockedReq_accesses::total 1704523 # number of LoadLockedReq accesses(hits+misses) 1755system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1703490 # number of StoreCondReq accesses(hits+misses) 1756system.cpu1.dcache.StoreCondReq_accesses::total 1703490 # number of StoreCondReq accesses(hits+misses) 1757system.cpu1.dcache.demand_accesses::cpu1.data 134304822 # number of demand (read+write) accesses 1758system.cpu1.dcache.demand_accesses::total 134304822 # number of demand (read+write) accesses 1759system.cpu1.dcache.overall_accesses::cpu1.data 135111845 # number of overall (read+write) accesses 1760system.cpu1.dcache.overall_accesses::total 135111845 # number of overall (read+write) accesses 1761system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.038609 # miss rate for ReadReq accesses 1762system.cpu1.dcache.ReadReq_miss_rate::total 0.038609 # miss rate for ReadReq accesses 1763system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.034033 # miss rate for WriteReq accesses 1764system.cpu1.dcache.WriteReq_miss_rate::total 0.034033 # miss rate for WriteReq accesses 1765system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.763364 # miss rate for SoftPFReq accesses 1766system.cpu1.dcache.SoftPFReq_miss_rate::total 0.763364 # miss rate for SoftPFReq accesses 1767system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.900177 # miss rate for WriteLineReq accesses 1768system.cpu1.dcache.WriteLineReq_miss_rate::total 0.900177 # miss rate for WriteLineReq accesses 1769system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.083944 # miss rate for LoadLockedReq accesses 1770system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.083944 # miss rate for LoadLockedReq accesses 1771system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.108572 # miss rate for StoreCondReq accesses 1772system.cpu1.dcache.StoreCondReq_miss_rate::total 0.108572 # miss rate for StoreCondReq accesses 1773system.cpu1.dcache.demand_miss_rate::cpu1.data 0.039307 # miss rate for demand accesses 1774system.cpu1.dcache.demand_miss_rate::total 0.039307 # miss rate for demand accesses 1775system.cpu1.dcache.overall_miss_rate::cpu1.data 0.043632 # miss rate for overall accesses 1776system.cpu1.dcache.overall_miss_rate::total 0.043632 # miss rate for overall accesses 1777system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14551.126490 # average ReadReq miss latency 1778system.cpu1.dcache.ReadReq_avg_miss_latency::total 14551.126490 # average ReadReq miss latency 1779system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18651.073178 # average WriteReq miss latency 1780system.cpu1.dcache.WriteReq_avg_miss_latency::total 18651.073178 # average WriteReq miss latency 1781system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 24393.754360 # average WriteLineReq miss latency 1782system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 24393.754360 # average WriteLineReq miss latency 1783system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14684.757312 # average LoadLockedReq miss latency 1784system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14684.757312 # average LoadLockedReq miss latency 1785system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 24715.740926 # average StoreCondReq miss latency 1786system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 24715.740926 # average StoreCondReq miss latency 1787system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 1788system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 1789system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 16966.295373 # average overall miss latency 1790system.cpu1.dcache.demand_avg_miss_latency::total 16966.295373 # average overall miss latency 1791system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15193.296319 # average overall miss latency 1792system.cpu1.dcache.overall_avg_miss_latency::total 15193.296319 # average overall miss latency 1793system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1794system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1795system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1796system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1797system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1798system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1799system.cpu1.dcache.writebacks::writebacks 4660691 # number of writebacks 1800system.cpu1.dcache.writebacks::total 4660691 # number of writebacks 1801system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 132278 # number of ReadReq MSHR hits 1802system.cpu1.dcache.ReadReq_mshr_hits::total 132278 # number of ReadReq MSHR hits 1803system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 894898 # number of WriteReq MSHR hits 1804system.cpu1.dcache.WriteReq_mshr_hits::total 894898 # number of WriteReq MSHR hits 1805system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 69 # number of WriteLineReq MSHR hits 1806system.cpu1.dcache.WriteLineReq_mshr_hits::total 69 # number of WriteLineReq MSHR hits 1807system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 37558 # number of LoadLockedReq MSHR hits 1808system.cpu1.dcache.LoadLockedReq_mshr_hits::total 37558 # number of LoadLockedReq MSHR hits 1809system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data 59 # number of StoreCondReq MSHR hits 1810system.cpu1.dcache.StoreCondReq_mshr_hits::total 59 # number of StoreCondReq MSHR hits 1811system.cpu1.dcache.demand_mshr_hits::cpu1.data 1027245 # number of demand (read+write) MSHR hits 1812system.cpu1.dcache.demand_mshr_hits::total 1027245 # number of demand (read+write) MSHR hits 1813system.cpu1.dcache.overall_mshr_hits::cpu1.data 1027245 # number of overall MSHR hits 1814system.cpu1.dcache.overall_mshr_hits::total 1027245 # number of overall MSHR hits 1815system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2597217 # number of ReadReq MSHR misses 1816system.cpu1.dcache.ReadReq_mshr_misses::total 2597217 # number of ReadReq MSHR misses 1817system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1254792 # number of WriteReq MSHR misses 1818system.cpu1.dcache.WriteReq_mshr_misses::total 1254792 # number of WriteReq MSHR misses 1819system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 615702 # number of SoftPFReq MSHR misses 1820system.cpu1.dcache.SoftPFReq_mshr_misses::total 615702 # number of SoftPFReq MSHR misses 1821system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 399858 # number of WriteLineReq MSHR misses 1822system.cpu1.dcache.WriteLineReq_mshr_misses::total 399858 # number of WriteLineReq MSHR misses 1823system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 105527 # number of LoadLockedReq MSHR misses 1824system.cpu1.dcache.LoadLockedReq_mshr_misses::total 105527 # number of LoadLockedReq MSHR misses 1825system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 184892 # number of StoreCondReq MSHR misses 1826system.cpu1.dcache.StoreCondReq_mshr_misses::total 184892 # number of StoreCondReq MSHR misses 1827system.cpu1.dcache.demand_mshr_misses::cpu1.data 4251867 # number of demand (read+write) MSHR misses 1828system.cpu1.dcache.demand_mshr_misses::total 4251867 # number of demand (read+write) MSHR misses 1829system.cpu1.dcache.overall_mshr_misses::cpu1.data 4867569 # number of overall MSHR misses 1830system.cpu1.dcache.overall_mshr_misses::total 4867569 # number of overall MSHR misses 1831system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 8793 # number of ReadReq MSHR uncacheable 1832system.cpu1.dcache.ReadReq_mshr_uncacheable::total 8793 # number of ReadReq MSHR uncacheable 1833system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 9091 # number of WriteReq MSHR uncacheable 1834system.cpu1.dcache.WriteReq_mshr_uncacheable::total 9091 # number of WriteReq MSHR uncacheable 1835system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 17884 # number of overall MSHR uncacheable misses 1836system.cpu1.dcache.overall_mshr_uncacheable_misses::total 17884 # number of overall MSHR uncacheable misses 1837system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 34245614000 # number of ReadReq MSHR miss cycles 1838system.cpu1.dcache.ReadReq_mshr_miss_latency::total 34245614000 # number of ReadReq MSHR miss cycles 1839system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 22880344500 # number of WriteReq MSHR miss cycles 1840system.cpu1.dcache.WriteReq_mshr_miss_latency::total 22880344500 # number of WriteReq MSHR miss cycles 1841system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 13431113500 # number of SoftPFReq MSHR miss cycles 1842system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 13431113500 # number of SoftPFReq MSHR miss cycles 1843system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 9350661500 # number of WriteLineReq MSHR miss cycles 1844system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 9350661500 # number of WriteLineReq MSHR miss cycles 1845system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1405417000 # number of LoadLockedReq MSHR miss cycles 1846system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1405417000 # number of LoadLockedReq MSHR miss cycles 1847system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4384302500 # number of StoreCondReq MSHR miss cycles 1848system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4384302500 # number of StoreCondReq MSHR miss cycles 1849system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 3898500 # number of StoreCondFailReq MSHR miss cycles 1850system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 3898500 # number of StoreCondFailReq MSHR miss cycles 1851system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 66476620000 # number of demand (read+write) MSHR miss cycles 1852system.cpu1.dcache.demand_mshr_miss_latency::total 66476620000 # number of demand (read+write) MSHR miss cycles 1853system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 79907733500 # number of overall MSHR miss cycles 1854system.cpu1.dcache.overall_mshr_miss_latency::total 79907733500 # number of overall MSHR miss cycles 1855system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 1305175500 # number of ReadReq MSHR uncacheable cycles 1856system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 1305175500 # number of ReadReq MSHR uncacheable cycles 1857system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1305175500 # number of overall MSHR uncacheable cycles 1858system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1305175500 # number of overall MSHR uncacheable cycles 1859system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036738 # mshr miss rate for ReadReq accesses 1860system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036738 # mshr miss rate for ReadReq accesses 1861system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.019865 # mshr miss rate for WriteReq accesses 1862system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.019865 # mshr miss rate for WriteReq accesses 1863system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.762930 # mshr miss rate for SoftPFReq accesses 1864system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.762930 # mshr miss rate for SoftPFReq accesses 1865system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.900022 # mshr miss rate for WriteLineReq accesses 1866system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.900022 # mshr miss rate for WriteLineReq accesses 1867system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.061910 # mshr miss rate for LoadLockedReq accesses 1868system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.061910 # mshr miss rate for LoadLockedReq accesses 1869system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.108537 # mshr miss rate for StoreCondReq accesses 1870system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.108537 # mshr miss rate for StoreCondReq accesses 1871system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031658 # mshr miss rate for demand accesses 1872system.cpu1.dcache.demand_mshr_miss_rate::total 0.031658 # mshr miss rate for demand accesses 1873system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.036026 # mshr miss rate for overall accesses 1874system.cpu1.dcache.overall_mshr_miss_rate::total 0.036026 # mshr miss rate for overall accesses 1875system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13185.503560 # average ReadReq mshr miss latency 1876system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13185.503560 # average ReadReq mshr miss latency 1877system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 18234.372310 # average WriteReq mshr miss latency 1878system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 18234.372310 # average WriteReq mshr miss latency 1879system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 21814.308708 # average SoftPFReq mshr miss latency 1880system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 21814.308708 # average SoftPFReq mshr miss latency 1881system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 23384.955409 # average WriteLineReq mshr miss latency 1882system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 23384.955409 # average WriteLineReq mshr miss latency 1883system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13318.079733 # average LoadLockedReq mshr miss latency 1884system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13318.079733 # average LoadLockedReq mshr miss latency 1885system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 23712.775566 # average StoreCondReq mshr miss latency 1886system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 23712.775566 # average StoreCondReq mshr miss latency 1887system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 1888system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 1889system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15634.689420 # average overall mshr miss latency 1890system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15634.689420 # average overall mshr miss latency 1891system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16416.353523 # average overall mshr miss latency 1892system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16416.353523 # average overall mshr miss latency 1893system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 148433.469806 # average ReadReq mshr uncacheable latency 1894system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 148433.469806 # average ReadReq mshr uncacheable latency 1895system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 72980.065981 # average overall mshr uncacheable latency 1896system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 72980.065981 # average overall mshr uncacheable latency 1897system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states 1898system.cpu1.icache.tags.replacements 8014386 # number of replacements 1899system.cpu1.icache.tags.tagsinuse 507.062567 # Cycle average of tags in use 1900system.cpu1.icache.tags.total_refs 202497896 # Total number of references to valid blocks. 1901system.cpu1.icache.tags.sampled_refs 8014898 # Sample count of references to valid blocks. 1902system.cpu1.icache.tags.avg_refs 25.265187 # Average number of references to valid blocks. 1903system.cpu1.icache.tags.warmup_cycle 8368004575000 # Cycle when the warmup percentage was hit. 1904system.cpu1.icache.tags.occ_blocks::cpu1.inst 507.062567 # Average occupied blocks per requestor 1905system.cpu1.icache.tags.occ_percent::cpu1.inst 0.990357 # Average percentage of cache occupancy 1906system.cpu1.icache.tags.occ_percent::total 0.990357 # Average percentage of cache occupancy 1907system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1908system.cpu1.icache.tags.age_task_id_blocks_1024::0 113 # Occupied blocks per task id 1909system.cpu1.icache.tags.age_task_id_blocks_1024::1 354 # Occupied blocks per task id 1910system.cpu1.icache.tags.age_task_id_blocks_1024::2 45 # Occupied blocks per task id 1911system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1912system.cpu1.icache.tags.tag_accesses 429040515 # Number of tag accesses 1913system.cpu1.icache.tags.data_accesses 429040515 # Number of data accesses 1914system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states 1915system.cpu1.icache.ReadReq_hits::cpu1.inst 202497896 # number of ReadReq hits 1916system.cpu1.icache.ReadReq_hits::total 202497896 # number of ReadReq hits 1917system.cpu1.icache.demand_hits::cpu1.inst 202497896 # number of demand (read+write) hits 1918system.cpu1.icache.demand_hits::total 202497896 # number of demand (read+write) hits 1919system.cpu1.icache.overall_hits::cpu1.inst 202497896 # number of overall hits 1920system.cpu1.icache.overall_hits::total 202497896 # number of overall hits 1921system.cpu1.icache.ReadReq_misses::cpu1.inst 8014908 # number of ReadReq misses 1922system.cpu1.icache.ReadReq_misses::total 8014908 # number of ReadReq misses 1923system.cpu1.icache.demand_misses::cpu1.inst 8014908 # number of demand (read+write) misses 1924system.cpu1.icache.demand_misses::total 8014908 # number of demand (read+write) misses 1925system.cpu1.icache.overall_misses::cpu1.inst 8014908 # number of overall misses 1926system.cpu1.icache.overall_misses::total 8014908 # number of overall misses 1927system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 81330977500 # number of ReadReq miss cycles 1928system.cpu1.icache.ReadReq_miss_latency::total 81330977500 # number of ReadReq miss cycles 1929system.cpu1.icache.demand_miss_latency::cpu1.inst 81330977500 # number of demand (read+write) miss cycles 1930system.cpu1.icache.demand_miss_latency::total 81330977500 # number of demand (read+write) miss cycles 1931system.cpu1.icache.overall_miss_latency::cpu1.inst 81330977500 # number of overall miss cycles 1932system.cpu1.icache.overall_miss_latency::total 81330977500 # number of overall miss cycles 1933system.cpu1.icache.ReadReq_accesses::cpu1.inst 210512804 # number of ReadReq accesses(hits+misses) 1934system.cpu1.icache.ReadReq_accesses::total 210512804 # number of ReadReq accesses(hits+misses) 1935system.cpu1.icache.demand_accesses::cpu1.inst 210512804 # number of demand (read+write) accesses 1936system.cpu1.icache.demand_accesses::total 210512804 # number of demand (read+write) accesses 1937system.cpu1.icache.overall_accesses::cpu1.inst 210512804 # number of overall (read+write) accesses 1938system.cpu1.icache.overall_accesses::total 210512804 # number of overall (read+write) accesses 1939system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.038073 # miss rate for ReadReq accesses 1940system.cpu1.icache.ReadReq_miss_rate::total 0.038073 # miss rate for ReadReq accesses 1941system.cpu1.icache.demand_miss_rate::cpu1.inst 0.038073 # miss rate for demand accesses 1942system.cpu1.icache.demand_miss_rate::total 0.038073 # miss rate for demand accesses 1943system.cpu1.icache.overall_miss_rate::cpu1.inst 0.038073 # miss rate for overall accesses 1944system.cpu1.icache.overall_miss_rate::total 0.038073 # miss rate for overall accesses 1945system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10147.462391 # average ReadReq miss latency 1946system.cpu1.icache.ReadReq_avg_miss_latency::total 10147.462391 # average ReadReq miss latency 1947system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10147.462391 # average overall miss latency 1948system.cpu1.icache.demand_avg_miss_latency::total 10147.462391 # average overall miss latency 1949system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10147.462391 # average overall miss latency 1950system.cpu1.icache.overall_avg_miss_latency::total 10147.462391 # average overall miss latency 1951system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1952system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1953system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1954system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1955system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1956system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1957system.cpu1.icache.writebacks::writebacks 8014386 # number of writebacks 1958system.cpu1.icache.writebacks::total 8014386 # number of writebacks 1959system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 8014908 # number of ReadReq MSHR misses 1960system.cpu1.icache.ReadReq_mshr_misses::total 8014908 # number of ReadReq MSHR misses 1961system.cpu1.icache.demand_mshr_misses::cpu1.inst 8014908 # number of demand (read+write) MSHR misses 1962system.cpu1.icache.demand_mshr_misses::total 8014908 # number of demand (read+write) MSHR misses 1963system.cpu1.icache.overall_mshr_misses::cpu1.inst 8014908 # number of overall MSHR misses 1964system.cpu1.icache.overall_mshr_misses::total 8014908 # number of overall MSHR misses 1965system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 95 # number of ReadReq MSHR uncacheable 1966system.cpu1.icache.ReadReq_mshr_uncacheable::total 95 # number of ReadReq MSHR uncacheable 1967system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 95 # number of overall MSHR uncacheable misses 1968system.cpu1.icache.overall_mshr_uncacheable_misses::total 95 # number of overall MSHR uncacheable misses 1969system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 77323524000 # number of ReadReq MSHR miss cycles 1970system.cpu1.icache.ReadReq_mshr_miss_latency::total 77323524000 # number of ReadReq MSHR miss cycles 1971system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 77323524000 # number of demand (read+write) MSHR miss cycles 1972system.cpu1.icache.demand_mshr_miss_latency::total 77323524000 # number of demand (read+write) MSHR miss cycles 1973system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 77323524000 # number of overall MSHR miss cycles 1974system.cpu1.icache.overall_mshr_miss_latency::total 77323524000 # number of overall MSHR miss cycles 1975system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8766500 # number of ReadReq MSHR uncacheable cycles 1976system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 8766500 # number of ReadReq MSHR uncacheable cycles 1977system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 8766500 # number of overall MSHR uncacheable cycles 1978system.cpu1.icache.overall_mshr_uncacheable_latency::total 8766500 # number of overall MSHR uncacheable cycles 1979system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.038073 # mshr miss rate for ReadReq accesses 1980system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.038073 # mshr miss rate for ReadReq accesses 1981system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.038073 # mshr miss rate for demand accesses 1982system.cpu1.icache.demand_mshr_miss_rate::total 0.038073 # mshr miss rate for demand accesses 1983system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.038073 # mshr miss rate for overall accesses 1984system.cpu1.icache.overall_mshr_miss_rate::total 0.038073 # mshr miss rate for overall accesses 1985system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 9647.462454 # average ReadReq mshr miss latency 1986system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 9647.462454 # average ReadReq mshr miss latency 1987system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 9647.462454 # average overall mshr miss latency 1988system.cpu1.icache.demand_avg_mshr_miss_latency::total 9647.462454 # average overall mshr miss latency 1989system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 9647.462454 # average overall mshr miss latency 1990system.cpu1.icache.overall_avg_mshr_miss_latency::total 9647.462454 # average overall mshr miss latency 1991system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 92278.947368 # average ReadReq mshr uncacheable latency 1992system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 92278.947368 # average ReadReq mshr uncacheable latency 1993system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 92278.947368 # average overall mshr uncacheable latency 1994system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 92278.947368 # average overall mshr uncacheable latency 1995system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states 1996system.cpu1.l2cache.prefetcher.num_hwpf_issued 6532358 # number of hwpf issued 1997system.cpu1.l2cache.prefetcher.pfIdentified 6532555 # number of prefetch candidates identified 1998system.cpu1.l2cache.prefetcher.pfBufferHit 172 # number of redundant prefetches already in prefetch queue 1999system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 2000system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 2001system.cpu1.l2cache.prefetcher.pfSpanPage 799581 # number of prefetches not generated due to page crossing 2002system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states 2003system.cpu1.l2cache.tags.replacements 2133098 # number of replacements 2004system.cpu1.l2cache.tags.tagsinuse 13038.197584 # Cycle average of tags in use 2005system.cpu1.l2cache.tags.total_refs 20019506 # Total number of references to valid blocks. 2006system.cpu1.l2cache.tags.sampled_refs 2148887 # Sample count of references to valid blocks. 2007system.cpu1.l2cache.tags.avg_refs 9.316221 # Average number of references to valid blocks. 2008system.cpu1.l2cache.tags.warmup_cycle 9619713453000 # Cycle when the warmup percentage was hit. 2009system.cpu1.l2cache.tags.occ_blocks::writebacks 11987.780509 # Average occupied blocks per requestor 2010system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 23.994022 # Average occupied blocks per requestor 2011system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 12.035388 # Average occupied blocks per requestor 2012system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 1014.387665 # Average occupied blocks per requestor 2013system.cpu1.l2cache.tags.occ_percent::writebacks 0.731676 # Average percentage of cache occupancy 2014system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.001464 # Average percentage of cache occupancy 2015system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000735 # Average percentage of cache occupancy 2016system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.061913 # Average percentage of cache occupancy 2017system.cpu1.l2cache.tags.occ_percent::total 0.795788 # Average percentage of cache occupancy 2018system.cpu1.l2cache.tags.occ_task_id_blocks::1022 829 # Occupied blocks per task id 2019system.cpu1.l2cache.tags.occ_task_id_blocks::1023 65 # Occupied blocks per task id 2020system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14895 # Occupied blocks per task id 2021system.cpu1.l2cache.tags.age_task_id_blocks_1022::0 11 # Occupied blocks per task id 2022system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 17 # Occupied blocks per task id 2023system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 152 # Occupied blocks per task id 2024system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 567 # Occupied blocks per task id 2025system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 82 # Occupied blocks per task id 2026system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id 2027system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 8 # Occupied blocks per task id 2028system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 55 # Occupied blocks per task id 2029system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 1 # Occupied blocks per task id 2030system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 105 # Occupied blocks per task id 2031system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1161 # Occupied blocks per task id 2032system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5545 # Occupied blocks per task id 2033system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 7510 # Occupied blocks per task id 2034system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 574 # Occupied blocks per task id 2035system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.050598 # Percentage of cache occupancy per task id 2036system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.003967 # Percentage of cache occupancy per task id 2037system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.909119 # Percentage of cache occupancy per task id 2038system.cpu1.l2cache.tags.tag_accesses 428778233 # Number of tag accesses 2039system.cpu1.l2cache.tags.data_accesses 428778233 # Number of data accesses 2040system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states 2041system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 473132 # number of ReadReq hits 2042system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 155315 # number of ReadReq hits 2043system.cpu1.l2cache.ReadReq_hits::total 628447 # number of ReadReq hits 2044system.cpu1.l2cache.WritebackDirty_hits::writebacks 2939776 # number of WritebackDirty hits 2045system.cpu1.l2cache.WritebackDirty_hits::total 2939776 # number of WritebackDirty hits 2046system.cpu1.l2cache.WritebackClean_hits::writebacks 9733319 # number of WritebackClean hits 2047system.cpu1.l2cache.WritebackClean_hits::total 9733319 # number of WritebackClean hits 2048system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 413 # number of UpgradeReq hits 2049system.cpu1.l2cache.UpgradeReq_hits::total 413 # number of UpgradeReq hits 2050system.cpu1.l2cache.ReadExReq_hits::cpu1.data 783674 # number of ReadExReq hits 2051system.cpu1.l2cache.ReadExReq_hits::total 783674 # number of ReadExReq hits 2052system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 7365861 # number of ReadCleanReq hits 2053system.cpu1.l2cache.ReadCleanReq_hits::total 7365861 # number of ReadCleanReq hits 2054system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 2414791 # number of ReadSharedReq hits 2055system.cpu1.l2cache.ReadSharedReq_hits::total 2414791 # number of ReadSharedReq hits 2056system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 165268 # number of InvalidateReq hits 2057system.cpu1.l2cache.InvalidateReq_hits::total 165268 # number of InvalidateReq hits 2058system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 473132 # number of demand (read+write) hits 2059system.cpu1.l2cache.demand_hits::cpu1.itb.walker 155315 # number of demand (read+write) hits 2060system.cpu1.l2cache.demand_hits::cpu1.inst 7365861 # number of demand (read+write) hits 2061system.cpu1.l2cache.demand_hits::cpu1.data 3198465 # number of demand (read+write) hits 2062system.cpu1.l2cache.demand_hits::total 11192773 # number of demand (read+write) hits 2063system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 473132 # number of overall hits 2064system.cpu1.l2cache.overall_hits::cpu1.itb.walker 155315 # number of overall hits 2065system.cpu1.l2cache.overall_hits::cpu1.inst 7365861 # number of overall hits 2066system.cpu1.l2cache.overall_hits::cpu1.data 3198465 # number of overall hits 2067system.cpu1.l2cache.overall_hits::total 11192773 # number of overall hits 2068system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 11255 # number of ReadReq misses 2069system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 7950 # number of ReadReq misses 2070system.cpu1.l2cache.ReadReq_misses::total 19205 # number of ReadReq misses 2071system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 218866 # number of UpgradeReq misses 2072system.cpu1.l2cache.UpgradeReq_misses::total 218866 # number of UpgradeReq misses 2073system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 184883 # number of SCUpgradeReq misses 2074system.cpu1.l2cache.SCUpgradeReq_misses::total 184883 # number of SCUpgradeReq misses 2075system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 9 # number of SCUpgradeFailReq misses 2076system.cpu1.l2cache.SCUpgradeFailReq_misses::total 9 # number of SCUpgradeFailReq misses 2077system.cpu1.l2cache.ReadExReq_misses::cpu1.data 254182 # number of ReadExReq misses 2078system.cpu1.l2cache.ReadExReq_misses::total 254182 # number of ReadExReq misses 2079system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 649047 # number of ReadCleanReq misses 2080system.cpu1.l2cache.ReadCleanReq_misses::total 649047 # number of ReadCleanReq misses 2081system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 903423 # number of ReadSharedReq misses 2082system.cpu1.l2cache.ReadSharedReq_misses::total 903423 # number of ReadSharedReq misses 2083system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 232791 # number of InvalidateReq misses 2084system.cpu1.l2cache.InvalidateReq_misses::total 232791 # number of InvalidateReq misses 2085system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 11255 # number of demand (read+write) misses 2086system.cpu1.l2cache.demand_misses::cpu1.itb.walker 7950 # number of demand (read+write) misses 2087system.cpu1.l2cache.demand_misses::cpu1.inst 649047 # number of demand (read+write) misses 2088system.cpu1.l2cache.demand_misses::cpu1.data 1157605 # number of demand (read+write) misses 2089system.cpu1.l2cache.demand_misses::total 1825857 # number of demand (read+write) misses 2090system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 11255 # number of overall misses 2091system.cpu1.l2cache.overall_misses::cpu1.itb.walker 7950 # number of overall misses 2092system.cpu1.l2cache.overall_misses::cpu1.inst 649047 # number of overall misses 2093system.cpu1.l2cache.overall_misses::cpu1.data 1157605 # number of overall misses 2094system.cpu1.l2cache.overall_misses::total 1825857 # number of overall misses 2095system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 391701000 # number of ReadReq miss cycles 2096system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 275187000 # number of ReadReq miss cycles 2097system.cpu1.l2cache.ReadReq_miss_latency::total 666888000 # number of ReadReq miss cycles 2098system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 1898630500 # number of UpgradeReq miss cycles 2099system.cpu1.l2cache.UpgradeReq_miss_latency::total 1898630500 # number of UpgradeReq miss cycles 2100system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 1381240500 # number of SCUpgradeReq miss cycles 2101system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 1381240500 # number of SCUpgradeReq miss cycles 2102system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 3788499 # number of SCUpgradeFailReq miss cycles 2103system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 3788499 # number of SCUpgradeFailReq miss cycles 2104system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 10033557499 # number of ReadExReq miss cycles 2105system.cpu1.l2cache.ReadExReq_miss_latency::total 10033557499 # number of ReadExReq miss cycles 2106system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 20842529000 # number of ReadCleanReq miss cycles 2107system.cpu1.l2cache.ReadCleanReq_miss_latency::total 20842529000 # number of ReadCleanReq miss cycles 2108system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 28170928990 # number of ReadSharedReq miss cycles 2109system.cpu1.l2cache.ReadSharedReq_miss_latency::total 28170928990 # number of ReadSharedReq miss cycles 2110system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 350412000 # number of InvalidateReq miss cycles 2111system.cpu1.l2cache.InvalidateReq_miss_latency::total 350412000 # number of InvalidateReq miss cycles 2112system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 391701000 # number of demand (read+write) miss cycles 2113system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 275187000 # number of demand (read+write) miss cycles 2114system.cpu1.l2cache.demand_miss_latency::cpu1.inst 20842529000 # number of demand (read+write) miss cycles 2115system.cpu1.l2cache.demand_miss_latency::cpu1.data 38204486489 # number of demand (read+write) miss cycles 2116system.cpu1.l2cache.demand_miss_latency::total 59713903489 # number of demand (read+write) miss cycles 2117system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 391701000 # number of overall miss cycles 2118system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 275187000 # number of overall miss cycles 2119system.cpu1.l2cache.overall_miss_latency::cpu1.inst 20842529000 # number of overall miss cycles 2120system.cpu1.l2cache.overall_miss_latency::cpu1.data 38204486489 # number of overall miss cycles 2121system.cpu1.l2cache.overall_miss_latency::total 59713903489 # number of overall miss cycles 2122system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 484387 # number of ReadReq accesses(hits+misses) 2123system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 163265 # number of ReadReq accesses(hits+misses) 2124system.cpu1.l2cache.ReadReq_accesses::total 647652 # number of ReadReq accesses(hits+misses) 2125system.cpu1.l2cache.WritebackDirty_accesses::writebacks 2939776 # number of WritebackDirty accesses(hits+misses) 2126system.cpu1.l2cache.WritebackDirty_accesses::total 2939776 # number of WritebackDirty accesses(hits+misses) 2127system.cpu1.l2cache.WritebackClean_accesses::writebacks 9733319 # number of WritebackClean accesses(hits+misses) 2128system.cpu1.l2cache.WritebackClean_accesses::total 9733319 # number of WritebackClean accesses(hits+misses) 2129system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 219279 # number of UpgradeReq accesses(hits+misses) 2130system.cpu1.l2cache.UpgradeReq_accesses::total 219279 # number of UpgradeReq accesses(hits+misses) 2131system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 184883 # number of SCUpgradeReq accesses(hits+misses) 2132system.cpu1.l2cache.SCUpgradeReq_accesses::total 184883 # number of SCUpgradeReq accesses(hits+misses) 2133system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 9 # number of SCUpgradeFailReq accesses(hits+misses) 2134system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 9 # number of SCUpgradeFailReq accesses(hits+misses) 2135system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1037856 # number of ReadExReq accesses(hits+misses) 2136system.cpu1.l2cache.ReadExReq_accesses::total 1037856 # number of ReadExReq accesses(hits+misses) 2137system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 8014908 # number of ReadCleanReq accesses(hits+misses) 2138system.cpu1.l2cache.ReadCleanReq_accesses::total 8014908 # number of ReadCleanReq accesses(hits+misses) 2139system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 3318214 # number of ReadSharedReq accesses(hits+misses) 2140system.cpu1.l2cache.ReadSharedReq_accesses::total 3318214 # number of ReadSharedReq accesses(hits+misses) 2141system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 398059 # number of InvalidateReq accesses(hits+misses) 2142system.cpu1.l2cache.InvalidateReq_accesses::total 398059 # number of InvalidateReq accesses(hits+misses) 2143system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 484387 # number of demand (read+write) accesses 2144system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 163265 # number of demand (read+write) accesses 2145system.cpu1.l2cache.demand_accesses::cpu1.inst 8014908 # number of demand (read+write) accesses 2146system.cpu1.l2cache.demand_accesses::cpu1.data 4356070 # number of demand (read+write) accesses 2147system.cpu1.l2cache.demand_accesses::total 13018630 # number of demand (read+write) accesses 2148system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 484387 # number of overall (read+write) accesses 2149system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 163265 # number of overall (read+write) accesses 2150system.cpu1.l2cache.overall_accesses::cpu1.inst 8014908 # number of overall (read+write) accesses 2151system.cpu1.l2cache.overall_accesses::cpu1.data 4356070 # number of overall (read+write) accesses 2152system.cpu1.l2cache.overall_accesses::total 13018630 # number of overall (read+write) accesses 2153system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.023236 # miss rate for ReadReq accesses 2154system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.048694 # miss rate for ReadReq accesses 2155system.cpu1.l2cache.ReadReq_miss_rate::total 0.029653 # miss rate for ReadReq accesses 2156system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.998117 # miss rate for UpgradeReq accesses 2157system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.998117 # miss rate for UpgradeReq accesses 2158system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses 2159system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 2160system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses 2161system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 2162system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.244911 # miss rate for ReadExReq accesses 2163system.cpu1.l2cache.ReadExReq_miss_rate::total 0.244911 # miss rate for ReadExReq accesses 2164system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.080980 # miss rate for ReadCleanReq accesses 2165system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.080980 # miss rate for ReadCleanReq accesses 2166system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.272262 # miss rate for ReadSharedReq accesses 2167system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.272262 # miss rate for ReadSharedReq accesses 2168system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.584815 # miss rate for InvalidateReq accesses 2169system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.584815 # miss rate for InvalidateReq accesses 2170system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.023236 # miss rate for demand accesses 2171system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.048694 # miss rate for demand accesses 2172system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.080980 # miss rate for demand accesses 2173system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.265745 # miss rate for demand accesses 2174system.cpu1.l2cache.demand_miss_rate::total 0.140250 # miss rate for demand accesses 2175system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.023236 # miss rate for overall accesses 2176system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.048694 # miss rate for overall accesses 2177system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.080980 # miss rate for overall accesses 2178system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.265745 # miss rate for overall accesses 2179system.cpu1.l2cache.overall_miss_rate::total 0.140250 # miss rate for overall accesses 2180system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 34802.398934 # average ReadReq miss latency 2181system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 34614.716981 # average ReadReq miss latency 2182system.cpu1.l2cache.ReadReq_avg_miss_latency::total 34724.707108 # average ReadReq miss latency 2183system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 8674.853563 # average UpgradeReq miss latency 2184system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 8674.853563 # average UpgradeReq miss latency 2185system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 7470.889698 # average SCUpgradeReq miss latency 2186system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 7470.889698 # average SCUpgradeReq miss latency 2187system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 420944.333333 # average SCUpgradeFailReq miss latency 2188system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 420944.333333 # average SCUpgradeFailReq miss latency 2189system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 39473.910422 # average ReadExReq miss latency 2190system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 39473.910422 # average ReadExReq miss latency 2191system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 32112.511112 # average ReadCleanReq miss latency 2192system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 32112.511112 # average ReadCleanReq miss latency 2193system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 31182.435017 # average ReadSharedReq miss latency 2194system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 31182.435017 # average ReadSharedReq miss latency 2195system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 1505.264379 # average InvalidateReq miss latency 2196system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 1505.264379 # average InvalidateReq miss latency 2197system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 34802.398934 # average overall miss latency 2198system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 34614.716981 # average overall miss latency 2199system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 32112.511112 # average overall miss latency 2200system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 33003.042047 # average overall miss latency 2201system.cpu1.l2cache.demand_avg_miss_latency::total 32704.589400 # average overall miss latency 2202system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 34802.398934 # average overall miss latency 2203system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 34614.716981 # average overall miss latency 2204system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 32112.511112 # average overall miss latency 2205system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 33003.042047 # average overall miss latency 2206system.cpu1.l2cache.overall_avg_miss_latency::total 32704.589400 # average overall miss latency 2207system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2208system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2209system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 2210system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 2211system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2212system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2213system.cpu1.l2cache.unused_prefetches 43626 # number of HardPF blocks evicted w/o reference 2214system.cpu1.l2cache.writebacks::writebacks 1060166 # number of writebacks 2215system.cpu1.l2cache.writebacks::total 1060166 # number of writebacks 2216system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker 1 # number of ReadReq MSHR hits 2217system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 5 # number of ReadReq MSHR hits 2218system.cpu1.l2cache.ReadReq_mshr_hits::total 6 # number of ReadReq MSHR hits 2219system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 5457 # number of ReadExReq MSHR hits 2220system.cpu1.l2cache.ReadExReq_mshr_hits::total 5457 # number of ReadExReq MSHR hits 2221system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst 3 # number of ReadCleanReq MSHR hits 2222system.cpu1.l2cache.ReadCleanReq_mshr_hits::total 3 # number of ReadCleanReq MSHR hits 2223system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 376 # number of ReadSharedReq MSHR hits 2224system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 376 # number of ReadSharedReq MSHR hits 2225system.cpu1.l2cache.InvalidateReq_mshr_hits::cpu1.data 5 # number of InvalidateReq MSHR hits 2226system.cpu1.l2cache.InvalidateReq_mshr_hits::total 5 # number of InvalidateReq MSHR hits 2227system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker 1 # number of demand (read+write) MSHR hits 2228system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 5 # number of demand (read+write) MSHR hits 2229system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 3 # number of demand (read+write) MSHR hits 2230system.cpu1.l2cache.demand_mshr_hits::cpu1.data 5833 # number of demand (read+write) MSHR hits 2231system.cpu1.l2cache.demand_mshr_hits::total 5842 # number of demand (read+write) MSHR hits 2232system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker 1 # number of overall MSHR hits 2233system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 5 # number of overall MSHR hits 2234system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 3 # number of overall MSHR hits 2235system.cpu1.l2cache.overall_mshr_hits::cpu1.data 5833 # number of overall MSHR hits 2236system.cpu1.l2cache.overall_mshr_hits::total 5842 # number of overall MSHR hits 2237system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 11254 # number of ReadReq MSHR misses 2238system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 7945 # number of ReadReq MSHR misses 2239system.cpu1.l2cache.ReadReq_mshr_misses::total 19199 # number of ReadReq MSHR misses 2240system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 690270 # number of HardPFReq MSHR misses 2241system.cpu1.l2cache.HardPFReq_mshr_misses::total 690270 # number of HardPFReq MSHR misses 2242system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 218866 # number of UpgradeReq MSHR misses 2243system.cpu1.l2cache.UpgradeReq_mshr_misses::total 218866 # number of UpgradeReq MSHR misses 2244system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 184883 # number of SCUpgradeReq MSHR misses 2245system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 184883 # number of SCUpgradeReq MSHR misses 2246system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 9 # number of SCUpgradeFailReq MSHR misses 2247system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 9 # number of SCUpgradeFailReq MSHR misses 2248system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 248725 # number of ReadExReq MSHR misses 2249system.cpu1.l2cache.ReadExReq_mshr_misses::total 248725 # number of ReadExReq MSHR misses 2250system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 649044 # number of ReadCleanReq MSHR misses 2251system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 649044 # number of ReadCleanReq MSHR misses 2252system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 903047 # number of ReadSharedReq MSHR misses 2253system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 903047 # number of ReadSharedReq MSHR misses 2254system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data 232786 # number of InvalidateReq MSHR misses 2255system.cpu1.l2cache.InvalidateReq_mshr_misses::total 232786 # number of InvalidateReq MSHR misses 2256system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 11254 # number of demand (read+write) MSHR misses 2257system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 7945 # number of demand (read+write) MSHR misses 2258system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 649044 # number of demand (read+write) MSHR misses 2259system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1151772 # number of demand (read+write) MSHR misses 2260system.cpu1.l2cache.demand_mshr_misses::total 1820015 # number of demand (read+write) MSHR misses 2261system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 11254 # number of overall MSHR misses 2262system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 7945 # number of overall MSHR misses 2263system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 649044 # number of overall MSHR misses 2264system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1151772 # number of overall MSHR misses 2265system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 690270 # number of overall MSHR misses 2266system.cpu1.l2cache.overall_mshr_misses::total 2510285 # number of overall MSHR misses 2267system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 95 # number of ReadReq MSHR uncacheable 2268system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 8793 # number of ReadReq MSHR uncacheable 2269system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 8888 # number of ReadReq MSHR uncacheable 2270system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 9091 # number of WriteReq MSHR uncacheable 2271system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 9091 # number of WriteReq MSHR uncacheable 2272system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 95 # number of overall MSHR uncacheable misses 2273system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 17884 # number of overall MSHR uncacheable misses 2274system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 17979 # number of overall MSHR uncacheable misses 2275system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 324079500 # number of ReadReq MSHR miss cycles 2276system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 227423500 # number of ReadReq MSHR miss cycles 2277system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 551503000 # number of ReadReq MSHR miss cycles 2278system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 26884842389 # number of HardPFReq MSHR miss cycles 2279system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 26884842389 # number of HardPFReq MSHR miss cycles 2280system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 4561523494 # number of UpgradeReq MSHR miss cycles 2281system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 4561523494 # number of UpgradeReq MSHR miss cycles 2282system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 2993192497 # number of SCUpgradeReq MSHR miss cycles 2283system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 2993192497 # number of SCUpgradeReq MSHR miss cycles 2284system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 3356499 # number of SCUpgradeFailReq MSHR miss cycles 2285system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 3356499 # number of SCUpgradeFailReq MSHR miss cycles 2286system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 7853418999 # number of ReadExReq MSHR miss cycles 2287system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 7853418999 # number of ReadExReq MSHR miss cycles 2288system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 16948153000 # number of ReadCleanReq MSHR miss cycles 2289system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 16948153000 # number of ReadCleanReq MSHR miss cycles 2290system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 22723854990 # number of ReadSharedReq MSHR miss cycles 2291system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 22723854990 # number of ReadSharedReq MSHR miss cycles 2292system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 6164226500 # number of InvalidateReq MSHR miss cycles 2293system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 6164226500 # number of InvalidateReq MSHR miss cycles 2294system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 324079500 # number of demand (read+write) MSHR miss cycles 2295system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 227423500 # number of demand (read+write) MSHR miss cycles 2296system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 16948153000 # number of demand (read+write) MSHR miss cycles 2297system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 30577273989 # number of demand (read+write) MSHR miss cycles 2298system.cpu1.l2cache.demand_mshr_miss_latency::total 48076929989 # number of demand (read+write) MSHR miss cycles 2299system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 324079500 # number of overall MSHR miss cycles 2300system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 227423500 # number of overall MSHR miss cycles 2301system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 16948153000 # number of overall MSHR miss cycles 2302system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 30577273989 # number of overall MSHR miss cycles 2303system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 26884842389 # number of overall MSHR miss cycles 2304system.cpu1.l2cache.overall_mshr_miss_latency::total 74961772378 # number of overall MSHR miss cycles 2305system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8006500 # number of ReadReq MSHR uncacheable cycles 2306system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 1234720500 # number of ReadReq MSHR uncacheable cycles 2307system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 1242727000 # number of ReadReq MSHR uncacheable cycles 2308system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 8006500 # number of overall MSHR uncacheable cycles 2309system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 1234720500 # number of overall MSHR uncacheable cycles 2310system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 1242727000 # number of overall MSHR uncacheable cycles 2311system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.023233 # mshr miss rate for ReadReq accesses 2312system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.048663 # mshr miss rate for ReadReq accesses 2313system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.029644 # mshr miss rate for ReadReq accesses 2314system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 2315system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 2316system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.998117 # mshr miss rate for UpgradeReq accesses 2317system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.998117 # mshr miss rate for UpgradeReq accesses 2318system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses 2319system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 2320system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses 2321system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 2322system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.239653 # mshr miss rate for ReadExReq accesses 2323system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.239653 # mshr miss rate for ReadExReq accesses 2324system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.080980 # mshr miss rate for ReadCleanReq accesses 2325system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.080980 # mshr miss rate for ReadCleanReq accesses 2326system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.272149 # mshr miss rate for ReadSharedReq accesses 2327system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.272149 # mshr miss rate for ReadSharedReq accesses 2328system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.584803 # mshr miss rate for InvalidateReq accesses 2329system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.584803 # mshr miss rate for InvalidateReq accesses 2330system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.023233 # mshr miss rate for demand accesses 2331system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.048663 # mshr miss rate for demand accesses 2332system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.080980 # mshr miss rate for demand accesses 2333system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.264406 # mshr miss rate for demand accesses 2334system.cpu1.l2cache.demand_mshr_miss_rate::total 0.139801 # mshr miss rate for demand accesses 2335system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.023233 # mshr miss rate for overall accesses 2336system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.048663 # mshr miss rate for overall accesses 2337system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.080980 # mshr miss rate for overall accesses 2338system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.264406 # mshr miss rate for overall accesses 2339system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses 2340system.cpu1.l2cache.overall_mshr_miss_rate::total 0.192823 # mshr miss rate for overall accesses 2341system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 28796.827795 # average ReadReq mshr miss latency 2342system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 28624.732536 # average ReadReq mshr miss latency 2343system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 28725.610709 # average ReadReq mshr miss latency 2344system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 38948.299055 # average HardPFReq mshr miss latency 2345system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 38948.299055 # average HardPFReq mshr miss latency 2346system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20841.626813 # average UpgradeReq mshr miss latency 2347system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20841.626813 # average UpgradeReq mshr miss latency 2348system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 16189.657767 # average SCUpgradeReq mshr miss latency 2349system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 16189.657767 # average SCUpgradeReq mshr miss latency 2350system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 372944.333333 # average SCUpgradeFailReq mshr miss latency 2351system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 372944.333333 # average SCUpgradeFailReq mshr miss latency 2352system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 31574.707002 # average ReadExReq mshr miss latency 2353system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 31574.707002 # average ReadExReq mshr miss latency 2354system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 26112.486981 # average ReadCleanReq mshr miss latency 2355system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 26112.486981 # average ReadCleanReq mshr miss latency 2356system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 25163.535220 # average ReadSharedReq mshr miss latency 2357system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 25163.535220 # average ReadSharedReq mshr miss latency 2358system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 26480.228622 # average InvalidateReq mshr miss latency 2359system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 26480.228622 # average InvalidateReq mshr miss latency 2360system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 28796.827795 # average overall mshr miss latency 2361system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 28624.732536 # average overall mshr miss latency 2362system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 26112.486981 # average overall mshr miss latency 2363system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 26548.026857 # average overall mshr miss latency 2364system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 26415.677887 # average overall mshr miss latency 2365system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 28796.827795 # average overall mshr miss latency 2366system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 28624.732536 # average overall mshr miss latency 2367system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 26112.486981 # average overall mshr miss latency 2368system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 26548.026857 # average overall mshr miss latency 2369system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 38948.299055 # average overall mshr miss latency 2370system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 29861.857270 # average overall mshr miss latency 2371system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 84278.947368 # average ReadReq mshr uncacheable latency 2372system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 140420.846128 # average ReadReq mshr uncacheable latency 2373system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 139820.769577 # average ReadReq mshr uncacheable latency 2374system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 84278.947368 # average overall mshr uncacheable latency 2375system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 69040.511071 # average overall mshr uncacheable latency 2376system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 69121.030091 # average overall mshr uncacheable latency 2377system.cpu1.toL2Bus.snoop_filter.tot_requests 26150144 # Total number of requests made to the snoop filter. 2378system.cpu1.toL2Bus.snoop_filter.hit_single_requests 13381244 # Number of requests hitting in the snoop filter with a single holder of the requested data. 2379system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 1981 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 2380system.cpu1.toL2Bus.snoop_filter.tot_snoops 1969364 # Total number of snoops made to the snoop filter. 2381system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 1969026 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 2382system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 338 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 2383system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states 2384system.cpu1.toL2Bus.trans_dist::ReadReq 732517 # Transaction distribution 2385system.cpu1.toL2Bus.trans_dist::ReadResp 12156991 # Transaction distribution 2386system.cpu1.toL2Bus.trans_dist::WriteReq 9091 # Transaction distribution 2387system.cpu1.toL2Bus.trans_dist::WriteResp 9091 # Transaction distribution 2388system.cpu1.toL2Bus.trans_dist::WritebackDirty 4007359 # Transaction distribution 2389system.cpu1.toL2Bus.trans_dist::WritebackClean 9735300 # Transaction distribution 2390system.cpu1.toL2Bus.trans_dist::CleanEvict 2694691 # Transaction distribution 2391system.cpu1.toL2Bus.trans_dist::HardPFReq 886167 # Transaction distribution 2392system.cpu1.toL2Bus.trans_dist::HardPFResp 3 # Transaction distribution 2393system.cpu1.toL2Bus.trans_dist::UpgradeReq 430328 # Transaction distribution 2394system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 337223 # Transaction distribution 2395system.cpu1.toL2Bus.trans_dist::UpgradeResp 468486 # Transaction distribution 2396system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 75 # Transaction distribution 2397system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 138 # Transaction distribution 2398system.cpu1.toL2Bus.trans_dist::ReadExReq 1067899 # Transaction distribution 2399system.cpu1.toL2Bus.trans_dist::ReadExResp 1044213 # Transaction distribution 2400system.cpu1.toL2Bus.trans_dist::ReadCleanReq 8014908 # Transaction distribution 2401system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4433895 # Transaction distribution 2402system.cpu1.toL2Bus.trans_dist::InvalidateReq 458319 # Transaction distribution 2403system.cpu1.toL2Bus.trans_dist::InvalidateResp 398059 # Transaction distribution 2404system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 24044391 # Packet count per connected master and slave (bytes) 2405system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 15175224 # Packet count per connected master and slave (bytes) 2406system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 343569 # Packet count per connected master and slave (bytes) 2407system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1027712 # Packet count per connected master and slave (bytes) 2408system.cpu1.toL2Bus.pkt_count::total 40590896 # Packet count per connected master and slave (bytes) 2409system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1025880832 # Cumulative packet size per connected master and slave (bytes) 2410system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 583383788 # Cumulative packet size per connected master and slave (bytes) 2411system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1306120 # Cumulative packet size per connected master and slave (bytes) 2412system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 3875096 # Cumulative packet size per connected master and slave (bytes) 2413system.cpu1.toL2Bus.pkt_size::total 1614445836 # Cumulative packet size per connected master and slave (bytes) 2414system.cpu1.toL2Bus.snoops 6456023 # Total snoops (count) 2415system.cpu1.toL2Bus.snoopTraffic 75189768 # Total snoop traffic (bytes) 2416system.cpu1.toL2Bus.snoop_fanout::samples 20132697 # Request fanout histogram 2417system.cpu1.toL2Bus.snoop_fanout::mean 0.112928 # Request fanout histogram 2418system.cpu1.toL2Bus.snoop_fanout::stdev 0.316558 # Request fanout histogram 2419system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2420system.cpu1.toL2Bus.snoop_fanout::0 17859482 88.71% 88.71% # Request fanout histogram 2421system.cpu1.toL2Bus.snoop_fanout::1 2272877 11.29% 100.00% # Request fanout histogram 2422system.cpu1.toL2Bus.snoop_fanout::2 338 0.00% 100.00% # Request fanout histogram 2423system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2424system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 2425system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 2426system.cpu1.toL2Bus.snoop_fanout::total 20132697 # Request fanout histogram 2427system.cpu1.toL2Bus.reqLayer0.occupancy 25974578977 # Layer occupancy (ticks) 2428system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 2429system.cpu1.toL2Bus.snoopLayer0.occupancy 179053447 # Layer occupancy (ticks) 2430system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 2431system.cpu1.toL2Bus.respLayer0.occupancy 12025219550 # Layer occupancy (ticks) 2432system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 2433system.cpu1.toL2Bus.respLayer1.occupancy 6952751265 # Layer occupancy (ticks) 2434system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 2435system.cpu1.toL2Bus.respLayer2.occupancy 180351405 # Layer occupancy (ticks) 2436system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 2437system.cpu1.toL2Bus.respLayer3.occupancy 543399850 # Layer occupancy (ticks) 2438system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 2439system.iobus.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states 2440system.iobus.trans_dist::ReadReq 40387 # Transaction distribution 2441system.iobus.trans_dist::ReadResp 40387 # Transaction distribution 2442system.iobus.trans_dist::WriteReq 136979 # Transaction distribution 2443system.iobus.trans_dist::WriteResp 136979 # Transaction distribution 2444system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47808 # Packet count per connected master and slave (bytes) 2445system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 2446system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 2447system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) 2448system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) 2449system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 2450system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 2451system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 2452system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 2453system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) 2454system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 2455system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29808 # Packet count per connected master and slave (bytes) 2456system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) 2457system.iobus.pkt_count_system.bridge.master::total 122950 # Packet count per connected master and slave (bytes) 2458system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231702 # Packet count per connected master and slave (bytes) 2459system.iobus.pkt_count_system.realview.ide.dma::total 231702 # Packet count per connected master and slave (bytes) 2460system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) 2461system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) 2462system.iobus.pkt_count::total 354732 # Packet count per connected master and slave (bytes) 2463system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47828 # Cumulative packet size per connected master and slave (bytes) 2464system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) 2465system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) 2466system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) 2467system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) 2468system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 2469system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2470system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2471system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2472system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) 2473system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2474system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17703 # Cumulative packet size per connected master and slave (bytes) 2475system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) 2476system.iobus.pkt_size_system.bridge.master::total 155965 # Cumulative packet size per connected master and slave (bytes) 2477system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7355160 # Cumulative packet size per connected master and slave (bytes) 2478system.iobus.pkt_size_system.realview.ide.dma::total 7355160 # Cumulative packet size per connected master and slave (bytes) 2479system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 2480system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) 2481system.iobus.pkt_size::total 7513211 # Cumulative packet size per connected master and slave (bytes) 2482system.iobus.reqLayer0.occupancy 42458502 # Layer occupancy (ticks) 2483system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 2484system.iobus.reqLayer1.occupancy 11500 # Layer occupancy (ticks) 2485system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 2486system.iobus.reqLayer2.occupancy 311001 # Layer occupancy (ticks) 2487system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 2488system.iobus.reqLayer3.occupancy 9000 # Layer occupancy (ticks) 2489system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 2490system.iobus.reqLayer4.occupancy 9000 # Layer occupancy (ticks) 2491system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 2492system.iobus.reqLayer10.occupancy 9500 # Layer occupancy (ticks) 2493system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 2494system.iobus.reqLayer13.occupancy 10500 # Layer occupancy (ticks) 2495system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 2496system.iobus.reqLayer14.occupancy 10000 # Layer occupancy (ticks) 2497system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 2498system.iobus.reqLayer15.occupancy 9500 # Layer occupancy (ticks) 2499system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 2500system.iobus.reqLayer16.occupancy 15000 # Layer occupancy (ticks) 2501system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 2502system.iobus.reqLayer17.occupancy 9000 # Layer occupancy (ticks) 2503system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 2504system.iobus.reqLayer23.occupancy 26063002 # Layer occupancy (ticks) 2505system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 2506system.iobus.reqLayer24.occupancy 34444001 # Layer occupancy (ticks) 2507system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 2508system.iobus.reqLayer25.occupancy 570734934 # Layer occupancy (ticks) 2509system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 2510system.iobus.respLayer0.occupancy 92958000 # Layer occupancy (ticks) 2511system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 2512system.iobus.respLayer3.occupancy 148142000 # Layer occupancy (ticks) 2513system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 2514system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) 2515system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) 2516system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states 2517system.iocache.tags.replacements 115832 # number of replacements 2518system.iocache.tags.tagsinuse 11.305903 # Cycle average of tags in use 2519system.iocache.tags.total_refs 3 # Total number of references to valid blocks. 2520system.iocache.tags.sampled_refs 115848 # Sample count of references to valid blocks. 2521system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. 2522system.iocache.tags.warmup_cycle 9127528857000 # Cycle when the warmup percentage was hit. 2523system.iocache.tags.occ_blocks::realview.ethernet 3.833923 # Average occupied blocks per requestor 2524system.iocache.tags.occ_blocks::realview.ide 7.471980 # Average occupied blocks per requestor 2525system.iocache.tags.occ_percent::realview.ethernet 0.239620 # Average percentage of cache occupancy 2526system.iocache.tags.occ_percent::realview.ide 0.466999 # Average percentage of cache occupancy 2527system.iocache.tags.occ_percent::total 0.706619 # Average percentage of cache occupancy 2528system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 2529system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 2530system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 2531system.iocache.tags.tag_accesses 1043016 # Number of tag accesses 2532system.iocache.tags.data_accesses 1043016 # Number of data accesses 2533system.iocache.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states 2534system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses 2535system.iocache.ReadReq_misses::realview.ide 8867 # number of ReadReq misses 2536system.iocache.ReadReq_misses::total 8904 # number of ReadReq misses 2537system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 2538system.iocache.WriteReq_misses::total 3 # number of WriteReq misses 2539system.iocache.WriteLineReq_misses::realview.ide 106984 # number of WriteLineReq misses 2540system.iocache.WriteLineReq_misses::total 106984 # number of WriteLineReq misses 2541system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses 2542system.iocache.demand_misses::realview.ide 115851 # number of demand (read+write) misses 2543system.iocache.demand_misses::total 115891 # number of demand (read+write) misses 2544system.iocache.overall_misses::realview.ethernet 40 # number of overall misses 2545system.iocache.overall_misses::realview.ide 115851 # number of overall misses 2546system.iocache.overall_misses::total 115891 # number of overall misses 2547system.iocache.ReadReq_miss_latency::realview.ethernet 5198000 # number of ReadReq miss cycles 2548system.iocache.ReadReq_miss_latency::realview.ide 1647274031 # number of ReadReq miss cycles 2549system.iocache.ReadReq_miss_latency::total 1652472031 # number of ReadReq miss cycles 2550system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles 2551system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles 2552system.iocache.WriteLineReq_miss_latency::realview.ide 12886794903 # number of WriteLineReq miss cycles 2553system.iocache.WriteLineReq_miss_latency::total 12886794903 # number of WriteLineReq miss cycles 2554system.iocache.demand_miss_latency::realview.ethernet 5567000 # number of demand (read+write) miss cycles 2555system.iocache.demand_miss_latency::realview.ide 14534068934 # number of demand (read+write) miss cycles 2556system.iocache.demand_miss_latency::total 14539635934 # number of demand (read+write) miss cycles 2557system.iocache.overall_miss_latency::realview.ethernet 5567000 # number of overall miss cycles 2558system.iocache.overall_miss_latency::realview.ide 14534068934 # number of overall miss cycles 2559system.iocache.overall_miss_latency::total 14539635934 # number of overall miss cycles 2560system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) 2561system.iocache.ReadReq_accesses::realview.ide 8867 # number of ReadReq accesses(hits+misses) 2562system.iocache.ReadReq_accesses::total 8904 # number of ReadReq accesses(hits+misses) 2563system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 2564system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 2565system.iocache.WriteLineReq_accesses::realview.ide 106984 # number of WriteLineReq accesses(hits+misses) 2566system.iocache.WriteLineReq_accesses::total 106984 # number of WriteLineReq accesses(hits+misses) 2567system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses 2568system.iocache.demand_accesses::realview.ide 115851 # number of demand (read+write) accesses 2569system.iocache.demand_accesses::total 115891 # number of demand (read+write) accesses 2570system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses 2571system.iocache.overall_accesses::realview.ide 115851 # number of overall (read+write) accesses 2572system.iocache.overall_accesses::total 115891 # number of overall (read+write) accesses 2573system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 2574system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 2575system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 2576system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 2577system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 2578system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 2579system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 2580system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses 2581system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 2582system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 2583system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses 2584system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 2585system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 2586system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140486.486486 # average ReadReq miss latency 2587system.iocache.ReadReq_avg_miss_latency::realview.ide 185775.801398 # average ReadReq miss latency 2588system.iocache.ReadReq_avg_miss_latency::total 185587.604560 # average ReadReq miss latency 2589system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency 2590system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency 2591system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120455.347557 # average WriteLineReq miss latency 2592system.iocache.WriteLineReq_avg_miss_latency::total 120455.347557 # average WriteLineReq miss latency 2593system.iocache.demand_avg_miss_latency::realview.ethernet 139175 # average overall miss latency 2594system.iocache.demand_avg_miss_latency::realview.ide 125454.842289 # average overall miss latency 2595system.iocache.demand_avg_miss_latency::total 125459.577827 # average overall miss latency 2596system.iocache.overall_avg_miss_latency::realview.ethernet 139175 # average overall miss latency 2597system.iocache.overall_avg_miss_latency::realview.ide 125454.842289 # average overall miss latency 2598system.iocache.overall_avg_miss_latency::total 125459.577827 # average overall miss latency 2599system.iocache.blocked_cycles::no_mshrs 32243 # number of cycles access was blocked 2600system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2601system.iocache.blocked::no_mshrs 3515 # number of cycles access was blocked 2602system.iocache.blocked::no_targets 0 # number of cycles access was blocked 2603system.iocache.avg_blocked_cycles::no_mshrs 9.172973 # average number of cycles each access was blocked 2604system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2605system.iocache.writebacks::writebacks 106950 # number of writebacks 2606system.iocache.writebacks::total 106950 # number of writebacks 2607system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses 2608system.iocache.ReadReq_mshr_misses::realview.ide 8867 # number of ReadReq MSHR misses 2609system.iocache.ReadReq_mshr_misses::total 8904 # number of ReadReq MSHR misses 2610system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses 2611system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses 2612system.iocache.WriteLineReq_mshr_misses::realview.ide 106984 # number of WriteLineReq MSHR misses 2613system.iocache.WriteLineReq_mshr_misses::total 106984 # number of WriteLineReq MSHR misses 2614system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses 2615system.iocache.demand_mshr_misses::realview.ide 115851 # number of demand (read+write) MSHR misses 2616system.iocache.demand_mshr_misses::total 115891 # number of demand (read+write) MSHR misses 2617system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses 2618system.iocache.overall_mshr_misses::realview.ide 115851 # number of overall MSHR misses 2619system.iocache.overall_mshr_misses::total 115891 # number of overall MSHR misses 2620system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3348000 # number of ReadReq MSHR miss cycles 2621system.iocache.ReadReq_mshr_miss_latency::realview.ide 1203924031 # number of ReadReq MSHR miss cycles 2622system.iocache.ReadReq_mshr_miss_latency::total 1207272031 # number of ReadReq MSHR miss cycles 2623system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles 2624system.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles 2625system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7528956843 # number of WriteLineReq MSHR miss cycles 2626system.iocache.WriteLineReq_mshr_miss_latency::total 7528956843 # number of WriteLineReq MSHR miss cycles 2627system.iocache.demand_mshr_miss_latency::realview.ethernet 3567000 # number of demand (read+write) MSHR miss cycles 2628system.iocache.demand_mshr_miss_latency::realview.ide 8732880874 # number of demand (read+write) MSHR miss cycles 2629system.iocache.demand_mshr_miss_latency::total 8736447874 # number of demand (read+write) MSHR miss cycles 2630system.iocache.overall_mshr_miss_latency::realview.ethernet 3567000 # number of overall MSHR miss cycles 2631system.iocache.overall_mshr_miss_latency::realview.ide 8732880874 # number of overall MSHR miss cycles 2632system.iocache.overall_mshr_miss_latency::total 8736447874 # number of overall MSHR miss cycles 2633system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses 2634system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 2635system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 2636system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses 2637system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 2638system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 2639system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 2640system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses 2641system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 2642system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 2643system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses 2644system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 2645system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 2646system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90486.486486 # average ReadReq mshr miss latency 2647system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 135775.801398 # average ReadReq mshr miss latency 2648system.iocache.ReadReq_avg_mshr_miss_latency::total 135587.604560 # average ReadReq mshr miss latency 2649system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency 2650system.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency 2651system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70374.605950 # average WriteLineReq mshr miss latency 2652system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70374.605950 # average WriteLineReq mshr miss latency 2653system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89175 # average overall mshr miss latency 2654system.iocache.demand_avg_mshr_miss_latency::realview.ide 75380.280481 # average overall mshr miss latency 2655system.iocache.demand_avg_mshr_miss_latency::total 75385.041755 # average overall mshr miss latency 2656system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89175 # average overall mshr miss latency 2657system.iocache.overall_avg_mshr_miss_latency::realview.ide 75380.280481 # average overall mshr miss latency 2658system.iocache.overall_avg_mshr_miss_latency::total 75385.041755 # average overall mshr miss latency 2659system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states 2660system.l2c.tags.replacements 1436798 # number of replacements 2661system.l2c.tags.tagsinuse 63641.257392 # Cycle average of tags in use 2662system.l2c.tags.total_refs 6808742 # Total number of references to valid blocks. 2663system.l2c.tags.sampled_refs 1497176 # Sample count of references to valid blocks. 2664system.l2c.tags.avg_refs 4.547723 # Average number of references to valid blocks. 2665system.l2c.tags.warmup_cycle 8050623000 # Cycle when the warmup percentage was hit. 2666system.l2c.tags.occ_blocks::writebacks 20256.980304 # Average occupied blocks per requestor 2667system.l2c.tags.occ_blocks::cpu0.dtb.walker 307.265586 # Average occupied blocks per requestor 2668system.l2c.tags.occ_blocks::cpu0.itb.walker 477.600666 # Average occupied blocks per requestor 2669system.l2c.tags.occ_blocks::cpu0.inst 6075.269789 # Average occupied blocks per requestor 2670system.l2c.tags.occ_blocks::cpu0.data 12531.509900 # Average occupied blocks per requestor 2671system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 19419.437449 # Average occupied blocks per requestor 2672system.l2c.tags.occ_blocks::cpu1.dtb.walker 11.305032 # Average occupied blocks per requestor 2673system.l2c.tags.occ_blocks::cpu1.itb.walker 4.128844 # Average occupied blocks per requestor 2674system.l2c.tags.occ_blocks::cpu1.inst 2389.320183 # Average occupied blocks per requestor 2675system.l2c.tags.occ_blocks::cpu1.data 1436.582929 # Average occupied blocks per requestor 2676system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 731.856711 # Average occupied blocks per requestor 2677system.l2c.tags.occ_percent::writebacks 0.309097 # Average percentage of cache occupancy 2678system.l2c.tags.occ_percent::cpu0.dtb.walker 0.004689 # Average percentage of cache occupancy 2679system.l2c.tags.occ_percent::cpu0.itb.walker 0.007288 # Average percentage of cache occupancy 2680system.l2c.tags.occ_percent::cpu0.inst 0.092701 # Average percentage of cache occupancy 2681system.l2c.tags.occ_percent::cpu0.data 0.191216 # Average percentage of cache occupancy 2682system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.296317 # Average percentage of cache occupancy 2683system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000173 # Average percentage of cache occupancy 2684system.l2c.tags.occ_percent::cpu1.itb.walker 0.000063 # Average percentage of cache occupancy 2685system.l2c.tags.occ_percent::cpu1.inst 0.036458 # Average percentage of cache occupancy 2686system.l2c.tags.occ_percent::cpu1.data 0.021921 # Average percentage of cache occupancy 2687system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.011167 # Average percentage of cache occupancy 2688system.l2c.tags.occ_percent::total 0.971089 # Average percentage of cache occupancy 2689system.l2c.tags.occ_task_id_blocks::1022 10768 # Occupied blocks per task id 2690system.l2c.tags.occ_task_id_blocks::1023 197 # Occupied blocks per task id 2691system.l2c.tags.occ_task_id_blocks::1024 49413 # Occupied blocks per task id 2692system.l2c.tags.age_task_id_blocks_1022::1 9 # Occupied blocks per task id 2693system.l2c.tags.age_task_id_blocks_1022::2 162 # Occupied blocks per task id 2694system.l2c.tags.age_task_id_blocks_1022::3 3598 # Occupied blocks per task id 2695system.l2c.tags.age_task_id_blocks_1022::4 6999 # Occupied blocks per task id 2696system.l2c.tags.age_task_id_blocks_1023::3 18 # Occupied blocks per task id 2697system.l2c.tags.age_task_id_blocks_1023::4 179 # Occupied blocks per task id 2698system.l2c.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id 2699system.l2c.tags.age_task_id_blocks_1024::1 298 # Occupied blocks per task id 2700system.l2c.tags.age_task_id_blocks_1024::2 2209 # Occupied blocks per task id 2701system.l2c.tags.age_task_id_blocks_1024::3 15374 # Occupied blocks per task id 2702system.l2c.tags.age_task_id_blocks_1024::4 31482 # Occupied blocks per task id 2703system.l2c.tags.occ_task_id_percent::1022 0.164307 # Percentage of cache occupancy per task id 2704system.l2c.tags.occ_task_id_percent::1023 0.003006 # Percentage of cache occupancy per task id 2705system.l2c.tags.occ_task_id_percent::1024 0.753983 # Percentage of cache occupancy per task id 2706system.l2c.tags.tag_accesses 82887108 # Number of tag accesses 2707system.l2c.tags.data_accesses 82887108 # Number of data accesses 2708system.l2c.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states 2709system.l2c.WritebackDirty_hits::writebacks 2851442 # number of WritebackDirty hits 2710system.l2c.WritebackDirty_hits::total 2851442 # number of WritebackDirty hits 2711system.l2c.UpgradeReq_hits::cpu0.data 184675 # number of UpgradeReq hits 2712system.l2c.UpgradeReq_hits::cpu1.data 129782 # number of UpgradeReq hits 2713system.l2c.UpgradeReq_hits::total 314457 # number of UpgradeReq hits 2714system.l2c.SCUpgradeReq_hits::cpu0.data 47164 # number of SCUpgradeReq hits 2715system.l2c.SCUpgradeReq_hits::cpu1.data 36238 # number of SCUpgradeReq hits 2716system.l2c.SCUpgradeReq_hits::total 83402 # number of SCUpgradeReq hits 2717system.l2c.ReadExReq_hits::cpu0.data 58975 # number of ReadExReq hits 2718system.l2c.ReadExReq_hits::cpu1.data 57393 # number of ReadExReq hits 2719system.l2c.ReadExReq_hits::total 116368 # number of ReadExReq hits 2720system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 7045 # number of ReadSharedReq hits 2721system.l2c.ReadSharedReq_hits::cpu0.itb.walker 4376 # number of ReadSharedReq hits 2722system.l2c.ReadSharedReq_hits::cpu0.inst 746247 # number of ReadSharedReq hits 2723system.l2c.ReadSharedReq_hits::cpu0.data 677498 # number of ReadSharedReq hits 2724system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 343450 # number of ReadSharedReq hits 2725system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 6710 # number of ReadSharedReq hits 2726system.l2c.ReadSharedReq_hits::cpu1.itb.walker 4818 # number of ReadSharedReq hits 2727system.l2c.ReadSharedReq_hits::cpu1.inst 604538 # number of ReadSharedReq hits 2728system.l2c.ReadSharedReq_hits::cpu1.data 564393 # number of ReadSharedReq hits 2729system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 306025 # number of ReadSharedReq hits 2730system.l2c.ReadSharedReq_hits::total 3265100 # number of ReadSharedReq hits 2731system.l2c.InvalidateReq_hits::cpu0.data 138219 # number of InvalidateReq hits 2732system.l2c.InvalidateReq_hits::cpu1.data 125546 # number of InvalidateReq hits 2733system.l2c.InvalidateReq_hits::total 263765 # number of InvalidateReq hits 2734system.l2c.demand_hits::cpu0.dtb.walker 7045 # number of demand (read+write) hits 2735system.l2c.demand_hits::cpu0.itb.walker 4376 # number of demand (read+write) hits 2736system.l2c.demand_hits::cpu0.inst 746247 # number of demand (read+write) hits 2737system.l2c.demand_hits::cpu0.data 736473 # number of demand (read+write) hits 2738system.l2c.demand_hits::cpu0.l2cache.prefetcher 343450 # number of demand (read+write) hits 2739system.l2c.demand_hits::cpu1.dtb.walker 6710 # number of demand (read+write) hits 2740system.l2c.demand_hits::cpu1.itb.walker 4818 # number of demand (read+write) hits 2741system.l2c.demand_hits::cpu1.inst 604538 # number of demand (read+write) hits 2742system.l2c.demand_hits::cpu1.data 621786 # number of demand (read+write) hits 2743system.l2c.demand_hits::cpu1.l2cache.prefetcher 306025 # number of demand (read+write) hits 2744system.l2c.demand_hits::total 3381468 # number of demand (read+write) hits 2745system.l2c.overall_hits::cpu0.dtb.walker 7045 # number of overall hits 2746system.l2c.overall_hits::cpu0.itb.walker 4376 # number of overall hits 2747system.l2c.overall_hits::cpu0.inst 746247 # number of overall hits 2748system.l2c.overall_hits::cpu0.data 736473 # number of overall hits 2749system.l2c.overall_hits::cpu0.l2cache.prefetcher 343450 # number of overall hits 2750system.l2c.overall_hits::cpu1.dtb.walker 6710 # number of overall hits 2751system.l2c.overall_hits::cpu1.itb.walker 4818 # number of overall hits 2752system.l2c.overall_hits::cpu1.inst 604538 # number of overall hits 2753system.l2c.overall_hits::cpu1.data 621786 # number of overall hits 2754system.l2c.overall_hits::cpu1.l2cache.prefetcher 306025 # number of overall hits 2755system.l2c.overall_hits::total 3381468 # number of overall hits 2756system.l2c.UpgradeReq_misses::cpu0.data 65595 # number of UpgradeReq misses 2757system.l2c.UpgradeReq_misses::cpu1.data 60730 # number of UpgradeReq misses 2758system.l2c.UpgradeReq_misses::total 126325 # number of UpgradeReq misses 2759system.l2c.SCUpgradeReq_misses::cpu0.data 12636 # number of SCUpgradeReq misses 2760system.l2c.SCUpgradeReq_misses::cpu1.data 10558 # number of SCUpgradeReq misses 2761system.l2c.SCUpgradeReq_misses::total 23194 # number of SCUpgradeReq misses 2762system.l2c.ReadExReq_misses::cpu0.data 86809 # number of ReadExReq misses 2763system.l2c.ReadExReq_misses::cpu1.data 47256 # number of ReadExReq misses 2764system.l2c.ReadExReq_misses::total 134065 # number of ReadExReq misses 2765system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 2557 # number of ReadSharedReq misses 2766system.l2c.ReadSharedReq_misses::cpu0.itb.walker 2464 # number of ReadSharedReq misses 2767system.l2c.ReadSharedReq_misses::cpu0.inst 78739 # number of ReadSharedReq misses 2768system.l2c.ReadSharedReq_misses::cpu0.data 176748 # number of ReadSharedReq misses 2769system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 289930 # number of ReadSharedReq misses 2770system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 1566 # number of ReadSharedReq misses 2771system.l2c.ReadSharedReq_misses::cpu1.itb.walker 1157 # number of ReadSharedReq misses 2772system.l2c.ReadSharedReq_misses::cpu1.inst 44505 # number of ReadSharedReq misses 2773system.l2c.ReadSharedReq_misses::cpu1.data 80821 # number of ReadSharedReq misses 2774system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 170404 # number of ReadSharedReq misses 2775system.l2c.ReadSharedReq_misses::total 848891 # number of ReadSharedReq misses 2776system.l2c.InvalidateReq_misses::cpu0.data 477170 # number of InvalidateReq misses 2777system.l2c.InvalidateReq_misses::cpu1.data 94656 # number of InvalidateReq misses 2778system.l2c.InvalidateReq_misses::total 571826 # number of InvalidateReq misses 2779system.l2c.demand_misses::cpu0.dtb.walker 2557 # number of demand (read+write) misses 2780system.l2c.demand_misses::cpu0.itb.walker 2464 # number of demand (read+write) misses 2781system.l2c.demand_misses::cpu0.inst 78739 # number of demand (read+write) misses 2782system.l2c.demand_misses::cpu0.data 263557 # number of demand (read+write) misses 2783system.l2c.demand_misses::cpu0.l2cache.prefetcher 289930 # number of demand (read+write) misses 2784system.l2c.demand_misses::cpu1.dtb.walker 1566 # number of demand (read+write) misses 2785system.l2c.demand_misses::cpu1.itb.walker 1157 # number of demand (read+write) misses 2786system.l2c.demand_misses::cpu1.inst 44505 # number of demand (read+write) misses 2787system.l2c.demand_misses::cpu1.data 128077 # number of demand (read+write) misses 2788system.l2c.demand_misses::cpu1.l2cache.prefetcher 170404 # number of demand (read+write) misses 2789system.l2c.demand_misses::total 982956 # number of demand (read+write) misses 2790system.l2c.overall_misses::cpu0.dtb.walker 2557 # number of overall misses 2791system.l2c.overall_misses::cpu0.itb.walker 2464 # number of overall misses 2792system.l2c.overall_misses::cpu0.inst 78739 # number of overall misses 2793system.l2c.overall_misses::cpu0.data 263557 # number of overall misses 2794system.l2c.overall_misses::cpu0.l2cache.prefetcher 289930 # number of overall misses 2795system.l2c.overall_misses::cpu1.dtb.walker 1566 # number of overall misses 2796system.l2c.overall_misses::cpu1.itb.walker 1157 # number of overall misses 2797system.l2c.overall_misses::cpu1.inst 44505 # number of overall misses 2798system.l2c.overall_misses::cpu1.data 128077 # number of overall misses 2799system.l2c.overall_misses::cpu1.l2cache.prefetcher 170404 # number of overall misses 2800system.l2c.overall_misses::total 982956 # number of overall misses 2801system.l2c.UpgradeReq_miss_latency::cpu0.data 456935000 # number of UpgradeReq miss cycles 2802system.l2c.UpgradeReq_miss_latency::cpu1.data 428124500 # number of UpgradeReq miss cycles 2803system.l2c.UpgradeReq_miss_latency::total 885059500 # number of UpgradeReq miss cycles 2804system.l2c.SCUpgradeReq_miss_latency::cpu0.data 88094500 # number of SCUpgradeReq miss cycles 2805system.l2c.SCUpgradeReq_miss_latency::cpu1.data 70625000 # number of SCUpgradeReq miss cycles 2806system.l2c.SCUpgradeReq_miss_latency::total 158719500 # number of SCUpgradeReq miss cycles 2807system.l2c.ReadExReq_miss_latency::cpu0.data 7719270500 # number of ReadExReq miss cycles 2808system.l2c.ReadExReq_miss_latency::cpu1.data 3911139500 # number of ReadExReq miss cycles 2809system.l2c.ReadExReq_miss_latency::total 11630410000 # number of ReadExReq miss cycles 2810system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 226838000 # number of ReadSharedReq miss cycles 2811system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 219007500 # number of ReadSharedReq miss cycles 2812system.l2c.ReadSharedReq_miss_latency::cpu0.inst 6705086500 # number of ReadSharedReq miss cycles 2813system.l2c.ReadSharedReq_miss_latency::cpu0.data 15776824000 # number of ReadSharedReq miss cycles 2814system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 36609242451 # number of ReadSharedReq miss cycles 2815system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 145187000 # number of ReadSharedReq miss cycles 2816system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 107589500 # number of ReadSharedReq miss cycles 2817system.l2c.ReadSharedReq_miss_latency::cpu1.inst 3760779000 # number of ReadSharedReq miss cycles 2818system.l2c.ReadSharedReq_miss_latency::cpu1.data 7519043500 # number of ReadSharedReq miss cycles 2819system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 21421936717 # number of ReadSharedReq miss cycles 2820system.l2c.ReadSharedReq_miss_latency::total 92491534168 # number of ReadSharedReq miss cycles 2821system.l2c.InvalidateReq_miss_latency::cpu0.data 63068500 # number of InvalidateReq miss cycles 2822system.l2c.InvalidateReq_miss_latency::cpu1.data 48974000 # number of InvalidateReq miss cycles 2823system.l2c.InvalidateReq_miss_latency::total 112042500 # number of InvalidateReq miss cycles 2824system.l2c.demand_miss_latency::cpu0.dtb.walker 226838000 # number of demand (read+write) miss cycles 2825system.l2c.demand_miss_latency::cpu0.itb.walker 219007500 # number of demand (read+write) miss cycles 2826system.l2c.demand_miss_latency::cpu0.inst 6705086500 # number of demand (read+write) miss cycles 2827system.l2c.demand_miss_latency::cpu0.data 23496094500 # number of demand (read+write) miss cycles 2828system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 36609242451 # number of demand (read+write) miss cycles 2829system.l2c.demand_miss_latency::cpu1.dtb.walker 145187000 # number of demand (read+write) miss cycles 2830system.l2c.demand_miss_latency::cpu1.itb.walker 107589500 # number of demand (read+write) miss cycles 2831system.l2c.demand_miss_latency::cpu1.inst 3760779000 # number of demand (read+write) miss cycles 2832system.l2c.demand_miss_latency::cpu1.data 11430183000 # number of demand (read+write) miss cycles 2833system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 21421936717 # number of demand (read+write) miss cycles 2834system.l2c.demand_miss_latency::total 104121944168 # number of demand (read+write) miss cycles 2835system.l2c.overall_miss_latency::cpu0.dtb.walker 226838000 # number of overall miss cycles 2836system.l2c.overall_miss_latency::cpu0.itb.walker 219007500 # number of overall miss cycles 2837system.l2c.overall_miss_latency::cpu0.inst 6705086500 # number of overall miss cycles 2838system.l2c.overall_miss_latency::cpu0.data 23496094500 # number of overall miss cycles 2839system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 36609242451 # number of overall miss cycles 2840system.l2c.overall_miss_latency::cpu1.dtb.walker 145187000 # number of overall miss cycles 2841system.l2c.overall_miss_latency::cpu1.itb.walker 107589500 # number of overall miss cycles 2842system.l2c.overall_miss_latency::cpu1.inst 3760779000 # number of overall miss cycles 2843system.l2c.overall_miss_latency::cpu1.data 11430183000 # number of overall miss cycles 2844system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 21421936717 # number of overall miss cycles 2845system.l2c.overall_miss_latency::total 104121944168 # number of overall miss cycles 2846system.l2c.WritebackDirty_accesses::writebacks 2851442 # number of WritebackDirty accesses(hits+misses) 2847system.l2c.WritebackDirty_accesses::total 2851442 # number of WritebackDirty accesses(hits+misses) 2848system.l2c.UpgradeReq_accesses::cpu0.data 250270 # number of UpgradeReq accesses(hits+misses) 2849system.l2c.UpgradeReq_accesses::cpu1.data 190512 # number of UpgradeReq accesses(hits+misses) 2850system.l2c.UpgradeReq_accesses::total 440782 # number of UpgradeReq accesses(hits+misses) 2851system.l2c.SCUpgradeReq_accesses::cpu0.data 59800 # number of SCUpgradeReq accesses(hits+misses) 2852system.l2c.SCUpgradeReq_accesses::cpu1.data 46796 # number of SCUpgradeReq accesses(hits+misses) 2853system.l2c.SCUpgradeReq_accesses::total 106596 # number of SCUpgradeReq accesses(hits+misses) 2854system.l2c.ReadExReq_accesses::cpu0.data 145784 # number of ReadExReq accesses(hits+misses) 2855system.l2c.ReadExReq_accesses::cpu1.data 104649 # number of ReadExReq accesses(hits+misses) 2856system.l2c.ReadExReq_accesses::total 250433 # number of ReadExReq accesses(hits+misses) 2857system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 9602 # number of ReadSharedReq accesses(hits+misses) 2858system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 6840 # number of ReadSharedReq accesses(hits+misses) 2859system.l2c.ReadSharedReq_accesses::cpu0.inst 824986 # number of ReadSharedReq accesses(hits+misses) 2860system.l2c.ReadSharedReq_accesses::cpu0.data 854246 # number of ReadSharedReq accesses(hits+misses) 2861system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 633380 # number of ReadSharedReq accesses(hits+misses) 2862system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 8276 # number of ReadSharedReq accesses(hits+misses) 2863system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 5975 # number of ReadSharedReq accesses(hits+misses) 2864system.l2c.ReadSharedReq_accesses::cpu1.inst 649043 # number of ReadSharedReq accesses(hits+misses) 2865system.l2c.ReadSharedReq_accesses::cpu1.data 645214 # number of ReadSharedReq accesses(hits+misses) 2866system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 476429 # number of ReadSharedReq accesses(hits+misses) 2867system.l2c.ReadSharedReq_accesses::total 4113991 # number of ReadSharedReq accesses(hits+misses) 2868system.l2c.InvalidateReq_accesses::cpu0.data 615389 # number of InvalidateReq accesses(hits+misses) 2869system.l2c.InvalidateReq_accesses::cpu1.data 220202 # number of InvalidateReq accesses(hits+misses) 2870system.l2c.InvalidateReq_accesses::total 835591 # number of InvalidateReq accesses(hits+misses) 2871system.l2c.demand_accesses::cpu0.dtb.walker 9602 # number of demand (read+write) accesses 2872system.l2c.demand_accesses::cpu0.itb.walker 6840 # number of demand (read+write) accesses 2873system.l2c.demand_accesses::cpu0.inst 824986 # number of demand (read+write) accesses 2874system.l2c.demand_accesses::cpu0.data 1000030 # number of demand (read+write) accesses 2875system.l2c.demand_accesses::cpu0.l2cache.prefetcher 633380 # number of demand (read+write) accesses 2876system.l2c.demand_accesses::cpu1.dtb.walker 8276 # number of demand (read+write) accesses 2877system.l2c.demand_accesses::cpu1.itb.walker 5975 # number of demand (read+write) accesses 2878system.l2c.demand_accesses::cpu1.inst 649043 # number of demand (read+write) accesses 2879system.l2c.demand_accesses::cpu1.data 749863 # number of demand (read+write) accesses 2880system.l2c.demand_accesses::cpu1.l2cache.prefetcher 476429 # number of demand (read+write) accesses 2881system.l2c.demand_accesses::total 4364424 # number of demand (read+write) accesses 2882system.l2c.overall_accesses::cpu0.dtb.walker 9602 # number of overall (read+write) accesses 2883system.l2c.overall_accesses::cpu0.itb.walker 6840 # number of overall (read+write) accesses 2884system.l2c.overall_accesses::cpu0.inst 824986 # number of overall (read+write) accesses 2885system.l2c.overall_accesses::cpu0.data 1000030 # number of overall (read+write) accesses 2886system.l2c.overall_accesses::cpu0.l2cache.prefetcher 633380 # number of overall (read+write) accesses 2887system.l2c.overall_accesses::cpu1.dtb.walker 8276 # number of overall (read+write) accesses 2888system.l2c.overall_accesses::cpu1.itb.walker 5975 # number of overall (read+write) accesses 2889system.l2c.overall_accesses::cpu1.inst 649043 # number of overall (read+write) accesses 2890system.l2c.overall_accesses::cpu1.data 749863 # number of overall (read+write) accesses 2891system.l2c.overall_accesses::cpu1.l2cache.prefetcher 476429 # number of overall (read+write) accesses 2892system.l2c.overall_accesses::total 4364424 # number of overall (read+write) accesses 2893system.l2c.UpgradeReq_miss_rate::cpu0.data 0.262097 # miss rate for UpgradeReq accesses 2894system.l2c.UpgradeReq_miss_rate::cpu1.data 0.318773 # miss rate for UpgradeReq accesses 2895system.l2c.UpgradeReq_miss_rate::total 0.286593 # miss rate for UpgradeReq accesses 2896system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.211304 # miss rate for SCUpgradeReq accesses 2897system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.225618 # miss rate for SCUpgradeReq accesses 2898system.l2c.SCUpgradeReq_miss_rate::total 0.217588 # miss rate for SCUpgradeReq accesses 2899system.l2c.ReadExReq_miss_rate::cpu0.data 0.595463 # miss rate for ReadExReq accesses 2900system.l2c.ReadExReq_miss_rate::cpu1.data 0.451567 # miss rate for ReadExReq accesses 2901system.l2c.ReadExReq_miss_rate::total 0.535333 # miss rate for ReadExReq accesses 2902system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.266299 # miss rate for ReadSharedReq accesses 2903system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.360234 # miss rate for ReadSharedReq accesses 2904system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.095443 # miss rate for ReadSharedReq accesses 2905system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.206905 # miss rate for ReadSharedReq accesses 2906system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.457750 # miss rate for ReadSharedReq accesses 2907system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.189222 # miss rate for ReadSharedReq accesses 2908system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.193640 # miss rate for ReadSharedReq accesses 2909system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.068570 # miss rate for ReadSharedReq accesses 2910system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.125262 # miss rate for ReadSharedReq accesses 2911system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.357669 # miss rate for ReadSharedReq accesses 2912system.l2c.ReadSharedReq_miss_rate::total 0.206342 # miss rate for ReadSharedReq accesses 2913system.l2c.InvalidateReq_miss_rate::cpu0.data 0.775396 # miss rate for InvalidateReq accesses 2914system.l2c.InvalidateReq_miss_rate::cpu1.data 0.429860 # miss rate for InvalidateReq accesses 2915system.l2c.InvalidateReq_miss_rate::total 0.684337 # miss rate for InvalidateReq accesses 2916system.l2c.demand_miss_rate::cpu0.dtb.walker 0.266299 # miss rate for demand accesses 2917system.l2c.demand_miss_rate::cpu0.itb.walker 0.360234 # miss rate for demand accesses 2918system.l2c.demand_miss_rate::cpu0.inst 0.095443 # miss rate for demand accesses 2919system.l2c.demand_miss_rate::cpu0.data 0.263549 # miss rate for demand accesses 2920system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.457750 # miss rate for demand accesses 2921system.l2c.demand_miss_rate::cpu1.dtb.walker 0.189222 # miss rate for demand accesses 2922system.l2c.demand_miss_rate::cpu1.itb.walker 0.193640 # miss rate for demand accesses 2923system.l2c.demand_miss_rate::cpu1.inst 0.068570 # miss rate for demand accesses 2924system.l2c.demand_miss_rate::cpu1.data 0.170801 # miss rate for demand accesses 2925system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.357669 # miss rate for demand accesses 2926system.l2c.demand_miss_rate::total 0.225220 # miss rate for demand accesses 2927system.l2c.overall_miss_rate::cpu0.dtb.walker 0.266299 # miss rate for overall accesses 2928system.l2c.overall_miss_rate::cpu0.itb.walker 0.360234 # miss rate for overall accesses 2929system.l2c.overall_miss_rate::cpu0.inst 0.095443 # miss rate for overall accesses 2930system.l2c.overall_miss_rate::cpu0.data 0.263549 # miss rate for overall accesses 2931system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.457750 # miss rate for overall accesses 2932system.l2c.overall_miss_rate::cpu1.dtb.walker 0.189222 # miss rate for overall accesses 2933system.l2c.overall_miss_rate::cpu1.itb.walker 0.193640 # miss rate for overall accesses 2934system.l2c.overall_miss_rate::cpu1.inst 0.068570 # miss rate for overall accesses 2935system.l2c.overall_miss_rate::cpu1.data 0.170801 # miss rate for overall accesses 2936system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.357669 # miss rate for overall accesses 2937system.l2c.overall_miss_rate::total 0.225220 # miss rate for overall accesses 2938system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 6966.003506 # average UpgradeReq miss latency 2939system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 7049.637741 # average UpgradeReq miss latency 2940system.l2c.UpgradeReq_avg_miss_latency::total 7006.210172 # average UpgradeReq miss latency 2941system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 6971.707819 # average SCUpgradeReq miss latency 2942system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 6689.240386 # average SCUpgradeReq miss latency 2943system.l2c.SCUpgradeReq_avg_miss_latency::total 6843.127533 # average SCUpgradeReq miss latency 2944system.l2c.ReadExReq_avg_miss_latency::cpu0.data 88922.467716 # average ReadExReq miss latency 2945system.l2c.ReadExReq_avg_miss_latency::cpu1.data 82764.929321 # average ReadExReq miss latency 2946system.l2c.ReadExReq_avg_miss_latency::total 86752.023272 # average ReadExReq miss latency 2947system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 88712.553774 # average ReadSharedReq miss latency 2948system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 88882.913961 # average ReadSharedReq miss latency 2949system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 85155.850341 # average ReadSharedReq miss latency 2950system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 89261.683301 # average ReadSharedReq miss latency 2951system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 126269.245856 # average ReadSharedReq miss latency 2952system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 92712.005109 # average ReadSharedReq miss latency 2953system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 92990.060501 # average ReadSharedReq miss latency 2954system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 84502.392990 # average ReadSharedReq miss latency 2955system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 93033.289615 # average ReadSharedReq miss latency 2956system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 125712.640061 # average ReadSharedReq miss latency 2957system.l2c.ReadSharedReq_avg_miss_latency::total 108955.724784 # average ReadSharedReq miss latency 2958system.l2c.InvalidateReq_avg_miss_latency::cpu0.data 132.171972 # average InvalidateReq miss latency 2959system.l2c.InvalidateReq_avg_miss_latency::cpu1.data 517.389283 # average InvalidateReq miss latency 2960system.l2c.InvalidateReq_avg_miss_latency::total 195.938100 # average InvalidateReq miss latency 2961system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 88712.553774 # average overall miss latency 2962system.l2c.demand_avg_miss_latency::cpu0.itb.walker 88882.913961 # average overall miss latency 2963system.l2c.demand_avg_miss_latency::cpu0.inst 85155.850341 # average overall miss latency 2964system.l2c.demand_avg_miss_latency::cpu0.data 89149.954279 # average overall miss latency 2965system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 126269.245856 # average overall miss latency 2966system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 92712.005109 # average overall miss latency 2967system.l2c.demand_avg_miss_latency::cpu1.itb.walker 92990.060501 # average overall miss latency 2968system.l2c.demand_avg_miss_latency::cpu1.inst 84502.392990 # average overall miss latency 2969system.l2c.demand_avg_miss_latency::cpu1.data 89244.618472 # average overall miss latency 2970system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 125712.640061 # average overall miss latency 2971system.l2c.demand_avg_miss_latency::total 105927.370267 # average overall miss latency 2972system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 88712.553774 # average overall miss latency 2973system.l2c.overall_avg_miss_latency::cpu0.itb.walker 88882.913961 # average overall miss latency 2974system.l2c.overall_avg_miss_latency::cpu0.inst 85155.850341 # average overall miss latency 2975system.l2c.overall_avg_miss_latency::cpu0.data 89149.954279 # average overall miss latency 2976system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 126269.245856 # average overall miss latency 2977system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 92712.005109 # average overall miss latency 2978system.l2c.overall_avg_miss_latency::cpu1.itb.walker 92990.060501 # average overall miss latency 2979system.l2c.overall_avg_miss_latency::cpu1.inst 84502.392990 # average overall miss latency 2980system.l2c.overall_avg_miss_latency::cpu1.data 89244.618472 # average overall miss latency 2981system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 125712.640061 # average overall miss latency 2982system.l2c.overall_avg_miss_latency::total 105927.370267 # average overall miss latency 2983system.l2c.blocked_cycles::no_mshrs 198 # number of cycles access was blocked 2984system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 2985system.l2c.blocked::no_mshrs 3 # number of cycles access was blocked 2986system.l2c.blocked::no_targets 0 # number of cycles access was blocked 2987system.l2c.avg_blocked_cycles::no_mshrs 66 # average number of cycles each access was blocked 2988system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2989system.l2c.writebacks::writebacks 1121516 # number of writebacks 2990system.l2c.writebacks::total 1121516 # number of writebacks 2991system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 148 # number of ReadSharedReq MSHR hits 2992system.l2c.ReadSharedReq_mshr_hits::cpu0.data 11 # number of ReadSharedReq MSHR hits 2993system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 139 # number of ReadSharedReq MSHR hits 2994system.l2c.ReadSharedReq_mshr_hits::cpu1.data 17 # number of ReadSharedReq MSHR hits 2995system.l2c.ReadSharedReq_mshr_hits::total 315 # number of ReadSharedReq MSHR hits 2996system.l2c.demand_mshr_hits::cpu0.inst 148 # number of demand (read+write) MSHR hits 2997system.l2c.demand_mshr_hits::cpu0.data 11 # number of demand (read+write) MSHR hits 2998system.l2c.demand_mshr_hits::cpu1.inst 139 # number of demand (read+write) MSHR hits 2999system.l2c.demand_mshr_hits::cpu1.data 17 # number of demand (read+write) MSHR hits 3000system.l2c.demand_mshr_hits::total 315 # number of demand (read+write) MSHR hits 3001system.l2c.overall_mshr_hits::cpu0.inst 148 # number of overall MSHR hits 3002system.l2c.overall_mshr_hits::cpu0.data 11 # number of overall MSHR hits 3003system.l2c.overall_mshr_hits::cpu1.inst 139 # number of overall MSHR hits 3004system.l2c.overall_mshr_hits::cpu1.data 17 # number of overall MSHR hits 3005system.l2c.overall_mshr_hits::total 315 # number of overall MSHR hits 3006system.l2c.CleanEvict_mshr_misses::writebacks 53239 # number of CleanEvict MSHR misses 3007system.l2c.CleanEvict_mshr_misses::total 53239 # number of CleanEvict MSHR misses 3008system.l2c.UpgradeReq_mshr_misses::cpu0.data 65595 # number of UpgradeReq MSHR misses 3009system.l2c.UpgradeReq_mshr_misses::cpu1.data 60730 # number of UpgradeReq MSHR misses 3010system.l2c.UpgradeReq_mshr_misses::total 126325 # number of UpgradeReq MSHR misses 3011system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 12636 # number of SCUpgradeReq MSHR misses 3012system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 10558 # number of SCUpgradeReq MSHR misses 3013system.l2c.SCUpgradeReq_mshr_misses::total 23194 # number of SCUpgradeReq MSHR misses 3014system.l2c.ReadExReq_mshr_misses::cpu0.data 86809 # number of ReadExReq MSHR misses 3015system.l2c.ReadExReq_mshr_misses::cpu1.data 47256 # number of ReadExReq MSHR misses 3016system.l2c.ReadExReq_mshr_misses::total 134065 # number of ReadExReq MSHR misses 3017system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 2557 # number of ReadSharedReq MSHR misses 3018system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 2464 # number of ReadSharedReq MSHR misses 3019system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 78591 # number of ReadSharedReq MSHR misses 3020system.l2c.ReadSharedReq_mshr_misses::cpu0.data 176737 # number of ReadSharedReq MSHR misses 3021system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 289930 # number of ReadSharedReq MSHR misses 3022system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 1566 # number of ReadSharedReq MSHR misses 3023system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker 1157 # number of ReadSharedReq MSHR misses 3024system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 44366 # number of ReadSharedReq MSHR misses 3025system.l2c.ReadSharedReq_mshr_misses::cpu1.data 80804 # number of ReadSharedReq MSHR misses 3026system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 170404 # number of ReadSharedReq MSHR misses 3027system.l2c.ReadSharedReq_mshr_misses::total 848576 # number of ReadSharedReq MSHR misses 3028system.l2c.InvalidateReq_mshr_misses::cpu0.data 477170 # number of InvalidateReq MSHR misses 3029system.l2c.InvalidateReq_mshr_misses::cpu1.data 94656 # number of InvalidateReq MSHR misses 3030system.l2c.InvalidateReq_mshr_misses::total 571826 # number of InvalidateReq MSHR misses 3031system.l2c.demand_mshr_misses::cpu0.dtb.walker 2557 # number of demand (read+write) MSHR misses 3032system.l2c.demand_mshr_misses::cpu0.itb.walker 2464 # number of demand (read+write) MSHR misses 3033system.l2c.demand_mshr_misses::cpu0.inst 78591 # number of demand (read+write) MSHR misses 3034system.l2c.demand_mshr_misses::cpu0.data 263546 # number of demand (read+write) MSHR misses 3035system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 289930 # number of demand (read+write) MSHR misses 3036system.l2c.demand_mshr_misses::cpu1.dtb.walker 1566 # number of demand (read+write) MSHR misses 3037system.l2c.demand_mshr_misses::cpu1.itb.walker 1157 # number of demand (read+write) MSHR misses 3038system.l2c.demand_mshr_misses::cpu1.inst 44366 # number of demand (read+write) MSHR misses 3039system.l2c.demand_mshr_misses::cpu1.data 128060 # number of demand (read+write) MSHR misses 3040system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 170404 # number of demand (read+write) MSHR misses 3041system.l2c.demand_mshr_misses::total 982641 # number of demand (read+write) MSHR misses 3042system.l2c.overall_mshr_misses::cpu0.dtb.walker 2557 # number of overall MSHR misses 3043system.l2c.overall_mshr_misses::cpu0.itb.walker 2464 # number of overall MSHR misses 3044system.l2c.overall_mshr_misses::cpu0.inst 78591 # number of overall MSHR misses 3045system.l2c.overall_mshr_misses::cpu0.data 263546 # number of overall MSHR misses 3046system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 289930 # number of overall MSHR misses 3047system.l2c.overall_mshr_misses::cpu1.dtb.walker 1566 # number of overall MSHR misses 3048system.l2c.overall_mshr_misses::cpu1.itb.walker 1157 # number of overall MSHR misses 3049system.l2c.overall_mshr_misses::cpu1.inst 44366 # number of overall MSHR misses 3050system.l2c.overall_mshr_misses::cpu1.data 128060 # number of overall MSHR misses 3051system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 170404 # number of overall MSHR misses 3052system.l2c.overall_mshr_misses::total 982641 # number of overall MSHR misses 3053system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 52300 # number of ReadReq MSHR uncacheable 3054system.l2c.ReadReq_mshr_uncacheable::cpu0.data 29793 # number of ReadReq MSHR uncacheable 3055system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 95 # number of ReadReq MSHR uncacheable 3056system.l2c.ReadReq_mshr_uncacheable::cpu1.data 8791 # number of ReadReq MSHR uncacheable 3057system.l2c.ReadReq_mshr_uncacheable::total 90979 # number of ReadReq MSHR uncacheable 3058system.l2c.WriteReq_mshr_uncacheable::cpu0.data 29400 # number of WriteReq MSHR uncacheable 3059system.l2c.WriteReq_mshr_uncacheable::cpu1.data 9091 # number of WriteReq MSHR uncacheable 3060system.l2c.WriteReq_mshr_uncacheable::total 38491 # number of WriteReq MSHR uncacheable 3061system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 52300 # number of overall MSHR uncacheable misses 3062system.l2c.overall_mshr_uncacheable_misses::cpu0.data 59193 # number of overall MSHR uncacheable misses 3063system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 95 # number of overall MSHR uncacheable misses 3064system.l2c.overall_mshr_uncacheable_misses::cpu1.data 17882 # number of overall MSHR uncacheable misses 3065system.l2c.overall_mshr_uncacheable_misses::total 129470 # number of overall MSHR uncacheable misses 3066system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 1410582996 # number of UpgradeReq MSHR miss cycles 3067system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 1311057994 # number of UpgradeReq MSHR miss cycles 3068system.l2c.UpgradeReq_mshr_miss_latency::total 2721640990 # number of UpgradeReq MSHR miss cycles 3069system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 310816999 # number of SCUpgradeReq MSHR miss cycles 3070system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 259803998 # number of SCUpgradeReq MSHR miss cycles 3071system.l2c.SCUpgradeReq_mshr_miss_latency::total 570620997 # number of SCUpgradeReq MSHR miss cycles 3072system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 6851145073 # number of ReadExReq MSHR miss cycles 3073system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3438526610 # number of ReadExReq MSHR miss cycles 3074system.l2c.ReadExReq_mshr_miss_latency::total 10289671683 # number of ReadExReq MSHR miss cycles 3075system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 201267501 # number of ReadSharedReq MSHR miss cycles 3076system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 194366502 # number of ReadSharedReq MSHR miss cycles 3077system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 5908962562 # number of ReadSharedReq MSHR miss cycles 3078system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 14008544736 # number of ReadSharedReq MSHR miss cycles 3079system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 33709734391 # number of ReadSharedReq MSHR miss cycles 3080system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 129525503 # number of ReadSharedReq MSHR miss cycles 3081system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 96018502 # number of ReadSharedReq MSHR miss cycles 3082system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 3307546077 # number of ReadSharedReq MSHR miss cycles 3083system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 6709739262 # number of ReadSharedReq MSHR miss cycles 3084system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 19717611814 # number of ReadSharedReq MSHR miss cycles 3085system.l2c.ReadSharedReq_mshr_miss_latency::total 83983316850 # number of ReadSharedReq MSHR miss cycles 3086system.l2c.InvalidateReq_mshr_miss_latency::cpu0.data 9978148501 # number of InvalidateReq MSHR miss cycles 3087system.l2c.InvalidateReq_mshr_miss_latency::cpu1.data 1974697000 # number of InvalidateReq MSHR miss cycles 3088system.l2c.InvalidateReq_mshr_miss_latency::total 11952845501 # number of InvalidateReq MSHR miss cycles 3089system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 201267501 # number of demand (read+write) MSHR miss cycles 3090system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 194366502 # number of demand (read+write) MSHR miss cycles 3091system.l2c.demand_mshr_miss_latency::cpu0.inst 5908962562 # number of demand (read+write) MSHR miss cycles 3092system.l2c.demand_mshr_miss_latency::cpu0.data 20859689809 # number of demand (read+write) MSHR miss cycles 3093system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 33709734391 # number of demand (read+write) MSHR miss cycles 3094system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 129525503 # number of demand (read+write) MSHR miss cycles 3095system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 96018502 # number of demand (read+write) MSHR miss cycles 3096system.l2c.demand_mshr_miss_latency::cpu1.inst 3307546077 # number of demand (read+write) MSHR miss cycles 3097system.l2c.demand_mshr_miss_latency::cpu1.data 10148265872 # number of demand (read+write) MSHR miss cycles 3098system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 19717611814 # number of demand (read+write) MSHR miss cycles 3099system.l2c.demand_mshr_miss_latency::total 94272988533 # number of demand (read+write) MSHR miss cycles 3100system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 201267501 # number of overall MSHR miss cycles 3101system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 194366502 # number of overall MSHR miss cycles 3102system.l2c.overall_mshr_miss_latency::cpu0.inst 5908962562 # number of overall MSHR miss cycles 3103system.l2c.overall_mshr_miss_latency::cpu0.data 20859689809 # number of overall MSHR miss cycles 3104system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 33709734391 # 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number of ReadReq MSHR uncacheable cycles 3115system.l2c.ReadReq_mshr_uncacheable_latency::total 9303136013 # number of ReadReq MSHR uncacheable cycles 3116system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 3320084000 # number of overall MSHR uncacheable cycles 3117system.l2c.overall_mshr_uncacheable_latency::cpu0.data 4900695009 # number of overall MSHR uncacheable cycles 3118system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 6011000 # number of overall MSHR uncacheable cycles 3119system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1076346004 # number of overall MSHR uncacheable cycles 3120system.l2c.overall_mshr_uncacheable_latency::total 9303136013 # number of overall MSHR uncacheable cycles 3121system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 3122system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 3123system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.262097 # mshr miss rate for UpgradeReq accesses 3124system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.318773 # mshr miss rate for UpgradeReq accesses 3125system.l2c.UpgradeReq_mshr_miss_rate::total 0.286593 # mshr miss rate for UpgradeReq accesses 3126system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.211304 # mshr miss rate for SCUpgradeReq accesses 3127system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.225618 # mshr miss rate for SCUpgradeReq accesses 3128system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.217588 # mshr miss rate for SCUpgradeReq accesses 3129system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.595463 # mshr miss rate for ReadExReq accesses 3130system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.451567 # mshr miss rate for ReadExReq accesses 3131system.l2c.ReadExReq_mshr_miss_rate::total 0.535333 # mshr miss rate for ReadExReq accesses 3132system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.266299 # mshr miss rate for ReadSharedReq accesses 3133system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.360234 # mshr miss rate for ReadSharedReq accesses 3134system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.095263 # mshr miss rate for ReadSharedReq accesses 3135system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.206892 # mshr miss rate for ReadSharedReq accesses 3136system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.457750 # mshr miss rate for ReadSharedReq accesses 3137system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.189222 # mshr miss rate for ReadSharedReq accesses 3138system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.193640 # mshr miss rate for ReadSharedReq accesses 3139system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.068356 # mshr miss rate for ReadSharedReq accesses 3140system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.125236 # mshr miss rate for ReadSharedReq accesses 3141system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.357669 # mshr miss rate for ReadSharedReq accesses 3142system.l2c.ReadSharedReq_mshr_miss_rate::total 0.206266 # mshr miss rate for ReadSharedReq accesses 3143system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data 0.775396 # mshr miss rate for InvalidateReq accesses 3144system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.429860 # mshr miss rate for InvalidateReq accesses 3145system.l2c.InvalidateReq_mshr_miss_rate::total 0.684337 # mshr miss rate for InvalidateReq accesses 3146system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.266299 # mshr miss rate for demand accesses 3147system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.360234 # mshr miss rate for demand accesses 3148system.l2c.demand_mshr_miss_rate::cpu0.inst 0.095263 # mshr miss rate for demand accesses 3149system.l2c.demand_mshr_miss_rate::cpu0.data 0.263538 # mshr miss rate for demand accesses 3150system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.457750 # mshr miss rate for demand accesses 3151system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.189222 # mshr miss rate for demand accesses 3152system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.193640 # mshr miss rate for demand accesses 3153system.l2c.demand_mshr_miss_rate::cpu1.inst 0.068356 # mshr miss rate for demand accesses 3154system.l2c.demand_mshr_miss_rate::cpu1.data 0.170778 # mshr miss rate for demand accesses 3155system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.357669 # mshr miss rate for demand accesses 3156system.l2c.demand_mshr_miss_rate::total 0.225148 # mshr miss rate for demand accesses 3157system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.266299 # mshr miss rate for overall accesses 3158system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.360234 # mshr miss rate for overall accesses 3159system.l2c.overall_mshr_miss_rate::cpu0.inst 0.095263 # mshr miss rate for overall accesses 3160system.l2c.overall_mshr_miss_rate::cpu0.data 0.263538 # mshr miss rate for overall accesses 3161system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.457750 # mshr miss rate for overall accesses 3162system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.189222 # mshr miss rate for overall accesses 3163system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.193640 # mshr miss rate for overall accesses 3164system.l2c.overall_mshr_miss_rate::cpu1.inst 0.068356 # mshr miss rate for overall accesses 3165system.l2c.overall_mshr_miss_rate::cpu1.data 0.170778 # mshr miss rate for overall accesses 3166system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.357669 # mshr miss rate for overall accesses 3167system.l2c.overall_mshr_miss_rate::total 0.225148 # mshr miss rate for overall accesses 3168system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 21504.428630 # average UpgradeReq mshr miss latency 3169system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 21588.308809 # average UpgradeReq mshr miss latency 3170system.l2c.UpgradeReq_avg_mshr_miss_latency::total 21544.753533 # average UpgradeReq mshr miss latency 3171system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 24597.736546 # average SCUpgradeReq mshr miss latency 3172system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24607.311801 # average SCUpgradeReq mshr miss latency 3173system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 24602.095240 # average SCUpgradeReq mshr miss latency 3174system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 78922.059614 # average ReadExReq mshr miss latency 3175system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 72763.810098 # average ReadExReq mshr miss latency 3176system.l2c.ReadExReq_avg_mshr_miss_latency::total 76751.364510 # average ReadExReq mshr miss latency 3177system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 78712.358623 # average ReadSharedReq mshr miss latency 3178system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 78882.508929 # average ReadSharedReq mshr miss latency 3179system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 75186.249850 # average ReadSharedReq mshr miss latency 3180system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 79262.094163 # average ReadSharedReq mshr miss latency 3181system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 116268.528234 # average ReadSharedReq mshr miss latency 3182system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 82711.049170 # average ReadSharedReq mshr miss latency 3183system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 82989.197926 # average ReadSharedReq mshr miss latency 3184system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 74551.369900 # average ReadSharedReq mshr miss latency 3185system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 83037.216747 # average ReadSharedReq mshr miss latency 3186system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 115710.968135 # average ReadSharedReq mshr miss latency 3187system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 98969.705542 # average ReadSharedReq mshr miss latency 3188system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 20911.097724 # average InvalidateReq mshr miss latency 3189system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 20861.825980 # average InvalidateReq mshr miss latency 3190system.l2c.InvalidateReq_avg_mshr_miss_latency::total 20902.941631 # average InvalidateReq mshr miss latency 3191system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 78712.358623 # average overall mshr miss latency 3192system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 78882.508929 # average overall mshr miss latency 3193system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 75186.249850 # average overall mshr miss latency 3194system.l2c.demand_avg_mshr_miss_latency::cpu0.data 79150.090720 # average overall mshr miss latency 3195system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 116268.528234 # average overall mshr miss latency 3196system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 82711.049170 # average overall mshr miss latency 3197system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 82989.197926 # average overall mshr miss latency 3198system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 74551.369900 # average overall mshr miss latency 3199system.l2c.demand_avg_mshr_miss_latency::cpu1.data 79246.180478 # average overall mshr miss latency 3200system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 115710.968135 # average overall mshr miss latency 3201system.l2c.demand_avg_mshr_miss_latency::total 95938.382922 # average overall mshr miss latency 3202system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 78712.358623 # average overall mshr miss latency 3203system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 78882.508929 # average overall mshr miss latency 3204system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 75186.249850 # average overall mshr miss latency 3205system.l2c.overall_avg_mshr_miss_latency::cpu0.data 79150.090720 # average overall mshr miss latency 3206system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 116268.528234 # average overall mshr miss latency 3207system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 82711.049170 # average overall mshr miss latency 3208system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 82989.197926 # average overall mshr miss latency 3209system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 74551.369900 # average overall mshr miss latency 3210system.l2c.overall_avg_mshr_miss_latency::cpu1.data 79246.180478 # average overall mshr miss latency 3211system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 115710.968135 # average overall mshr miss latency 3212system.l2c.overall_avg_mshr_miss_latency::total 95938.382922 # average overall mshr miss latency 3213system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 63481.529637 # average ReadReq mshr uncacheable latency 3214system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 164491.491592 # average ReadReq mshr uncacheable latency 3215system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 63273.684211 # average ReadReq mshr uncacheable latency 3216system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 122437.265840 # average ReadReq mshr uncacheable latency 3217system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 102255.861386 # average ReadReq mshr uncacheable latency 3218system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 63481.529637 # average overall mshr uncacheable latency 3219system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 82791.799858 # average overall mshr uncacheable latency 3220system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 63273.684211 # average overall mshr uncacheable latency 3221system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 60191.589531 # average overall mshr uncacheable latency 3222system.l2c.overall_avg_mshr_uncacheable_latency::total 71855.534201 # average overall mshr uncacheable latency 3223system.membus.snoop_filter.tot_requests 3914348 # Total number of requests made to the snoop filter. 3224system.membus.snoop_filter.hit_single_requests 2362357 # Number of requests hitting in the snoop filter with a single holder of the requested data. 3225system.membus.snoop_filter.hit_multi_requests 2871 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 3226system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 3227system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 3228system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 3229system.membus.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states 3230system.membus.trans_dist::ReadReq 90979 # Transaction distribution 3231system.membus.trans_dist::ReadResp 948459 # Transaction distribution 3232system.membus.trans_dist::WriteReq 38491 # Transaction distribution 3233system.membus.trans_dist::WriteResp 38491 # Transaction distribution 3234system.membus.trans_dist::WritebackDirty 1228466 # Transaction distribution 3235system.membus.trans_dist::CleanEvict 265252 # Transaction distribution 3236system.membus.trans_dist::UpgradeReq 443986 # Transaction distribution 3237system.membus.trans_dist::SCUpgradeReq 298688 # Transaction distribution 3238system.membus.trans_dist::UpgradeResp 23 # Transaction distribution 3239system.membus.trans_dist::SCUpgradeFailReq 2 # Transaction distribution 3240system.membus.trans_dist::ReadExReq 145286 # Transaction distribution 3241system.membus.trans_dist::ReadExResp 128554 # Transaction distribution 3242system.membus.trans_dist::ReadSharedReq 857480 # Transaction distribution 3243system.membus.trans_dist::InvalidateReq 675140 # Transaction distribution 3244system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122950 # Packet count per connected master and slave (bytes) 3245system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 54 # Packet count per connected master and slave (bytes) 3246system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 25980 # Packet count per connected master and slave (bytes) 3247system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4768940 # Packet count per connected master and slave (bytes) 3248system.membus.pkt_count_system.l2c.mem_side::total 4917924 # Packet count per connected master and slave (bytes) 3249system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 238548 # Packet count per connected master and slave (bytes) 3250system.membus.pkt_count_system.iocache.mem_side::total 238548 # Packet count per connected master and slave (bytes) 3251system.membus.pkt_count::total 5156472 # Packet count per connected master and slave (bytes) 3252system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155965 # Cumulative packet size per connected master and slave (bytes) 3253system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1388 # Cumulative packet size per connected master and slave (bytes) 3254system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 51960 # Cumulative packet size per connected master and slave (bytes) 3255system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 137639872 # Cumulative packet size per connected master and slave (bytes) 3256system.membus.pkt_size_system.l2c.mem_side::total 137849185 # Cumulative packet size per connected master and slave (bytes) 3257system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7281600 # Cumulative packet size per connected master and slave (bytes) 3258system.membus.pkt_size_system.iocache.mem_side::total 7281600 # Cumulative packet size per connected master and slave (bytes) 3259system.membus.pkt_size::total 145130785 # Cumulative packet size per connected master and slave (bytes) 3260system.membus.snoops 603530 # Total snoops (count) 3261system.membus.snoopTraffic 179328 # Total snoop traffic (bytes) 3262system.membus.snoop_fanout::samples 2550056 # Request fanout histogram 3263system.membus.snoop_fanout::mean 0.011955 # Request fanout histogram 3264system.membus.snoop_fanout::stdev 0.108685 # Request fanout histogram 3265system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 3266system.membus.snoop_fanout::0 2519569 98.80% 98.80% # Request fanout histogram 3267system.membus.snoop_fanout::1 30487 1.20% 100.00% # Request fanout histogram 3268system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 3269system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 3270system.membus.snoop_fanout::min_value 0 # Request fanout histogram 3271system.membus.snoop_fanout::max_value 1 # Request fanout histogram 3272system.membus.snoop_fanout::total 2550056 # Request fanout histogram 3273system.membus.reqLayer0.occupancy 103375494 # Layer occupancy (ticks) 3274system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 3275system.membus.reqLayer1.occupancy 34812 # Layer occupancy (ticks) 3276system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 3277system.membus.reqLayer2.occupancy 21768496 # Layer occupancy (ticks) 3278system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 3279system.membus.reqLayer5.occupancy 8632891321 # Layer occupancy (ticks) 3280system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 3281system.membus.respLayer2.occupancy 5537724663 # Layer occupancy (ticks) 3282system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 3283system.membus.respLayer3.occupancy 45395946 # Layer occupancy (ticks) 3284system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 3285system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states 3286system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states 3287system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states 3288system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states 3289system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states 3290system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states 3291system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states 3292system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 3293system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 3294system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 3295system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 3296system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 3297system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks 3298system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states 3299system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states 3300system.realview.ethernet.txBytes 966 # Bytes Transmitted 3301system.realview.ethernet.txPackets 3 # Number of Packets Transmitted 3302system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device 3303system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device 3304system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 3305system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 3306system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 3307system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 3308system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 3309system.realview.ethernet.totBandwidth 163 # Total Bandwidth (bits/s) 3310system.realview.ethernet.totPackets 3 # Total Packets 3311system.realview.ethernet.totBytes 966 # Total Bytes 3312system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) 3313system.realview.ethernet.txBandwidth 163 # Transmit Bandwidth (bits/s) 3314system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) 3315system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 3316system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post 3317system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 3318system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 3319system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post 3320system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 3321system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 3322system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post 3323system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 3324system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 3325system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post 3326system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 3327system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 3328system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post 3329system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 3330system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 3331system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post 3332system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 3333system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 3334system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 3335system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 3336system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 3337system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 3338system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 3339system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 3340system.realview.ethernet.postedInterrupts 13 # number of posts to CPU 3341system.realview.ethernet.droppedPackets 0 # number of packets dropped 3342system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states 3343system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states 3344system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states 3345system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states 3346system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states 3347system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states 3348system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states 3349system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 3350system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 3351system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 3352system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks 3353system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states 3354system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states 3355system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states 3356system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states 3357system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states 3358system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states 3359system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states 3360system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states 3361system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states 3362system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states 3363system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states 3364system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states 3365system.toL2Bus.snoop_filter.tot_requests 12809826 # Total number of requests made to the snoop filter. 3366system.toL2Bus.snoop_filter.hit_single_requests 6934559 # Number of requests hitting in the snoop filter with a single holder of the requested data. 3367system.toL2Bus.snoop_filter.hit_multi_requests 2124865 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 3368system.toL2Bus.snoop_filter.tot_snoops 137043 # Total number of snoops made to the snoop filter. 3369system.toL2Bus.snoop_filter.hit_single_snoops 124917 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 3370system.toL2Bus.snoop_filter.hit_multi_snoops 12126 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 3371system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states 3372system.toL2Bus.trans_dist::ReadReq 90981 # Transaction distribution 3373system.toL2Bus.trans_dist::ReadResp 4987806 # Transaction distribution 3374system.toL2Bus.trans_dist::WriteReq 38491 # Transaction distribution 3375system.toL2Bus.trans_dist::WriteResp 38491 # Transaction distribution 3376system.toL2Bus.trans_dist::WritebackDirty 3972958 # Transaction distribution 3377system.toL2Bus.trans_dist::CleanEvict 3104635 # Transaction distribution 3378system.toL2Bus.trans_dist::UpgradeReq 749262 # Transaction distribution 3379system.toL2Bus.trans_dist::SCUpgradeReq 382090 # Transaction distribution 3380system.toL2Bus.trans_dist::UpgradeResp 1131352 # Transaction distribution 3381system.toL2Bus.trans_dist::SCUpgradeFailReq 138 # Transaction distribution 3382system.toL2Bus.trans_dist::UpgradeFailResp 138 # Transaction distribution 3383system.toL2Bus.trans_dist::ReadExReq 306540 # Transaction distribution 3384system.toL2Bus.trans_dist::ReadExResp 306540 # Transaction distribution 3385system.toL2Bus.trans_dist::ReadSharedReq 4897318 # Transaction distribution 3386system.toL2Bus.trans_dist::InvalidateReq 863164 # Transaction distribution 3387system.toL2Bus.trans_dist::InvalidateResp 835591 # Transaction distribution 3388system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 11082342 # Packet count per connected master and slave (bytes) 3389system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7735233 # Packet count per connected master and slave (bytes) 3390system.toL2Bus.pkt_count::total 18817575 # Packet count per connected master and slave (bytes) 3391system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 276628165 # Cumulative packet size per connected master and slave (bytes) 3392system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 188875292 # Cumulative packet size per connected master and slave (bytes) 3393system.toL2Bus.pkt_size::total 465503457 # Cumulative packet size per connected master and slave (bytes) 3394system.toL2Bus.snoops 2889580 # Total snoops (count) 3395system.toL2Bus.snoopTraffic 125478224 # Total snoop traffic (bytes) 3396system.toL2Bus.snoop_fanout::samples 8764836 # Request fanout histogram 3397system.toL2Bus.snoop_fanout::mean 0.360858 # Request fanout histogram 3398system.toL2Bus.snoop_fanout::stdev 0.483121 # Request fanout histogram 3399system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 3400system.toL2Bus.snoop_fanout::0 5614105 64.05% 64.05% # Request fanout histogram 3401system.toL2Bus.snoop_fanout::1 3138605 35.81% 99.86% # Request fanout histogram 3402system.toL2Bus.snoop_fanout::2 12126 0.14% 100.00% # Request fanout histogram 3403system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 3404system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 3405system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 3406system.toL2Bus.snoop_fanout::total 8764836 # Request fanout histogram 3407system.toL2Bus.reqLayer0.occupancy 9763497454 # Layer occupancy (ticks) 3408system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 3409system.toL2Bus.snoopLayer0.occupancy 2559907 # Layer occupancy (ticks) 3410system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 3411system.toL2Bus.respLayer0.occupancy 5082599079 # Layer occupancy (ticks) 3412system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 3413system.toL2Bus.respLayer1.occupancy 3859782501 # Layer occupancy (ticks) 3414system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 3415 3416---------- End Simulation Statistics ---------- 3417