---------- Begin Simulation Statistics ---------- sim_seconds 47.445489 # Number of seconds simulated sim_ticks 47445489241000 # Number of ticks simulated final_tick 47445489241000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks host_inst_rate 208966 # Simulator instruction rate (inst/s) host_op_rate 245756 # Simulator op (including micro ops) rate (op/s) host_tick_rate 10881126125 # Simulator tick rate (ticks/s) host_mem_usage 759660 # Number of bytes of host memory used host_seconds 4360.35 # Real time elapsed on the host sim_insts 911162440 # Number of instructions simulated sim_ops 1071583187 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu0.dtb.walker 163648 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 157696 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.inst 8375360 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.data 16685256 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.l2cache.prefetcher 18550592 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 100224 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.itb.walker 74048 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.inst 2844864 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.data 7994832 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.l2cache.prefetcher 10895744 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 436800 # Number of bytes read from this memory system.physmem.bytes_read::total 66279064 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu0.inst 8375360 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::cpu1.inst 2844864 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 11220224 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 78621824 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory system.physmem.bytes_written::total 78642408 # Number of bytes written to this memory system.physmem.num_reads::cpu0.dtb.walker 2557 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2464 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.inst 130865 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.data 260720 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.l2cache.prefetcher 289853 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 1566 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.itb.walker 1157 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.inst 44451 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.data 124932 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.l2cache.prefetcher 170246 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 6825 # Number of read requests responded to by this memory system.physmem.num_reads::total 1035636 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 1228466 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory system.physmem.num_writes::total 1231040 # Number of write requests responded to by this memory system.physmem.bw_read::cpu0.dtb.walker 3449 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 3324 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.inst 176526 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.data 351672 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.l2cache.prefetcher 390987 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 2112 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.itb.walker 1561 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.inst 59961 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.data 168506 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.l2cache.prefetcher 229648 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 9206 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 1396952 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu0.inst 176526 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu1.inst 59961 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 236487 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_write::writebacks 1657098 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 434 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::total 1657532 # Write bandwidth from this memory (bytes/s) system.physmem.bw_total::writebacks 1657098 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 3449 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 3324 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.inst 176526 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.data 352106 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.l2cache.prefetcher 390987 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 2112 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.itb.walker 1561 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.inst 59961 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.data 168506 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.l2cache.prefetcher 229648 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 9206 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 3054484 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 1035636 # Number of read requests accepted system.physmem.writeReqs 1231040 # Number of write requests accepted system.physmem.readBursts 1035636 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 1231040 # Number of DRAM write bursts, including those merged in the write queue system.physmem.bytesReadDRAM 66252160 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 28544 # Total number of bytes read from write queue system.physmem.bytesWritten 78640192 # Total number of bytes written to DRAM system.physmem.bytesReadSys 66279064 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 78642408 # Total written bytes from the system interface side system.physmem.servicedByWrQ 446 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 2268 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 59521 # Per bank write bursts system.physmem.perBankRdBursts::1 66808 # Per bank write bursts system.physmem.perBankRdBursts::2 62154 # Per bank write bursts system.physmem.perBankRdBursts::3 70128 # Per bank write bursts system.physmem.perBankRdBursts::4 60732 # Per bank write bursts system.physmem.perBankRdBursts::5 72109 # Per bank write bursts system.physmem.perBankRdBursts::6 58717 # Per bank write bursts system.physmem.perBankRdBursts::7 62140 # Per bank write bursts system.physmem.perBankRdBursts::8 50595 # Per bank write bursts system.physmem.perBankRdBursts::9 107916 # Per bank write bursts system.physmem.perBankRdBursts::10 54809 # Per bank write bursts system.physmem.perBankRdBursts::11 63010 # Per bank write bursts system.physmem.perBankRdBursts::12 57730 # Per bank write bursts system.physmem.perBankRdBursts::13 64314 # Per bank write bursts system.physmem.perBankRdBursts::14 61474 # Per bank write bursts system.physmem.perBankRdBursts::15 63033 # Per bank write bursts system.physmem.perBankWrBursts::0 75175 # Per bank write bursts system.physmem.perBankWrBursts::1 80913 # Per bank write bursts system.physmem.perBankWrBursts::2 75568 # Per bank write bursts system.physmem.perBankWrBursts::3 82272 # Per bank write bursts system.physmem.perBankWrBursts::4 75546 # Per bank write bursts system.physmem.perBankWrBursts::5 83102 # Per bank write bursts system.physmem.perBankWrBursts::6 75765 # Per bank write bursts system.physmem.perBankWrBursts::7 76740 # Per bank write bursts system.physmem.perBankWrBursts::8 69114 # Per bank write bursts system.physmem.perBankWrBursts::9 73138 # Per bank write bursts system.physmem.perBankWrBursts::10 71733 # Per bank write bursts system.physmem.perBankWrBursts::11 77960 # Per bank write bursts system.physmem.perBankWrBursts::12 74616 # Per bank write bursts system.physmem.perBankWrBursts::13 78881 # Per bank write bursts system.physmem.perBankWrBursts::14 78631 # Per bank write bursts system.physmem.perBankWrBursts::15 79599 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 48 # Number of times write queue was full causing retry system.physmem.totGap 47445487151500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 25 # Read request sizes (log2) system.physmem.readPktSize::4 5 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) system.physmem.readPktSize::6 1035606 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 2 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 1228466 # Write request sizes (log2) system.physmem.rdQLenPdf::0 692790 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 121307 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 45775 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 35632 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 30940 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 28399 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 26620 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 23199 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 20889 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 3694 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 1663 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 1197 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 944 # What read queue length does an incoming req see system.physmem.rdQLenPdf::13 702 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 419 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 350 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 273 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 228 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 102 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 60 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 6 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::15 27376 # What write queue length does an incoming req see system.physmem.wrQLenPdf::16 35697 # What write queue length does an incoming req see system.physmem.wrQLenPdf::17 51705 # What write queue length does an incoming req see system.physmem.wrQLenPdf::18 59824 # What write queue length does an incoming req see system.physmem.wrQLenPdf::19 65779 # What write queue length does an incoming req see system.physmem.wrQLenPdf::20 68512 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 70877 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 72860 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 75714 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 75511 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 79365 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 82384 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 78677 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 77306 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 82372 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 73265 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 67472 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 64363 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 3236 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 2482 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 1926 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 1455 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 1166 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 922 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 878 # What write queue length does an incoming req see system.physmem.wrQLenPdf::40 663 # What write queue length does an incoming req see system.physmem.wrQLenPdf::41 558 # What write queue length does an incoming req see system.physmem.wrQLenPdf::42 539 # What write queue length does an incoming req see system.physmem.wrQLenPdf::43 435 # What write queue length does an incoming req see system.physmem.wrQLenPdf::44 477 # What write queue length does an incoming req see system.physmem.wrQLenPdf::45 423 # What write queue length does an incoming req see system.physmem.wrQLenPdf::46 525 # What write queue length does an incoming req see system.physmem.wrQLenPdf::47 457 # What write queue length does an incoming req see system.physmem.wrQLenPdf::48 414 # What write queue length does an incoming req see system.physmem.wrQLenPdf::49 431 # What write queue length does an incoming req see system.physmem.wrQLenPdf::50 338 # What write queue length does an incoming req see system.physmem.wrQLenPdf::51 283 # What write queue length does an incoming req see system.physmem.wrQLenPdf::52 266 # What write queue length does an incoming req see system.physmem.wrQLenPdf::53 273 # What write queue length does an incoming req see system.physmem.wrQLenPdf::54 259 # What write queue length does an incoming req see system.physmem.wrQLenPdf::55 245 # What write queue length does an incoming req see system.physmem.wrQLenPdf::56 169 # What write queue length does an incoming req see system.physmem.wrQLenPdf::57 155 # What write queue length does an incoming req see system.physmem.wrQLenPdf::58 130 # What write queue length does an incoming req see system.physmem.wrQLenPdf::59 138 # What write queue length does an incoming req see system.physmem.wrQLenPdf::60 111 # What write queue length does an incoming req see system.physmem.wrQLenPdf::61 131 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 69 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 144 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 1012110 # Bytes accessed per row activation system.physmem.bytesPerActivate::mean 143.157878 # Bytes accessed per row activation system.physmem.bytesPerActivate::gmean 97.072288 # Bytes accessed per row activation system.physmem.bytesPerActivate::stdev 192.644368 # Bytes accessed per row activation system.physmem.bytesPerActivate::0-127 686114 67.79% 67.79% # Bytes accessed per row activation system.physmem.bytesPerActivate::128-255 195882 19.35% 87.14% # Bytes accessed per row activation system.physmem.bytesPerActivate::256-383 47037 4.65% 91.79% # Bytes accessed per row activation system.physmem.bytesPerActivate::384-511 20980 2.07% 93.86% # Bytes accessed per row activation system.physmem.bytesPerActivate::512-639 15295 1.51% 95.38% # Bytes accessed per row activation system.physmem.bytesPerActivate::640-767 9865 0.97% 96.35% # Bytes accessed per row activation system.physmem.bytesPerActivate::768-895 6724 0.66% 97.01% # Bytes accessed per row activation system.physmem.bytesPerActivate::896-1023 5499 0.54% 97.56% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 24714 2.44% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 1012110 # Bytes accessed per row activation system.physmem.rdPerTurnAround::samples 60277 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::mean 17.173764 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::stdev 160.670576 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::0-1023 60274 100.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::25600-26623 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::29696-30719 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::total 60277 # Reads before turning the bus around for writes system.physmem.wrPerTurnAround::samples 60277 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::mean 20.385105 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::gmean 18.691366 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::stdev 13.394945 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::16-19 52026 86.31% 86.31% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::20-23 2335 3.87% 90.19% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::24-27 778 1.29% 91.48% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::28-31 614 1.02% 92.49% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::32-35 994 1.65% 94.14% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::36-39 490 0.81% 94.96% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::40-43 334 0.55% 95.51% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::44-47 282 0.47% 95.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::48-51 206 0.34% 96.32% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::52-55 170 0.28% 96.60% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::56-59 135 0.22% 96.83% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::60-63 158 0.26% 97.09% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::64-67 477 0.79% 97.88% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::68-71 137 0.23% 98.11% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::72-75 123 0.20% 98.31% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::76-79 110 0.18% 98.49% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::80-83 87 0.14% 98.64% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::84-87 84 0.14% 98.78% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::88-91 91 0.15% 98.93% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::92-95 102 0.17% 99.10% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::96-99 72 0.12% 99.22% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::100-103 71 0.12% 99.33% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::104-107 64 0.11% 99.44% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::108-111 59 0.10% 99.54% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::112-115 43 0.07% 99.61% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::116-119 45 0.07% 99.68% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::120-123 41 0.07% 99.75% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::124-127 40 0.07% 99.82% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::128-131 47 0.08% 99.90% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::132-135 20 0.03% 99.93% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::136-139 11 0.02% 99.95% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::140-143 5 0.01% 99.96% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::144-147 4 0.01% 99.96% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::148-151 1 0.00% 99.97% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::152-155 2 0.00% 99.97% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::156-159 4 0.01% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::160-163 8 0.01% 99.99% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::168-171 1 0.00% 99.99% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::172-175 4 0.01% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::180-183 1 0.00% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::184-187 1 0.00% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 60277 # Writes before turning the bus around for reads system.physmem.totQLat 35377622933 # Total ticks spent queuing system.physmem.totMemAccLat 54787435433 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 5175950000 # Total ticks spent in databus transfers system.physmem.avgQLat 34175.00 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst system.physmem.avgMemAccLat 52925.00 # Average memory access latency per DRAM burst system.physmem.avgRdBW 1.40 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 1.66 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 1.40 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 1.66 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.15 # Average read queue length when enqueuing system.physmem.avgWrQLen 27.61 # Average write queue length when enqueuing system.physmem.readRowHits 780044 # Number of row buffer hits during reads system.physmem.writeRowHits 471783 # Number of row buffer hits during writes system.physmem.readRowHitRate 75.35 # Row buffer hit rate for reads system.physmem.writeRowHitRate 38.39 # Row buffer hit rate for writes system.physmem.avgGap 20931746.38 # Average gap between requests system.physmem.pageHitRate 55.29 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 3937837680 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 2148621750 # Energy for precharge commands per rank (pJ) system.physmem_0.readEnergy 3995955600 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 4050479520 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 3098908325760 # Energy for refresh commands per rank (pJ) system.physmem_0.actBackEnergy 1191842451045 # Energy for active background per rank (pJ) system.physmem_0.preBackEnergy 27421814259750 # Energy for precharge background per rank (pJ) system.physmem_0.totalEnergy 31726697931105 # Total energy per rank (pJ) system.physmem_0.averagePower 668.697958 # Core power per rank (mW) system.physmem_0.memoryStateTime::IDLE 45618359398995 # Time in different power states system.physmem_0.memoryStateTime::REF 1584308960000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_0.memoryStateTime::ACT 242820245005 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_1.actEnergy 3713615640 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 2026278375 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 4078440600 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 3911723280 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 3098908325760 # Energy for refresh commands per rank (pJ) system.physmem_1.actBackEnergy 1186342158240 # Energy for active background per rank (pJ) system.physmem_1.preBackEnergy 27426639078000 # Energy for precharge background per rank (pJ) system.physmem_1.totalEnergy 31725619619895 # Total energy per rank (pJ) system.physmem_1.averagePower 668.675231 # Core power per rank (mW) system.physmem_1.memoryStateTime::IDLE 45626361005854 # Time in different power states system.physmem_1.memoryStateTime::REF 1584308960000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 234814164146 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu0.inst 704 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 640 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 1388 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu0.inst 704 # Number of instructions bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu1.inst 640 # Number of instructions bytes read from this memory system.realview.nvmem.bytes_inst_read::total 1344 # Number of instructions bytes read from this memory system.realview.nvmem.num_reads::cpu0.inst 11 # Number of read requests responded to by this memory system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory system.realview.nvmem.num_reads::cpu1.inst 10 # Number of read requests responded to by this memory system.realview.nvmem.num_reads::cpu1.data 1 # Number of read requests responded to by this memory system.realview.nvmem.num_reads::total 27 # Number of read requests responded to by this memory system.realview.nvmem.bw_read::cpu0.inst 15 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_read::cpu1.inst 13 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_read::cpu1.data 0 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_read::total 29 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_inst_read::cpu0.inst 15 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_inst_read::cpu1.inst 13 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_inst_read::total 28 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.inst 15 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.inst 13 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 29 # Total bandwidth to/from this memory (bytes/s) system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states system.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states system.bridge.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 1671 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6846976 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1674 # Number of DMA write transactions. system.cpu0.branchPred.lookups 160314756 # Number of BP lookups system.cpu0.branchPred.condPredicted 112651620 # Number of conditional branches predicted system.cpu0.branchPred.condIncorrect 7238532 # Number of conditional branches incorrect system.cpu0.branchPred.BTBLookups 119384108 # Number of BTB lookups system.cpu0.branchPred.BTBHits 83018284 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu0.branchPred.BTBHitPct 69.538807 # BTB Hit Percentage system.cpu0.branchPred.usedRAS 19042266 # Number of times the RAS was used to get a target. system.cpu0.branchPred.RASInCorrect 1248322 # Number of incorrect RAS predictions. system.cpu0.branchPred.indirectLookups 4272460 # Number of indirect predictor lookups. system.cpu0.branchPred.indirectHits 2939923 # Number of indirect target hits. system.cpu0.branchPred.indirectMisses 1332537 # Number of indirect misses. system.cpu0.branchPredindirectMispredicted 468796 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states system.cpu0.dtb.walker.walks 329365 # Table walker walks requested system.cpu0.dtb.walker.walksLong 329365 # Table walker walks initiated with long descriptors system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 11619 # Level at which table walker walks with long descriptors terminate system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 95372 # Level at which table walker walks with long descriptors terminate system.cpu0.dtb.walker.walkWaitTime::samples 329365 # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walkWaitTime::0 329365 100.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walkWaitTime::total 329365 # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walkCompletionTime::samples 106991 # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::mean 23090.091690 # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::gmean 21491.120734 # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::stdev 15706.739319 # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::0-65535 105441 98.55% 98.55% # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::65536-131071 1327 1.24% 99.79% # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::131072-196607 42 0.04% 99.83% # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::196608-262143 76 0.07% 99.90% # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::262144-327679 69 0.06% 99.97% # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::327680-393215 15 0.01% 99.98% # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::393216-458751 14 0.01% 99.99% # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::458752-524287 6 0.01% 100.00% # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::total 106991 # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walksPending::samples 734573704 # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::0 734573704 100.00% 100.00% # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::total 734573704 # Table walker pending requests distribution system.cpu0.dtb.walker.walkPageSizes::4K 95372 89.14% 89.14% # Table walker page sizes translated system.cpu0.dtb.walker.walkPageSizes::2M 11619 10.86% 100.00% # Table walker page sizes translated system.cpu0.dtb.walker.walkPageSizes::total 106991 # Table walker page sizes translated system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 329365 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 329365 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 106991 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 106991 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin::total 436356 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses system.cpu0.dtb.read_hits 103710651 # DTB read hits system.cpu0.dtb.read_misses 276993 # DTB read misses system.cpu0.dtb.write_hits 90811723 # DTB write hits system.cpu0.dtb.write_misses 52372 # DTB write misses system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 43240 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 1075 # Number of times TLB was flushed by ASID system.cpu0.dtb.flush_entries 42132 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 2205 # Number of TLB faults due to alignment restrictions system.cpu0.dtb.prefetch_faults 11314 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 11590 # Number of TLB faults due to permissions restrictions system.cpu0.dtb.read_accesses 103987644 # DTB read accesses system.cpu0.dtb.write_accesses 90864095 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses system.cpu0.dtb.hits 194522374 # DTB hits system.cpu0.dtb.misses 329365 # DTB misses system.cpu0.dtb.accesses 194851739 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states system.cpu0.itb.walker.walks 72209 # Table walker walks requested system.cpu0.itb.walker.walksLong 72209 # Table walker walks initiated with long descriptors system.cpu0.itb.walker.walksLongTerminationLevel::Level2 611 # Level at which table walker walks with long descriptors terminate system.cpu0.itb.walker.walksLongTerminationLevel::Level3 59557 # Level at which table walker walks with long descriptors terminate system.cpu0.itb.walker.walkWaitTime::samples 72209 # Table walker wait (enqueue to first request) latency system.cpu0.itb.walker.walkWaitTime::0 72209 100.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu0.itb.walker.walkWaitTime::total 72209 # Table walker wait (enqueue to first request) latency system.cpu0.itb.walker.walkCompletionTime::samples 60168 # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::mean 25971.338585 # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::gmean 23756.230706 # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::stdev 17963.019846 # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::0-32767 55134 91.63% 91.63% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::32768-65535 3439 5.72% 97.35% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::65536-98303 6 0.01% 97.36% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::98304-131071 1442 2.40% 99.76% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::131072-163839 23 0.04% 99.79% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::163840-196607 16 0.03% 99.82% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::196608-229375 52 0.09% 99.91% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::229376-262143 23 0.04% 99.95% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::262144-294911 9 0.01% 99.96% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::294912-327679 12 0.02% 99.98% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::327680-360447 6 0.01% 99.99% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::360448-393215 4 0.01% 100.00% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::458752-491519 2 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::total 60168 # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walksPending::samples 733851204 # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::0 733851204 100.00% 100.00% # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::total 733851204 # Table walker pending requests distribution system.cpu0.itb.walker.walkPageSizes::4K 59557 98.98% 98.98% # Table walker page sizes translated system.cpu0.itb.walker.walkPageSizes::2M 611 1.02% 100.00% # Table walker page sizes translated system.cpu0.itb.walker.walkPageSizes::total 60168 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 72209 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Requested::total 72209 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 60168 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::total 60168 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin::total 132377 # Table walker requests started/completed, data/inst system.cpu0.itb.inst_hits 285203366 # ITB inst hits system.cpu0.itb.inst_misses 72209 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 43240 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 1075 # Number of times TLB was flushed by ASID system.cpu0.itb.flush_entries 30424 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 190431 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses system.cpu0.itb.inst_accesses 285275575 # ITB inst accesses system.cpu0.itb.hits 285203366 # DTB hits system.cpu0.itb.misses 72209 # DTB misses system.cpu0.itb.accesses 285275575 # DTB accesses system.cpu0.numPwrStateTransitions 26302 # Number of power state transitions system.cpu0.pwrStateClkGateDist::samples 13151 # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::mean 3564690271.200593 # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::stdev 65409151988.663887 # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::underflows 3759 28.58% 28.58% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::1000-5e+10 9361 71.18% 99.76% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 1 0.01% 99.77% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.01% 99.78% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11 4 0.03% 99.81% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::2.5e+11-3e+11 1 0.01% 99.82% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 1 0.01% 99.83% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::5e+11-5.5e+11 2 0.02% 99.84% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::6e+11-6.5e+11 1 0.01% 99.85% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::7e+11-7.5e+11 1 0.01% 99.86% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::8.5e+11-9e+11 1 0.01% 99.86% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::overflows 18 0.14% 100.00% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::max_value 1988779311380 # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::total 13151 # Distribution of time spent in the clock gated state system.cpu0.pwrStateResidencyTicks::ON 566247484441 # Cumulative time (in ticks) in various power states system.cpu0.pwrStateResidencyTicks::CLK_GATED 46879241756559 # Cumulative time (in ticks) in various power states system.cpu0.numCycles 1132534446 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.committedInsts 532076805 # Number of instructions committed system.cpu0.committedOps 624758290 # Number of ops (including micro ops) committed system.cpu0.discardedOps 52154793 # Number of ops (including micro ops) which were discarded before commit system.cpu0.numFetchSuspends 4664 # Number of times Execute suspended instruction fetching system.cpu0.quiesceCycles 93759282538 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt system.cpu0.cpi 2.128517 # CPI: cycles per instruction system.cpu0.ipc 0.469811 # IPC: instructions per cycle system.cpu0.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction system.cpu0.op_class_0::IntAlu 432780145 69.27% 69.27% # Class of committed instruction system.cpu0.op_class_0::IntMult 1412970 0.23% 69.50% # Class of committed instruction system.cpu0.op_class_0::IntDiv 69899 0.01% 69.51% # Class of committed instruction system.cpu0.op_class_0::FloatAdd 0 0.00% 69.51% # Class of committed instruction system.cpu0.op_class_0::FloatCmp 0 0.00% 69.51% # Class of committed instruction system.cpu0.op_class_0::FloatCvt 0 0.00% 69.51% # Class of committed instruction system.cpu0.op_class_0::FloatMult 0 0.00% 69.51% # Class of committed instruction system.cpu0.op_class_0::FloatDiv 0 0.00% 69.51% # Class of committed instruction system.cpu0.op_class_0::FloatSqrt 0 0.00% 69.51% # Class of committed instruction system.cpu0.op_class_0::SimdAdd 0 0.00% 69.51% # Class of committed instruction system.cpu0.op_class_0::SimdAddAcc 0 0.00% 69.51% # Class of committed instruction system.cpu0.op_class_0::SimdAlu 0 0.00% 69.51% # Class of committed instruction system.cpu0.op_class_0::SimdCmp 0 0.00% 69.51% # Class of committed instruction system.cpu0.op_class_0::SimdCvt 0 0.00% 69.51% # Class of committed instruction system.cpu0.op_class_0::SimdMisc 0 0.00% 69.51% # Class of committed instruction system.cpu0.op_class_0::SimdMult 0 0.00% 69.51% # Class of committed instruction system.cpu0.op_class_0::SimdMultAcc 0 0.00% 69.51% # Class of committed instruction system.cpu0.op_class_0::SimdShift 0 0.00% 69.51% # Class of committed instruction system.cpu0.op_class_0::SimdShiftAcc 0 0.00% 69.51% # Class of committed instruction system.cpu0.op_class_0::SimdSqrt 0 0.00% 69.51% # Class of committed instruction system.cpu0.op_class_0::SimdFloatAdd 0 0.00% 69.51% # Class of committed instruction system.cpu0.op_class_0::SimdFloatAlu 0 0.00% 69.51% # Class of committed instruction system.cpu0.op_class_0::SimdFloatCmp 0 0.00% 69.51% # Class of committed instruction system.cpu0.op_class_0::SimdFloatCvt 0 0.00% 69.51% # Class of committed instruction system.cpu0.op_class_0::SimdFloatDiv 0 0.00% 69.51% # Class of committed instruction system.cpu0.op_class_0::SimdFloatMisc 79522 0.01% 69.52% # Class of committed instruction system.cpu0.op_class_0::SimdFloatMult 0 0.00% 69.52% # Class of committed instruction system.cpu0.op_class_0::SimdFloatMultAcc 0 0.00% 69.52% # Class of committed instruction system.cpu0.op_class_0::SimdFloatSqrt 0 0.00% 69.52% # Class of committed instruction system.cpu0.op_class_0::MemRead 99981749 16.00% 85.52% # Class of committed instruction system.cpu0.op_class_0::MemWrite 90434005 14.48% 100.00% # Class of committed instruction system.cpu0.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu0.op_class_0::total 624758290 # Class of committed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 13151 # number of quiesce instructions executed system.cpu0.tickCycles 847175236 # Number of cycles that the object actually ticked system.cpu0.idleCycles 285359210 # Total number of cycles that the object has spent stopped system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states system.cpu0.dcache.tags.replacements 6574289 # number of replacements system.cpu0.dcache.tags.tagsinuse 508.066535 # Cycle average of tags in use system.cpu0.dcache.tags.total_refs 184992173 # Total number of references to valid blocks. system.cpu0.dcache.tags.sampled_refs 6574801 # Sample count of references to valid blocks. system.cpu0.dcache.tags.avg_refs 28.136543 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 5039429000 # Cycle when the warmup percentage was hit. system.cpu0.dcache.tags.occ_blocks::cpu0.data 508.066535 # Average occupied blocks per requestor system.cpu0.dcache.tags.occ_percent::cpu0.data 0.992317 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.992317 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::0 211 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::1 229 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 72 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu0.dcache.tags.tag_accesses 392594755 # Number of tag accesses system.cpu0.dcache.tags.data_accesses 392594755 # Number of data accesses system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states system.cpu0.dcache.ReadReq_hits::cpu0.data 95401287 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::total 95401287 # number of ReadReq hits system.cpu0.dcache.WriteReq_hits::cpu0.data 84287466 # number of WriteReq hits system.cpu0.dcache.WriteReq_hits::total 84287466 # number of WriteReq hits system.cpu0.dcache.SoftPFReq_hits::cpu0.data 321965 # number of SoftPFReq hits system.cpu0.dcache.SoftPFReq_hits::total 321965 # number of SoftPFReq hits system.cpu0.dcache.WriteLineReq_hits::cpu0.data 280846 # number of WriteLineReq hits system.cpu0.dcache.WriteLineReq_hits::total 280846 # number of WriteLineReq hits system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 2060188 # number of LoadLockedReq hits system.cpu0.dcache.LoadLockedReq_hits::total 2060188 # number of LoadLockedReq hits system.cpu0.dcache.StoreCondReq_hits::cpu0.data 2061125 # number of StoreCondReq hits system.cpu0.dcache.StoreCondReq_hits::total 2061125 # number of StoreCondReq hits system.cpu0.dcache.demand_hits::cpu0.data 179969599 # number of demand (read+write) hits system.cpu0.dcache.demand_hits::total 179969599 # number of demand (read+write) hits system.cpu0.dcache.overall_hits::cpu0.data 180291564 # number of overall hits system.cpu0.dcache.overall_hits::total 180291564 # number of overall hits system.cpu0.dcache.ReadReq_misses::cpu0.data 3840217 # number of ReadReq misses system.cpu0.dcache.ReadReq_misses::total 3840217 # number of ReadReq misses system.cpu0.dcache.WriteReq_misses::cpu0.data 2718306 # number of WriteReq misses system.cpu0.dcache.WriteReq_misses::total 2718306 # number of WriteReq misses system.cpu0.dcache.SoftPFReq_misses::cpu0.data 733729 # number of SoftPFReq misses system.cpu0.dcache.SoftPFReq_misses::total 733729 # number of SoftPFReq misses system.cpu0.dcache.WriteLineReq_misses::cpu0.data 858022 # number of WriteLineReq misses system.cpu0.dcache.WriteLineReq_misses::total 858022 # number of WriteLineReq misses system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 199658 # number of LoadLockedReq misses system.cpu0.dcache.LoadLockedReq_misses::total 199658 # number of LoadLockedReq misses system.cpu0.dcache.StoreCondReq_misses::cpu0.data 197397 # number of StoreCondReq misses system.cpu0.dcache.StoreCondReq_misses::total 197397 # number of StoreCondReq misses system.cpu0.dcache.demand_misses::cpu0.data 7416545 # number of demand (read+write) misses system.cpu0.dcache.demand_misses::total 7416545 # number of demand (read+write) misses system.cpu0.dcache.overall_misses::cpu0.data 8150274 # number of overall misses system.cpu0.dcache.overall_misses::total 8150274 # number of overall misses system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 59779296000 # number of ReadReq miss cycles system.cpu0.dcache.ReadReq_miss_latency::total 59779296000 # number of ReadReq miss cycles system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 54754909500 # number of WriteReq miss cycles system.cpu0.dcache.WriteReq_miss_latency::total 54754909500 # number of WriteReq miss cycles system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 28457275000 # number of WriteLineReq miss cycles system.cpu0.dcache.WriteLineReq_miss_latency::total 28457275000 # number of WriteLineReq miss cycles system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2995014000 # number of LoadLockedReq miss cycles system.cpu0.dcache.LoadLockedReq_miss_latency::total 2995014000 # number of LoadLockedReq miss cycles system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4953933500 # number of StoreCondReq miss cycles system.cpu0.dcache.StoreCondReq_miss_latency::total 4953933500 # number of StoreCondReq miss cycles system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 3818500 # number of StoreCondFailReq miss cycles system.cpu0.dcache.StoreCondFailReq_miss_latency::total 3818500 # number of StoreCondFailReq miss cycles system.cpu0.dcache.demand_miss_latency::cpu0.data 142991480500 # number of demand (read+write) miss cycles system.cpu0.dcache.demand_miss_latency::total 142991480500 # number of demand (read+write) miss cycles system.cpu0.dcache.overall_miss_latency::cpu0.data 142991480500 # number of overall miss cycles system.cpu0.dcache.overall_miss_latency::total 142991480500 # number of overall miss cycles system.cpu0.dcache.ReadReq_accesses::cpu0.data 99241504 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.ReadReq_accesses::total 99241504 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::cpu0.data 87005772 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::total 87005772 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 1055694 # number of SoftPFReq accesses(hits+misses) system.cpu0.dcache.SoftPFReq_accesses::total 1055694 # number of SoftPFReq accesses(hits+misses) system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1138868 # number of WriteLineReq accesses(hits+misses) system.cpu0.dcache.WriteLineReq_accesses::total 1138868 # number of WriteLineReq accesses(hits+misses) system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2259846 # number of LoadLockedReq accesses(hits+misses) system.cpu0.dcache.LoadLockedReq_accesses::total 2259846 # number of LoadLockedReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2258522 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::total 2258522 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.demand_accesses::cpu0.data 187386144 # number of demand (read+write) accesses system.cpu0.dcache.demand_accesses::total 187386144 # number of demand (read+write) accesses system.cpu0.dcache.overall_accesses::cpu0.data 188441838 # number of overall (read+write) accesses system.cpu0.dcache.overall_accesses::total 188441838 # number of overall (read+write) accesses system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.038696 # miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_miss_rate::total 0.038696 # miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.031243 # miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_miss_rate::total 0.031243 # miss rate for WriteReq accesses system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.695021 # miss rate for SoftPFReq accesses system.cpu0.dcache.SoftPFReq_miss_rate::total 0.695021 # miss rate for SoftPFReq accesses system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.753399 # miss rate for WriteLineReq accesses system.cpu0.dcache.WriteLineReq_miss_rate::total 0.753399 # miss rate for WriteLineReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.088350 # miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.088350 # miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.087401 # miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::total 0.087401 # miss rate for StoreCondReq accesses system.cpu0.dcache.demand_miss_rate::cpu0.data 0.039579 # miss rate for demand accesses system.cpu0.dcache.demand_miss_rate::total 0.039579 # miss rate for demand accesses system.cpu0.dcache.overall_miss_rate::cpu0.data 0.043251 # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::total 0.043251 # miss rate for overall accesses system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15566.645322 # average ReadReq miss latency system.cpu0.dcache.ReadReq_avg_miss_latency::total 15566.645322 # average ReadReq miss latency system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 20143.026392 # average WriteReq miss latency system.cpu0.dcache.WriteReq_avg_miss_latency::total 20143.026392 # average WriteReq miss latency system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 33166.136766 # average WriteLineReq miss latency system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 33166.136766 # average WriteLineReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15000.721233 # average LoadLockedReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15000.721233 # average LoadLockedReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 25096.295790 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 25096.295790 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19280.066460 # average overall miss latency system.cpu0.dcache.demand_avg_miss_latency::total 19280.066460 # average overall miss latency system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 17544.377097 # average overall miss latency system.cpu0.dcache.overall_avg_miss_latency::total 17544.377097 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.writebacks::writebacks 6574291 # number of writebacks system.cpu0.dcache.writebacks::total 6574291 # number of writebacks system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 237792 # number of ReadReq MSHR hits system.cpu0.dcache.ReadReq_mshr_hits::total 237792 # number of ReadReq MSHR hits system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1117306 # number of WriteReq MSHR hits system.cpu0.dcache.WriteReq_mshr_hits::total 1117306 # number of WriteReq MSHR hits system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 90 # number of WriteLineReq MSHR hits system.cpu0.dcache.WriteLineReq_mshr_hits::total 90 # number of WriteLineReq MSHR hits system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 48445 # number of LoadLockedReq MSHR hits system.cpu0.dcache.LoadLockedReq_mshr_hits::total 48445 # number of LoadLockedReq MSHR hits system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data 60 # number of StoreCondReq MSHR hits system.cpu0.dcache.StoreCondReq_mshr_hits::total 60 # number of StoreCondReq MSHR hits system.cpu0.dcache.demand_mshr_hits::cpu0.data 1355188 # number of demand (read+write) MSHR hits system.cpu0.dcache.demand_mshr_hits::total 1355188 # number of demand (read+write) MSHR hits system.cpu0.dcache.overall_mshr_hits::cpu0.data 1355188 # number of overall MSHR hits system.cpu0.dcache.overall_mshr_hits::total 1355188 # number of overall MSHR hits system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3602425 # number of ReadReq MSHR misses system.cpu0.dcache.ReadReq_mshr_misses::total 3602425 # number of ReadReq MSHR misses system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1601000 # number of WriteReq MSHR misses system.cpu0.dcache.WriteReq_mshr_misses::total 1601000 # number of WriteReq MSHR misses system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 732137 # number of SoftPFReq MSHR misses system.cpu0.dcache.SoftPFReq_mshr_misses::total 732137 # number of SoftPFReq MSHR misses system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 857932 # number of WriteLineReq MSHR misses system.cpu0.dcache.WriteLineReq_mshr_misses::total 857932 # number of WriteLineReq MSHR misses system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 151213 # number of LoadLockedReq MSHR misses system.cpu0.dcache.LoadLockedReq_mshr_misses::total 151213 # number of LoadLockedReq MSHR misses system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 197337 # number of StoreCondReq MSHR misses system.cpu0.dcache.StoreCondReq_mshr_misses::total 197337 # number of StoreCondReq MSHR misses system.cpu0.dcache.demand_mshr_misses::cpu0.data 6061357 # number of demand (read+write) MSHR misses system.cpu0.dcache.demand_mshr_misses::total 6061357 # number of demand (read+write) MSHR misses system.cpu0.dcache.overall_mshr_misses::cpu0.data 6793494 # number of overall MSHR misses system.cpu0.dcache.overall_mshr_misses::total 6793494 # number of overall MSHR misses system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 29793 # number of ReadReq MSHR uncacheable system.cpu0.dcache.ReadReq_mshr_uncacheable::total 29793 # number of ReadReq MSHR uncacheable system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 29400 # number of WriteReq MSHR uncacheable system.cpu0.dcache.WriteReq_mshr_uncacheable::total 29400 # number of WriteReq MSHR uncacheable system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 59193 # number of overall MSHR uncacheable misses system.cpu0.dcache.overall_mshr_uncacheable_misses::total 59193 # number of overall MSHR uncacheable misses system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 50925119500 # number of ReadReq MSHR miss cycles system.cpu0.dcache.ReadReq_mshr_miss_latency::total 50925119500 # number of ReadReq MSHR miss cycles system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 31536308500 # number of WriteReq MSHR miss cycles system.cpu0.dcache.WriteReq_mshr_miss_latency::total 31536308500 # number of WriteReq MSHR miss cycles system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 16544300500 # number of SoftPFReq MSHR miss cycles system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 16544300500 # number of SoftPFReq MSHR miss cycles system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 27594364000 # number of WriteLineReq MSHR miss cycles system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 27594364000 # number of WriteLineReq MSHR miss cycles system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1964885000 # number of LoadLockedReq MSHR miss cycles system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1964885000 # number of LoadLockedReq MSHR miss cycles system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4754516500 # number of StoreCondReq MSHR miss cycles system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4754516500 # number of StoreCondReq MSHR miss cycles system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 3441500 # number of StoreCondFailReq MSHR miss cycles system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 3441500 # number of StoreCondFailReq MSHR miss cycles system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 110055792000 # number of demand (read+write) MSHR miss cycles system.cpu0.dcache.demand_mshr_miss_latency::total 110055792000 # number of demand (read+write) MSHR miss cycles system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 126600092500 # number of overall MSHR miss cycles system.cpu0.dcache.overall_mshr_miss_latency::total 126600092500 # number of overall MSHR miss cycles system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5675765000 # number of ReadReq MSHR uncacheable cycles system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5675765000 # number of ReadReq MSHR uncacheable cycles system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5675765000 # number of overall MSHR uncacheable cycles system.cpu0.dcache.overall_mshr_uncacheable_latency::total 5675765000 # number of overall MSHR uncacheable cycles system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036300 # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036300 # mshr miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018401 # mshr miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018401 # mshr miss rate for WriteReq accesses system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.693513 # mshr miss rate for SoftPFReq accesses system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.693513 # mshr miss rate for SoftPFReq accesses system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.753320 # mshr miss rate for WriteLineReq accesses system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.753320 # mshr miss rate for WriteLineReq accesses system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.066913 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.066913 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.087374 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.087374 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.032347 # mshr miss rate for demand accesses system.cpu0.dcache.demand_mshr_miss_rate::total 0.032347 # mshr miss rate for demand accesses system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.036051 # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::total 0.036051 # mshr miss rate for overall accesses system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14136.344129 # average ReadReq mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14136.344129 # average ReadReq mshr miss latency system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 19697.881636 # average WriteReq mshr miss latency system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 19697.881636 # average WriteReq mshr miss latency system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 22597.274144 # average SoftPFReq mshr miss latency system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 22597.274144 # average SoftPFReq mshr miss latency system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 32163.812517 # average WriteLineReq mshr miss latency system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 32163.812517 # average WriteLineReq mshr miss latency system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12994.153942 # average LoadLockedReq mshr miss latency system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12994.153942 # average LoadLockedReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 24093.385934 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 24093.385934 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18156.955942 # average overall mshr miss latency system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18156.955942 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 18635.490441 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18635.490441 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 190506.662639 # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 190506.662639 # average ReadReq mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 95885.746625 # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 95885.746625 # average overall mshr uncacheable latency system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states system.cpu0.icache.tags.replacements 10998491 # number of replacements system.cpu0.icache.tags.tagsinuse 511.932591 # Cycle average of tags in use system.cpu0.icache.tags.total_refs 274007938 # Total number of references to valid blocks. system.cpu0.icache.tags.sampled_refs 10999003 # Sample count of references to valid blocks. system.cpu0.icache.tags.avg_refs 24.912070 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 22037323000 # Cycle when the warmup percentage was hit. system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.932591 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999868 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.999868 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::0 207 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::1 273 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::2 32 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu0.icache.tags.tag_accesses 581012885 # Number of tag accesses system.cpu0.icache.tags.data_accesses 581012885 # Number of data accesses system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states system.cpu0.icache.ReadReq_hits::cpu0.inst 274007938 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::total 274007938 # number of ReadReq hits system.cpu0.icache.demand_hits::cpu0.inst 274007938 # number of demand (read+write) hits system.cpu0.icache.demand_hits::total 274007938 # number of demand (read+write) hits system.cpu0.icache.overall_hits::cpu0.inst 274007938 # number of overall hits system.cpu0.icache.overall_hits::total 274007938 # number of overall hits system.cpu0.icache.ReadReq_misses::cpu0.inst 10999003 # number of ReadReq misses system.cpu0.icache.ReadReq_misses::total 10999003 # number of ReadReq misses system.cpu0.icache.demand_misses::cpu0.inst 10999003 # number of demand (read+write) misses system.cpu0.icache.demand_misses::total 10999003 # number of demand (read+write) misses system.cpu0.icache.overall_misses::cpu0.inst 10999003 # number of overall misses system.cpu0.icache.overall_misses::total 10999003 # number of overall misses system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 111429437000 # number of ReadReq miss cycles system.cpu0.icache.ReadReq_miss_latency::total 111429437000 # number of ReadReq miss cycles system.cpu0.icache.demand_miss_latency::cpu0.inst 111429437000 # number of demand (read+write) miss cycles system.cpu0.icache.demand_miss_latency::total 111429437000 # number of demand (read+write) miss cycles system.cpu0.icache.overall_miss_latency::cpu0.inst 111429437000 # number of overall miss cycles system.cpu0.icache.overall_miss_latency::total 111429437000 # number of overall miss cycles system.cpu0.icache.ReadReq_accesses::cpu0.inst 285006941 # number of ReadReq accesses(hits+misses) system.cpu0.icache.ReadReq_accesses::total 285006941 # number of ReadReq accesses(hits+misses) system.cpu0.icache.demand_accesses::cpu0.inst 285006941 # number of demand (read+write) accesses system.cpu0.icache.demand_accesses::total 285006941 # number of demand (read+write) accesses system.cpu0.icache.overall_accesses::cpu0.inst 285006941 # number of overall (read+write) accesses system.cpu0.icache.overall_accesses::total 285006941 # number of overall (read+write) accesses system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.038592 # miss rate for ReadReq accesses system.cpu0.icache.ReadReq_miss_rate::total 0.038592 # miss rate for ReadReq accesses system.cpu0.icache.demand_miss_rate::cpu0.inst 0.038592 # miss rate for demand accesses system.cpu0.icache.demand_miss_rate::total 0.038592 # miss rate for demand accesses system.cpu0.icache.overall_miss_rate::cpu0.inst 0.038592 # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::total 0.038592 # miss rate for overall accesses system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10130.867043 # average ReadReq miss latency system.cpu0.icache.ReadReq_avg_miss_latency::total 10130.867043 # average ReadReq miss latency system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10130.867043 # average overall miss latency system.cpu0.icache.demand_avg_miss_latency::total 10130.867043 # average overall miss latency system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10130.867043 # average overall miss latency system.cpu0.icache.overall_avg_miss_latency::total 10130.867043 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.writebacks::writebacks 10998491 # number of writebacks system.cpu0.icache.writebacks::total 10998491 # number of writebacks system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 10999003 # number of ReadReq MSHR misses system.cpu0.icache.ReadReq_mshr_misses::total 10999003 # number of ReadReq MSHR misses system.cpu0.icache.demand_mshr_misses::cpu0.inst 10999003 # number of demand (read+write) MSHR misses system.cpu0.icache.demand_mshr_misses::total 10999003 # number of demand (read+write) MSHR misses system.cpu0.icache.overall_mshr_misses::cpu0.inst 10999003 # number of overall MSHR misses system.cpu0.icache.overall_mshr_misses::total 10999003 # number of overall MSHR misses system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 52300 # number of ReadReq MSHR uncacheable system.cpu0.icache.ReadReq_mshr_uncacheable::total 52300 # number of ReadReq MSHR uncacheable system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 52300 # number of overall MSHR uncacheable misses system.cpu0.icache.overall_mshr_uncacheable_misses::total 52300 # number of overall MSHR uncacheable misses system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 105929935500 # number of ReadReq MSHR miss cycles system.cpu0.icache.ReadReq_mshr_miss_latency::total 105929935500 # number of ReadReq MSHR miss cycles system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 105929935500 # number of demand (read+write) MSHR miss cycles system.cpu0.icache.demand_mshr_miss_latency::total 105929935500 # number of demand (read+write) MSHR miss cycles system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 105929935500 # number of overall MSHR miss cycles system.cpu0.icache.overall_mshr_miss_latency::total 105929935500 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 4836784500 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 4836784500 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 4836784500 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 4836784500 # number of overall MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.038592 # mshr miss rate for ReadReq accesses system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.038592 # mshr miss rate for ReadReq accesses system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.038592 # mshr miss rate for demand accesses system.cpu0.icache.demand_mshr_miss_rate::total 0.038592 # mshr miss rate for demand accesses system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.038592 # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_miss_rate::total 0.038592 # mshr miss rate for overall accesses system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9630.867043 # average ReadReq mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9630.867043 # average ReadReq mshr miss latency system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9630.867043 # average overall mshr miss latency system.cpu0.icache.demand_avg_mshr_miss_latency::total 9630.867043 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9630.867043 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_miss_latency::total 9630.867043 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 92481.539197 # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 92481.539197 # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 92481.539197 # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 92481.539197 # average overall mshr uncacheable latency system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states system.cpu0.l2cache.prefetcher.num_hwpf_issued 8833822 # number of hwpf issued system.cpu0.l2cache.prefetcher.pfIdentified 8835143 # number of prefetch candidates identified system.cpu0.l2cache.prefetcher.pfBufferHit 1166 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size system.cpu0.l2cache.prefetcher.pfSpanPage 1192777 # number of prefetches not generated due to page crossing system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states system.cpu0.l2cache.tags.replacements 3147716 # number of replacements system.cpu0.l2cache.tags.tagsinuse 16192.217188 # Cycle average of tags in use system.cpu0.l2cache.tags.total_refs 27546589 # Total number of references to valid blocks. system.cpu0.l2cache.tags.sampled_refs 3163437 # Sample count of references to valid blocks. system.cpu0.l2cache.tags.avg_refs 8.707804 # Average number of references to valid blocks. system.cpu0.l2cache.tags.warmup_cycle 5661168000 # Cycle when the warmup percentage was hit. system.cpu0.l2cache.tags.occ_blocks::writebacks 15379.701531 # Average occupied blocks per requestor system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 70.199902 # Average occupied blocks per requestor system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 67.449935 # Average occupied blocks per requestor system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 674.865820 # Average occupied blocks per requestor system.cpu0.l2cache.tags.occ_percent::writebacks 0.938702 # Average percentage of cache occupancy system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.004285 # Average percentage of cache occupancy system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.004117 # Average percentage of cache occupancy system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.041191 # Average percentage of cache occupancy system.cpu0.l2cache.tags.occ_percent::total 0.988295 # Average percentage of cache occupancy system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1251 # Occupied blocks per task id system.cpu0.l2cache.tags.occ_task_id_blocks::1023 80 # Occupied blocks per task id system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14390 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1022::0 7 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 16 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 214 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 985 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 29 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 13 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 66 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 230 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 603 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4671 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 8629 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 257 # Occupied blocks per task id system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.076355 # Percentage of cache occupancy per task id system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.004883 # Percentage of cache occupancy per task id system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.878296 # Percentage of cache occupancy per task id system.cpu0.l2cache.tags.tag_accesses 591522987 # Number of tag accesses system.cpu0.l2cache.tags.data_accesses 591522987 # Number of data accesses system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 626255 # number of ReadReq hits system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 186723 # number of ReadReq hits system.cpu0.l2cache.ReadReq_hits::total 812978 # number of ReadReq hits system.cpu0.l2cache.WritebackDirty_hits::writebacks 4288810 # number of WritebackDirty hits system.cpu0.l2cache.WritebackDirty_hits::total 4288810 # number of WritebackDirty hits system.cpu0.l2cache.WritebackClean_hits::writebacks 13280453 # number of WritebackClean hits system.cpu0.l2cache.WritebackClean_hits::total 13280453 # number of WritebackClean hits system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 665 # number of UpgradeReq hits system.cpu0.l2cache.UpgradeReq_hits::total 665 # number of UpgradeReq hits system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 1 # number of SCUpgradeReq hits system.cpu0.l2cache.SCUpgradeReq_hits::total 1 # number of SCUpgradeReq hits system.cpu0.l2cache.ReadExReq_hits::cpu0.data 1035920 # number of ReadExReq hits system.cpu0.l2cache.ReadExReq_hits::total 1035920 # number of ReadExReq hits system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 10174002 # number of ReadCleanReq hits system.cpu0.l2cache.ReadCleanReq_hits::total 10174002 # number of ReadCleanReq hits system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 3369103 # number of ReadSharedReq hits system.cpu0.l2cache.ReadSharedReq_hits::total 3369103 # number of ReadSharedReq hits system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 227555 # number of InvalidateReq hits system.cpu0.l2cache.InvalidateReq_hits::total 227555 # number of InvalidateReq hits system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 626255 # number of demand (read+write) hits system.cpu0.l2cache.demand_hits::cpu0.itb.walker 186723 # number of demand (read+write) hits system.cpu0.l2cache.demand_hits::cpu0.inst 10174002 # number of demand (read+write) hits system.cpu0.l2cache.demand_hits::cpu0.data 4405023 # number of demand (read+write) hits system.cpu0.l2cache.demand_hits::total 15392003 # number of demand (read+write) hits system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 626255 # number of overall hits system.cpu0.l2cache.overall_hits::cpu0.itb.walker 186723 # number of overall hits system.cpu0.l2cache.overall_hits::cpu0.inst 10174002 # number of overall hits system.cpu0.l2cache.overall_hits::cpu0.data 4405023 # number of overall hits system.cpu0.l2cache.overall_hits::total 15392003 # number of overall hits system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 13618 # number of ReadReq misses system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 9516 # number of ReadReq misses system.cpu0.l2cache.ReadReq_misses::total 23134 # number of ReadReq misses system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 275991 # number of UpgradeReq misses system.cpu0.l2cache.UpgradeReq_misses::total 275991 # number of UpgradeReq misses system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 197331 # number of SCUpgradeReq misses system.cpu0.l2cache.SCUpgradeReq_misses::total 197331 # number of SCUpgradeReq misses system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 5 # number of SCUpgradeFailReq misses system.cpu0.l2cache.SCUpgradeFailReq_misses::total 5 # number of SCUpgradeFailReq misses system.cpu0.l2cache.ReadExReq_misses::cpu0.data 297475 # number of ReadExReq misses system.cpu0.l2cache.ReadExReq_misses::total 297475 # number of ReadExReq misses system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 825000 # number of ReadCleanReq misses system.cpu0.l2cache.ReadCleanReq_misses::total 825000 # number of ReadCleanReq misses system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 1116183 # 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number of ReadExReq miss cycles system.cpu0.l2cache.ReadExReq_miss_latency::total 14927255997 # number of ReadExReq miss cycles system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 27980842000 # number of ReadCleanReq miss cycles system.cpu0.l2cache.ReadCleanReq_miss_latency::total 27980842000 # number of ReadCleanReq miss cycles system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 40509457995 # number of ReadSharedReq miss cycles system.cpu0.l2cache.ReadSharedReq_miss_latency::total 40509457995 # number of ReadSharedReq miss cycles system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data 326706500 # number of InvalidateReq miss cycles system.cpu0.l2cache.InvalidateReq_miss_latency::total 326706500 # number of InvalidateReq miss cycles system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 516990000 # number of demand (read+write) miss cycles system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 406929500 # number of demand (read+write) miss cycles system.cpu0.l2cache.demand_miss_latency::cpu0.inst 27980842000 # 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number of WritebackDirty accesses(hits+misses) system.cpu0.l2cache.WritebackDirty_accesses::total 4288810 # number of WritebackDirty accesses(hits+misses) system.cpu0.l2cache.WritebackClean_accesses::writebacks 13280453 # number of WritebackClean accesses(hits+misses) system.cpu0.l2cache.WritebackClean_accesses::total 13280453 # number of WritebackClean accesses(hits+misses) system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 276656 # number of UpgradeReq accesses(hits+misses) system.cpu0.l2cache.UpgradeReq_accesses::total 276656 # number of UpgradeReq accesses(hits+misses) system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 197332 # number of SCUpgradeReq accesses(hits+misses) system.cpu0.l2cache.SCUpgradeReq_accesses::total 197332 # number of SCUpgradeReq accesses(hits+misses) system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 5 # number of SCUpgradeFailReq accesses(hits+misses) system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 5 # number of SCUpgradeFailReq accesses(hits+misses) system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1333395 # number of ReadExReq accesses(hits+misses) system.cpu0.l2cache.ReadExReq_accesses::total 1333395 # number of ReadExReq accesses(hits+misses) system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 10999002 # number of ReadCleanReq accesses(hits+misses) system.cpu0.l2cache.ReadCleanReq_accesses::total 10999002 # number of ReadCleanReq accesses(hits+misses) system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 4485286 # number of ReadSharedReq accesses(hits+misses) system.cpu0.l2cache.ReadSharedReq_accesses::total 4485286 # number of ReadSharedReq accesses(hits+misses) system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 855584 # number of InvalidateReq accesses(hits+misses) system.cpu0.l2cache.InvalidateReq_accesses::total 855584 # number of InvalidateReq accesses(hits+misses) system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 639873 # number of demand (read+write) accesses system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 196239 # number of demand (read+write) accesses system.cpu0.l2cache.demand_accesses::cpu0.inst 10999002 # number of demand (read+write) accesses system.cpu0.l2cache.demand_accesses::cpu0.data 5818681 # number of demand (read+write) accesses system.cpu0.l2cache.demand_accesses::total 17653795 # number of demand (read+write) accesses system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 639873 # number of overall (read+write) accesses system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 196239 # number of overall (read+write) accesses system.cpu0.l2cache.overall_accesses::cpu0.inst 10999002 # number of overall (read+write) accesses system.cpu0.l2cache.overall_accesses::cpu0.data 5818681 # number of overall (read+write) accesses system.cpu0.l2cache.overall_accesses::total 17653795 # number of overall (read+write) accesses system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.021282 # miss rate for ReadReq accesses system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.048492 # miss rate for ReadReq accesses system.cpu0.l2cache.ReadReq_miss_rate::total 0.027669 # miss rate for ReadReq accesses system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.997596 # 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number of ReadReq MSHR miss cycles system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 785051000 # number of ReadReq MSHR miss cycles system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 42685466504 # number of HardPFReq MSHR miss cycles system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 42685466504 # number of HardPFReq MSHR miss cycles system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 5679653996 # number of UpgradeReq MSHR miss cycles system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 5679653996 # number of UpgradeReq MSHR miss cycles system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 3269289499 # number of SCUpgradeReq MSHR miss cycles system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 3269289499 # number of SCUpgradeReq MSHR miss cycles system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 2944999 # number of SCUpgradeFailReq MSHR miss cycles system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 2944999 # number of SCUpgradeFailReq MSHR miss cycles system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 11923656997 # number of ReadExReq MSHR miss cycles system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 11923656997 # number of ReadExReq MSHR miss cycles system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 23030463500 # number of ReadCleanReq MSHR miss cycles system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 23030463500 # number of ReadCleanReq MSHR miss cycles system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 33712054495 # number of ReadSharedReq MSHR miss cycles system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 33712054495 # number of ReadSharedReq MSHR miss cycles system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 20896498500 # number of InvalidateReq MSHR miss cycles system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 20896498500 # number of InvalidateReq MSHR miss cycles system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 435264000 # number of demand (read+write) MSHR miss cycles system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 349787000 # number of demand (read+write) MSHR miss cycles system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 23030463500 # number of demand (read+write) MSHR miss cycles system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 45635711492 # number of demand (read+write) MSHR miss cycles system.cpu0.l2cache.demand_mshr_miss_latency::total 69451225992 # number of demand (read+write) MSHR miss cycles system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 435264000 # number of overall MSHR miss cycles system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 349787000 # number of overall MSHR miss cycles system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 23030463500 # number of overall MSHR miss cycles system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 45635711492 # number of overall MSHR miss cycles system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 42685466504 # number of overall MSHR miss cycles system.cpu0.l2cache.overall_mshr_miss_latency::total 112136692496 # number of overall MSHR miss cycles system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 4418384500 # number of ReadReq MSHR uncacheable cycles system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5437142000 # number of ReadReq MSHR uncacheable cycles system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 9855526500 # number of ReadReq MSHR uncacheable cycles system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 4418384500 # number of overall MSHR uncacheable cycles system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 5437142000 # number of overall MSHR uncacheable cycles system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 9855526500 # number of overall MSHR uncacheable cycles system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.021281 # mshr miss rate for ReadReq accesses system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.048472 # mshr miss rate for ReadReq accesses system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.027663 # mshr miss rate for ReadReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.997596 # mshr miss rate for UpgradeReq accesses system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.997596 # mshr miss rate for UpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.999995 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.999995 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.215232 # mshr miss rate for ReadExReq accesses system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.215232 # mshr miss rate for ReadExReq accesses system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.075006 # mshr miss rate for ReadCleanReq accesses system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.075006 # mshr miss rate for ReadCleanReq accesses system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.248615 # mshr miss rate for ReadSharedReq accesses system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.248615 # mshr miss rate for ReadSharedReq accesses system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.734031 # mshr miss rate for InvalidateReq accesses system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.734031 # mshr miss rate for InvalidateReq accesses system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.021281 # mshr miss rate for demand accesses system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.048472 # mshr miss rate for demand accesses system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.075006 # mshr miss rate for demand accesses system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.240965 # mshr miss rate for demand accesses system.cpu0.l2cache.demand_mshr_miss_rate::total 0.127464 # mshr miss rate for demand accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.021281 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.048472 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.075006 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.240965 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::total 0.177578 # mshr miss rate for overall accesses system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 31964.749945 # average ReadReq mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 36773.233810 # average ReadReq mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 33942.280254 # average ReadReq mshr miss latency system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 48247.921077 # average HardPFReq mshr miss latency system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 48247.921077 # average HardPFReq mshr miss latency system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20579.127566 # average UpgradeReq mshr miss latency system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20579.127566 # average UpgradeReq mshr miss latency system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 16567.541334 # average SCUpgradeReq mshr miss latency system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 16567.541334 # average SCUpgradeReq mshr miss latency system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 588999.800000 # average SCUpgradeFailReq mshr miss latency system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 588999.800000 # average SCUpgradeFailReq mshr miss latency system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 41547.435606 # average ReadExReq mshr miss latency system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 41547.435606 # average ReadExReq mshr miss latency system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 27916.187063 # average ReadCleanReq mshr miss latency system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 27916.187063 # average ReadCleanReq mshr miss latency system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 30232.016808 # average ReadSharedReq mshr miss latency system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 30232.016808 # average ReadSharedReq mshr miss latency system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 33273.354564 # average InvalidateReq mshr miss latency system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 33273.354564 # average InvalidateReq mshr miss latency system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 31964.749945 # average overall mshr miss latency system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 36773.233810 # average overall mshr miss latency system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 27916.187063 # average overall mshr miss latency system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 32548.114608 # average overall mshr miss latency system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 30864.262300 # average overall mshr miss latency system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 31964.749945 # average overall mshr miss latency system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 36773.233810 # average overall mshr miss latency system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 27916.187063 # average overall mshr miss latency system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 32548.114608 # average overall mshr miss latency system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 48247.921077 # average overall mshr miss latency system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 35770.124238 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 84481.539197 # average ReadReq mshr uncacheable latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182497.298023 # average ReadReq mshr uncacheable latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 120053.189675 # average ReadReq mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 84481.539197 # average overall mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 91854.476036 # average overall mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 88395.921717 # average overall mshr uncacheable latency system.cpu0.toL2Bus.snoop_filter.tot_requests 36072564 # Total number of requests made to the snoop filter. system.cpu0.toL2Bus.snoop_filter.hit_single_requests 18399437 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 3515 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu0.toL2Bus.snoop_filter.tot_snoops 2427957 # Total number of snoops made to the snoop filter. system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 2427386 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 571 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states system.cpu0.toL2Bus.trans_dist::ReadReq 1003133 # Transaction distribution system.cpu0.toL2Bus.trans_dist::ReadResp 16585926 # Transaction distribution system.cpu0.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution system.cpu0.toL2Bus.trans_dist::WriteReq 29400 # Transaction distribution system.cpu0.toL2Bus.trans_dist::WriteResp 29400 # Transaction distribution system.cpu0.toL2Bus.trans_dist::WritebackDirty 6083435 # Transaction distribution system.cpu0.toL2Bus.trans_dist::WritebackClean 13283967 # Transaction distribution system.cpu0.toL2Bus.trans_dist::CleanEvict 3350152 # Transaction distribution system.cpu0.toL2Bus.trans_dist::HardPFReq 1133444 # Transaction distribution system.cpu0.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution system.cpu0.toL2Bus.trans_dist::UpgradeReq 490495 # Transaction distribution system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 347636 # Transaction distribution system.cpu0.toL2Bus.trans_dist::UpgradeResp 543136 # Transaction distribution system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 77 # Transaction distribution system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 138 # Transaction distribution system.cpu0.toL2Bus.trans_dist::ReadExReq 1366077 # Transaction distribution system.cpu0.toL2Bus.trans_dist::ReadExResp 1342549 # Transaction distribution system.cpu0.toL2Bus.trans_dist::ReadCleanReq 10999003 # Transaction distribution system.cpu0.toL2Bus.trans_dist::ReadSharedReq 5499511 # Transaction distribution system.cpu0.toL2Bus.trans_dist::InvalidateReq 903440 # Transaction distribution system.cpu0.toL2Bus.trans_dist::InvalidateResp 855584 # Transaction distribution system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 33101096 # Packet count per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 21166131 # Packet count per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 412052 # Packet count per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1345098 # Packet count per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_count::total 56024377 # Packet count per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 1411186752 # Cumulative packet size per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 800229141 # Cumulative packet size per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1569912 # Cumulative packet size per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 5118984 # Cumulative packet size per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_size::total 2218104789 # Cumulative packet size per connected master and slave (bytes) system.cpu0.toL2Bus.snoops 7999072 # Total snoops (count) system.cpu0.toL2Bus.snoopTraffic 122429440 # Total snoop traffic (bytes) system.cpu0.toL2Bus.snoop_fanout::samples 26916994 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::mean 0.103450 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::stdev 0.304616 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::0 24132997 89.66% 89.66% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::1 2783426 10.34% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::2 571 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::total 26916994 # Request fanout histogram system.cpu0.toL2Bus.reqLayer0.occupancy 35963769502 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.cpu0.toL2Bus.snoopLayer0.occupancy 196401052 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) system.cpu0.toL2Bus.respLayer0.occupancy 16580139110 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu0.toL2Bus.respLayer1.occupancy 9441182874 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu0.toL2Bus.respLayer2.occupancy 215851922 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) system.cpu0.toL2Bus.respLayer3.occupancy 705346257 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu1.branchPred.lookups 118915951 # Number of BP lookups system.cpu1.branchPred.condPredicted 85033049 # Number of conditional branches predicted system.cpu1.branchPred.condIncorrect 5367569 # Number of conditional branches incorrect system.cpu1.branchPred.BTBLookups 89750040 # Number of BTB lookups system.cpu1.branchPred.BTBHits 63411692 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu1.branchPred.BTBHitPct 70.653664 # BTB Hit Percentage system.cpu1.branchPred.usedRAS 13468810 # Number of times the RAS was used to get a target. system.cpu1.branchPred.RASInCorrect 887929 # Number of incorrect RAS predictions. system.cpu1.branchPred.indirectLookups 3084567 # Number of indirect predictor lookups. system.cpu1.branchPred.indirectHits 1998882 # Number of indirect target hits. system.cpu1.branchPred.indirectMisses 1085685 # Number of indirect misses. system.cpu1.branchPredindirectMispredicted 396796 # Number of mispredicted indirect branches. system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states system.cpu1.dtb.walker.walks 246313 # Table walker walks requested system.cpu1.dtb.walker.walksLong 246313 # Table walker walks initiated with long descriptors system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 8582 # Level at which table walker walks with long descriptors terminate system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 75463 # Level at which table walker walks with long descriptors terminate system.cpu1.dtb.walker.walkWaitTime::samples 246313 # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walkWaitTime::0 246313 100.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walkWaitTime::total 246313 # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walkCompletionTime::samples 84045 # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::mean 22346.070557 # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::gmean 21064.042846 # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::stdev 12361.258067 # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::0-32767 79296 94.35% 94.35% # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::32768-65535 4004 4.76% 99.11% # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::65536-98303 175 0.21% 99.32% # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::98304-131071 458 0.54% 99.87% # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::131072-163839 22 0.03% 99.89% # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::163840-196607 12 0.01% 99.91% # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::196608-229375 27 0.03% 99.94% # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::229376-262143 10 0.01% 99.95% # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::262144-294911 13 0.02% 99.97% # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::294912-327679 13 0.02% 99.98% # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::327680-360447 6 0.01% 99.99% # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::360448-393215 3 0.00% 99.99% # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::393216-425983 3 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::458752-491519 2 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::total 84045 # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walksPending::samples -766256056 # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::0 -766256056 100.00% 100.00% # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::total -766256056 # Table walker pending requests distribution system.cpu1.dtb.walker.walkPageSizes::4K 75463 89.79% 89.79% # Table walker page sizes translated system.cpu1.dtb.walker.walkPageSizes::2M 8582 10.21% 100.00% # Table walker page sizes translated system.cpu1.dtb.walker.walkPageSizes::total 84045 # Table walker page sizes translated system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 246313 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 246313 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 84045 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 84045 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin::total 330358 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses system.cpu1.dtb.read_hits 74020776 # DTB read hits system.cpu1.dtb.read_misses 200548 # DTB read misses system.cpu1.dtb.write_hits 65603987 # DTB write hits system.cpu1.dtb.write_misses 45765 # DTB write misses system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 43240 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 1075 # Number of times TLB was flushed by ASID system.cpu1.dtb.flush_entries 34845 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 889 # Number of TLB faults due to alignment restrictions system.cpu1.dtb.prefetch_faults 6796 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 11277 # Number of TLB faults due to permissions restrictions system.cpu1.dtb.read_accesses 74221324 # DTB read accesses system.cpu1.dtb.write_accesses 65649752 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses system.cpu1.dtb.hits 139624763 # DTB hits system.cpu1.dtb.misses 246313 # DTB misses system.cpu1.dtb.accesses 139871076 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states system.cpu1.itb.walker.walks 60327 # Table walker walks requested system.cpu1.itb.walker.walksLong 60327 # Table walker walks initiated with long descriptors system.cpu1.itb.walker.walksLongTerminationLevel::Level2 545 # Level at which table walker walks with long descriptors terminate system.cpu1.itb.walker.walksLongTerminationLevel::Level3 52409 # Level at which table walker walks with long descriptors terminate system.cpu1.itb.walker.walkWaitTime::samples 60327 # Table walker wait (enqueue to first request) latency system.cpu1.itb.walker.walkWaitTime::0 60327 100.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu1.itb.walker.walkWaitTime::total 60327 # Table walker wait (enqueue to first request) latency system.cpu1.itb.walker.walkCompletionTime::samples 52954 # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::mean 24879.980738 # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::gmean 23402.458623 # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::stdev 13318.614145 # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::0-32767 48523 91.63% 91.63% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::32768-65535 3764 7.11% 98.74% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::65536-98303 13 0.02% 98.76% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::98304-131071 577 1.09% 99.85% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::131072-163839 18 0.03% 99.89% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::163840-196607 8 0.02% 99.90% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::196608-229375 20 0.04% 99.94% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::229376-262143 20 0.04% 99.98% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::262144-294911 3 0.01% 99.98% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::294912-327679 4 0.01% 99.99% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::327680-360447 1 0.00% 99.99% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::360448-393215 1 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::393216-425983 1 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::total 52954 # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walksPending::samples -766782556 # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::0 -766782556 100.00% 100.00% # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::total -766782556 # Table walker pending requests distribution system.cpu1.itb.walker.walkPageSizes::4K 52409 98.97% 98.97% # Table walker page sizes translated system.cpu1.itb.walker.walkPageSizes::2M 545 1.03% 100.00% # Table walker page sizes translated system.cpu1.itb.walker.walkPageSizes::total 52954 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 60327 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Requested::total 60327 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 52954 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::total 52954 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin::total 113281 # Table walker requests started/completed, data/inst system.cpu1.itb.inst_hits 210682225 # ITB inst hits system.cpu1.itb.inst_misses 60327 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 43240 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 1075 # Number of times TLB was flushed by ASID system.cpu1.itb.flush_entries 24520 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 163777 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses system.cpu1.itb.inst_accesses 210742552 # ITB inst accesses system.cpu1.itb.hits 210682225 # DTB hits system.cpu1.itb.misses 60327 # DTB misses system.cpu1.itb.accesses 210742552 # DTB accesses system.cpu1.numPwrStateTransitions 10392 # Number of power state transitions system.cpu1.pwrStateClkGateDist::samples 5196 # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::mean 9053828227.255966 # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::stdev 188730440437.234528 # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::underflows 3531 67.96% 67.96% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::1000-5e+10 1645 31.66% 99.62% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::5e+10-1e+11 9 0.17% 99.79% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 1 0.02% 99.81% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 1 0.02% 99.83% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::7.5e+11-8e+11 1 0.02% 99.85% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::9.5e+11-1e+12 1 0.02% 99.87% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::overflows 7 0.13% 100.00% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::max_value 7351146453012 # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::total 5196 # Distribution of time spent in the clock gated state system.cpu1.pwrStateResidencyTicks::ON 401797772178 # Cumulative time (in ticks) in various power states system.cpu1.pwrStateResidencyTicks::CLK_GATED 47043691468822 # Cumulative time (in ticks) in various power states system.cpu1.numCycles 803603609 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.committedInsts 379085635 # Number of instructions committed system.cpu1.committedOps 446824897 # Number of ops (including micro ops) committed system.cpu1.discardedOps 44295367 # Number of ops (including micro ops) which were discarded before commit system.cpu1.numFetchSuspends 4823 # Number of times Execute suspended instruction fetching system.cpu1.quiesceCycles 94088042190 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt system.cpu1.cpi 2.119847 # CPI: cycles per instruction system.cpu1.ipc 0.471732 # IPC: instructions per cycle system.cpu1.op_class_0::No_OpClass 1 0.00% 0.00% # Class of committed instruction system.cpu1.op_class_0::IntAlu 309274392 69.22% 69.22% # Class of committed instruction system.cpu1.op_class_0::IntMult 866353 0.19% 69.41% # Class of committed instruction system.cpu1.op_class_0::IntDiv 49212 0.01% 69.42% # Class of committed instruction system.cpu1.op_class_0::FloatAdd 0 0.00% 69.42% # Class of committed instruction system.cpu1.op_class_0::FloatCmp 0 0.00% 69.42% # Class of committed instruction system.cpu1.op_class_0::FloatCvt 0 0.00% 69.42% # Class of committed instruction system.cpu1.op_class_0::FloatMult 0 0.00% 69.42% # Class of committed instruction system.cpu1.op_class_0::FloatDiv 0 0.00% 69.42% # Class of committed instruction system.cpu1.op_class_0::FloatSqrt 0 0.00% 69.42% # Class of committed instruction system.cpu1.op_class_0::SimdAdd 0 0.00% 69.42% # Class of committed instruction system.cpu1.op_class_0::SimdAddAcc 0 0.00% 69.42% # Class of committed instruction system.cpu1.op_class_0::SimdAlu 0 0.00% 69.42% # Class of committed instruction system.cpu1.op_class_0::SimdCmp 0 0.00% 69.42% # Class of committed instruction system.cpu1.op_class_0::SimdCvt 0 0.00% 69.42% # Class of committed instruction system.cpu1.op_class_0::SimdMisc 0 0.00% 69.42% # Class of committed instruction system.cpu1.op_class_0::SimdMult 0 0.00% 69.42% # Class of committed instruction system.cpu1.op_class_0::SimdMultAcc 0 0.00% 69.42% # Class of committed instruction system.cpu1.op_class_0::SimdShift 0 0.00% 69.42% # Class of committed instruction system.cpu1.op_class_0::SimdShiftAcc 0 0.00% 69.42% # Class of committed instruction system.cpu1.op_class_0::SimdSqrt 0 0.00% 69.42% # Class of committed instruction system.cpu1.op_class_0::SimdFloatAdd 8 0.00% 69.42% # Class of committed instruction system.cpu1.op_class_0::SimdFloatAlu 0 0.00% 69.42% # Class of committed instruction system.cpu1.op_class_0::SimdFloatCmp 13 0.00% 69.42% # Class of committed instruction system.cpu1.op_class_0::SimdFloatCvt 21 0.00% 69.42% # Class of committed instruction system.cpu1.op_class_0::SimdFloatDiv 0 0.00% 69.42% # Class of committed instruction system.cpu1.op_class_0::SimdFloatMisc 34424 0.01% 69.43% # Class of committed instruction system.cpu1.op_class_0::SimdFloatMult 0 0.00% 69.43% # Class of committed instruction system.cpu1.op_class_0::SimdFloatMultAcc 0 0.00% 69.43% # Class of committed instruction system.cpu1.op_class_0::SimdFloatSqrt 0 0.00% 69.43% # Class of committed instruction system.cpu1.op_class_0::MemRead 71272038 15.95% 85.38% # Class of committed instruction system.cpu1.op_class_0::MemWrite 65328435 14.62% 100.00% # Class of committed instruction system.cpu1.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu1.op_class_0::total 446824897 # Class of committed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 5196 # number of quiesce instructions executed system.cpu1.tickCycles 627540865 # Number of cycles that the object actually ticked system.cpu1.idleCycles 176062744 # Total number of cycles that the object has spent stopped system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states system.cpu1.dcache.tags.replacements 4660684 # number of replacements system.cpu1.dcache.tags.tagsinuse 434.489996 # Cycle average of tags in use system.cpu1.dcache.tags.total_refs 132775101 # Total number of references to valid blocks. system.cpu1.dcache.tags.sampled_refs 4661196 # Sample count of references to valid blocks. system.cpu1.dcache.tags.avg_refs 28.485200 # Average number of references to valid blocks. system.cpu1.dcache.tags.warmup_cycle 8377585211000 # Cycle when the warmup percentage was hit. system.cpu1.dcache.tags.occ_blocks::cpu1.data 434.489996 # Average occupied blocks per requestor system.cpu1.dcache.tags.occ_percent::cpu1.data 0.848613 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_percent::total 0.848613 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::0 72 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::1 401 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::2 39 # Occupied blocks per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu1.dcache.tags.tag_accesses 281793929 # Number of tag accesses system.cpu1.dcache.tags.data_accesses 281793929 # Number of data accesses system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states system.cpu1.dcache.ReadReq_hits::cpu1.data 67965873 # number of ReadReq hits system.cpu1.dcache.ReadReq_hits::total 67965873 # number of ReadReq hits system.cpu1.dcache.WriteReq_hits::cpu1.data 61015488 # number of WriteReq hits system.cpu1.dcache.WriteReq_hits::total 61015488 # number of WriteReq hits system.cpu1.dcache.SoftPFReq_hits::cpu1.data 190971 # number of SoftPFReq hits system.cpu1.dcache.SoftPFReq_hits::total 190971 # number of SoftPFReq hits system.cpu1.dcache.WriteLineReq_hits::cpu1.data 44349 # number of WriteLineReq hits system.cpu1.dcache.WriteLineReq_hits::total 44349 # number of WriteLineReq hits system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1561438 # number of LoadLockedReq hits system.cpu1.dcache.LoadLockedReq_hits::total 1561438 # number of LoadLockedReq hits system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1518539 # number of StoreCondReq hits system.cpu1.dcache.StoreCondReq_hits::total 1518539 # number of StoreCondReq hits system.cpu1.dcache.demand_hits::cpu1.data 129025710 # number of demand (read+write) hits system.cpu1.dcache.demand_hits::total 129025710 # number of demand (read+write) hits system.cpu1.dcache.overall_hits::cpu1.data 129216681 # number of overall hits system.cpu1.dcache.overall_hits::total 129216681 # number of overall hits system.cpu1.dcache.ReadReq_misses::cpu1.data 2729495 # number of ReadReq misses system.cpu1.dcache.ReadReq_misses::total 2729495 # number of ReadReq misses system.cpu1.dcache.WriteReq_misses::cpu1.data 2149690 # number of WriteReq misses system.cpu1.dcache.WriteReq_misses::total 2149690 # number of WriteReq misses system.cpu1.dcache.SoftPFReq_misses::cpu1.data 616052 # number of SoftPFReq misses system.cpu1.dcache.SoftPFReq_misses::total 616052 # number of SoftPFReq misses system.cpu1.dcache.WriteLineReq_misses::cpu1.data 399927 # number of WriteLineReq misses system.cpu1.dcache.WriteLineReq_misses::total 399927 # number of WriteLineReq misses system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 143085 # number of LoadLockedReq misses system.cpu1.dcache.LoadLockedReq_misses::total 143085 # number of LoadLockedReq misses system.cpu1.dcache.StoreCondReq_misses::cpu1.data 184951 # number of StoreCondReq misses system.cpu1.dcache.StoreCondReq_misses::total 184951 # number of StoreCondReq misses system.cpu1.dcache.demand_misses::cpu1.data 5279112 # number of demand (read+write) misses system.cpu1.dcache.demand_misses::total 5279112 # number of demand (read+write) misses system.cpu1.dcache.overall_misses::cpu1.data 5895164 # number of overall misses system.cpu1.dcache.overall_misses::total 5895164 # number of overall misses system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 39717227000 # number of ReadReq miss cycles system.cpu1.dcache.ReadReq_miss_latency::total 39717227000 # number of ReadReq miss cycles system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 40094025500 # number of WriteReq miss cycles system.cpu1.dcache.WriteReq_miss_latency::total 40094025500 # number of WriteReq miss cycles system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 9755721000 # number of WriteLineReq miss cycles system.cpu1.dcache.WriteLineReq_miss_latency::total 9755721000 # number of WriteLineReq miss cycles system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2101168500 # number of LoadLockedReq miss cycles system.cpu1.dcache.LoadLockedReq_miss_latency::total 2101168500 # number of LoadLockedReq miss cycles system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4571201000 # number of StoreCondReq miss cycles system.cpu1.dcache.StoreCondReq_miss_latency::total 4571201000 # number of StoreCondReq miss cycles system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 4144500 # number of StoreCondFailReq miss cycles system.cpu1.dcache.StoreCondFailReq_miss_latency::total 4144500 # number of StoreCondFailReq miss cycles system.cpu1.dcache.demand_miss_latency::cpu1.data 89566973500 # number of demand (read+write) miss cycles system.cpu1.dcache.demand_miss_latency::total 89566973500 # number of demand (read+write) miss cycles system.cpu1.dcache.overall_miss_latency::cpu1.data 89566973500 # number of overall miss cycles system.cpu1.dcache.overall_miss_latency::total 89566973500 # number of overall miss cycles system.cpu1.dcache.ReadReq_accesses::cpu1.data 70695368 # number of ReadReq accesses(hits+misses) system.cpu1.dcache.ReadReq_accesses::total 70695368 # number of ReadReq accesses(hits+misses) system.cpu1.dcache.WriteReq_accesses::cpu1.data 63165178 # number of WriteReq accesses(hits+misses) system.cpu1.dcache.WriteReq_accesses::total 63165178 # number of WriteReq accesses(hits+misses) system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 807023 # number of SoftPFReq accesses(hits+misses) system.cpu1.dcache.SoftPFReq_accesses::total 807023 # number of SoftPFReq accesses(hits+misses) system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 444276 # number of WriteLineReq accesses(hits+misses) system.cpu1.dcache.WriteLineReq_accesses::total 444276 # number of WriteLineReq accesses(hits+misses) system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1704523 # number of LoadLockedReq accesses(hits+misses) system.cpu1.dcache.LoadLockedReq_accesses::total 1704523 # number of LoadLockedReq accesses(hits+misses) system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1703490 # number of StoreCondReq accesses(hits+misses) system.cpu1.dcache.StoreCondReq_accesses::total 1703490 # number of StoreCondReq accesses(hits+misses) system.cpu1.dcache.demand_accesses::cpu1.data 134304822 # number of demand (read+write) accesses system.cpu1.dcache.demand_accesses::total 134304822 # number of demand (read+write) accesses system.cpu1.dcache.overall_accesses::cpu1.data 135111845 # number of overall (read+write) accesses system.cpu1.dcache.overall_accesses::total 135111845 # number of overall (read+write) accesses system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.038609 # miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_miss_rate::total 0.038609 # miss rate for ReadReq accesses system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.034033 # miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_miss_rate::total 0.034033 # miss rate for WriteReq accesses system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.763364 # miss rate for SoftPFReq accesses system.cpu1.dcache.SoftPFReq_miss_rate::total 0.763364 # miss rate for SoftPFReq accesses system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.900177 # miss rate for WriteLineReq accesses system.cpu1.dcache.WriteLineReq_miss_rate::total 0.900177 # miss rate for WriteLineReq accesses system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.083944 # miss rate for LoadLockedReq accesses system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.083944 # miss rate for LoadLockedReq accesses system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.108572 # miss rate for StoreCondReq accesses system.cpu1.dcache.StoreCondReq_miss_rate::total 0.108572 # miss rate for StoreCondReq accesses system.cpu1.dcache.demand_miss_rate::cpu1.data 0.039307 # miss rate for demand accesses system.cpu1.dcache.demand_miss_rate::total 0.039307 # miss rate for demand accesses system.cpu1.dcache.overall_miss_rate::cpu1.data 0.043632 # miss rate for overall accesses system.cpu1.dcache.overall_miss_rate::total 0.043632 # miss rate for overall accesses system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14551.126490 # average ReadReq miss latency system.cpu1.dcache.ReadReq_avg_miss_latency::total 14551.126490 # average ReadReq miss latency system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18651.073178 # average WriteReq miss latency system.cpu1.dcache.WriteReq_avg_miss_latency::total 18651.073178 # average WriteReq miss latency system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 24393.754360 # average WriteLineReq miss latency system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 24393.754360 # average WriteLineReq miss latency system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14684.757312 # average LoadLockedReq miss latency system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14684.757312 # average LoadLockedReq miss latency system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 24715.740926 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 24715.740926 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 16966.295373 # average overall miss latency system.cpu1.dcache.demand_avg_miss_latency::total 16966.295373 # average overall miss latency system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15193.296319 # average overall miss latency system.cpu1.dcache.overall_avg_miss_latency::total 15193.296319 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.writebacks::writebacks 4660691 # number of writebacks system.cpu1.dcache.writebacks::total 4660691 # number of writebacks system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 132278 # number of ReadReq MSHR hits system.cpu1.dcache.ReadReq_mshr_hits::total 132278 # number of ReadReq MSHR hits system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 894898 # number of WriteReq MSHR hits system.cpu1.dcache.WriteReq_mshr_hits::total 894898 # number of WriteReq MSHR hits system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 69 # number of WriteLineReq MSHR hits system.cpu1.dcache.WriteLineReq_mshr_hits::total 69 # number of WriteLineReq MSHR hits system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 37558 # number of LoadLockedReq MSHR hits system.cpu1.dcache.LoadLockedReq_mshr_hits::total 37558 # number of LoadLockedReq MSHR hits system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data 59 # number of StoreCondReq MSHR hits system.cpu1.dcache.StoreCondReq_mshr_hits::total 59 # number of StoreCondReq MSHR hits system.cpu1.dcache.demand_mshr_hits::cpu1.data 1027245 # number of demand (read+write) MSHR hits system.cpu1.dcache.demand_mshr_hits::total 1027245 # number of demand (read+write) MSHR hits system.cpu1.dcache.overall_mshr_hits::cpu1.data 1027245 # number of overall MSHR hits system.cpu1.dcache.overall_mshr_hits::total 1027245 # number of overall MSHR hits system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2597217 # number of ReadReq MSHR misses system.cpu1.dcache.ReadReq_mshr_misses::total 2597217 # number of ReadReq MSHR misses system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1254792 # number of WriteReq MSHR misses system.cpu1.dcache.WriteReq_mshr_misses::total 1254792 # number of WriteReq MSHR misses system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 615702 # number of SoftPFReq MSHR misses system.cpu1.dcache.SoftPFReq_mshr_misses::total 615702 # number of SoftPFReq MSHR misses system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 399858 # number of WriteLineReq MSHR misses system.cpu1.dcache.WriteLineReq_mshr_misses::total 399858 # number of WriteLineReq MSHR misses system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 105527 # number of LoadLockedReq MSHR misses system.cpu1.dcache.LoadLockedReq_mshr_misses::total 105527 # number of LoadLockedReq MSHR misses system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 184892 # number of StoreCondReq MSHR misses system.cpu1.dcache.StoreCondReq_mshr_misses::total 184892 # number of StoreCondReq MSHR misses system.cpu1.dcache.demand_mshr_misses::cpu1.data 4251867 # number of demand (read+write) MSHR misses system.cpu1.dcache.demand_mshr_misses::total 4251867 # number of demand (read+write) MSHR misses system.cpu1.dcache.overall_mshr_misses::cpu1.data 4867569 # number of overall MSHR misses system.cpu1.dcache.overall_mshr_misses::total 4867569 # number of overall MSHR misses system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 8793 # number of ReadReq MSHR uncacheable system.cpu1.dcache.ReadReq_mshr_uncacheable::total 8793 # number of ReadReq MSHR uncacheable system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 9091 # number of WriteReq MSHR uncacheable system.cpu1.dcache.WriteReq_mshr_uncacheable::total 9091 # number of WriteReq MSHR uncacheable system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 17884 # number of overall MSHR uncacheable misses system.cpu1.dcache.overall_mshr_uncacheable_misses::total 17884 # number of overall MSHR uncacheable misses system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 34245614000 # number of ReadReq MSHR miss cycles system.cpu1.dcache.ReadReq_mshr_miss_latency::total 34245614000 # number of ReadReq MSHR miss cycles system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 22880344500 # number of WriteReq MSHR miss cycles system.cpu1.dcache.WriteReq_mshr_miss_latency::total 22880344500 # number of WriteReq MSHR miss cycles system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 13431113500 # number of SoftPFReq MSHR miss cycles system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 13431113500 # number of SoftPFReq MSHR miss cycles system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 9350661500 # number of WriteLineReq MSHR miss cycles system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 9350661500 # number of WriteLineReq MSHR miss cycles system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1405417000 # number of LoadLockedReq MSHR miss cycles system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1405417000 # number of LoadLockedReq MSHR miss cycles system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4384302500 # number of StoreCondReq MSHR miss cycles system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4384302500 # number of StoreCondReq MSHR miss cycles system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 3898500 # number of StoreCondFailReq MSHR miss cycles system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 3898500 # number of StoreCondFailReq MSHR miss cycles system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 66476620000 # number of demand (read+write) MSHR miss cycles system.cpu1.dcache.demand_mshr_miss_latency::total 66476620000 # number of demand (read+write) MSHR miss cycles system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 79907733500 # number of overall MSHR miss cycles system.cpu1.dcache.overall_mshr_miss_latency::total 79907733500 # number of overall MSHR miss cycles system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 1305175500 # number of ReadReq MSHR uncacheable cycles system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 1305175500 # number of ReadReq MSHR uncacheable cycles system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1305175500 # number of overall MSHR uncacheable cycles system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1305175500 # number of overall MSHR uncacheable cycles system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036738 # mshr miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036738 # mshr miss rate for ReadReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.019865 # mshr miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.019865 # mshr miss rate for WriteReq accesses system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.762930 # mshr miss rate for SoftPFReq accesses system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.762930 # mshr miss rate for SoftPFReq accesses system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.900022 # mshr miss rate for WriteLineReq accesses system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.900022 # mshr miss rate for WriteLineReq accesses system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.061910 # mshr miss rate for LoadLockedReq accesses system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.061910 # mshr miss rate for LoadLockedReq accesses system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.108537 # mshr miss rate for StoreCondReq accesses system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.108537 # mshr miss rate for StoreCondReq accesses system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031658 # mshr miss rate for demand accesses system.cpu1.dcache.demand_mshr_miss_rate::total 0.031658 # mshr miss rate for demand accesses system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.036026 # mshr miss rate for overall accesses system.cpu1.dcache.overall_mshr_miss_rate::total 0.036026 # mshr miss rate for overall accesses system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13185.503560 # average ReadReq mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13185.503560 # average ReadReq mshr miss latency system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 18234.372310 # average WriteReq mshr miss latency system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 18234.372310 # average WriteReq mshr miss latency system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 21814.308708 # average SoftPFReq mshr miss latency system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 21814.308708 # average SoftPFReq mshr miss latency system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 23384.955409 # average WriteLineReq mshr miss latency system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 23384.955409 # average WriteLineReq mshr miss latency system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13318.079733 # average LoadLockedReq mshr miss latency system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13318.079733 # average LoadLockedReq mshr miss latency system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 23712.775566 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 23712.775566 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15634.689420 # average overall mshr miss latency system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15634.689420 # average overall mshr miss latency system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16416.353523 # average overall mshr miss latency system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16416.353523 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 148433.469806 # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 148433.469806 # average ReadReq mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 72980.065981 # average overall mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 72980.065981 # average overall mshr uncacheable latency system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states system.cpu1.icache.tags.replacements 8014386 # number of replacements system.cpu1.icache.tags.tagsinuse 507.062567 # Cycle average of tags in use system.cpu1.icache.tags.total_refs 202497896 # Total number of references to valid blocks. system.cpu1.icache.tags.sampled_refs 8014898 # Sample count of references to valid blocks. system.cpu1.icache.tags.avg_refs 25.265187 # Average number of references to valid blocks. system.cpu1.icache.tags.warmup_cycle 8368004575000 # Cycle when the warmup percentage was hit. system.cpu1.icache.tags.occ_blocks::cpu1.inst 507.062567 # Average occupied blocks per requestor system.cpu1.icache.tags.occ_percent::cpu1.inst 0.990357 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_percent::total 0.990357 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::0 113 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::1 354 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::2 45 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu1.icache.tags.tag_accesses 429040515 # Number of tag accesses system.cpu1.icache.tags.data_accesses 429040515 # Number of data accesses system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states system.cpu1.icache.ReadReq_hits::cpu1.inst 202497896 # number of ReadReq hits system.cpu1.icache.ReadReq_hits::total 202497896 # number of ReadReq hits system.cpu1.icache.demand_hits::cpu1.inst 202497896 # number of demand (read+write) hits system.cpu1.icache.demand_hits::total 202497896 # number of demand (read+write) hits system.cpu1.icache.overall_hits::cpu1.inst 202497896 # number of overall hits system.cpu1.icache.overall_hits::total 202497896 # number of overall hits system.cpu1.icache.ReadReq_misses::cpu1.inst 8014908 # number of ReadReq misses system.cpu1.icache.ReadReq_misses::total 8014908 # number of ReadReq misses system.cpu1.icache.demand_misses::cpu1.inst 8014908 # number of demand (read+write) misses system.cpu1.icache.demand_misses::total 8014908 # number of demand (read+write) misses system.cpu1.icache.overall_misses::cpu1.inst 8014908 # number of overall misses system.cpu1.icache.overall_misses::total 8014908 # number of overall misses system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 81330977500 # number of ReadReq miss cycles system.cpu1.icache.ReadReq_miss_latency::total 81330977500 # number of ReadReq miss cycles system.cpu1.icache.demand_miss_latency::cpu1.inst 81330977500 # number of demand (read+write) miss cycles system.cpu1.icache.demand_miss_latency::total 81330977500 # number of demand (read+write) miss cycles system.cpu1.icache.overall_miss_latency::cpu1.inst 81330977500 # number of overall miss cycles system.cpu1.icache.overall_miss_latency::total 81330977500 # number of overall miss cycles system.cpu1.icache.ReadReq_accesses::cpu1.inst 210512804 # number of ReadReq accesses(hits+misses) system.cpu1.icache.ReadReq_accesses::total 210512804 # number of ReadReq accesses(hits+misses) system.cpu1.icache.demand_accesses::cpu1.inst 210512804 # number of demand (read+write) accesses system.cpu1.icache.demand_accesses::total 210512804 # number of demand (read+write) accesses system.cpu1.icache.overall_accesses::cpu1.inst 210512804 # number of overall (read+write) accesses system.cpu1.icache.overall_accesses::total 210512804 # number of overall (read+write) accesses system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.038073 # miss rate for ReadReq accesses system.cpu1.icache.ReadReq_miss_rate::total 0.038073 # miss rate for ReadReq accesses system.cpu1.icache.demand_miss_rate::cpu1.inst 0.038073 # miss rate for demand accesses system.cpu1.icache.demand_miss_rate::total 0.038073 # miss rate for demand accesses system.cpu1.icache.overall_miss_rate::cpu1.inst 0.038073 # miss rate for overall accesses system.cpu1.icache.overall_miss_rate::total 0.038073 # miss rate for overall accesses system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10147.462391 # average ReadReq miss latency system.cpu1.icache.ReadReq_avg_miss_latency::total 10147.462391 # average ReadReq miss latency system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10147.462391 # average overall miss latency system.cpu1.icache.demand_avg_miss_latency::total 10147.462391 # average overall miss latency system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10147.462391 # average overall miss latency system.cpu1.icache.overall_avg_miss_latency::total 10147.462391 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.writebacks::writebacks 8014386 # number of writebacks system.cpu1.icache.writebacks::total 8014386 # number of writebacks system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 8014908 # number of ReadReq MSHR misses system.cpu1.icache.ReadReq_mshr_misses::total 8014908 # number of ReadReq MSHR misses system.cpu1.icache.demand_mshr_misses::cpu1.inst 8014908 # number of demand (read+write) MSHR misses system.cpu1.icache.demand_mshr_misses::total 8014908 # number of demand (read+write) MSHR misses system.cpu1.icache.overall_mshr_misses::cpu1.inst 8014908 # number of overall MSHR misses system.cpu1.icache.overall_mshr_misses::total 8014908 # number of overall MSHR misses system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 95 # number of ReadReq MSHR uncacheable system.cpu1.icache.ReadReq_mshr_uncacheable::total 95 # number of ReadReq MSHR uncacheable system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 95 # number of overall MSHR uncacheable misses system.cpu1.icache.overall_mshr_uncacheable_misses::total 95 # number of overall MSHR uncacheable misses system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 77323524000 # number of ReadReq MSHR miss cycles system.cpu1.icache.ReadReq_mshr_miss_latency::total 77323524000 # number of ReadReq MSHR miss cycles system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 77323524000 # number of demand (read+write) MSHR miss cycles system.cpu1.icache.demand_mshr_miss_latency::total 77323524000 # number of demand (read+write) MSHR miss cycles system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 77323524000 # number of overall MSHR miss cycles system.cpu1.icache.overall_mshr_miss_latency::total 77323524000 # number of overall MSHR miss cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8766500 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 8766500 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 8766500 # number of overall MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::total 8766500 # number of overall MSHR uncacheable cycles system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.038073 # mshr miss rate for ReadReq accesses system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.038073 # mshr miss rate for ReadReq accesses system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.038073 # mshr miss rate for demand accesses system.cpu1.icache.demand_mshr_miss_rate::total 0.038073 # mshr miss rate for demand accesses system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.038073 # mshr miss rate for overall accesses system.cpu1.icache.overall_mshr_miss_rate::total 0.038073 # mshr miss rate for overall accesses system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 9647.462454 # average ReadReq mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 9647.462454 # average ReadReq mshr miss latency system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 9647.462454 # average overall mshr miss latency system.cpu1.icache.demand_avg_mshr_miss_latency::total 9647.462454 # average overall mshr miss latency system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 9647.462454 # average overall mshr miss latency system.cpu1.icache.overall_avg_mshr_miss_latency::total 9647.462454 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 92278.947368 # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 92278.947368 # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 92278.947368 # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 92278.947368 # average overall mshr uncacheable latency system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states system.cpu1.l2cache.prefetcher.num_hwpf_issued 6532358 # number of hwpf issued system.cpu1.l2cache.prefetcher.pfIdentified 6532555 # number of prefetch candidates identified system.cpu1.l2cache.prefetcher.pfBufferHit 172 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size system.cpu1.l2cache.prefetcher.pfSpanPage 799581 # number of prefetches not generated due to page crossing system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states system.cpu1.l2cache.tags.replacements 2133098 # number of replacements system.cpu1.l2cache.tags.tagsinuse 13038.197584 # Cycle average of tags in use system.cpu1.l2cache.tags.total_refs 20019506 # Total number of references to valid blocks. system.cpu1.l2cache.tags.sampled_refs 2148887 # Sample count of references to valid blocks. system.cpu1.l2cache.tags.avg_refs 9.316221 # Average number of references to valid blocks. system.cpu1.l2cache.tags.warmup_cycle 9619713453000 # Cycle when the warmup percentage was hit. system.cpu1.l2cache.tags.occ_blocks::writebacks 11987.780509 # Average occupied blocks per requestor system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 23.994022 # Average occupied blocks per requestor system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 12.035388 # Average occupied blocks per requestor system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 1014.387665 # Average occupied blocks per requestor system.cpu1.l2cache.tags.occ_percent::writebacks 0.731676 # Average percentage of cache occupancy system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.001464 # Average percentage of cache occupancy system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000735 # Average percentage of cache occupancy system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.061913 # Average percentage of cache occupancy system.cpu1.l2cache.tags.occ_percent::total 0.795788 # Average percentage of cache occupancy system.cpu1.l2cache.tags.occ_task_id_blocks::1022 829 # Occupied blocks per task id system.cpu1.l2cache.tags.occ_task_id_blocks::1023 65 # Occupied blocks per task id system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14895 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1022::0 11 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 17 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 152 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 567 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 82 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 8 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 55 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 1 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 105 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1161 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5545 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 7510 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 574 # Occupied blocks per task id system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.050598 # Percentage of cache occupancy per task id system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.003967 # Percentage of cache occupancy per task id system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.909119 # Percentage of cache occupancy per task id system.cpu1.l2cache.tags.tag_accesses 428778233 # Number of tag accesses system.cpu1.l2cache.tags.data_accesses 428778233 # Number of data accesses system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 473132 # number of ReadReq hits system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 155315 # number of ReadReq hits system.cpu1.l2cache.ReadReq_hits::total 628447 # number of ReadReq hits system.cpu1.l2cache.WritebackDirty_hits::writebacks 2939776 # number of WritebackDirty hits system.cpu1.l2cache.WritebackDirty_hits::total 2939776 # number of WritebackDirty hits system.cpu1.l2cache.WritebackClean_hits::writebacks 9733319 # number of WritebackClean hits system.cpu1.l2cache.WritebackClean_hits::total 9733319 # number of WritebackClean hits system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 413 # number of UpgradeReq hits system.cpu1.l2cache.UpgradeReq_hits::total 413 # number of UpgradeReq hits system.cpu1.l2cache.ReadExReq_hits::cpu1.data 783674 # number of ReadExReq hits system.cpu1.l2cache.ReadExReq_hits::total 783674 # number of ReadExReq hits system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 7365861 # number of ReadCleanReq hits system.cpu1.l2cache.ReadCleanReq_hits::total 7365861 # number of ReadCleanReq hits system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 2414791 # number of ReadSharedReq hits system.cpu1.l2cache.ReadSharedReq_hits::total 2414791 # number of ReadSharedReq hits system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 165268 # number of InvalidateReq hits system.cpu1.l2cache.InvalidateReq_hits::total 165268 # number of InvalidateReq hits system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 473132 # number of demand (read+write) hits system.cpu1.l2cache.demand_hits::cpu1.itb.walker 155315 # number of demand (read+write) hits system.cpu1.l2cache.demand_hits::cpu1.inst 7365861 # number of demand (read+write) hits system.cpu1.l2cache.demand_hits::cpu1.data 3198465 # number of demand (read+write) hits system.cpu1.l2cache.demand_hits::total 11192773 # number of demand (read+write) hits system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 473132 # number of overall hits system.cpu1.l2cache.overall_hits::cpu1.itb.walker 155315 # number of overall hits system.cpu1.l2cache.overall_hits::cpu1.inst 7365861 # number of overall hits system.cpu1.l2cache.overall_hits::cpu1.data 3198465 # number of overall hits system.cpu1.l2cache.overall_hits::total 11192773 # number of overall hits system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 11255 # number of ReadReq misses system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 7950 # number of ReadReq misses system.cpu1.l2cache.ReadReq_misses::total 19205 # number of ReadReq misses system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 218866 # number of UpgradeReq misses system.cpu1.l2cache.UpgradeReq_misses::total 218866 # number of UpgradeReq misses system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 184883 # number of SCUpgradeReq misses system.cpu1.l2cache.SCUpgradeReq_misses::total 184883 # number of SCUpgradeReq misses system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 9 # number of SCUpgradeFailReq misses system.cpu1.l2cache.SCUpgradeFailReq_misses::total 9 # number of SCUpgradeFailReq misses system.cpu1.l2cache.ReadExReq_misses::cpu1.data 254182 # number of ReadExReq misses system.cpu1.l2cache.ReadExReq_misses::total 254182 # number of ReadExReq misses system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 649047 # number of ReadCleanReq misses system.cpu1.l2cache.ReadCleanReq_misses::total 649047 # number of ReadCleanReq misses system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 903423 # number of ReadSharedReq misses system.cpu1.l2cache.ReadSharedReq_misses::total 903423 # number of ReadSharedReq misses system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 232791 # number of InvalidateReq misses system.cpu1.l2cache.InvalidateReq_misses::total 232791 # number of InvalidateReq misses system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 11255 # number of demand (read+write) misses system.cpu1.l2cache.demand_misses::cpu1.itb.walker 7950 # number of demand (read+write) misses system.cpu1.l2cache.demand_misses::cpu1.inst 649047 # number of demand (read+write) misses system.cpu1.l2cache.demand_misses::cpu1.data 1157605 # number of demand (read+write) misses system.cpu1.l2cache.demand_misses::total 1825857 # number of demand (read+write) misses system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 11255 # number of overall misses system.cpu1.l2cache.overall_misses::cpu1.itb.walker 7950 # number of overall misses system.cpu1.l2cache.overall_misses::cpu1.inst 649047 # number of overall misses system.cpu1.l2cache.overall_misses::cpu1.data 1157605 # number of overall misses system.cpu1.l2cache.overall_misses::total 1825857 # number of overall misses system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 391701000 # number of ReadReq miss cycles system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 275187000 # number of ReadReq miss cycles system.cpu1.l2cache.ReadReq_miss_latency::total 666888000 # number of ReadReq miss cycles system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 1898630500 # number of UpgradeReq miss cycles system.cpu1.l2cache.UpgradeReq_miss_latency::total 1898630500 # number of UpgradeReq miss cycles system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 1381240500 # number of SCUpgradeReq miss cycles system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 1381240500 # number of SCUpgradeReq miss cycles system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 3788499 # number of SCUpgradeFailReq miss cycles system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 3788499 # number of SCUpgradeFailReq miss cycles system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 10033557499 # number of ReadExReq miss cycles system.cpu1.l2cache.ReadExReq_miss_latency::total 10033557499 # number of ReadExReq miss cycles system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 20842529000 # number of ReadCleanReq miss cycles system.cpu1.l2cache.ReadCleanReq_miss_latency::total 20842529000 # number of ReadCleanReq miss cycles system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 28170928990 # number of ReadSharedReq miss cycles system.cpu1.l2cache.ReadSharedReq_miss_latency::total 28170928990 # number of ReadSharedReq miss cycles system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 350412000 # number of InvalidateReq miss cycles system.cpu1.l2cache.InvalidateReq_miss_latency::total 350412000 # number of InvalidateReq miss cycles system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 391701000 # number of demand (read+write) miss cycles system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 275187000 # number of demand (read+write) miss cycles system.cpu1.l2cache.demand_miss_latency::cpu1.inst 20842529000 # number of demand (read+write) miss cycles system.cpu1.l2cache.demand_miss_latency::cpu1.data 38204486489 # number of demand (read+write) miss cycles system.cpu1.l2cache.demand_miss_latency::total 59713903489 # number of demand (read+write) miss cycles system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 391701000 # number of overall miss cycles system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 275187000 # number of overall miss cycles system.cpu1.l2cache.overall_miss_latency::cpu1.inst 20842529000 # number of overall miss cycles system.cpu1.l2cache.overall_miss_latency::cpu1.data 38204486489 # number of overall miss cycles system.cpu1.l2cache.overall_miss_latency::total 59713903489 # number of overall miss cycles system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 484387 # number of ReadReq accesses(hits+misses) system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 163265 # number of ReadReq accesses(hits+misses) system.cpu1.l2cache.ReadReq_accesses::total 647652 # number of ReadReq accesses(hits+misses) system.cpu1.l2cache.WritebackDirty_accesses::writebacks 2939776 # number of WritebackDirty accesses(hits+misses) system.cpu1.l2cache.WritebackDirty_accesses::total 2939776 # number of WritebackDirty accesses(hits+misses) system.cpu1.l2cache.WritebackClean_accesses::writebacks 9733319 # number of WritebackClean accesses(hits+misses) system.cpu1.l2cache.WritebackClean_accesses::total 9733319 # number of WritebackClean accesses(hits+misses) system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 219279 # number of UpgradeReq accesses(hits+misses) system.cpu1.l2cache.UpgradeReq_accesses::total 219279 # number of UpgradeReq accesses(hits+misses) system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 184883 # number of SCUpgradeReq accesses(hits+misses) system.cpu1.l2cache.SCUpgradeReq_accesses::total 184883 # number of SCUpgradeReq accesses(hits+misses) system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 9 # number of SCUpgradeFailReq accesses(hits+misses) system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 9 # number of SCUpgradeFailReq accesses(hits+misses) system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1037856 # number of ReadExReq accesses(hits+misses) system.cpu1.l2cache.ReadExReq_accesses::total 1037856 # number of ReadExReq accesses(hits+misses) system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 8014908 # number of ReadCleanReq accesses(hits+misses) system.cpu1.l2cache.ReadCleanReq_accesses::total 8014908 # number of ReadCleanReq accesses(hits+misses) system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 3318214 # number of ReadSharedReq accesses(hits+misses) system.cpu1.l2cache.ReadSharedReq_accesses::total 3318214 # number of ReadSharedReq accesses(hits+misses) system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 398059 # number of InvalidateReq accesses(hits+misses) system.cpu1.l2cache.InvalidateReq_accesses::total 398059 # number of InvalidateReq accesses(hits+misses) system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 484387 # number of demand (read+write) accesses system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 163265 # number of demand (read+write) accesses system.cpu1.l2cache.demand_accesses::cpu1.inst 8014908 # number of demand (read+write) accesses system.cpu1.l2cache.demand_accesses::cpu1.data 4356070 # number of demand (read+write) accesses system.cpu1.l2cache.demand_accesses::total 13018630 # number of demand (read+write) accesses system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 484387 # number of overall (read+write) accesses system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 163265 # number of overall (read+write) accesses system.cpu1.l2cache.overall_accesses::cpu1.inst 8014908 # number of overall (read+write) accesses system.cpu1.l2cache.overall_accesses::cpu1.data 4356070 # number of overall (read+write) accesses system.cpu1.l2cache.overall_accesses::total 13018630 # number of overall (read+write) accesses system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.023236 # miss rate for ReadReq accesses system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.048694 # miss rate for ReadReq accesses system.cpu1.l2cache.ReadReq_miss_rate::total 0.029653 # miss rate for ReadReq accesses system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.998117 # miss rate for UpgradeReq accesses system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.998117 # miss rate for UpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.244911 # miss rate for ReadExReq accesses system.cpu1.l2cache.ReadExReq_miss_rate::total 0.244911 # miss rate for ReadExReq accesses system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.080980 # miss rate for ReadCleanReq accesses system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.080980 # miss rate for ReadCleanReq accesses system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.272262 # miss rate for ReadSharedReq accesses system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.272262 # miss rate for ReadSharedReq accesses system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.584815 # miss rate for InvalidateReq accesses system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.584815 # miss rate for InvalidateReq accesses system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.023236 # miss rate for demand accesses system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.048694 # miss rate for demand accesses system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.080980 # miss rate for demand accesses system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.265745 # miss rate for demand accesses system.cpu1.l2cache.demand_miss_rate::total 0.140250 # miss rate for demand accesses system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.023236 # miss rate for overall accesses system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.048694 # miss rate for overall accesses system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.080980 # miss rate for overall accesses system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.265745 # miss rate for overall accesses system.cpu1.l2cache.overall_miss_rate::total 0.140250 # miss rate for overall accesses system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 34802.398934 # average ReadReq miss latency system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 34614.716981 # average ReadReq miss latency system.cpu1.l2cache.ReadReq_avg_miss_latency::total 34724.707108 # average ReadReq miss latency system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 8674.853563 # average UpgradeReq miss latency system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 8674.853563 # average UpgradeReq miss latency system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 7470.889698 # average SCUpgradeReq miss latency system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 7470.889698 # average SCUpgradeReq miss latency system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 420944.333333 # average SCUpgradeFailReq miss latency system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 420944.333333 # average SCUpgradeFailReq miss latency system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 39473.910422 # average ReadExReq miss latency system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 39473.910422 # average ReadExReq miss latency system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 32112.511112 # average ReadCleanReq miss latency system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 32112.511112 # average ReadCleanReq miss latency system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 31182.435017 # average ReadSharedReq miss latency system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 31182.435017 # average ReadSharedReq miss latency system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 1505.264379 # average InvalidateReq miss latency system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 1505.264379 # average InvalidateReq miss latency system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 34802.398934 # average overall miss latency system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 34614.716981 # average overall miss latency system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 32112.511112 # average overall miss latency system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 33003.042047 # average overall miss latency system.cpu1.l2cache.demand_avg_miss_latency::total 32704.589400 # average overall miss latency system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 34802.398934 # average overall miss latency system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 34614.716981 # average overall miss latency system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 32112.511112 # average overall miss latency system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 33003.042047 # average overall miss latency system.cpu1.l2cache.overall_avg_miss_latency::total 32704.589400 # average overall miss latency system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.l2cache.unused_prefetches 43626 # number of HardPF blocks evicted w/o reference system.cpu1.l2cache.writebacks::writebacks 1060166 # number of writebacks system.cpu1.l2cache.writebacks::total 1060166 # number of writebacks system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker 1 # number of ReadReq MSHR hits system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 5 # number of ReadReq MSHR hits system.cpu1.l2cache.ReadReq_mshr_hits::total 6 # number of ReadReq MSHR hits system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 5457 # number of ReadExReq MSHR hits system.cpu1.l2cache.ReadExReq_mshr_hits::total 5457 # number of ReadExReq MSHR hits system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst 3 # number of ReadCleanReq MSHR hits system.cpu1.l2cache.ReadCleanReq_mshr_hits::total 3 # number of ReadCleanReq MSHR hits system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 376 # number of ReadSharedReq MSHR hits system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 376 # number of ReadSharedReq MSHR hits system.cpu1.l2cache.InvalidateReq_mshr_hits::cpu1.data 5 # number of InvalidateReq MSHR hits system.cpu1.l2cache.InvalidateReq_mshr_hits::total 5 # number of InvalidateReq MSHR hits system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker 1 # number of demand (read+write) MSHR hits system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 5 # number of demand (read+write) MSHR hits system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 3 # number of demand (read+write) MSHR hits system.cpu1.l2cache.demand_mshr_hits::cpu1.data 5833 # number of demand (read+write) MSHR hits system.cpu1.l2cache.demand_mshr_hits::total 5842 # number of demand (read+write) MSHR hits system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker 1 # number of overall MSHR hits system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 5 # number of overall MSHR hits system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 3 # number of overall MSHR hits system.cpu1.l2cache.overall_mshr_hits::cpu1.data 5833 # number of overall MSHR hits system.cpu1.l2cache.overall_mshr_hits::total 5842 # number of overall MSHR hits system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 11254 # number of ReadReq MSHR misses system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 7945 # number of ReadReq MSHR misses system.cpu1.l2cache.ReadReq_mshr_misses::total 19199 # number of ReadReq MSHR misses system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 690270 # number of HardPFReq MSHR misses system.cpu1.l2cache.HardPFReq_mshr_misses::total 690270 # number of HardPFReq MSHR misses system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 218866 # number of UpgradeReq MSHR misses system.cpu1.l2cache.UpgradeReq_mshr_misses::total 218866 # number of UpgradeReq MSHR misses system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 184883 # number of SCUpgradeReq MSHR misses system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 184883 # number of SCUpgradeReq MSHR misses system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 9 # number of SCUpgradeFailReq MSHR misses system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 9 # number of SCUpgradeFailReq MSHR misses system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 248725 # number of ReadExReq MSHR misses system.cpu1.l2cache.ReadExReq_mshr_misses::total 248725 # number of ReadExReq MSHR misses system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 649044 # number of ReadCleanReq MSHR misses system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 649044 # number of ReadCleanReq MSHR misses system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 903047 # number of ReadSharedReq MSHR misses system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 903047 # number of ReadSharedReq MSHR misses system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data 232786 # number of InvalidateReq MSHR misses system.cpu1.l2cache.InvalidateReq_mshr_misses::total 232786 # number of InvalidateReq MSHR misses system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 11254 # number of demand (read+write) MSHR misses system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 7945 # number of demand (read+write) MSHR misses system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 649044 # number of demand (read+write) MSHR misses system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1151772 # number of demand (read+write) MSHR misses system.cpu1.l2cache.demand_mshr_misses::total 1820015 # number of demand (read+write) MSHR misses system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 11254 # number of overall MSHR misses system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 7945 # number of overall MSHR misses system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 649044 # number of overall MSHR misses system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1151772 # number of overall MSHR misses system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 690270 # number of overall MSHR misses system.cpu1.l2cache.overall_mshr_misses::total 2510285 # number of overall MSHR misses system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 95 # number of ReadReq MSHR uncacheable system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 8793 # number of ReadReq MSHR uncacheable system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 8888 # number of ReadReq MSHR uncacheable system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 9091 # number of WriteReq MSHR uncacheable system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 9091 # number of WriteReq MSHR uncacheable system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 95 # number of overall MSHR uncacheable misses system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 17884 # number of overall MSHR uncacheable misses system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 17979 # number of overall MSHR uncacheable misses system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 324079500 # number of ReadReq MSHR miss cycles system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 227423500 # number of ReadReq MSHR miss cycles system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 551503000 # number of ReadReq MSHR miss cycles system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 26884842389 # number of HardPFReq MSHR miss cycles system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 26884842389 # number of HardPFReq MSHR miss cycles system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 4561523494 # number of UpgradeReq MSHR miss cycles system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 4561523494 # number of UpgradeReq MSHR miss cycles system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 2993192497 # number of SCUpgradeReq MSHR miss cycles system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 2993192497 # number of SCUpgradeReq MSHR miss cycles system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 3356499 # number of SCUpgradeFailReq MSHR miss cycles system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 3356499 # number of SCUpgradeFailReq MSHR miss cycles system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 7853418999 # number of ReadExReq MSHR miss cycles system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 7853418999 # number of ReadExReq MSHR miss cycles system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 16948153000 # number of ReadCleanReq MSHR miss cycles system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 16948153000 # number of ReadCleanReq MSHR miss cycles system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 22723854990 # number of ReadSharedReq MSHR miss cycles system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 22723854990 # number of ReadSharedReq MSHR miss cycles system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 6164226500 # number of InvalidateReq MSHR miss cycles system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 6164226500 # number of InvalidateReq MSHR miss cycles system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 324079500 # number of demand (read+write) MSHR miss cycles system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 227423500 # number of demand (read+write) MSHR miss cycles system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 16948153000 # number of demand (read+write) MSHR miss cycles system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 30577273989 # number of demand (read+write) MSHR miss cycles system.cpu1.l2cache.demand_mshr_miss_latency::total 48076929989 # number of demand (read+write) MSHR miss cycles system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 324079500 # number of overall MSHR miss cycles system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 227423500 # number of overall MSHR miss cycles system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 16948153000 # number of overall MSHR miss cycles system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 30577273989 # number of overall MSHR miss cycles system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 26884842389 # number of overall MSHR miss cycles system.cpu1.l2cache.overall_mshr_miss_latency::total 74961772378 # number of overall MSHR miss cycles system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8006500 # number of ReadReq MSHR uncacheable cycles system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 1234720500 # number of ReadReq MSHR uncacheable cycles system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 1242727000 # number of ReadReq MSHR uncacheable cycles system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 8006500 # number of overall MSHR uncacheable cycles system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 1234720500 # number of overall MSHR uncacheable cycles system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 1242727000 # number of overall MSHR uncacheable cycles system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.023233 # mshr miss rate for ReadReq accesses system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.048663 # mshr miss rate for ReadReq accesses system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.029644 # mshr miss rate for ReadReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.998117 # mshr miss rate for UpgradeReq accesses system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.998117 # mshr miss rate for UpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.239653 # mshr miss rate for ReadExReq accesses system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.239653 # mshr miss rate for ReadExReq accesses system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.080980 # mshr miss rate for ReadCleanReq accesses system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.080980 # mshr miss rate for ReadCleanReq accesses system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.272149 # mshr miss rate for ReadSharedReq accesses system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.272149 # mshr miss rate for ReadSharedReq accesses system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.584803 # mshr miss rate for InvalidateReq accesses system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.584803 # mshr miss rate for InvalidateReq accesses system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.023233 # mshr miss rate for demand accesses system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.048663 # mshr miss rate for demand accesses system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.080980 # mshr miss rate for demand accesses system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.264406 # mshr miss rate for demand accesses system.cpu1.l2cache.demand_mshr_miss_rate::total 0.139801 # mshr miss rate for demand accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.023233 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.048663 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.080980 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.264406 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::total 0.192823 # mshr miss rate for overall accesses system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 28796.827795 # average ReadReq mshr miss latency system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 28624.732536 # average ReadReq mshr miss latency system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 28725.610709 # average ReadReq mshr miss latency system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 38948.299055 # average HardPFReq mshr miss latency system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 38948.299055 # average HardPFReq mshr miss latency system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20841.626813 # average UpgradeReq mshr miss latency system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20841.626813 # average UpgradeReq mshr miss latency system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 16189.657767 # average SCUpgradeReq mshr miss latency system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 16189.657767 # average SCUpgradeReq mshr miss latency system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 372944.333333 # average SCUpgradeFailReq mshr miss latency system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 372944.333333 # average SCUpgradeFailReq mshr miss latency system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 31574.707002 # average ReadExReq mshr miss latency system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 31574.707002 # average ReadExReq mshr miss latency system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 26112.486981 # average ReadCleanReq mshr miss latency system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 26112.486981 # average ReadCleanReq mshr miss latency system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 25163.535220 # average ReadSharedReq mshr miss latency system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 25163.535220 # average ReadSharedReq mshr miss latency system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 26480.228622 # average InvalidateReq mshr miss latency system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 26480.228622 # average InvalidateReq mshr miss latency system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 28796.827795 # average overall mshr miss latency system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 28624.732536 # average overall mshr miss latency system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 26112.486981 # average overall mshr miss latency system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 26548.026857 # average overall mshr miss latency system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 26415.677887 # average overall mshr miss latency system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 28796.827795 # average overall mshr miss latency system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 28624.732536 # average overall mshr miss latency system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 26112.486981 # average overall mshr miss latency system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 26548.026857 # average overall mshr miss latency system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 38948.299055 # average overall mshr miss latency system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 29861.857270 # average overall mshr miss latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 84278.947368 # average ReadReq mshr uncacheable latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 140420.846128 # average ReadReq mshr uncacheable latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 139820.769577 # average ReadReq mshr uncacheable latency system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 84278.947368 # average overall mshr uncacheable latency system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 69040.511071 # average overall mshr uncacheable latency system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 69121.030091 # average overall mshr uncacheable latency system.cpu1.toL2Bus.snoop_filter.tot_requests 26150144 # Total number of requests made to the snoop filter. system.cpu1.toL2Bus.snoop_filter.hit_single_requests 13381244 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 1981 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu1.toL2Bus.snoop_filter.tot_snoops 1969364 # Total number of snoops made to the snoop filter. system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 1969026 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 338 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states system.cpu1.toL2Bus.trans_dist::ReadReq 732517 # Transaction distribution system.cpu1.toL2Bus.trans_dist::ReadResp 12156991 # Transaction distribution system.cpu1.toL2Bus.trans_dist::WriteReq 9091 # Transaction distribution system.cpu1.toL2Bus.trans_dist::WriteResp 9091 # Transaction distribution system.cpu1.toL2Bus.trans_dist::WritebackDirty 4007359 # Transaction distribution system.cpu1.toL2Bus.trans_dist::WritebackClean 9735300 # Transaction distribution system.cpu1.toL2Bus.trans_dist::CleanEvict 2694691 # Transaction distribution system.cpu1.toL2Bus.trans_dist::HardPFReq 886167 # Transaction distribution system.cpu1.toL2Bus.trans_dist::HardPFResp 3 # Transaction distribution system.cpu1.toL2Bus.trans_dist::UpgradeReq 430328 # Transaction distribution system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 337223 # Transaction distribution system.cpu1.toL2Bus.trans_dist::UpgradeResp 468486 # Transaction distribution system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 75 # Transaction distribution system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 138 # Transaction distribution system.cpu1.toL2Bus.trans_dist::ReadExReq 1067899 # Transaction distribution system.cpu1.toL2Bus.trans_dist::ReadExResp 1044213 # Transaction distribution system.cpu1.toL2Bus.trans_dist::ReadCleanReq 8014908 # Transaction distribution system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4433895 # Transaction distribution system.cpu1.toL2Bus.trans_dist::InvalidateReq 458319 # Transaction distribution system.cpu1.toL2Bus.trans_dist::InvalidateResp 398059 # Transaction distribution system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 24044391 # Packet count per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 15175224 # Packet count per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 343569 # Packet count per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1027712 # Packet count per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_count::total 40590896 # Packet count per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1025880832 # Cumulative packet size per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 583383788 # Cumulative packet size per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1306120 # Cumulative packet size per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 3875096 # Cumulative packet size per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_size::total 1614445836 # Cumulative packet size per connected master and slave (bytes) system.cpu1.toL2Bus.snoops 6456023 # Total snoops (count) system.cpu1.toL2Bus.snoopTraffic 75189768 # Total snoop traffic (bytes) system.cpu1.toL2Bus.snoop_fanout::samples 20132697 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::mean 0.112928 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::stdev 0.316558 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::0 17859482 88.71% 88.71% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::1 2272877 11.29% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::2 338 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::total 20132697 # Request fanout histogram system.cpu1.toL2Bus.reqLayer0.occupancy 25974578977 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.cpu1.toL2Bus.snoopLayer0.occupancy 179053447 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) system.cpu1.toL2Bus.respLayer0.occupancy 12025219550 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu1.toL2Bus.respLayer1.occupancy 6952751265 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu1.toL2Bus.respLayer2.occupancy 180351405 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) system.cpu1.toL2Bus.respLayer3.occupancy 543399850 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states system.iobus.trans_dist::ReadReq 40387 # Transaction distribution system.iobus.trans_dist::ReadResp 40387 # Transaction distribution system.iobus.trans_dist::WriteReq 136979 # Transaction distribution system.iobus.trans_dist::WriteResp 136979 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47808 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29808 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 122950 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231702 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::total 231702 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::total 354732 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47828 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17703 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 155965 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7355160 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::total 7355160 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 7513211 # Cumulative packet size per connected master and slave (bytes) system.iobus.reqLayer0.occupancy 42458502 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 311001 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer3.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer10.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer13.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer14.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer15.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer16.occupancy 15000 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer23.occupancy 26063002 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer24.occupancy 34444001 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer25.occupancy 570734934 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 92958000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer3.occupancy 148142000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states system.iocache.tags.replacements 115832 # number of replacements system.iocache.tags.tagsinuse 11.305903 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 115848 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. system.iocache.tags.warmup_cycle 9127528857000 # Cycle when the warmup percentage was hit. system.iocache.tags.occ_blocks::realview.ethernet 3.833923 # Average occupied blocks per requestor system.iocache.tags.occ_blocks::realview.ide 7.471980 # Average occupied blocks per requestor system.iocache.tags.occ_percent::realview.ethernet 0.239620 # Average percentage of cache occupancy system.iocache.tags.occ_percent::realview.ide 0.466999 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.706619 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 1043016 # Number of tag accesses system.iocache.tags.data_accesses 1043016 # Number of data accesses system.iocache.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses system.iocache.ReadReq_misses::realview.ide 8867 # number of ReadReq misses system.iocache.ReadReq_misses::total 8904 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteLineReq_misses::realview.ide 106984 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 106984 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses system.iocache.demand_misses::realview.ide 115851 # number of demand (read+write) misses system.iocache.demand_misses::total 115891 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses system.iocache.overall_misses::realview.ide 115851 # number of overall misses system.iocache.overall_misses::total 115891 # number of overall misses system.iocache.ReadReq_miss_latency::realview.ethernet 5198000 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::realview.ide 1647274031 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 1652472031 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles system.iocache.WriteLineReq_miss_latency::realview.ide 12886794903 # number of WriteLineReq miss cycles system.iocache.WriteLineReq_miss_latency::total 12886794903 # number of WriteLineReq miss cycles system.iocache.demand_miss_latency::realview.ethernet 5567000 # number of demand (read+write) miss cycles system.iocache.demand_miss_latency::realview.ide 14534068934 # number of demand (read+write) miss cycles system.iocache.demand_miss_latency::total 14539635934 # number of demand (read+write) miss cycles system.iocache.overall_miss_latency::realview.ethernet 5567000 # number of overall miss cycles system.iocache.overall_miss_latency::realview.ide 14534068934 # number of overall miss cycles system.iocache.overall_miss_latency::total 14539635934 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::realview.ide 8867 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 8904 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 106984 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106984 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses system.iocache.demand_accesses::realview.ide 115851 # number of demand (read+write) accesses system.iocache.demand_accesses::total 115891 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses system.iocache.overall_accesses::realview.ide 115851 # number of overall (read+write) accesses system.iocache.overall_accesses::total 115891 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140486.486486 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::realview.ide 185775.801398 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total 185587.604560 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120455.347557 # average WriteLineReq miss latency system.iocache.WriteLineReq_avg_miss_latency::total 120455.347557 # average WriteLineReq miss latency system.iocache.demand_avg_miss_latency::realview.ethernet 139175 # average overall miss latency system.iocache.demand_avg_miss_latency::realview.ide 125454.842289 # average overall miss latency system.iocache.demand_avg_miss_latency::total 125459.577827 # average overall miss latency system.iocache.overall_avg_miss_latency::realview.ethernet 139175 # average overall miss latency system.iocache.overall_avg_miss_latency::realview.ide 125454.842289 # average overall miss latency system.iocache.overall_avg_miss_latency::total 125459.577827 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 32243 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 3515 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked system.iocache.avg_blocked_cycles::no_mshrs 9.172973 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 106950 # number of writebacks system.iocache.writebacks::total 106950 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses system.iocache.ReadReq_mshr_misses::realview.ide 8867 # number of ReadReq MSHR misses system.iocache.ReadReq_mshr_misses::total 8904 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 106984 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 106984 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses system.iocache.demand_mshr_misses::realview.ide 115851 # number of demand (read+write) MSHR misses system.iocache.demand_mshr_misses::total 115891 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses system.iocache.overall_mshr_misses::realview.ide 115851 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 115891 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3348000 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::realview.ide 1203924031 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 1207272031 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7528956843 # number of WriteLineReq MSHR miss cycles system.iocache.WriteLineReq_mshr_miss_latency::total 7528956843 # number of WriteLineReq MSHR miss cycles system.iocache.demand_mshr_miss_latency::realview.ethernet 3567000 # number of demand (read+write) MSHR miss cycles system.iocache.demand_mshr_miss_latency::realview.ide 8732880874 # number of demand (read+write) MSHR miss cycles system.iocache.demand_mshr_miss_latency::total 8736447874 # number of demand (read+write) MSHR miss cycles system.iocache.overall_mshr_miss_latency::realview.ethernet 3567000 # number of overall MSHR miss cycles system.iocache.overall_mshr_miss_latency::realview.ide 8732880874 # number of overall MSHR miss cycles system.iocache.overall_mshr_miss_latency::total 8736447874 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90486.486486 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 135775.801398 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::total 135587.604560 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70374.605950 # average WriteLineReq mshr miss latency system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70374.605950 # average WriteLineReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89175 # average overall mshr miss latency system.iocache.demand_avg_mshr_miss_latency::realview.ide 75380.280481 # average overall mshr miss latency system.iocache.demand_avg_mshr_miss_latency::total 75385.041755 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89175 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::realview.ide 75380.280481 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::total 75385.041755 # average overall mshr miss latency system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states system.l2c.tags.replacements 1436798 # number of replacements system.l2c.tags.tagsinuse 63641.257392 # Cycle average of tags in use system.l2c.tags.total_refs 6808742 # Total number of references to valid blocks. system.l2c.tags.sampled_refs 1497176 # Sample count of references to valid blocks. system.l2c.tags.avg_refs 4.547723 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 8050623000 # Cycle when the warmup percentage was hit. system.l2c.tags.occ_blocks::writebacks 20256.980304 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.dtb.walker 307.265586 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.itb.walker 477.600666 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.inst 6075.269789 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.data 12531.509900 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 19419.437449 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1.dtb.walker 11.305032 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1.itb.walker 4.128844 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1.inst 2389.320183 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1.data 1436.582929 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 731.856711 # Average occupied blocks per requestor system.l2c.tags.occ_percent::writebacks 0.309097 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.dtb.walker 0.004689 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.007288 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.inst 0.092701 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.data 0.191216 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.296317 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000173 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.itb.walker 0.000063 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.inst 0.036458 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.data 0.021921 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.011167 # Average percentage of cache occupancy system.l2c.tags.occ_percent::total 0.971089 # Average percentage of cache occupancy system.l2c.tags.occ_task_id_blocks::1022 10768 # Occupied blocks per task id system.l2c.tags.occ_task_id_blocks::1023 197 # Occupied blocks per task id system.l2c.tags.occ_task_id_blocks::1024 49413 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1022::1 9 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1022::2 162 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1022::3 3598 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1022::4 6999 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1023::3 18 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1023::4 179 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::1 298 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::2 2209 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::3 15374 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::4 31482 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1022 0.164307 # Percentage of cache occupancy per task id system.l2c.tags.occ_task_id_percent::1023 0.003006 # Percentage of cache occupancy per task id system.l2c.tags.occ_task_id_percent::1024 0.753983 # Percentage of cache occupancy per task id system.l2c.tags.tag_accesses 82887108 # Number of tag accesses system.l2c.tags.data_accesses 82887108 # Number of data accesses system.l2c.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states system.l2c.WritebackDirty_hits::writebacks 2851442 # number of WritebackDirty hits system.l2c.WritebackDirty_hits::total 2851442 # number of WritebackDirty hits system.l2c.UpgradeReq_hits::cpu0.data 184675 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu1.data 129782 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 314457 # number of UpgradeReq hits system.l2c.SCUpgradeReq_hits::cpu0.data 47164 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::cpu1.data 36238 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::total 83402 # number of SCUpgradeReq hits system.l2c.ReadExReq_hits::cpu0.data 58975 # number of ReadExReq hits system.l2c.ReadExReq_hits::cpu1.data 57393 # number of ReadExReq hits system.l2c.ReadExReq_hits::total 116368 # number of ReadExReq hits system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 7045 # number of ReadSharedReq hits system.l2c.ReadSharedReq_hits::cpu0.itb.walker 4376 # number of ReadSharedReq hits system.l2c.ReadSharedReq_hits::cpu0.inst 746247 # number of ReadSharedReq hits system.l2c.ReadSharedReq_hits::cpu0.data 677498 # number of ReadSharedReq hits system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 343450 # number of ReadSharedReq hits system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 6710 # number of ReadSharedReq hits system.l2c.ReadSharedReq_hits::cpu1.itb.walker 4818 # number of ReadSharedReq hits system.l2c.ReadSharedReq_hits::cpu1.inst 604538 # number of ReadSharedReq hits system.l2c.ReadSharedReq_hits::cpu1.data 564393 # number of ReadSharedReq hits system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 306025 # number of ReadSharedReq hits system.l2c.ReadSharedReq_hits::total 3265100 # number of ReadSharedReq hits system.l2c.InvalidateReq_hits::cpu0.data 138219 # number of InvalidateReq hits system.l2c.InvalidateReq_hits::cpu1.data 125546 # number of InvalidateReq hits system.l2c.InvalidateReq_hits::total 263765 # number of InvalidateReq hits system.l2c.demand_hits::cpu0.dtb.walker 7045 # number of demand (read+write) hits system.l2c.demand_hits::cpu0.itb.walker 4376 # number of demand (read+write) hits system.l2c.demand_hits::cpu0.inst 746247 # number of demand (read+write) hits system.l2c.demand_hits::cpu0.data 736473 # number of demand (read+write) hits system.l2c.demand_hits::cpu0.l2cache.prefetcher 343450 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.dtb.walker 6710 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.itb.walker 4818 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.inst 604538 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.data 621786 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.l2cache.prefetcher 306025 # number of demand (read+write) hits system.l2c.demand_hits::total 3381468 # number of demand (read+write) hits system.l2c.overall_hits::cpu0.dtb.walker 7045 # number of overall hits system.l2c.overall_hits::cpu0.itb.walker 4376 # number of overall hits system.l2c.overall_hits::cpu0.inst 746247 # number of overall hits system.l2c.overall_hits::cpu0.data 736473 # number of overall hits system.l2c.overall_hits::cpu0.l2cache.prefetcher 343450 # number of overall hits system.l2c.overall_hits::cpu1.dtb.walker 6710 # number of overall hits system.l2c.overall_hits::cpu1.itb.walker 4818 # number of overall hits system.l2c.overall_hits::cpu1.inst 604538 # number of overall hits system.l2c.overall_hits::cpu1.data 621786 # number of overall hits system.l2c.overall_hits::cpu1.l2cache.prefetcher 306025 # number of overall hits system.l2c.overall_hits::total 3381468 # number of overall hits system.l2c.UpgradeReq_misses::cpu0.data 65595 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::cpu1.data 60730 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::total 126325 # number of UpgradeReq misses system.l2c.SCUpgradeReq_misses::cpu0.data 12636 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::cpu1.data 10558 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::total 23194 # number of SCUpgradeReq misses system.l2c.ReadExReq_misses::cpu0.data 86809 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu1.data 47256 # number of ReadExReq misses system.l2c.ReadExReq_misses::total 134065 # number of ReadExReq misses system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 2557 # number of ReadSharedReq misses system.l2c.ReadSharedReq_misses::cpu0.itb.walker 2464 # number of ReadSharedReq misses system.l2c.ReadSharedReq_misses::cpu0.inst 78739 # number of ReadSharedReq misses system.l2c.ReadSharedReq_misses::cpu0.data 176748 # number of ReadSharedReq misses system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 289930 # number of ReadSharedReq misses system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 1566 # number of ReadSharedReq misses system.l2c.ReadSharedReq_misses::cpu1.itb.walker 1157 # number of ReadSharedReq misses system.l2c.ReadSharedReq_misses::cpu1.inst 44505 # number of ReadSharedReq misses system.l2c.ReadSharedReq_misses::cpu1.data 80821 # number of ReadSharedReq misses system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 170404 # number of ReadSharedReq misses system.l2c.ReadSharedReq_misses::total 848891 # number of ReadSharedReq misses system.l2c.InvalidateReq_misses::cpu0.data 477170 # number of InvalidateReq misses system.l2c.InvalidateReq_misses::cpu1.data 94656 # number of InvalidateReq misses system.l2c.InvalidateReq_misses::total 571826 # number of InvalidateReq misses system.l2c.demand_misses::cpu0.dtb.walker 2557 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 2464 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.inst 78739 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.data 263557 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.l2cache.prefetcher 289930 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.dtb.walker 1566 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.itb.walker 1157 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.inst 44505 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.data 128077 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.l2cache.prefetcher 170404 # number of demand (read+write) misses system.l2c.demand_misses::total 982956 # number of demand (read+write) misses system.l2c.overall_misses::cpu0.dtb.walker 2557 # number of overall misses system.l2c.overall_misses::cpu0.itb.walker 2464 # number of overall misses system.l2c.overall_misses::cpu0.inst 78739 # number of overall misses system.l2c.overall_misses::cpu0.data 263557 # number of overall misses system.l2c.overall_misses::cpu0.l2cache.prefetcher 289930 # number of overall misses system.l2c.overall_misses::cpu1.dtb.walker 1566 # number of overall misses system.l2c.overall_misses::cpu1.itb.walker 1157 # number of overall misses system.l2c.overall_misses::cpu1.inst 44505 # number of overall misses system.l2c.overall_misses::cpu1.data 128077 # number of overall misses system.l2c.overall_misses::cpu1.l2cache.prefetcher 170404 # number of overall misses system.l2c.overall_misses::total 982956 # number of overall misses system.l2c.UpgradeReq_miss_latency::cpu0.data 456935000 # number of UpgradeReq miss cycles system.l2c.UpgradeReq_miss_latency::cpu1.data 428124500 # number of UpgradeReq miss cycles system.l2c.UpgradeReq_miss_latency::total 885059500 # number of UpgradeReq miss cycles system.l2c.SCUpgradeReq_miss_latency::cpu0.data 88094500 # number of SCUpgradeReq miss cycles system.l2c.SCUpgradeReq_miss_latency::cpu1.data 70625000 # number of SCUpgradeReq miss cycles system.l2c.SCUpgradeReq_miss_latency::total 158719500 # number of SCUpgradeReq miss cycles system.l2c.ReadExReq_miss_latency::cpu0.data 7719270500 # number of ReadExReq miss cycles system.l2c.ReadExReq_miss_latency::cpu1.data 3911139500 # number of ReadExReq miss cycles system.l2c.ReadExReq_miss_latency::total 11630410000 # number of ReadExReq miss cycles system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 226838000 # number of ReadSharedReq miss cycles system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 219007500 # number of ReadSharedReq miss cycles system.l2c.ReadSharedReq_miss_latency::cpu0.inst 6705086500 # number of ReadSharedReq miss cycles system.l2c.ReadSharedReq_miss_latency::cpu0.data 15776824000 # number of ReadSharedReq miss cycles system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 36609242451 # number of ReadSharedReq miss cycles system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 145187000 # number of ReadSharedReq miss cycles system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 107589500 # number of ReadSharedReq miss cycles system.l2c.ReadSharedReq_miss_latency::cpu1.inst 3760779000 # number of ReadSharedReq miss cycles system.l2c.ReadSharedReq_miss_latency::cpu1.data 7519043500 # number of ReadSharedReq miss cycles system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 21421936717 # number of ReadSharedReq miss cycles system.l2c.ReadSharedReq_miss_latency::total 92491534168 # number of ReadSharedReq miss cycles system.l2c.InvalidateReq_miss_latency::cpu0.data 63068500 # number of InvalidateReq miss cycles system.l2c.InvalidateReq_miss_latency::cpu1.data 48974000 # number of InvalidateReq miss cycles system.l2c.InvalidateReq_miss_latency::total 112042500 # number of InvalidateReq miss cycles system.l2c.demand_miss_latency::cpu0.dtb.walker 226838000 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu0.itb.walker 219007500 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu0.inst 6705086500 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu0.data 23496094500 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 36609242451 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu1.dtb.walker 145187000 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu1.itb.walker 107589500 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu1.inst 3760779000 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu1.data 11430183000 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 21421936717 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::total 104121944168 # number of demand (read+write) miss cycles system.l2c.overall_miss_latency::cpu0.dtb.walker 226838000 # number of overall miss cycles system.l2c.overall_miss_latency::cpu0.itb.walker 219007500 # number of overall miss cycles system.l2c.overall_miss_latency::cpu0.inst 6705086500 # number of overall miss cycles system.l2c.overall_miss_latency::cpu0.data 23496094500 # number of overall miss cycles system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 36609242451 # number of overall miss cycles system.l2c.overall_miss_latency::cpu1.dtb.walker 145187000 # number of overall miss cycles system.l2c.overall_miss_latency::cpu1.itb.walker 107589500 # number of overall miss cycles system.l2c.overall_miss_latency::cpu1.inst 3760779000 # number of overall miss cycles system.l2c.overall_miss_latency::cpu1.data 11430183000 # number of overall miss cycles system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 21421936717 # number of overall miss cycles system.l2c.overall_miss_latency::total 104121944168 # number of overall miss cycles system.l2c.WritebackDirty_accesses::writebacks 2851442 # number of WritebackDirty accesses(hits+misses) system.l2c.WritebackDirty_accesses::total 2851442 # number of WritebackDirty accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu0.data 250270 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu1.data 190512 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::total 440782 # number of UpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::cpu0.data 59800 # number of SCUpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::cpu1.data 46796 # number of SCUpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::total 106596 # number of SCUpgradeReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu0.data 145784 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu1.data 104649 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::total 250433 # number of ReadExReq accesses(hits+misses) system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 9602 # number of ReadSharedReq accesses(hits+misses) system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 6840 # number of ReadSharedReq accesses(hits+misses) system.l2c.ReadSharedReq_accesses::cpu0.inst 824986 # number of ReadSharedReq accesses(hits+misses) system.l2c.ReadSharedReq_accesses::cpu0.data 854246 # number of ReadSharedReq accesses(hits+misses) system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 633380 # number of ReadSharedReq accesses(hits+misses) system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 8276 # number of ReadSharedReq accesses(hits+misses) system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 5975 # number of ReadSharedReq accesses(hits+misses) system.l2c.ReadSharedReq_accesses::cpu1.inst 649043 # number of ReadSharedReq accesses(hits+misses) system.l2c.ReadSharedReq_accesses::cpu1.data 645214 # number of ReadSharedReq accesses(hits+misses) system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 476429 # number of ReadSharedReq accesses(hits+misses) system.l2c.ReadSharedReq_accesses::total 4113991 # number of ReadSharedReq accesses(hits+misses) system.l2c.InvalidateReq_accesses::cpu0.data 615389 # number of InvalidateReq accesses(hits+misses) system.l2c.InvalidateReq_accesses::cpu1.data 220202 # number of InvalidateReq accesses(hits+misses) system.l2c.InvalidateReq_accesses::total 835591 # number of InvalidateReq accesses(hits+misses) system.l2c.demand_accesses::cpu0.dtb.walker 9602 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu0.itb.walker 6840 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu0.inst 824986 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu0.data 1000030 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu0.l2cache.prefetcher 633380 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.dtb.walker 8276 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.itb.walker 5975 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.inst 649043 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.data 749863 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.l2cache.prefetcher 476429 # number of demand (read+write) accesses system.l2c.demand_accesses::total 4364424 # number of demand (read+write) accesses system.l2c.overall_accesses::cpu0.dtb.walker 9602 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu0.itb.walker 6840 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu0.inst 824986 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu0.data 1000030 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu0.l2cache.prefetcher 633380 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu1.dtb.walker 8276 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu1.itb.walker 5975 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu1.inst 649043 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu1.data 749863 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu1.l2cache.prefetcher 476429 # number of overall (read+write) accesses system.l2c.overall_accesses::total 4364424 # number of overall (read+write) accesses system.l2c.UpgradeReq_miss_rate::cpu0.data 0.262097 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu1.data 0.318773 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::total 0.286593 # miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.211304 # miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.225618 # miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::total 0.217588 # miss rate for SCUpgradeReq accesses system.l2c.ReadExReq_miss_rate::cpu0.data 0.595463 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu1.data 0.451567 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::total 0.535333 # miss rate for ReadExReq accesses system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.266299 # miss rate for ReadSharedReq accesses system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.360234 # miss rate for ReadSharedReq accesses system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.095443 # miss rate for ReadSharedReq accesses system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.206905 # miss rate for ReadSharedReq accesses system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.457750 # miss rate for ReadSharedReq accesses system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.189222 # miss rate for ReadSharedReq accesses system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.193640 # miss rate for ReadSharedReq accesses system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.068570 # miss rate for ReadSharedReq accesses system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.125262 # miss rate for ReadSharedReq accesses system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.357669 # miss rate for ReadSharedReq accesses system.l2c.ReadSharedReq_miss_rate::total 0.206342 # miss rate for ReadSharedReq accesses system.l2c.InvalidateReq_miss_rate::cpu0.data 0.775396 # miss rate for InvalidateReq accesses system.l2c.InvalidateReq_miss_rate::cpu1.data 0.429860 # miss rate for InvalidateReq accesses system.l2c.InvalidateReq_miss_rate::total 0.684337 # miss rate for InvalidateReq accesses system.l2c.demand_miss_rate::cpu0.dtb.walker 0.266299 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.itb.walker 0.360234 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.inst 0.095443 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.data 0.263549 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.457750 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.dtb.walker 0.189222 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.itb.walker 0.193640 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.inst 0.068570 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.data 0.170801 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.357669 # miss rate for demand accesses system.l2c.demand_miss_rate::total 0.225220 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu0.dtb.walker 0.266299 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.itb.walker 0.360234 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.inst 0.095443 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.data 0.263549 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.457750 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.dtb.walker 0.189222 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.itb.walker 0.193640 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.inst 0.068570 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.data 0.170801 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.357669 # miss rate for overall accesses system.l2c.overall_miss_rate::total 0.225220 # miss rate for overall accesses system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 6966.003506 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 7049.637741 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::total 7006.210172 # average UpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 6971.707819 # average SCUpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 6689.240386 # average SCUpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::total 6843.127533 # average SCUpgradeReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu0.data 88922.467716 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu1.data 82764.929321 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::total 86752.023272 # average ReadExReq miss latency system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 88712.553774 # average ReadSharedReq miss latency system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 88882.913961 # average ReadSharedReq miss latency system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 85155.850341 # average ReadSharedReq miss latency system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 89261.683301 # average ReadSharedReq miss latency system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 126269.245856 # average ReadSharedReq miss latency system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 92712.005109 # average ReadSharedReq miss latency system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 92990.060501 # average ReadSharedReq miss latency system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 84502.392990 # average ReadSharedReq miss latency system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 93033.289615 # average ReadSharedReq miss latency system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 125712.640061 # average ReadSharedReq miss latency system.l2c.ReadSharedReq_avg_miss_latency::total 108955.724784 # average ReadSharedReq miss latency system.l2c.InvalidateReq_avg_miss_latency::cpu0.data 132.171972 # average InvalidateReq miss latency system.l2c.InvalidateReq_avg_miss_latency::cpu1.data 517.389283 # average InvalidateReq miss latency system.l2c.InvalidateReq_avg_miss_latency::total 195.938100 # average InvalidateReq miss latency system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 88712.553774 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu0.itb.walker 88882.913961 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu0.inst 85155.850341 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu0.data 89149.954279 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 126269.245856 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 92712.005109 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu1.itb.walker 92990.060501 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu1.inst 84502.392990 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu1.data 89244.618472 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 125712.640061 # average overall miss latency system.l2c.demand_avg_miss_latency::total 105927.370267 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 88712.553774 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.itb.walker 88882.913961 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.inst 85155.850341 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.data 89149.954279 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 126269.245856 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 92712.005109 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.itb.walker 92990.060501 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.inst 84502.392990 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.data 89244.618472 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 125712.640061 # average overall miss latency system.l2c.overall_avg_miss_latency::total 105927.370267 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 198 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 3 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked system.l2c.avg_blocked_cycles::no_mshrs 66 # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.writebacks::writebacks 1121516 # number of writebacks system.l2c.writebacks::total 1121516 # number of writebacks system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 148 # number of ReadSharedReq MSHR hits system.l2c.ReadSharedReq_mshr_hits::cpu0.data 11 # number of ReadSharedReq MSHR hits system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 139 # number of ReadSharedReq MSHR hits system.l2c.ReadSharedReq_mshr_hits::cpu1.data 17 # number of ReadSharedReq MSHR hits system.l2c.ReadSharedReq_mshr_hits::total 315 # number of ReadSharedReq MSHR hits system.l2c.demand_mshr_hits::cpu0.inst 148 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::cpu0.data 11 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::cpu1.inst 139 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::cpu1.data 17 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::total 315 # number of demand (read+write) MSHR hits system.l2c.overall_mshr_hits::cpu0.inst 148 # number of overall MSHR hits system.l2c.overall_mshr_hits::cpu0.data 11 # number of overall MSHR hits system.l2c.overall_mshr_hits::cpu1.inst 139 # number of overall MSHR hits system.l2c.overall_mshr_hits::cpu1.data 17 # number of overall MSHR hits system.l2c.overall_mshr_hits::total 315 # number of overall MSHR hits system.l2c.CleanEvict_mshr_misses::writebacks 53239 # number of CleanEvict MSHR misses system.l2c.CleanEvict_mshr_misses::total 53239 # number of CleanEvict MSHR misses system.l2c.UpgradeReq_mshr_misses::cpu0.data 65595 # number of UpgradeReq MSHR misses system.l2c.UpgradeReq_mshr_misses::cpu1.data 60730 # number of UpgradeReq MSHR misses system.l2c.UpgradeReq_mshr_misses::total 126325 # number of UpgradeReq MSHR misses system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 12636 # number of SCUpgradeReq MSHR misses system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 10558 # number of SCUpgradeReq MSHR misses system.l2c.SCUpgradeReq_mshr_misses::total 23194 # number of SCUpgradeReq MSHR misses system.l2c.ReadExReq_mshr_misses::cpu0.data 86809 # number of ReadExReq MSHR misses system.l2c.ReadExReq_mshr_misses::cpu1.data 47256 # number of ReadExReq MSHR misses system.l2c.ReadExReq_mshr_misses::total 134065 # number of ReadExReq MSHR misses system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 2557 # number of ReadSharedReq MSHR misses system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 2464 # number of ReadSharedReq MSHR misses system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 78591 # number of ReadSharedReq MSHR misses system.l2c.ReadSharedReq_mshr_misses::cpu0.data 176737 # number of ReadSharedReq MSHR misses system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 289930 # number of ReadSharedReq MSHR misses system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 1566 # number of ReadSharedReq MSHR misses system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker 1157 # number of ReadSharedReq MSHR misses system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 44366 # number of ReadSharedReq MSHR misses system.l2c.ReadSharedReq_mshr_misses::cpu1.data 80804 # number of ReadSharedReq MSHR misses system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 170404 # number of ReadSharedReq MSHR misses system.l2c.ReadSharedReq_mshr_misses::total 848576 # number of ReadSharedReq MSHR misses system.l2c.InvalidateReq_mshr_misses::cpu0.data 477170 # number of InvalidateReq MSHR misses system.l2c.InvalidateReq_mshr_misses::cpu1.data 94656 # number of InvalidateReq MSHR misses system.l2c.InvalidateReq_mshr_misses::total 571826 # number of InvalidateReq MSHR misses system.l2c.demand_mshr_misses::cpu0.dtb.walker 2557 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu0.itb.walker 2464 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu0.inst 78591 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu0.data 263546 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 289930 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu1.dtb.walker 1566 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu1.itb.walker 1157 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu1.inst 44366 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu1.data 128060 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 170404 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::total 982641 # number of demand (read+write) MSHR misses system.l2c.overall_mshr_misses::cpu0.dtb.walker 2557 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu0.itb.walker 2464 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu0.inst 78591 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu0.data 263546 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 289930 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu1.dtb.walker 1566 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu1.itb.walker 1157 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu1.inst 44366 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu1.data 128060 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 170404 # number of overall MSHR misses system.l2c.overall_mshr_misses::total 982641 # number of overall MSHR misses system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 52300 # number of ReadReq MSHR uncacheable system.l2c.ReadReq_mshr_uncacheable::cpu0.data 29793 # number of ReadReq MSHR uncacheable system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 95 # number of ReadReq MSHR uncacheable system.l2c.ReadReq_mshr_uncacheable::cpu1.data 8791 # number of ReadReq MSHR uncacheable system.l2c.ReadReq_mshr_uncacheable::total 90979 # number of ReadReq MSHR uncacheable system.l2c.WriteReq_mshr_uncacheable::cpu0.data 29400 # number of WriteReq MSHR uncacheable system.l2c.WriteReq_mshr_uncacheable::cpu1.data 9091 # number of WriteReq MSHR uncacheable system.l2c.WriteReq_mshr_uncacheable::total 38491 # number of WriteReq MSHR uncacheable system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 52300 # number of overall MSHR uncacheable misses system.l2c.overall_mshr_uncacheable_misses::cpu0.data 59193 # number of overall MSHR uncacheable misses system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 95 # number of overall MSHR uncacheable misses system.l2c.overall_mshr_uncacheable_misses::cpu1.data 17882 # number of overall MSHR uncacheable misses system.l2c.overall_mshr_uncacheable_misses::total 129470 # number of overall MSHR uncacheable misses system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 1410582996 # number of UpgradeReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 1311057994 # number of UpgradeReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_latency::total 2721640990 # number of UpgradeReq MSHR miss cycles system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 310816999 # number of SCUpgradeReq MSHR miss cycles system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 259803998 # number of SCUpgradeReq MSHR miss cycles system.l2c.SCUpgradeReq_mshr_miss_latency::total 570620997 # number of SCUpgradeReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 6851145073 # number of ReadExReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3438526610 # number of ReadExReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_latency::total 10289671683 # number of ReadExReq MSHR miss cycles system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 201267501 # number of ReadSharedReq MSHR miss cycles system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 194366502 # number of ReadSharedReq MSHR miss cycles system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 5908962562 # number of ReadSharedReq MSHR miss cycles system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 14008544736 # number of ReadSharedReq MSHR miss cycles system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 33709734391 # number of ReadSharedReq MSHR miss cycles system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 129525503 # number of ReadSharedReq MSHR miss cycles system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 96018502 # number of ReadSharedReq MSHR miss cycles system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 3307546077 # number of ReadSharedReq MSHR miss cycles system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 6709739262 # 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number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 129525503 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 96018502 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu1.inst 3307546077 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu1.data 10148265872 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 19717611814 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::total 94272988533 # number of demand (read+write) MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 201267501 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 194366502 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.inst 5908962562 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.data 20859689809 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 33709734391 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 129525503 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 96018502 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu1.inst 3307546077 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu1.data 10148265872 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 19717611814 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::total 94272988533 # number of overall MSHR miss cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 3320084000 # number of ReadReq MSHR uncacheable cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 4900695009 # number of ReadReq MSHR uncacheable cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 6011000 # number of ReadReq MSHR uncacheable cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 1076346004 # number of ReadReq MSHR uncacheable cycles system.l2c.ReadReq_mshr_uncacheable_latency::total 9303136013 # number of ReadReq MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 3320084000 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu0.data 4900695009 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 6011000 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1076346004 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::total 9303136013 # number of overall MSHR uncacheable cycles system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.262097 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.318773 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::total 0.286593 # mshr miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.211304 # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.225618 # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.217588 # mshr miss rate for SCUpgradeReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.595463 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.451567 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::total 0.535333 # mshr miss rate for ReadExReq accesses system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.266299 # mshr miss rate for ReadSharedReq accesses system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.360234 # mshr miss rate for ReadSharedReq accesses system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.095263 # mshr miss rate for ReadSharedReq accesses system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.206892 # mshr miss rate for ReadSharedReq accesses system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.457750 # mshr miss rate for ReadSharedReq accesses system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.189222 # mshr miss rate for ReadSharedReq accesses system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.193640 # mshr miss rate for ReadSharedReq accesses system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.068356 # mshr miss rate for ReadSharedReq accesses system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.125236 # mshr miss rate for ReadSharedReq accesses system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.357669 # mshr miss rate for ReadSharedReq accesses system.l2c.ReadSharedReq_mshr_miss_rate::total 0.206266 # mshr miss rate for ReadSharedReq accesses system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data 0.775396 # mshr miss rate for InvalidateReq accesses system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.429860 # mshr miss rate for InvalidateReq accesses system.l2c.InvalidateReq_mshr_miss_rate::total 0.684337 # mshr miss rate for InvalidateReq accesses system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.266299 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.360234 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu0.inst 0.095263 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu0.data 0.263538 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.457750 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.189222 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.193640 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu1.inst 0.068356 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu1.data 0.170778 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.357669 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::total 0.225148 # mshr miss rate for demand accesses system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.266299 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.360234 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu0.inst 0.095263 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu0.data 0.263538 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.457750 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.189222 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.193640 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu1.inst 0.068356 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu1.data 0.170778 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.357669 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::total 0.225148 # mshr miss rate for overall accesses system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 21504.428630 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 21588.308809 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::total 21544.753533 # average UpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 24597.736546 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24607.311801 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 24602.095240 # average SCUpgradeReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 78922.059614 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 72763.810098 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::total 76751.364510 # average ReadExReq mshr miss latency system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 78712.358623 # average ReadSharedReq mshr miss latency system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 78882.508929 # average ReadSharedReq mshr miss latency system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 75186.249850 # average ReadSharedReq mshr miss latency system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 79262.094163 # average ReadSharedReq mshr miss latency system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 116268.528234 # average ReadSharedReq mshr miss latency system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 82711.049170 # average ReadSharedReq mshr miss latency system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 82989.197926 # average ReadSharedReq mshr miss latency system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 74551.369900 # average ReadSharedReq mshr miss latency system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 83037.216747 # average ReadSharedReq mshr miss latency system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 115710.968135 # average ReadSharedReq mshr miss latency system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 98969.705542 # average ReadSharedReq mshr miss latency system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 20911.097724 # average InvalidateReq mshr miss latency system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 20861.825980 # average InvalidateReq mshr miss latency system.l2c.InvalidateReq_avg_mshr_miss_latency::total 20902.941631 # average InvalidateReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 78712.358623 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 78882.508929 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 75186.249850 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.data 79150.090720 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 116268.528234 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 82711.049170 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 82989.197926 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 74551.369900 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.data 79246.180478 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 115710.968135 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::total 95938.382922 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 78712.358623 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 78882.508929 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 75186.249850 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.data 79150.090720 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 116268.528234 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 82711.049170 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 82989.197926 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 74551.369900 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.data 79246.180478 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 115710.968135 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::total 95938.382922 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 63481.529637 # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 164491.491592 # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 63273.684211 # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 122437.265840 # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 102255.861386 # average ReadReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 63481.529637 # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 82791.799858 # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 63273.684211 # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 60191.589531 # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total 71855.534201 # average overall mshr uncacheable latency system.membus.snoop_filter.tot_requests 3914348 # Total number of requests made to the snoop filter. system.membus.snoop_filter.hit_single_requests 2362357 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 2871 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 90979 # Transaction distribution system.membus.trans_dist::ReadResp 948459 # Transaction distribution system.membus.trans_dist::WriteReq 38491 # Transaction distribution system.membus.trans_dist::WriteResp 38491 # Transaction distribution system.membus.trans_dist::WritebackDirty 1228466 # Transaction distribution system.membus.trans_dist::CleanEvict 265252 # Transaction distribution system.membus.trans_dist::UpgradeReq 443986 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 298688 # Transaction distribution system.membus.trans_dist::UpgradeResp 23 # Transaction distribution system.membus.trans_dist::SCUpgradeFailReq 2 # Transaction distribution system.membus.trans_dist::ReadExReq 145286 # Transaction distribution system.membus.trans_dist::ReadExResp 128554 # Transaction distribution system.membus.trans_dist::ReadSharedReq 857480 # Transaction distribution system.membus.trans_dist::InvalidateReq 675140 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122950 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 54 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 25980 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4768940 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::total 4917924 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 238548 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 238548 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 5156472 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155965 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1388 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 51960 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 137639872 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::total 137849185 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7281600 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 7281600 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 145130785 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 603530 # Total snoops (count) system.membus.snoopTraffic 179328 # Total snoop traffic (bytes) system.membus.snoop_fanout::samples 2550056 # Request fanout histogram system.membus.snoop_fanout::mean 0.011955 # Request fanout histogram system.membus.snoop_fanout::stdev 0.108685 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 2519569 98.80% 98.80% # Request fanout histogram system.membus.snoop_fanout::1 30487 1.20% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram system.membus.snoop_fanout::total 2550056 # Request fanout histogram system.membus.reqLayer0.occupancy 103375494 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 34812 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) system.membus.reqLayer2.occupancy 21768496 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer5.occupancy 8632891321 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) system.membus.respLayer2.occupancy 5537724663 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.membus.respLayer3.occupancy 45395946 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA system.realview.ethernet.totBandwidth 163 # Total Bandwidth (bits/s) system.realview.ethernet.totPackets 3 # Total Packets system.realview.ethernet.totBytes 966 # Total Bytes system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) system.realview.ethernet.txBandwidth 163 # Transmit Bandwidth (bits/s) system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states system.toL2Bus.snoop_filter.tot_requests 12809826 # Total number of requests made to the snoop filter. system.toL2Bus.snoop_filter.hit_single_requests 6934559 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_requests 2124865 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.toL2Bus.snoop_filter.tot_snoops 137043 # Total number of snoops made to the snoop filter. system.toL2Bus.snoop_filter.hit_single_snoops 124917 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 12126 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states system.toL2Bus.trans_dist::ReadReq 90981 # Transaction distribution system.toL2Bus.trans_dist::ReadResp 4987806 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 38491 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 38491 # Transaction distribution system.toL2Bus.trans_dist::WritebackDirty 3972958 # Transaction distribution system.toL2Bus.trans_dist::CleanEvict 3104635 # Transaction distribution system.toL2Bus.trans_dist::UpgradeReq 749262 # Transaction distribution system.toL2Bus.trans_dist::SCUpgradeReq 382090 # Transaction distribution system.toL2Bus.trans_dist::UpgradeResp 1131352 # Transaction distribution system.toL2Bus.trans_dist::SCUpgradeFailReq 138 # Transaction distribution system.toL2Bus.trans_dist::UpgradeFailResp 138 # Transaction distribution system.toL2Bus.trans_dist::ReadExReq 306540 # Transaction distribution system.toL2Bus.trans_dist::ReadExResp 306540 # Transaction distribution system.toL2Bus.trans_dist::ReadSharedReq 4897318 # Transaction distribution system.toL2Bus.trans_dist::InvalidateReq 863164 # Transaction distribution system.toL2Bus.trans_dist::InvalidateResp 835591 # Transaction distribution system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 11082342 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7735233 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count::total 18817575 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 276628165 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 188875292 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size::total 465503457 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.snoops 2889580 # Total snoops (count) system.toL2Bus.snoopTraffic 125478224 # Total snoop traffic (bytes) system.toL2Bus.snoop_fanout::samples 8764836 # Request fanout histogram system.toL2Bus.snoop_fanout::mean 0.360858 # Request fanout histogram system.toL2Bus.snoop_fanout::stdev 0.483121 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 5614105 64.05% 64.05% # Request fanout histogram system.toL2Bus.snoop_fanout::1 3138605 35.81% 99.86% # Request fanout histogram system.toL2Bus.snoop_fanout::2 12126 0.14% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram system.toL2Bus.snoop_fanout::total 8764836 # Request fanout histogram system.toL2Bus.reqLayer0.occupancy 9763497454 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) system.toL2Bus.snoopLayer0.occupancy 2559907 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) system.toL2Bus.respLayer0.occupancy 5082599079 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.toL2Bus.respLayer1.occupancy 3859782501 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ----------