stats.txt revision 11336
110515SAli.Saidi@ARM.com 210515SAli.Saidi@ARM.com---------- Begin Simulation Statistics ---------- 311336Sandreas.hansson@arm.comsim_seconds 47.461935 # Number of seconds simulated 411336Sandreas.hansson@arm.comsim_ticks 47461934895000 # Number of ticks simulated 511336Sandreas.hansson@arm.comfinal_tick 47461934895000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 610515SAli.Saidi@ARM.comsim_freq 1000000000000 # Frequency of simulated ticks 711336Sandreas.hansson@arm.comhost_inst_rate 231788 # Simulator instruction rate (inst/s) 811336Sandreas.hansson@arm.comhost_op_rate 272612 # Simulator op (including micro ops) rate (op/s) 911336Sandreas.hansson@arm.comhost_tick_rate 12136870284 # Simulator tick rate (ticks/s) 1011336Sandreas.hansson@arm.comhost_mem_usage 762440 # Number of bytes of host memory used 1111336Sandreas.hansson@arm.comhost_seconds 3910.56 # Real time elapsed on the host 1211336Sandreas.hansson@arm.comsim_insts 906421729 # Number of instructions simulated 1311336Sandreas.hansson@arm.comsim_ops 1066065309 # Number of ops (including micro ops) simulated 1410515SAli.Saidi@ARM.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1510515SAli.Saidi@ARM.comsystem.clk_domain.clock 1000 # Clock period in ticks 1611336Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.dtb.walker 128960 # Number of bytes read from this memory 1711336Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.itb.walker 112832 # Number of bytes read from this memory 1811336Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.inst 8192640 # Number of bytes read from this memory 1911336Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.data 40731208 # Number of bytes read from this memory 2011336Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.l2cache.prefetcher 14846528 # Number of bytes read from this memory 2111336Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.dtb.walker 153920 # Number of bytes read from this memory 2211336Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.itb.walker 132096 # Number of bytes read from this memory 2311336Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.inst 3008640 # Number of bytes read from this memory 2411336Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.data 17045264 # Number of bytes read from this memory 2511336Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.l2cache.prefetcher 15179584 # Number of bytes read from this memory 2611336Sandreas.hansson@arm.comsystem.physmem.bytes_read::realview.ide 435648 # Number of bytes read from this memory 2711336Sandreas.hansson@arm.comsystem.physmem.bytes_read::total 99967320 # Number of bytes read from this memory 2811336Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu0.inst 8192640 # Number of instructions bytes read from this memory 2911336Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu1.inst 3008640 # Number of instructions bytes read from this memory 3011336Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::total 11201280 # Number of instructions bytes read from this memory 3111336Sandreas.hansson@arm.comsystem.physmem.bytes_written::writebacks 79350912 # Number of bytes written to this memory 3210827Sandreas.hansson@arm.comsystem.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory 3310636Snilay@cs.wisc.edusystem.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory 3411336Sandreas.hansson@arm.comsystem.physmem.bytes_written::total 79371496 # Number of bytes written to this memory 3511336Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.dtb.walker 2015 # Number of read requests responded to by this memory 3611336Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.itb.walker 1763 # Number of read requests responded to by this memory 3711336Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.inst 128010 # Number of read requests responded to by this memory 3811336Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.data 636438 # Number of read requests responded to by this memory 3911336Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.l2cache.prefetcher 231977 # Number of read requests responded to by this memory 4011336Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.dtb.walker 2405 # Number of read requests responded to by this memory 4111336Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.itb.walker 2064 # Number of read requests responded to by this memory 4211336Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.inst 47010 # Number of read requests responded to by this memory 4311336Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.data 266345 # Number of read requests responded to by this memory 4411336Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.l2cache.prefetcher 237181 # Number of read requests responded to by this memory 4511336Sandreas.hansson@arm.comsystem.physmem.num_reads::realview.ide 6807 # Number of read requests responded to by this memory 4611336Sandreas.hansson@arm.comsystem.physmem.num_reads::total 1562015 # Number of read requests responded to by this memory 4711336Sandreas.hansson@arm.comsystem.physmem.num_writes::writebacks 1239858 # Number of write requests responded to by this memory 4810827Sandreas.hansson@arm.comsystem.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory 4910636Snilay@cs.wisc.edusystem.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory 5011336Sandreas.hansson@arm.comsystem.physmem.num_writes::total 1242432 # Number of write requests responded to by this memory 5111336Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.dtb.walker 2717 # Total read bandwidth from this memory (bytes/s) 5211336Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.itb.walker 2377 # Total read bandwidth from this memory (bytes/s) 5311336Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.inst 172615 # Total read bandwidth from this memory (bytes/s) 5411336Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.data 858187 # Total read bandwidth from this memory (bytes/s) 5511336Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.l2cache.prefetcher 312809 # Total read bandwidth from this memory (bytes/s) 5611336Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.dtb.walker 3243 # Total read bandwidth from this memory (bytes/s) 5711336Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.itb.walker 2783 # Total read bandwidth from this memory (bytes/s) 5811336Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.inst 63391 # Total read bandwidth from this memory (bytes/s) 5911336Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.data 359135 # Total read bandwidth from this memory (bytes/s) 6011336Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.l2cache.prefetcher 319826 # Total read bandwidth from this memory (bytes/s) 6111336Sandreas.hansson@arm.comsystem.physmem.bw_read::realview.ide 9179 # Total read bandwidth from this memory (bytes/s) 6211336Sandreas.hansson@arm.comsystem.physmem.bw_read::total 2106263 # Total read bandwidth from this memory (bytes/s) 6311336Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu0.inst 172615 # Instruction read bandwidth from this memory (bytes/s) 6411336Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu1.inst 63391 # Instruction read bandwidth from this memory (bytes/s) 6511336Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::total 236006 # Instruction read bandwidth from this memory (bytes/s) 6611336Sandreas.hansson@arm.comsystem.physmem.bw_write::writebacks 1671885 # Write bandwidth from this memory (bytes/s) 6711201Sandreas.hansson@arm.comsystem.physmem.bw_write::cpu0.data 434 # Write bandwidth from this memory (bytes/s) 6810636Snilay@cs.wisc.edusystem.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) 6911336Sandreas.hansson@arm.comsystem.physmem.bw_write::total 1672319 # Write bandwidth from this memory (bytes/s) 7011336Sandreas.hansson@arm.comsystem.physmem.bw_total::writebacks 1671885 # Total bandwidth to/from this memory (bytes/s) 7111336Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.dtb.walker 2717 # Total bandwidth to/from this memory (bytes/s) 7211336Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.itb.walker 2377 # Total bandwidth to/from this memory (bytes/s) 7311336Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.inst 172615 # Total bandwidth to/from this memory (bytes/s) 7411336Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.data 858620 # Total bandwidth to/from this memory (bytes/s) 7511336Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.l2cache.prefetcher 312809 # Total bandwidth to/from this memory (bytes/s) 7611336Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.dtb.walker 3243 # Total bandwidth to/from this memory (bytes/s) 7711336Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.itb.walker 2783 # Total bandwidth to/from this memory (bytes/s) 7811336Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.inst 63391 # Total bandwidth to/from this memory (bytes/s) 7911336Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.data 359136 # Total bandwidth to/from this memory (bytes/s) 8011336Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.l2cache.prefetcher 319826 # Total bandwidth to/from this memory (bytes/s) 8111336Sandreas.hansson@arm.comsystem.physmem.bw_total::realview.ide 9179 # Total bandwidth to/from this memory (bytes/s) 8211336Sandreas.hansson@arm.comsystem.physmem.bw_total::total 3778582 # Total bandwidth to/from this memory (bytes/s) 8311336Sandreas.hansson@arm.comsystem.physmem.readReqs 1562015 # Number of read requests accepted 8411336Sandreas.hansson@arm.comsystem.physmem.writeReqs 1242432 # Number of write requests accepted 8511336Sandreas.hansson@arm.comsystem.physmem.readBursts 1562015 # Number of DRAM read bursts, including those serviced by the write queue 8611336Sandreas.hansson@arm.comsystem.physmem.writeBursts 1242432 # Number of DRAM write bursts, including those merged in the write queue 8711336Sandreas.hansson@arm.comsystem.physmem.bytesReadDRAM 99934848 # Total number of bytes read from DRAM 8811336Sandreas.hansson@arm.comsystem.physmem.bytesReadWrQ 34112 # Total number of bytes read from write queue 8911336Sandreas.hansson@arm.comsystem.physmem.bytesWritten 79370432 # Total number of bytes written to DRAM 9011336Sandreas.hansson@arm.comsystem.physmem.bytesReadSys 99967320 # Total read bytes from the system interface side 9111336Sandreas.hansson@arm.comsystem.physmem.bytesWrittenSys 79371496 # Total written bytes from the system interface side 9211336Sandreas.hansson@arm.comsystem.physmem.servicedByWrQ 533 # Number of DRAM read bursts serviced by the write queue 9311201Sandreas.hansson@arm.comsystem.physmem.mergedWrBursts 2246 # Number of DRAM write bursts merged with an existing one 9411336Sandreas.hansson@arm.comsystem.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 9511336Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::0 93757 # Per bank write bursts 9611336Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::1 100629 # Per bank write bursts 9711336Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::2 93977 # Per bank write bursts 9811336Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::3 99615 # Per bank write bursts 9911336Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::4 97211 # Per bank write bursts 10011336Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::5 108899 # Per bank write bursts 10111336Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::6 95410 # Per bank write bursts 10211336Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::7 95079 # Per bank write bursts 10311336Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::8 84413 # Per bank write bursts 10411336Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::9 140545 # Per bank write bursts 10511336Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::10 87149 # Per bank write bursts 10611336Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::11 92128 # Per bank write bursts 10711336Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::12 89605 # Per bank write bursts 10811336Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::13 97795 # Per bank write bursts 10911336Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::14 91413 # Per bank write bursts 11011336Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::15 93857 # Per bank write bursts 11111336Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::0 74634 # Per bank write bursts 11211336Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::1 80843 # Per bank write bursts 11311336Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::2 76779 # Per bank write bursts 11411336Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::3 81501 # Per bank write bursts 11511336Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::4 79021 # Per bank write bursts 11611336Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::5 86869 # Per bank write bursts 11711336Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::6 77167 # Per bank write bursts 11811336Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::7 78926 # Per bank write bursts 11911336Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::8 71646 # Per bank write bursts 12011336Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::9 75252 # Per bank write bursts 12111336Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::10 73334 # Per bank write bursts 12211336Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::11 76259 # Per bank write bursts 12311336Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::12 74746 # Per bank write bursts 12411336Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::13 79667 # Per bank write bursts 12511336Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::14 75302 # Per bank write bursts 12611336Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::15 78217 # Per bank write bursts 12710515SAli.Saidi@ARM.comsystem.physmem.numRdRetry 0 # Number of times read queue was full causing retry 12811336Sandreas.hansson@arm.comsystem.physmem.numWrRetry 64 # Number of times write queue was full causing retry 12911336Sandreas.hansson@arm.comsystem.physmem.totGap 47461932782500 # Total gap between requests 13010515SAli.Saidi@ARM.comsystem.physmem.readPktSize::0 0 # Read request sizes (log2) 13110515SAli.Saidi@ARM.comsystem.physmem.readPktSize::1 0 # Read request sizes (log2) 13210515SAli.Saidi@ARM.comsystem.physmem.readPktSize::2 0 # Read request sizes (log2) 13310827Sandreas.hansson@arm.comsystem.physmem.readPktSize::3 25 # Read request sizes (log2) 13410515SAli.Saidi@ARM.comsystem.physmem.readPktSize::4 5 # Read request sizes (log2) 13510515SAli.Saidi@ARM.comsystem.physmem.readPktSize::5 0 # Read request sizes (log2) 13611336Sandreas.hansson@arm.comsystem.physmem.readPktSize::6 1561985 # Read request sizes (log2) 13710515SAli.Saidi@ARM.comsystem.physmem.writePktSize::0 0 # Write request sizes (log2) 13810515SAli.Saidi@ARM.comsystem.physmem.writePktSize::1 0 # Write request sizes (log2) 13910515SAli.Saidi@ARM.comsystem.physmem.writePktSize::2 2 # Write request sizes (log2) 14010827Sandreas.hansson@arm.comsystem.physmem.writePktSize::3 2572 # Write request sizes (log2) 14110515SAli.Saidi@ARM.comsystem.physmem.writePktSize::4 0 # Write request sizes (log2) 14210515SAli.Saidi@ARM.comsystem.physmem.writePktSize::5 0 # Write request sizes (log2) 14311336Sandreas.hansson@arm.comsystem.physmem.writePktSize::6 1239858 # Write request sizes (log2) 14411336Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::0 973357 # What read queue length does an incoming req see 14511336Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::1 368872 # What read queue length does an incoming req see 14611336Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::2 48939 # What read queue length does an incoming req see 14711336Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::3 35383 # What read queue length does an incoming req see 14811336Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::4 30040 # What read queue length does an incoming req see 14911336Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::5 27781 # What read queue length does an incoming req see 15011336Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::6 24940 # What read queue length does an incoming req see 15111336Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::7 22435 # What read queue length does an incoming req see 15211336Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::8 19175 # What read queue length does an incoming req see 15311336Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::9 4270 # What read queue length does an incoming req see 15411336Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::10 1963 # What read queue length does an incoming req see 15511336Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::11 1251 # What read queue length does an incoming req see 15611336Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::12 910 # What read queue length does an incoming req see 15711336Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::13 672 # What read queue length does an incoming req see 15811336Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::14 409 # What read queue length does an incoming req see 15911336Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::15 353 # What read queue length does an incoming req see 16011336Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::16 290 # What read queue length does an incoming req see 16111336Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::17 241 # What read queue length does an incoming req see 16211336Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::18 109 # What read queue length does an incoming req see 16311336Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::19 70 # What read queue length does an incoming req see 16411336Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::20 9 # What read queue length does an incoming req see 16511336Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::21 7 # What read queue length does an incoming req see 16611336Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::22 3 # What read queue length does an incoming req see 16711336Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::23 2 # What read queue length does an incoming req see 16811336Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::24 1 # What read queue length does an incoming req see 16910515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 17010515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 17110515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 17210515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 17310515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 17410515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 17510515SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 17610515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 17710515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 17810515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 17910515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 18010515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 18110515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 18210515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 18310515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 18410515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 18510515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 18610515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 18710515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 18810515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 18910515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 19010515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 19111336Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::15 20126 # What write queue length does an incoming req see 19211336Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::16 23872 # What write queue length does an incoming req see 19311336Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::17 45415 # What write queue length does an incoming req see 19411336Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::18 56281 # What write queue length does an incoming req see 19511336Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::19 64128 # What write queue length does an incoming req see 19611336Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::20 66477 # What write queue length does an incoming req see 19711336Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::21 70043 # What write queue length does an incoming req see 19811336Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::22 73662 # What write queue length does an incoming req see 19911336Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::23 76578 # What write queue length does an incoming req see 20011336Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::24 77244 # What write queue length does an incoming req see 20111336Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::25 79843 # What write queue length does an incoming req see 20211336Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::26 84567 # What write queue length does an incoming req see 20311336Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::27 82434 # What write queue length does an incoming req see 20411336Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::28 83310 # What write queue length does an incoming req see 20511336Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::29 91239 # What write queue length does an incoming req see 20611336Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::30 81410 # What write queue length does an incoming req see 20711336Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::31 76067 # What write queue length does an incoming req see 20811336Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::32 73611 # What write queue length does an incoming req see 20911336Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::33 3385 # What write queue length does an incoming req see 21011336Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::34 1421 # What write queue length does an incoming req see 21111336Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::35 940 # What write queue length does an incoming req see 21211336Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::36 727 # What write queue length does an incoming req see 21311336Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::37 640 # What write queue length does an incoming req see 21411336Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::38 568 # What write queue length does an incoming req see 21511336Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::39 422 # What write queue length does an incoming req see 21611336Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::40 365 # What write queue length does an incoming req see 21711336Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::41 390 # What write queue length does an incoming req see 21811336Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::42 333 # What write queue length does an incoming req see 21911336Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::43 338 # What write queue length does an incoming req see 22011336Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::44 374 # What write queue length does an incoming req see 22111336Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::45 362 # What write queue length does an incoming req see 22211336Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::46 231 # What write queue length does an incoming req see 22311336Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::47 275 # What write queue length does an incoming req see 22411336Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::48 228 # What write queue length does an incoming req see 22511336Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::49 247 # What write queue length does an incoming req see 22611336Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::50 311 # What write queue length does an incoming req see 22711336Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::51 204 # What write queue length does an incoming req see 22811336Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::52 261 # What write queue length does an incoming req see 22911336Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::53 236 # What write queue length does an incoming req see 23011336Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::54 227 # What write queue length does an incoming req see 23111336Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::55 124 # What write queue length does an incoming req see 23211336Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::56 170 # What write queue length does an incoming req see 23311336Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::57 185 # What write queue length does an incoming req see 23411336Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::58 133 # What write queue length does an incoming req see 23511336Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::59 155 # What write queue length does an incoming req see 23611336Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::60 142 # What write queue length does an incoming req see 23711336Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::61 234 # What write queue length does an incoming req see 23811336Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::62 86 # What write queue length does an incoming req see 23911336Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::63 150 # What write queue length does an incoming req see 24011336Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::samples 991222 # Bytes accessed per row activation 24111336Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::mean 180.892514 # Bytes accessed per row activation 24211336Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::gmean 111.543893 # Bytes accessed per row activation 24311336Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::stdev 240.536828 # Bytes accessed per row activation 24411336Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::0-127 614355 61.98% 61.98% # Bytes accessed per row activation 24511336Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::128-255 184510 18.61% 80.59% # Bytes accessed per row activation 24611336Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::256-383 61267 6.18% 86.77% # Bytes accessed per row activation 24711336Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::384-511 32396 3.27% 90.04% # Bytes accessed per row activation 24811336Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::512-639 21556 2.17% 92.22% # Bytes accessed per row activation 24911336Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::640-767 13955 1.41% 93.63% # Bytes accessed per row activation 25011336Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::768-895 9658 0.97% 94.60% # Bytes accessed per row activation 25111336Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::896-1023 9476 0.96% 95.56% # Bytes accessed per row activation 25211336Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::1024-1151 44049 4.44% 100.00% # Bytes accessed per row activation 25311336Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::total 991222 # Bytes accessed per row activation 25411336Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::samples 69967 # Reads before turning the bus around for writes 25511336Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::mean 22.317164 # Reads before turning the bus around for writes 25611336Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::stdev 326.421262 # Reads before turning the bus around for writes 25711336Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::0-4095 69964 100.00% 100.00% # Reads before turning the bus around for writes 25810892Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::4096-8191 1 0.00% 100.00% # Reads before turning the bus around for writes 25910892Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::24576-28671 1 0.00% 100.00% # Reads before turning the bus around for writes 26011103Snilay@cs.wisc.edusystem.physmem.rdPerTurnAround::81920-86015 1 0.00% 100.00% # Reads before turning the bus around for writes 26111336Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::total 69967 # Reads before turning the bus around for writes 26211336Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::samples 69967 # Writes before turning the bus around for reads 26311336Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::mean 17.724970 # Writes before turning the bus around for reads 26411336Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::gmean 17.179434 # Writes before turning the bus around for reads 26511336Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::stdev 7.169336 # Writes before turning the bus around for reads 26611336Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::16-19 65865 94.14% 94.14% # Writes before turning the bus around for reads 26711336Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::20-23 2036 2.91% 97.05% # Writes before turning the bus around for reads 26811336Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::24-27 254 0.36% 97.41% # Writes before turning the bus around for reads 26911336Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::28-31 187 0.27% 97.68% # Writes before turning the bus around for reads 27011336Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::32-35 141 0.20% 97.88% # Writes before turning the bus around for reads 27111336Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::36-39 122 0.17% 98.05% # Writes before turning the bus around for reads 27211336Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::40-43 214 0.31% 98.36% # Writes before turning the bus around for reads 27311336Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::44-47 78 0.11% 98.47% # Writes before turning the bus around for reads 27411336Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::48-51 271 0.39% 98.86% # Writes before turning the bus around for reads 27511336Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::52-55 64 0.09% 98.95% # Writes before turning the bus around for reads 27611336Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::56-59 34 0.05% 99.00% # Writes before turning the bus around for reads 27711336Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::60-63 49 0.07% 99.07% # Writes before turning the bus around for reads 27811336Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::64-67 243 0.35% 99.42% # Writes before turning the bus around for reads 27911336Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::68-71 32 0.05% 99.46% # Writes before turning the bus around for reads 28011336Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::72-75 40 0.06% 99.52% # Writes before turning the bus around for reads 28111336Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::76-79 104 0.15% 99.67% # Writes before turning the bus around for reads 28211336Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::80-83 171 0.24% 99.91% # Writes before turning the bus around for reads 28311245Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::84-87 3 0.00% 99.92% # Writes before turning the bus around for reads 28411336Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::88-91 3 0.00% 99.92% # Writes before turning the bus around for reads 28511336Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::92-95 3 0.00% 99.92% # Writes before turning the bus around for reads 28611336Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::96-99 1 0.00% 99.93% # Writes before turning the bus around for reads 28711336Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::100-103 3 0.00% 99.93% # Writes before turning the bus around for reads 28811336Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::104-107 1 0.00% 99.93% # Writes before turning the bus around for reads 28911336Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::108-111 1 0.00% 99.93% # Writes before turning the bus around for reads 29011336Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::112-115 3 0.00% 99.94% # Writes before turning the bus around for reads 29111336Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::128-131 14 0.02% 99.96% # Writes before turning the bus around for reads 29211336Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::132-135 3 0.00% 99.96% # Writes before turning the bus around for reads 29311336Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::136-139 1 0.00% 99.96% # Writes before turning the bus around for reads 29411336Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::144-147 14 0.02% 99.98% # Writes before turning the bus around for reads 29511336Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::152-155 1 0.00% 99.98% # Writes before turning the bus around for reads 29611336Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::156-159 2 0.00% 99.99% # Writes before turning the bus around for reads 29711336Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::160-163 2 0.00% 99.99% # Writes before turning the bus around for reads 29811336Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::164-167 1 0.00% 99.99% # Writes before turning the bus around for reads 29911336Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::168-171 1 0.00% 99.99% # Writes before turning the bus around for reads 30011336Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::172-175 1 0.00% 99.99% # Writes before turning the bus around for reads 30111336Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::176-179 2 0.00% 100.00% # Writes before turning the bus around for reads 30211336Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::180-183 1 0.00% 100.00% # Writes before turning the bus around for reads 30311336Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::184-187 1 0.00% 100.00% # Writes before turning the bus around for reads 30411336Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::total 69967 # Writes before turning the bus around for reads 30511336Sandreas.hansson@arm.comsystem.physmem.totQLat 43176438588 # Total ticks spent queuing 30611336Sandreas.hansson@arm.comsystem.physmem.totMemAccLat 72454226088 # Total ticks spent from burst creation until serviced by the DRAM 30711336Sandreas.hansson@arm.comsystem.physmem.totBusLat 7807410000 # Total ticks spent in databus transfers 30811336Sandreas.hansson@arm.comsystem.physmem.avgQLat 27650.94 # Average queueing delay per DRAM burst 30910515SAli.Saidi@ARM.comsystem.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 31011336Sandreas.hansson@arm.comsystem.physmem.avgMemAccLat 46400.94 # Average memory access latency per DRAM burst 31111336Sandreas.hansson@arm.comsystem.physmem.avgRdBW 2.11 # Average DRAM read bandwidth in MiByte/s 31211336Sandreas.hansson@arm.comsystem.physmem.avgWrBW 1.67 # Average achieved write bandwidth in MiByte/s 31311336Sandreas.hansson@arm.comsystem.physmem.avgRdBWSys 2.11 # Average system read bandwidth in MiByte/s 31411336Sandreas.hansson@arm.comsystem.physmem.avgWrBWSys 1.67 # Average system write bandwidth in MiByte/s 31510515SAli.Saidi@ARM.comsystem.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 31611245Sandreas.sandberg@arm.comsystem.physmem.busUtil 0.03 # Data bus utilization in percentage 31711336Sandreas.hansson@arm.comsystem.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads 31810892Sandreas.hansson@arm.comsystem.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes 31911336Sandreas.hansson@arm.comsystem.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing 32011336Sandreas.hansson@arm.comsystem.physmem.avgWrQLen 25.42 # Average write queue length when enqueuing 32111336Sandreas.hansson@arm.comsystem.physmem.readRowHits 1247973 # Number of row buffer hits during reads 32211336Sandreas.hansson@arm.comsystem.physmem.writeRowHits 562447 # Number of row buffer hits during writes 32311336Sandreas.hansson@arm.comsystem.physmem.readRowHitRate 79.92 # Row buffer hit rate for reads 32411336Sandreas.hansson@arm.comsystem.physmem.writeRowHitRate 45.35 # Row buffer hit rate for writes 32511336Sandreas.hansson@arm.comsystem.physmem.avgGap 16923811.64 # Average gap between requests 32611336Sandreas.hansson@arm.comsystem.physmem.pageHitRate 64.62 # Row buffer hit rate, read and write combined 32711336Sandreas.hansson@arm.comsystem.physmem_0.actEnergy 3897081720 # Energy for activate commands per rank (pJ) 32811336Sandreas.hansson@arm.comsystem.physmem_0.preEnergy 2126383875 # Energy for precharge commands per rank (pJ) 32911336Sandreas.hansson@arm.comsystem.physmem_0.readEnergy 6119692800 # Energy for read commands per rank (pJ) 33011336Sandreas.hansson@arm.comsystem.physmem_0.writeEnergy 4119595200 # Energy for write commands per rank (pJ) 33111336Sandreas.hansson@arm.comsystem.physmem_0.refreshEnergy 3099982404480 # Energy for refresh commands per rank (pJ) 33211336Sandreas.hansson@arm.comsystem.physmem_0.actBackEnergy 1216381568355 # Energy for active background per rank (pJ) 33311336Sandreas.hansson@arm.comsystem.physmem_0.preBackEnergy 27410155454250 # Energy for precharge background per rank (pJ) 33411336Sandreas.hansson@arm.comsystem.physmem_0.totalEnergy 31742782180680 # Total energy per rank (pJ) 33511336Sandreas.hansson@arm.comsystem.physmem_0.averagePower 668.805156 # Core power per rank (mW) 33611336Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::IDLE 45598728268843 # Time in different power states 33711336Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::REF 1584858080000 # Time in different power states 33810628Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 33911336Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::ACT 278346651157 # Time in different power states 34010628Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 34111336Sandreas.hansson@arm.comsystem.physmem_1.actEnergy 3596556600 # Energy for activate commands per rank (pJ) 34211336Sandreas.hansson@arm.comsystem.physmem_1.preEnergy 1962406875 # Energy for precharge commands per rank (pJ) 34311336Sandreas.hansson@arm.comsystem.physmem_1.readEnergy 6059788800 # Energy for read commands per rank (pJ) 34411336Sandreas.hansson@arm.comsystem.physmem_1.writeEnergy 3916661040 # Energy for write commands per rank (pJ) 34511336Sandreas.hansson@arm.comsystem.physmem_1.refreshEnergy 3099982404480 # Energy for refresh commands per rank (pJ) 34611336Sandreas.hansson@arm.comsystem.physmem_1.actBackEnergy 1207691479170 # Energy for active background per rank (pJ) 34711336Sandreas.hansson@arm.comsystem.physmem_1.preBackEnergy 27417778331250 # Energy for precharge background per rank (pJ) 34811336Sandreas.hansson@arm.comsystem.physmem_1.totalEnergy 31740987628215 # Total energy per rank (pJ) 34911336Sandreas.hansson@arm.comsystem.physmem_1.averagePower 668.767346 # Core power per rank (mW) 35011336Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::IDLE 45611421903472 # Time in different power states 35111336Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::REF 1584858080000 # Time in different power states 35210628Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 35311336Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::ACT 265649419028 # Time in different power states 35410628Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 35510636Snilay@cs.wisc.edusystem.realview.nvmem.bytes_read::cpu0.inst 704 # Number of bytes read from this memory 35610636Snilay@cs.wisc.edusystem.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory 35710636Snilay@cs.wisc.edusystem.realview.nvmem.bytes_read::cpu1.inst 576 # Number of bytes read from this memory 35810636Snilay@cs.wisc.edusystem.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory 35910515SAli.Saidi@ARM.comsystem.realview.nvmem.bytes_read::total 1324 # Number of bytes read from this memory 36010515SAli.Saidi@ARM.comsystem.realview.nvmem.bytes_inst_read::cpu0.inst 704 # Number of instructions bytes read from this memory 36110515SAli.Saidi@ARM.comsystem.realview.nvmem.bytes_inst_read::cpu1.inst 576 # Number of instructions bytes read from this memory 36210515SAli.Saidi@ARM.comsystem.realview.nvmem.bytes_inst_read::total 1280 # Number of instructions bytes read from this memory 36310636Snilay@cs.wisc.edusystem.realview.nvmem.num_reads::cpu0.inst 11 # Number of read requests responded to by this memory 36410636Snilay@cs.wisc.edusystem.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory 36510636Snilay@cs.wisc.edusystem.realview.nvmem.num_reads::cpu1.inst 9 # Number of read requests responded to by this memory 36610636Snilay@cs.wisc.edusystem.realview.nvmem.num_reads::cpu1.data 1 # Number of read requests responded to by this memory 36710515SAli.Saidi@ARM.comsystem.realview.nvmem.num_reads::total 26 # Number of read requests responded to by this memory 36810636Snilay@cs.wisc.edusystem.realview.nvmem.bw_read::cpu0.inst 15 # Total read bandwidth from this memory (bytes/s) 36910636Snilay@cs.wisc.edusystem.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s) 37010515SAli.Saidi@ARM.comsystem.realview.nvmem.bw_read::cpu1.inst 12 # Total read bandwidth from this memory (bytes/s) 37110636Snilay@cs.wisc.edusystem.realview.nvmem.bw_read::cpu1.data 0 # Total read bandwidth from this memory (bytes/s) 37210515SAli.Saidi@ARM.comsystem.realview.nvmem.bw_read::total 28 # Total read bandwidth from this memory (bytes/s) 37310515SAli.Saidi@ARM.comsystem.realview.nvmem.bw_inst_read::cpu0.inst 15 # Instruction read bandwidth from this memory (bytes/s) 37410515SAli.Saidi@ARM.comsystem.realview.nvmem.bw_inst_read::cpu1.inst 12 # Instruction read bandwidth from this memory (bytes/s) 37510515SAli.Saidi@ARM.comsystem.realview.nvmem.bw_inst_read::total 27 # Instruction read bandwidth from this memory (bytes/s) 37610636Snilay@cs.wisc.edusystem.realview.nvmem.bw_total::cpu0.inst 15 # Total bandwidth to/from this memory (bytes/s) 37710636Snilay@cs.wisc.edusystem.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s) 37810515SAli.Saidi@ARM.comsystem.realview.nvmem.bw_total::cpu1.inst 12 # Total bandwidth to/from this memory (bytes/s) 37910636Snilay@cs.wisc.edusystem.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) 38010515SAli.Saidi@ARM.comsystem.realview.nvmem.bw_total::total 28 # Total bandwidth to/from this memory (bytes/s) 38110585Sandreas.hansson@arm.comsystem.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 38210585Sandreas.hansson@arm.comsystem.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 38310585Sandreas.hansson@arm.comsystem.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 38411201Sandreas.hansson@arm.comsystem.cf0.dma_write_full_pages 1671 # Number of full page size DMA writes. 38511201Sandreas.hansson@arm.comsystem.cf0.dma_write_bytes 6846976 # Number of bytes transfered via DMA writes. 38611201Sandreas.hansson@arm.comsystem.cf0.dma_write_txs 1674 # Number of DMA write transactions. 38711336Sandreas.hansson@arm.comsystem.cpu0.branchPred.lookups 141158417 # Number of BP lookups 38811336Sandreas.hansson@arm.comsystem.cpu0.branchPred.condPredicted 100207840 # Number of conditional branches predicted 38911336Sandreas.hansson@arm.comsystem.cpu0.branchPred.condIncorrect 6289341 # Number of conditional branches incorrect 39011336Sandreas.hansson@arm.comsystem.cpu0.branchPred.BTBLookups 105574499 # Number of BTB lookups 39111336Sandreas.hansson@arm.comsystem.cpu0.branchPred.BTBHits 76948344 # Number of BTB hits 39210585Sandreas.hansson@arm.comsystem.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 39311336Sandreas.hansson@arm.comsystem.cpu0.branchPred.BTBHitPct 72.885351 # BTB Hit Percentage 39411336Sandreas.hansson@arm.comsystem.cpu0.branchPred.usedRAS 16552897 # Number of times the RAS was used to get a target. 39511336Sandreas.hansson@arm.comsystem.cpu0.branchPred.RASInCorrect 1094870 # Number of incorrect RAS predictions. 39610515SAli.Saidi@ARM.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 39710628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 39810628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 39910628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 40010628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 40110628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 40210628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 40310628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 40410628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 40510585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 40610585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 40710585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 40810585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 40910585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 41010585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 41110585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 41210585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 41310585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 41410585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 41510585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 41610585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 41710585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 41810585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 41910585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 42010585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 42110585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 42210585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 42310585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 42410585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 42510585Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 42611336Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walks 283140 # Table walker walks requested 42711336Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksLong 283140 # Table walker walks initiated with long descriptors 42811336Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksLongTerminationLevel::Level2 9717 # Level at which table walker walks with long descriptors terminate 42911336Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksLongTerminationLevel::Level3 79661 # Level at which table walker walks with long descriptors terminate 43011336Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkWaitTime::samples 283140 # Table walker wait (enqueue to first request) latency 43111336Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkWaitTime::0 283140 100.00% 100.00% # Table walker wait (enqueue to first request) latency 43211336Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkWaitTime::total 283140 # Table walker wait (enqueue to first request) latency 43311336Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::samples 89378 # Table walker service (enqueue to completion) latency 43411336Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::mean 23531.797534 # Table walker service (enqueue to completion) latency 43511336Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::gmean 21398.159545 # Table walker service (enqueue to completion) latency 43611336Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::stdev 20518.573843 # Table walker service (enqueue to completion) latency 43711336Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::0-65535 88174 98.65% 98.65% # Table walker service (enqueue to completion) latency 43811336Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::65536-131071 214 0.24% 98.89% # Table walker service (enqueue to completion) latency 43911336Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::131072-196607 839 0.94% 99.83% # Table walker service (enqueue to completion) latency 44011336Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::196608-262143 33 0.04% 99.87% # Table walker service (enqueue to completion) latency 44111336Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::262144-327679 38 0.04% 99.91% # Table walker service (enqueue to completion) latency 44211336Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::327680-393215 25 0.03% 99.94% # Table walker service (enqueue to completion) latency 44311336Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::393216-458751 35 0.04% 99.98% # Table walker service (enqueue to completion) latency 44411336Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::458752-524287 10 0.01% 99.99% # Table walker service (enqueue to completion) latency 44511336Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::524288-589823 8 0.01% 100.00% # Table walker service (enqueue to completion) latency 44611245Sandreas.sandberg@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 44711245Sandreas.sandberg@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::720896-786431 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 44811336Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::total 89378 # Table walker service (enqueue to completion) latency 44911201Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksPending::samples -909613592 # Table walker pending requests distribution 45011201Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksPending::0 -909613592 100.00% 100.00% # Table walker pending requests distribution 45111201Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksPending::total -909613592 # Table walker pending requests distribution 45211336Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkPageSizes::4K 79661 89.13% 89.13% # Table walker page sizes translated 45311336Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkPageSizes::2M 9717 10.87% 100.00% # Table walker page sizes translated 45411336Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkPageSizes::total 89378 # Table walker page sizes translated 45511336Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 283140 # Table walker requests started/completed, data/inst 45610628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 45711336Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Requested::total 283140 # Table walker requests started/completed, data/inst 45811336Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 89378 # Table walker requests started/completed, data/inst 45910628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 46011336Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Completed::total 89378 # Table walker requests started/completed, data/inst 46111336Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin::total 372518 # Table walker requests started/completed, data/inst 46210585Sandreas.hansson@arm.comsystem.cpu0.dtb.inst_hits 0 # ITB inst hits 46310585Sandreas.hansson@arm.comsystem.cpu0.dtb.inst_misses 0 # ITB inst misses 46411336Sandreas.hansson@arm.comsystem.cpu0.dtb.read_hits 90921588 # DTB read hits 46511336Sandreas.hansson@arm.comsystem.cpu0.dtb.read_misses 233548 # DTB read misses 46611336Sandreas.hansson@arm.comsystem.cpu0.dtb.write_hits 80603054 # DTB write hits 46711336Sandreas.hansson@arm.comsystem.cpu0.dtb.write_misses 49592 # DTB write misses 46810585Sandreas.hansson@arm.comsystem.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed 46910585Sandreas.hansson@arm.comsystem.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 47011336Sandreas.hansson@arm.comsystem.cpu0.dtb.flush_tlb_mva_asid 42784 # Number of times TLB was flushed by MVA & ASID 47111336Sandreas.hansson@arm.comsystem.cpu0.dtb.flush_tlb_asid 1060 # Number of times TLB was flushed by ASID 47211336Sandreas.hansson@arm.comsystem.cpu0.dtb.flush_entries 38267 # Number of entries that have been flushed from TLB 47311336Sandreas.hansson@arm.comsystem.cpu0.dtb.align_faults 2134 # Number of TLB faults due to alignment restrictions 47411336Sandreas.hansson@arm.comsystem.cpu0.dtb.prefetch_faults 9015 # Number of TLB faults due to prefetch 47510585Sandreas.hansson@arm.comsystem.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 47611336Sandreas.hansson@arm.comsystem.cpu0.dtb.perms_faults 11497 # Number of TLB faults due to permissions restrictions 47711336Sandreas.hansson@arm.comsystem.cpu0.dtb.read_accesses 91155136 # DTB read accesses 47811336Sandreas.hansson@arm.comsystem.cpu0.dtb.write_accesses 80652646 # DTB write accesses 47910585Sandreas.hansson@arm.comsystem.cpu0.dtb.inst_accesses 0 # ITB inst accesses 48011336Sandreas.hansson@arm.comsystem.cpu0.dtb.hits 171524642 # DTB hits 48111336Sandreas.hansson@arm.comsystem.cpu0.dtb.misses 283140 # DTB misses 48211336Sandreas.hansson@arm.comsystem.cpu0.dtb.accesses 171807782 # DTB accesses 48310628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 48410628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 48510628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 48610628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 48710628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 48810628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 48910628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 49010628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 49110585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 49210585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 49310585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 49410585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 49510585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 49610585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 49710585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 49810585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 49910585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 50010585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 50110585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 50210585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 50310585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 50410585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 50510585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 50610585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 50710585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 50810585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 50910585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 51010585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 51110585Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 51211336Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walks 66290 # Table walker walks requested 51311336Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walksLong 66290 # Table walker walks initiated with long descriptors 51411336Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walksLongTerminationLevel::Level2 665 # Level at which table walker walks with long descriptors terminate 51511336Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walksLongTerminationLevel::Level3 56612 # Level at which table walker walks with long descriptors terminate 51611336Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkWaitTime::samples 66290 # Table walker wait (enqueue to first request) latency 51711336Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkWaitTime::0 66290 100.00% 100.00% # Table walker wait (enqueue to first request) latency 51811336Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkWaitTime::total 66290 # Table walker wait (enqueue to first request) latency 51911336Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::samples 57277 # Table walker service (enqueue to completion) latency 52011336Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::mean 26707.997975 # Table walker service (enqueue to completion) latency 52111336Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::gmean 23913.035188 # Table walker service (enqueue to completion) latency 52211336Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::stdev 23204.196076 # Table walker service (enqueue to completion) latency 52311336Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::0-65535 56118 97.98% 97.98% # Table walker service (enqueue to completion) latency 52411336Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::65536-131071 13 0.02% 98.00% # Table walker service (enqueue to completion) latency 52511336Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::131072-196607 1037 1.81% 99.81% # Table walker service (enqueue to completion) latency 52611336Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::196608-262143 26 0.05% 99.86% # Table walker service (enqueue to completion) latency 52711336Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::262144-327679 46 0.08% 99.94% # Table walker service (enqueue to completion) latency 52811336Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::327680-393215 23 0.04% 99.98% # Table walker service (enqueue to completion) latency 52911336Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::393216-458751 11 0.02% 99.99% # Table walker service (enqueue to completion) latency 53011336Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::458752-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 53111336Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 53211336Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::total 57277 # Table walker service (enqueue to completion) latency 53311201Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walksPending::samples -910742092 # Table walker pending requests distribution 53411201Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walksPending::0 -910742092 100.00% 100.00% # Table walker pending requests distribution 53511201Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walksPending::total -910742092 # Table walker pending requests distribution 53611336Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkPageSizes::4K 56612 98.84% 98.84% # Table walker page sizes translated 53711336Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkPageSizes::2M 665 1.16% 100.00% # Table walker page sizes translated 53811336Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkPageSizes::total 57277 # Table walker page sizes translated 53910628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 54011336Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 66290 # Table walker requests started/completed, data/inst 54111336Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Requested::total 66290 # Table walker requests started/completed, data/inst 54210628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 54311336Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 57277 # Table walker requests started/completed, data/inst 54411336Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Completed::total 57277 # Table walker requests started/completed, data/inst 54511336Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin::total 123567 # Table walker requests started/completed, data/inst 54611336Sandreas.hansson@arm.comsystem.cpu0.itb.inst_hits 252665762 # ITB inst hits 54711336Sandreas.hansson@arm.comsystem.cpu0.itb.inst_misses 66290 # ITB inst misses 54810585Sandreas.hansson@arm.comsystem.cpu0.itb.read_hits 0 # DTB read hits 54910585Sandreas.hansson@arm.comsystem.cpu0.itb.read_misses 0 # DTB read misses 55010585Sandreas.hansson@arm.comsystem.cpu0.itb.write_hits 0 # DTB write hits 55110585Sandreas.hansson@arm.comsystem.cpu0.itb.write_misses 0 # DTB write misses 55210585Sandreas.hansson@arm.comsystem.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed 55310585Sandreas.hansson@arm.comsystem.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 55411336Sandreas.hansson@arm.comsystem.cpu0.itb.flush_tlb_mva_asid 42784 # Number of times TLB was flushed by MVA & ASID 55511336Sandreas.hansson@arm.comsystem.cpu0.itb.flush_tlb_asid 1060 # Number of times TLB was flushed by ASID 55611336Sandreas.hansson@arm.comsystem.cpu0.itb.flush_entries 27416 # Number of entries that have been flushed from TLB 55710585Sandreas.hansson@arm.comsystem.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 55810585Sandreas.hansson@arm.comsystem.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 55910585Sandreas.hansson@arm.comsystem.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 56011336Sandreas.hansson@arm.comsystem.cpu0.itb.perms_faults 203450 # Number of TLB faults due to permissions restrictions 56110585Sandreas.hansson@arm.comsystem.cpu0.itb.read_accesses 0 # DTB read accesses 56210585Sandreas.hansson@arm.comsystem.cpu0.itb.write_accesses 0 # DTB write accesses 56311336Sandreas.hansson@arm.comsystem.cpu0.itb.inst_accesses 252732052 # ITB inst accesses 56411336Sandreas.hansson@arm.comsystem.cpu0.itb.hits 252665762 # DTB hits 56511336Sandreas.hansson@arm.comsystem.cpu0.itb.misses 66290 # DTB misses 56611336Sandreas.hansson@arm.comsystem.cpu0.itb.accesses 252732052 # DTB accesses 56711336Sandreas.hansson@arm.comsystem.cpu0.numCycles 1081051562 # number of cpu cycles simulated 56810585Sandreas.hansson@arm.comsystem.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 56910585Sandreas.hansson@arm.comsystem.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 57011336Sandreas.hansson@arm.comsystem.cpu0.committedInsts 468741146 # Number of instructions committed 57111336Sandreas.hansson@arm.comsystem.cpu0.committedOps 550955855 # Number of ops (including micro ops) committed 57211336Sandreas.hansson@arm.comsystem.cpu0.discardedOps 47157402 # Number of ops (including micro ops) which were discarded before commit 57311336Sandreas.hansson@arm.comsystem.cpu0.numFetchSuspends 5078 # Number of times Execute suspended instruction fetching 57411336Sandreas.hansson@arm.comsystem.cpu0.quiesceCycles 93843643871 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 57511336Sandreas.hansson@arm.comsystem.cpu0.cpi 2.306287 # CPI: cycles per instruction 57611336Sandreas.hansson@arm.comsystem.cpu0.ipc 0.433597 # IPC: instructions per cycle 57710585Sandreas.hansson@arm.comsystem.cpu0.kern.inst.arm 0 # number of arm instructions executed 57811336Sandreas.hansson@arm.comsystem.cpu0.kern.inst.quiesce 5324 # number of quiesce instructions executed 57911336Sandreas.hansson@arm.comsystem.cpu0.tickCycles 755067683 # Number of cycles that the object actually ticked 58011336Sandreas.hansson@arm.comsystem.cpu0.idleCycles 325983879 # Total number of cycles that the object has spent stopped 58111336Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.replacements 5850262 # number of replacements 58211336Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.tagsinuse 501.214442 # Cycle average of tags in use 58311336Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.total_refs 162710873 # Total number of references to valid blocks. 58411336Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.sampled_refs 5850774 # Sample count of references to valid blocks. 58511336Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.avg_refs 27.810145 # Average number of references to valid blocks. 58611201Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.warmup_cycle 7690769000 # Cycle when the warmup percentage was hit. 58711336Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_blocks::cpu0.data 501.214442 # Average occupied blocks per requestor 58811336Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_percent::cpu0.data 0.978934 # Average percentage of cache occupancy 58911336Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_percent::total 0.978934 # Average percentage of cache occupancy 59011336Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 59111336Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::0 158 # Occupied blocks per task id 59211336Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::1 332 # Occupied blocks per task id 59311336Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::2 22 # Occupied blocks per task id 59411336Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 59511336Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.tag_accesses 346062459 # Number of tag accesses 59611336Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.data_accesses 346062459 # Number of data accesses 59711336Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_hits::cpu0.data 83268986 # number of ReadReq hits 59811336Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_hits::total 83268986 # number of ReadReq hits 59911336Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_hits::cpu0.data 74755135 # number of WriteReq hits 60011336Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_hits::total 74755135 # number of WriteReq hits 60111336Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_hits::cpu0.data 273368 # number of SoftPFReq hits 60211336Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_hits::total 273368 # number of SoftPFReq hits 60311336Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_hits::cpu0.data 183787 # number of WriteLineReq hits 60411336Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_hits::total 183787 # number of WriteLineReq hits 60511336Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1841830 # number of LoadLockedReq hits 60611336Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_hits::total 1841830 # number of LoadLockedReq hits 60711336Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_hits::cpu0.data 1806426 # number of StoreCondReq hits 60811336Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_hits::total 1806426 # number of StoreCondReq hits 60911336Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_hits::cpu0.data 158024121 # number of demand (read+write) hits 61011336Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_hits::total 158024121 # number of demand (read+write) hits 61111336Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_hits::cpu0.data 158297489 # number of overall hits 61211336Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_hits::total 158297489 # number of overall hits 61311336Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_misses::cpu0.data 3569470 # number of ReadReq misses 61411336Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_misses::total 3569470 # number of ReadReq misses 61511336Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_misses::cpu0.data 2481271 # number of WriteReq misses 61611336Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_misses::total 2481271 # number of WriteReq misses 61711336Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_misses::cpu0.data 690957 # number of SoftPFReq misses 61811336Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_misses::total 690957 # number of SoftPFReq misses 61911336Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_misses::cpu0.data 806074 # number of WriteLineReq misses 62011336Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_misses::total 806074 # number of WriteLineReq misses 62111336Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_misses::cpu0.data 173924 # number of LoadLockedReq misses 62211336Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_misses::total 173924 # number of LoadLockedReq misses 62311336Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_misses::cpu0.data 207838 # number of StoreCondReq misses 62411336Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_misses::total 207838 # number of StoreCondReq misses 62511336Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_misses::cpu0.data 6050741 # number of demand (read+write) misses 62611336Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_misses::total 6050741 # number of demand (read+write) misses 62711336Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_misses::cpu0.data 6741698 # number of overall misses 62811336Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_misses::total 6741698 # number of overall misses 62911336Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_miss_latency::cpu0.data 62945089000 # number of ReadReq miss cycles 63011336Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_miss_latency::total 62945089000 # number of ReadReq miss cycles 63111336Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_latency::cpu0.data 62898003000 # number of WriteReq miss cycles 63211336Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_latency::total 62898003000 # number of WriteReq miss cycles 63311336Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 71296883500 # number of WriteLineReq miss cycles 63411336Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_miss_latency::total 71296883500 # number of WriteLineReq miss cycles 63511336Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2825966000 # number of LoadLockedReq miss cycles 63611336Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_latency::total 2825966000 # number of LoadLockedReq miss cycles 63711336Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 5775275000 # number of StoreCondReq miss cycles 63811336Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_miss_latency::total 5775275000 # number of StoreCondReq miss cycles 63911336Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 4714000 # number of StoreCondFailReq miss cycles 64011336Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondFailReq_miss_latency::total 4714000 # number of StoreCondFailReq miss cycles 64111336Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_latency::cpu0.data 125843092000 # number of demand (read+write) miss cycles 64211336Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_latency::total 125843092000 # number of demand (read+write) miss cycles 64311336Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_latency::cpu0.data 125843092000 # number of overall miss cycles 64411336Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_latency::total 125843092000 # number of overall miss cycles 64511336Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_accesses::cpu0.data 86838456 # number of ReadReq accesses(hits+misses) 64611336Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_accesses::total 86838456 # number of ReadReq accesses(hits+misses) 64711336Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_accesses::cpu0.data 77236406 # number of WriteReq accesses(hits+misses) 64811336Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_accesses::total 77236406 # number of WriteReq accesses(hits+misses) 64911336Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_accesses::cpu0.data 964325 # number of SoftPFReq accesses(hits+misses) 65011336Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_accesses::total 964325 # number of SoftPFReq accesses(hits+misses) 65111336Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_accesses::cpu0.data 989861 # number of WriteLineReq accesses(hits+misses) 65211336Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_accesses::total 989861 # number of WriteLineReq accesses(hits+misses) 65311336Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2015754 # number of LoadLockedReq accesses(hits+misses) 65411336Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_accesses::total 2015754 # number of LoadLockedReq accesses(hits+misses) 65511336Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2014264 # number of StoreCondReq accesses(hits+misses) 65611336Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_accesses::total 2014264 # number of StoreCondReq accesses(hits+misses) 65711336Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_accesses::cpu0.data 164074862 # number of demand (read+write) accesses 65811336Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_accesses::total 164074862 # number of demand (read+write) accesses 65911336Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_accesses::cpu0.data 165039187 # number of overall (read+write) accesses 66011336Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_accesses::total 165039187 # number of overall (read+write) accesses 66111336Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.041105 # miss rate for ReadReq accesses 66211336Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_miss_rate::total 0.041105 # miss rate for ReadReq accesses 66311336Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.032126 # miss rate for WriteReq accesses 66411336Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_rate::total 0.032126 # miss rate for WriteReq accesses 66511336Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.716519 # miss rate for SoftPFReq accesses 66611336Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_miss_rate::total 0.716519 # miss rate for SoftPFReq accesses 66711336Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.814330 # miss rate for WriteLineReq accesses 66811336Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_miss_rate::total 0.814330 # miss rate for WriteLineReq accesses 66911336Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.086282 # miss rate for LoadLockedReq accesses 67011336Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_rate::total 0.086282 # miss rate for LoadLockedReq accesses 67111336Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.103183 # miss rate for StoreCondReq accesses 67211336Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_miss_rate::total 0.103183 # miss rate for StoreCondReq accesses 67311336Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_rate::cpu0.data 0.036878 # miss rate for demand accesses 67411336Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_rate::total 0.036878 # miss rate for demand accesses 67511336Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_rate::cpu0.data 0.040849 # miss rate for overall accesses 67611336Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_rate::total 0.040849 # miss rate for overall accesses 67711336Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 17634.295568 # average ReadReq miss latency 67811336Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_avg_miss_latency::total 17634.295568 # average ReadReq miss latency 67911336Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 25349.106567 # average WriteReq miss latency 68011336Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_avg_miss_latency::total 25349.106567 # average WriteReq miss latency 68111336Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 88449.551158 # average WriteLineReq miss latency 68211336Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_avg_miss_latency::total 88449.551158 # average WriteLineReq miss latency 68311336Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16248.280858 # average LoadLockedReq miss latency 68411336Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16248.280858 # average LoadLockedReq miss latency 68511336Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 27787.387292 # average StoreCondReq miss latency 68611336Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_avg_miss_latency::total 27787.387292 # average StoreCondReq miss latency 68710636Snilay@cs.wisc.edusystem.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency 68810585Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 68911336Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_avg_miss_latency::cpu0.data 20797.963754 # average overall miss latency 69011336Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_avg_miss_latency::total 20797.963754 # average overall miss latency 69111336Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_avg_miss_latency::cpu0.data 18666.379301 # average overall miss latency 69211336Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_avg_miss_latency::total 18666.379301 # average overall miss latency 69310585Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 69410585Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 69510585Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 69610585Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 69710585Sandreas.hansson@arm.comsystem.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 69810585Sandreas.hansson@arm.comsystem.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 69910585Sandreas.hansson@arm.comsystem.cpu0.dcache.fast_writes 0 # number of fast writes performed 70010585Sandreas.hansson@arm.comsystem.cpu0.dcache.cache_copies 0 # number of cache copies performed 70111336Sandreas.hansson@arm.comsystem.cpu0.dcache.writebacks::writebacks 5850286 # number of writebacks 70211336Sandreas.hansson@arm.comsystem.cpu0.dcache.writebacks::total 5850286 # number of writebacks 70311336Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 444097 # number of ReadReq MSHR hits 70411336Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_hits::total 444097 # number of ReadReq MSHR hits 70511336Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1026850 # number of WriteReq MSHR hits 70611336Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_hits::total 1026850 # number of WriteReq MSHR hits 70711336Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 104 # number of WriteLineReq MSHR hits 70811336Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_hits::total 104 # number of WriteLineReq MSHR hits 70911336Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 44524 # number of LoadLockedReq MSHR hits 71011336Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_hits::total 44524 # number of LoadLockedReq MSHR hits 71111336Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data 32 # number of StoreCondReq MSHR hits 71211336Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_hits::total 32 # number of StoreCondReq MSHR hits 71311336Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_hits::cpu0.data 1470947 # number of demand (read+write) MSHR hits 71411336Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_hits::total 1470947 # number of demand (read+write) MSHR hits 71511336Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_hits::cpu0.data 1470947 # number of overall MSHR hits 71611336Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_hits::total 1470947 # number of overall MSHR hits 71711336Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3125373 # number of ReadReq MSHR misses 71811336Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_misses::total 3125373 # number of ReadReq MSHR misses 71911336Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1454421 # number of WriteReq MSHR misses 72011336Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_misses::total 1454421 # number of WriteReq MSHR misses 72111336Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 689314 # number of SoftPFReq MSHR misses 72211336Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_mshr_misses::total 689314 # number of SoftPFReq MSHR misses 72311336Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 805970 # number of WriteLineReq MSHR misses 72411336Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_misses::total 805970 # number of WriteLineReq MSHR misses 72511336Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 129400 # number of LoadLockedReq MSHR misses 72611336Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_misses::total 129400 # number of LoadLockedReq MSHR misses 72711336Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 207806 # number of StoreCondReq MSHR misses 72811336Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_misses::total 207806 # number of StoreCondReq MSHR misses 72911336Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_misses::cpu0.data 4579794 # number of demand (read+write) MSHR misses 73011336Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_misses::total 4579794 # number of demand (read+write) MSHR misses 73111336Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_misses::cpu0.data 5269108 # number of overall MSHR misses 73211336Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_misses::total 5269108 # number of overall MSHR misses 73311336Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 19530 # number of ReadReq MSHR uncacheable 73411336Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_uncacheable::total 19530 # number of ReadReq MSHR uncacheable 73511336Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 21048 # number of WriteReq MSHR uncacheable 73611336Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_uncacheable::total 21048 # number of WriteReq MSHR uncacheable 73711336Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 40578 # number of overall MSHR uncacheable misses 73811336Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_uncacheable_misses::total 40578 # number of overall MSHR uncacheable misses 73911336Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 49230560000 # number of ReadReq MSHR miss cycles 74011336Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_miss_latency::total 49230560000 # number of ReadReq MSHR miss cycles 74111336Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 36276054500 # number of WriteReq MSHR miss cycles 74211336Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_miss_latency::total 36276054500 # number of WriteReq MSHR miss cycles 74311336Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 18434925500 # number of SoftPFReq MSHR miss cycles 74411336Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 18434925500 # number of SoftPFReq MSHR miss cycles 74511336Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 70481228500 # number of WriteLineReq MSHR miss cycles 74611336Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 70481228500 # number of WriteLineReq MSHR miss cycles 74711336Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1893845500 # number of LoadLockedReq MSHR miss cycles 74811336Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1893845500 # number of LoadLockedReq MSHR miss cycles 74911336Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 5565229000 # number of StoreCondReq MSHR miss cycles 75011336Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 5565229000 # number of StoreCondReq MSHR miss cycles 75111336Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 4561000 # number of StoreCondFailReq MSHR miss cycles 75211336Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 4561000 # number of StoreCondFailReq MSHR miss cycles 75311336Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 85506614500 # number of demand (read+write) MSHR miss cycles 75411336Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_miss_latency::total 85506614500 # number of demand (read+write) MSHR miss cycles 75511336Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 103941540000 # number of overall MSHR miss cycles 75611336Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_miss_latency::total 103941540000 # number of overall MSHR miss cycles 75711336Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3800939500 # number of ReadReq MSHR uncacheable cycles 75811336Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 3800939500 # number of ReadReq MSHR uncacheable cycles 75911336Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 3971667500 # number of WriteReq MSHR uncacheable cycles 76011336Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 3971667500 # number of WriteReq MSHR uncacheable cycles 76111336Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 7772607000 # number of overall MSHR uncacheable cycles 76211336Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_uncacheable_latency::total 7772607000 # number of overall MSHR uncacheable cycles 76311336Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.035991 # mshr miss rate for ReadReq accesses 76411336Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.035991 # mshr miss rate for ReadReq accesses 76511336Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018831 # mshr miss rate for WriteReq accesses 76611336Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018831 # mshr miss rate for WriteReq accesses 76711336Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.714815 # mshr miss rate for SoftPFReq accesses 76811336Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.714815 # mshr miss rate for SoftPFReq accesses 76911336Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.814225 # mshr miss rate for WriteLineReq accesses 77011336Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.814225 # mshr miss rate for WriteLineReq accesses 77111336Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.064194 # mshr miss rate for LoadLockedReq accesses 77211336Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.064194 # mshr miss rate for LoadLockedReq accesses 77311336Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.103167 # mshr miss rate for StoreCondReq accesses 77411336Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.103167 # mshr miss rate for StoreCondReq accesses 77511336Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027913 # mshr miss rate for demand accesses 77611336Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_miss_rate::total 0.027913 # mshr miss rate for demand accesses 77711336Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.031926 # mshr miss rate for overall accesses 77811336Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_miss_rate::total 0.031926 # mshr miss rate for overall accesses 77911336Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15751.899053 # average ReadReq mshr miss latency 78011336Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15751.899053 # average ReadReq mshr miss latency 78111336Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 24941.921562 # average WriteReq mshr miss latency 78211336Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 24941.921562 # average WriteReq mshr miss latency 78311336Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 26743.872169 # average SoftPFReq mshr miss latency 78411336Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 26743.872169 # average SoftPFReq mshr miss latency 78511336Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 87448.947852 # average WriteLineReq mshr miss latency 78611336Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 87448.947852 # average WriteLineReq mshr miss latency 78711336Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14635.591190 # average LoadLockedReq mshr miss latency 78811336Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14635.591190 # average LoadLockedReq mshr miss latency 78911336Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 26780.886981 # average StoreCondReq mshr miss latency 79011336Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 26780.886981 # average StoreCondReq mshr miss latency 79110636Snilay@cs.wisc.edusystem.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 79210585Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 79311336Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18670.406245 # average overall mshr miss latency 79411336Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_avg_mshr_miss_latency::total 18670.406245 # average overall mshr miss latency 79511336Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19726.591294 # average overall mshr miss latency 79611336Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_avg_mshr_miss_latency::total 19726.591294 # average overall mshr miss latency 79711336Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 194620.558116 # average ReadReq mshr uncacheable latency 79811336Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 194620.558116 # average ReadReq mshr uncacheable latency 79911336Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 188695.719308 # average WriteReq mshr uncacheable latency 80011336Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 188695.719308 # average WriteReq mshr uncacheable latency 80111336Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 191547.316280 # average overall mshr uncacheable latency 80211336Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 191547.316280 # average overall mshr uncacheable latency 80310585Sandreas.hansson@arm.comsystem.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 80411336Sandreas.hansson@arm.comsystem.cpu0.icache.tags.replacements 9594128 # number of replacements 80511336Sandreas.hansson@arm.comsystem.cpu0.icache.tags.tagsinuse 511.890921 # Cycle average of tags in use 80611336Sandreas.hansson@arm.comsystem.cpu0.icache.tags.total_refs 242861120 # Total number of references to valid blocks. 80711336Sandreas.hansson@arm.comsystem.cpu0.icache.tags.sampled_refs 9594640 # Sample count of references to valid blocks. 80811336Sandreas.hansson@arm.comsystem.cpu0.icache.tags.avg_refs 25.312166 # Average number of references to valid blocks. 80911201Sandreas.hansson@arm.comsystem.cpu0.icache.tags.warmup_cycle 40343615000 # Cycle when the warmup percentage was hit. 81011336Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_blocks::cpu0.inst 511.890921 # Average occupied blocks per requestor 81111201Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_percent::cpu0.inst 0.999787 # Average percentage of cache occupancy 81211201Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_percent::total 0.999787 # Average percentage of cache occupancy 81310585Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 81411336Sandreas.hansson@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::0 74 # Occupied blocks per task id 81511336Sandreas.hansson@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::1 191 # Occupied blocks per task id 81611336Sandreas.hansson@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::2 247 # Occupied blocks per task id 81710585Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 81811336Sandreas.hansson@arm.comsystem.cpu0.icache.tags.tag_accesses 514506190 # Number of tag accesses 81911336Sandreas.hansson@arm.comsystem.cpu0.icache.tags.data_accesses 514506190 # Number of data accesses 82011336Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_hits::cpu0.inst 242861120 # number of ReadReq hits 82111336Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_hits::total 242861120 # number of ReadReq hits 82211336Sandreas.hansson@arm.comsystem.cpu0.icache.demand_hits::cpu0.inst 242861120 # number of demand (read+write) hits 82311336Sandreas.hansson@arm.comsystem.cpu0.icache.demand_hits::total 242861120 # number of demand (read+write) hits 82411336Sandreas.hansson@arm.comsystem.cpu0.icache.overall_hits::cpu0.inst 242861120 # number of overall hits 82511336Sandreas.hansson@arm.comsystem.cpu0.icache.overall_hits::total 242861120 # number of overall hits 82611336Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_misses::cpu0.inst 9594650 # number of ReadReq misses 82711336Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_misses::total 9594650 # number of ReadReq misses 82811336Sandreas.hansson@arm.comsystem.cpu0.icache.demand_misses::cpu0.inst 9594650 # number of demand (read+write) misses 82911336Sandreas.hansson@arm.comsystem.cpu0.icache.demand_misses::total 9594650 # number of demand (read+write) misses 83011336Sandreas.hansson@arm.comsystem.cpu0.icache.overall_misses::cpu0.inst 9594650 # number of overall misses 83111336Sandreas.hansson@arm.comsystem.cpu0.icache.overall_misses::total 9594650 # number of overall misses 83211336Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_miss_latency::cpu0.inst 102613134000 # number of ReadReq miss cycles 83311336Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_miss_latency::total 102613134000 # number of ReadReq miss cycles 83411336Sandreas.hansson@arm.comsystem.cpu0.icache.demand_miss_latency::cpu0.inst 102613134000 # number of demand (read+write) miss cycles 83511336Sandreas.hansson@arm.comsystem.cpu0.icache.demand_miss_latency::total 102613134000 # number of demand (read+write) miss cycles 83611336Sandreas.hansson@arm.comsystem.cpu0.icache.overall_miss_latency::cpu0.inst 102613134000 # number of overall miss cycles 83711336Sandreas.hansson@arm.comsystem.cpu0.icache.overall_miss_latency::total 102613134000 # number of overall miss cycles 83811336Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_accesses::cpu0.inst 252455770 # number of ReadReq accesses(hits+misses) 83911336Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_accesses::total 252455770 # number of ReadReq accesses(hits+misses) 84011336Sandreas.hansson@arm.comsystem.cpu0.icache.demand_accesses::cpu0.inst 252455770 # number of demand (read+write) accesses 84111336Sandreas.hansson@arm.comsystem.cpu0.icache.demand_accesses::total 252455770 # number of demand (read+write) accesses 84211336Sandreas.hansson@arm.comsystem.cpu0.icache.overall_accesses::cpu0.inst 252455770 # number of overall (read+write) accesses 84311336Sandreas.hansson@arm.comsystem.cpu0.icache.overall_accesses::total 252455770 # number of overall (read+write) accesses 84411336Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.038005 # miss rate for ReadReq accesses 84511336Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_miss_rate::total 0.038005 # miss rate for ReadReq accesses 84611336Sandreas.hansson@arm.comsystem.cpu0.icache.demand_miss_rate::cpu0.inst 0.038005 # miss rate for demand accesses 84711336Sandreas.hansson@arm.comsystem.cpu0.icache.demand_miss_rate::total 0.038005 # miss rate for demand accesses 84811336Sandreas.hansson@arm.comsystem.cpu0.icache.overall_miss_rate::cpu0.inst 0.038005 # miss rate for overall accesses 84911336Sandreas.hansson@arm.comsystem.cpu0.icache.overall_miss_rate::total 0.038005 # miss rate for overall accesses 85011336Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10694.828264 # average ReadReq miss latency 85111336Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_avg_miss_latency::total 10694.828264 # average ReadReq miss latency 85211336Sandreas.hansson@arm.comsystem.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10694.828264 # average overall miss latency 85311336Sandreas.hansson@arm.comsystem.cpu0.icache.demand_avg_miss_latency::total 10694.828264 # average overall miss latency 85411336Sandreas.hansson@arm.comsystem.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10694.828264 # average overall miss latency 85511336Sandreas.hansson@arm.comsystem.cpu0.icache.overall_avg_miss_latency::total 10694.828264 # average overall miss latency 85610585Sandreas.hansson@arm.comsystem.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 85710585Sandreas.hansson@arm.comsystem.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 85810585Sandreas.hansson@arm.comsystem.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 85910585Sandreas.hansson@arm.comsystem.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 86010585Sandreas.hansson@arm.comsystem.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 86110585Sandreas.hansson@arm.comsystem.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 86210585Sandreas.hansson@arm.comsystem.cpu0.icache.fast_writes 0 # number of fast writes performed 86310585Sandreas.hansson@arm.comsystem.cpu0.icache.cache_copies 0 # number of cache copies performed 86411336Sandreas.hansson@arm.comsystem.cpu0.icache.writebacks::writebacks 9594128 # number of writebacks 86511336Sandreas.hansson@arm.comsystem.cpu0.icache.writebacks::total 9594128 # number of writebacks 86611336Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 9594650 # number of ReadReq MSHR misses 86711336Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_misses::total 9594650 # number of ReadReq MSHR misses 86811336Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_misses::cpu0.inst 9594650 # number of demand (read+write) MSHR misses 86911336Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_misses::total 9594650 # number of demand (read+write) MSHR misses 87011336Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_misses::cpu0.inst 9594650 # number of overall MSHR misses 87111336Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_misses::total 9594650 # number of overall MSHR misses 87211138Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 52309 # number of ReadReq MSHR uncacheable 87311138Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_uncacheable::total 52309 # number of ReadReq MSHR uncacheable 87411138Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 52309 # number of overall MSHR uncacheable misses 87511138Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_uncacheable_misses::total 52309 # number of overall MSHR uncacheable misses 87611336Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 97815809000 # number of ReadReq MSHR miss cycles 87711336Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_latency::total 97815809000 # number of ReadReq MSHR miss cycles 87811336Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 97815809000 # number of demand (read+write) MSHR miss cycles 87911336Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_miss_latency::total 97815809000 # number of demand (read+write) MSHR miss cycles 88011336Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 97815809000 # number of overall MSHR miss cycles 88111336Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_miss_latency::total 97815809000 # number of overall MSHR miss cycles 88211201Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 7414627000 # number of ReadReq MSHR uncacheable cycles 88311201Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 7414627000 # number of ReadReq MSHR uncacheable cycles 88411201Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 7414627000 # number of overall MSHR uncacheable cycles 88511201Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_uncacheable_latency::total 7414627000 # number of overall MSHR uncacheable cycles 88611336Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.038005 # mshr miss rate for ReadReq accesses 88711336Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_rate::total 0.038005 # mshr miss rate for ReadReq accesses 88811336Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.038005 # mshr miss rate for demand accesses 88911336Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_miss_rate::total 0.038005 # mshr miss rate for demand accesses 89011336Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.038005 # mshr miss rate for overall accesses 89111336Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_miss_rate::total 0.038005 # mshr miss rate for overall accesses 89211336Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10194.828264 # average ReadReq mshr miss latency 89311336Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10194.828264 # average ReadReq mshr miss latency 89411336Sandreas.hansson@arm.comsystem.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10194.828264 # average overall mshr miss latency 89511336Sandreas.hansson@arm.comsystem.cpu0.icache.demand_avg_mshr_miss_latency::total 10194.828264 # average overall mshr miss latency 89611336Sandreas.hansson@arm.comsystem.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10194.828264 # average overall mshr miss latency 89711336Sandreas.hansson@arm.comsystem.cpu0.icache.overall_avg_mshr_miss_latency::total 10194.828264 # average overall mshr miss latency 89811201Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 141746.678392 # average ReadReq mshr uncacheable latency 89911201Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 141746.678392 # average ReadReq mshr uncacheable latency 90011201Sandreas.hansson@arm.comsystem.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 141746.678392 # average overall mshr uncacheable latency 90111201Sandreas.hansson@arm.comsystem.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 141746.678392 # average overall mshr uncacheable latency 90210585Sandreas.hansson@arm.comsystem.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 90311336Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.num_hwpf_issued 8065650 # number of hwpf issued 90411336Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.pfIdentified 8066797 # number of prefetch candidates identified 90511336Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.pfBufferHit 1004 # number of redundant prefetches already in prefetch queue 90610628Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 90710628Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 90811336Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.pfSpanPage 1049003 # number of prefetches not generated due to page crossing 90911336Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.replacements 2949800 # number of replacements 91011336Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.tagsinuse 16165.081558 # Cycle average of tags in use 91111336Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.total_refs 23810069 # Total number of references to valid blocks. 91211336Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.sampled_refs 2965603 # Sample count of references to valid blocks. 91311336Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.avg_refs 8.028745 # Average number of references to valid blocks. 91411201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.warmup_cycle 9049945000 # Cycle when the warmup percentage was hit. 91511336Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_blocks::writebacks 15191.178363 # Average occupied blocks per requestor 91611336Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 63.510017 # Average occupied blocks per requestor 91711336Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 64.560721 # Average occupied blocks per requestor 91811336Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 845.832457 # Average occupied blocks per requestor 91911336Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::writebacks 0.927196 # Average percentage of cache occupancy 92011336Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003876 # Average percentage of cache occupancy 92111336Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.003940 # Average percentage of cache occupancy 92211336Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.051626 # Average percentage of cache occupancy 92311336Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::total 0.986638 # Average percentage of cache occupancy 92411336Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_blocks::1022 1186 # Occupied blocks per task id 92511336Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_blocks::1023 68 # Occupied blocks per task id 92611336Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_blocks::1024 14549 # Occupied blocks per task id 92711336Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1022::1 43 # Occupied blocks per task id 92811336Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1022::2 162 # Occupied blocks per task id 92911336Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1022::3 909 # Occupied blocks per task id 93011336Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1022::4 72 # Occupied blocks per task id 93111336Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id 93211336Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::2 45 # Occupied blocks per task id 93311336Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::3 19 # Occupied blocks per task id 93411336Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::4 3 # Occupied blocks per task id 93511336Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::0 130 # Occupied blocks per task id 93611336Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::1 878 # Occupied blocks per task id 93711336Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5504 # Occupied blocks per task id 93811336Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7511 # Occupied blocks per task id 93911336Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::4 526 # Occupied blocks per task id 94011336Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_percent::1022 0.072388 # Percentage of cache occupancy per task id 94111336Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_percent::1023 0.004150 # Percentage of cache occupancy per task id 94211336Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_percent::1024 0.888000 # Percentage of cache occupancy per task id 94311336Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.tag_accesses 520895158 # Number of tag accesses 94411336Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.data_accesses 520895158 # Number of data accesses 94511336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 527427 # number of ReadReq hits 94611336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 170829 # number of ReadReq hits 94711336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_hits::total 698256 # number of ReadReq hits 94811336Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackDirty_hits::writebacks 3866912 # number of WritebackDirty hits 94911336Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackDirty_hits::total 3866912 # number of WritebackDirty hits 95011336Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackClean_hits::writebacks 11575004 # number of WritebackClean hits 95111336Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackClean_hits::total 11575004 # number of WritebackClean hits 95211336Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_hits::cpu0.data 494 # number of UpgradeReq hits 95311336Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_hits::total 494 # number of UpgradeReq hits 95411336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_hits::cpu0.data 901398 # number of ReadExReq hits 95511336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_hits::total 901398 # number of ReadExReq hits 95611336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 8819397 # number of ReadCleanReq hits 95711336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_hits::total 8819397 # number of ReadCleanReq hits 95811336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 2877090 # number of ReadSharedReq hits 95911336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_hits::total 2877090 # number of ReadSharedReq hits 96011336Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_hits::cpu0.data 196747 # number of InvalidateReq hits 96111336Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_hits::total 196747 # number of InvalidateReq hits 96211336Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.dtb.walker 527427 # number of demand (read+write) hits 96311336Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.itb.walker 170829 # number of demand (read+write) hits 96411336Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.inst 8819397 # number of demand (read+write) hits 96511336Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.data 3778488 # number of demand (read+write) hits 96611336Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::total 13296141 # number of demand (read+write) hits 96711336Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.dtb.walker 527427 # number of overall hits 96811336Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.itb.walker 170829 # number of overall hits 96911336Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.inst 8819397 # number of overall hits 97011336Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.data 3778488 # number of overall hits 97111336Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::total 13296141 # number of overall hits 97211336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 12512 # number of ReadReq misses 97311336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 8836 # number of ReadReq misses 97411336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_misses::total 21348 # number of ReadReq misses 97511336Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackDirty_misses::writebacks 2 # number of WritebackDirty misses 97611336Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackDirty_misses::total 2 # number of WritebackDirty misses 97711336Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_misses::cpu0.data 265863 # number of UpgradeReq misses 97811336Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_misses::total 265863 # number of UpgradeReq misses 97911336Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 207797 # number of SCUpgradeReq misses 98011336Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_misses::total 207797 # number of SCUpgradeReq misses 98111245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 9 # number of SCUpgradeFailReq misses 98211245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_misses::total 9 # number of SCUpgradeFailReq misses 98311336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_misses::cpu0.data 295222 # number of ReadExReq misses 98411336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_misses::total 295222 # number of ReadExReq misses 98511336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 775252 # number of ReadCleanReq misses 98611336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_misses::total 775252 # number of ReadCleanReq misses 98711336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 1066801 # number of ReadSharedReq misses 98811336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_misses::total 1066801 # number of ReadSharedReq misses 98911336Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_misses::cpu0.data 607029 # number of InvalidateReq misses 99011336Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_misses::total 607029 # number of InvalidateReq misses 99111336Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.dtb.walker 12512 # number of demand (read+write) misses 99211336Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.itb.walker 8836 # number of demand (read+write) misses 99311336Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.inst 775252 # number of demand (read+write) misses 99411336Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.data 1362023 # number of demand (read+write) misses 99511336Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::total 2158623 # number of demand (read+write) misses 99611336Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.dtb.walker 12512 # number of overall misses 99711336Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.itb.walker 8836 # number of overall misses 99811336Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.inst 775252 # number of overall misses 99911336Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.data 1362023 # number of overall misses 100011336Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::total 2158623 # number of overall misses 100111336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 555558000 # number of ReadReq miss cycles 100211336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 430868000 # number of ReadReq miss cycles 100311336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_latency::total 986426000 # number of ReadReq miss cycles 100411336Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 3493305000 # number of UpgradeReq miss cycles 100511336Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_miss_latency::total 3493305000 # number of UpgradeReq miss cycles 100611336Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 1939943000 # number of SCUpgradeReq miss cycles 100711336Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_miss_latency::total 1939943000 # number of SCUpgradeReq miss cycles 100811336Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 4477498 # number of SCUpgradeFailReq miss cycles 100911336Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 4477498 # number of SCUpgradeFailReq miss cycles 101011336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 18708847499 # number of ReadExReq miss cycles 101111336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_miss_latency::total 18708847499 # number of ReadExReq miss cycles 101211336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 30179302500 # number of ReadCleanReq miss cycles 101311336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_miss_latency::total 30179302500 # number of ReadCleanReq miss cycles 101411336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 44632390995 # number of ReadSharedReq miss cycles 101511336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_miss_latency::total 44632390995 # number of ReadSharedReq miss cycles 101611336Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data 67815733000 # number of InvalidateReq miss cycles 101711336Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_miss_latency::total 67815733000 # number of InvalidateReq miss cycles 101811336Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 555558000 # number of demand (read+write) miss cycles 101911336Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 430868000 # number of demand (read+write) miss cycles 102011336Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_latency::cpu0.inst 30179302500 # number of demand (read+write) miss cycles 102111336Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_latency::cpu0.data 63341238494 # number of demand (read+write) miss cycles 102211336Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_latency::total 94506966994 # number of demand (read+write) miss cycles 102311336Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 555558000 # number of overall miss cycles 102411336Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 430868000 # number of overall miss cycles 102511336Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_latency::cpu0.inst 30179302500 # number of overall miss cycles 102611336Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_latency::cpu0.data 63341238494 # number of overall miss cycles 102711336Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_latency::total 94506966994 # number of overall miss cycles 102811336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 539939 # number of ReadReq accesses(hits+misses) 102911336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 179665 # number of ReadReq accesses(hits+misses) 103011336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_accesses::total 719604 # number of ReadReq accesses(hits+misses) 103111336Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackDirty_accesses::writebacks 3866914 # number of WritebackDirty accesses(hits+misses) 103211336Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackDirty_accesses::total 3866914 # number of WritebackDirty accesses(hits+misses) 103311336Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackClean_accesses::writebacks 11575004 # number of WritebackClean accesses(hits+misses) 103411336Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackClean_accesses::total 11575004 # number of WritebackClean accesses(hits+misses) 103511336Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 266357 # number of UpgradeReq accesses(hits+misses) 103611336Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_accesses::total 266357 # number of UpgradeReq accesses(hits+misses) 103711336Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 207797 # number of SCUpgradeReq accesses(hits+misses) 103811336Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_accesses::total 207797 # number of SCUpgradeReq accesses(hits+misses) 103911245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 9 # number of SCUpgradeFailReq accesses(hits+misses) 104011245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_accesses::total 9 # number of SCUpgradeFailReq accesses(hits+misses) 104111336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1196620 # number of ReadExReq accesses(hits+misses) 104211336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_accesses::total 1196620 # number of ReadExReq accesses(hits+misses) 104311336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 9594649 # number of ReadCleanReq accesses(hits+misses) 104411336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_accesses::total 9594649 # number of ReadCleanReq accesses(hits+misses) 104511336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 3943891 # number of ReadSharedReq accesses(hits+misses) 104611336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_accesses::total 3943891 # number of ReadSharedReq accesses(hits+misses) 104711336Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 803776 # number of InvalidateReq accesses(hits+misses) 104811336Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_accesses::total 803776 # number of InvalidateReq accesses(hits+misses) 104911336Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 539939 # number of demand (read+write) accesses 105011336Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.itb.walker 179665 # number of demand (read+write) accesses 105111336Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.inst 9594649 # number of demand (read+write) accesses 105211336Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.data 5140511 # number of demand (read+write) accesses 105311336Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::total 15454764 # number of demand (read+write) accesses 105411336Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 539939 # number of overall (read+write) accesses 105511336Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.itb.walker 179665 # number of overall (read+write) accesses 105611336Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.inst 9594649 # number of overall (read+write) accesses 105711336Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.data 5140511 # number of overall (read+write) accesses 105811336Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::total 15454764 # number of overall (read+write) accesses 105911336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.023173 # miss rate for ReadReq accesses 106011336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.049180 # miss rate for ReadReq accesses 106111336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::total 0.029666 # miss rate for ReadReq accesses 106211336Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackDirty_miss_rate::writebacks 0.000001 # miss rate for WritebackDirty accesses 106311336Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackDirty_miss_rate::total 0.000001 # miss rate for WritebackDirty accesses 106411336Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.998145 # miss rate for UpgradeReq accesses 106511336Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_miss_rate::total 0.998145 # miss rate for UpgradeReq accesses 106611201Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses 106711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 106810636Snilay@cs.wisc.edusystem.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses 106910585Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 107011336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.246713 # miss rate for ReadExReq accesses 107111336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_miss_rate::total 0.246713 # miss rate for ReadExReq accesses 107211336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.080800 # miss rate for ReadCleanReq accesses 107311336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.080800 # miss rate for ReadCleanReq accesses 107411336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.270495 # miss rate for ReadSharedReq accesses 107511336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.270495 # miss rate for ReadSharedReq accesses 107611336Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.755222 # miss rate for InvalidateReq accesses 107711336Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_miss_rate::total 0.755222 # miss rate for InvalidateReq accesses 107811336Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.023173 # miss rate for demand accesses 107911336Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.049180 # miss rate for demand accesses 108011336Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.080800 # miss rate for demand accesses 108111336Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.data 0.264959 # miss rate for demand accesses 108211336Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::total 0.139674 # miss rate for demand accesses 108311336Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.023173 # miss rate for overall accesses 108411336Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.049180 # miss rate for overall accesses 108511336Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.080800 # miss rate for overall accesses 108611336Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.data 0.264959 # miss rate for overall accesses 108711336Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::total 0.139674 # miss rate for overall accesses 108811336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 44402.014066 # average ReadReq miss latency 108911336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 48762.788592 # average ReadReq miss latency 109011336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_miss_latency::total 46206.951471 # average ReadReq miss latency 109111336Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 13139.492897 # average UpgradeReq miss latency 109211336Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 13139.492897 # average UpgradeReq miss latency 109311336Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 9335.760382 # average SCUpgradeReq miss latency 109411336Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 9335.760382 # average SCUpgradeReq miss latency 109511336Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 497499.777778 # average SCUpgradeFailReq miss latency 109611336Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 497499.777778 # average SCUpgradeFailReq miss latency 109711336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 63372.131816 # average ReadExReq miss latency 109811336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_avg_miss_latency::total 63372.131816 # average ReadExReq miss latency 109911336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 38928.377482 # average ReadCleanReq miss latency 110011336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 38928.377482 # average ReadCleanReq miss latency 110111336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 41837.597635 # average ReadSharedReq miss latency 110211336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 41837.597635 # average ReadSharedReq miss latency 110311336Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 111717.451720 # average InvalidateReq miss latency 110411336Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 111717.451720 # average InvalidateReq miss latency 110511336Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 44402.014066 # average overall miss latency 110611336Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 48762.788592 # average overall miss latency 110711336Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 38928.377482 # average overall miss latency 110811336Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 46505.263490 # average overall miss latency 110911336Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_miss_latency::total 43781.135934 # average overall miss latency 111011336Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 44402.014066 # average overall miss latency 111111336Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 48762.788592 # average overall miss latency 111211336Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 38928.377482 # average overall miss latency 111311336Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 46505.263490 # average overall miss latency 111411336Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_miss_latency::total 43781.135934 # average overall miss latency 111511336Sandreas.hansson@arm.comsystem.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 111610585Sandreas.hansson@arm.comsystem.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 111711336Sandreas.hansson@arm.comsystem.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 111810585Sandreas.hansson@arm.comsystem.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 111911336Sandreas.hansson@arm.comsystem.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 112010585Sandreas.hansson@arm.comsystem.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 112110585Sandreas.hansson@arm.comsystem.cpu0.l2cache.fast_writes 0 # number of fast writes performed 112210585Sandreas.hansson@arm.comsystem.cpu0.l2cache.cache_copies 0 # number of cache copies performed 112311336Sandreas.hansson@arm.comsystem.cpu0.l2cache.writebacks::writebacks 1702054 # number of writebacks 112411336Sandreas.hansson@arm.comsystem.cpu0.l2cache.writebacks::total 1702054 # number of writebacks 112511336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker 1 # number of ReadReq MSHR hits 112611336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 3 # number of ReadReq MSHR hits 112711336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_hits::total 4 # number of ReadReq MSHR hits 112811336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 8173 # number of ReadExReq MSHR hits 112911336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_hits::total 8173 # number of ReadExReq MSHR hits 113011336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 11 # number of ReadCleanReq MSHR hits 113111336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_hits::total 11 # number of ReadCleanReq MSHR hits 113211336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 1611 # number of ReadSharedReq MSHR hits 113311336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_hits::total 1611 # number of ReadSharedReq MSHR hits 113411336Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_hits::cpu0.data 4 # number of InvalidateReq MSHR hits 113511336Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_hits::total 4 # number of InvalidateReq MSHR hits 113611336Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker 1 # number of demand (read+write) MSHR hits 113711336Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 3 # number of demand (read+write) MSHR hits 113811336Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_hits::cpu0.inst 11 # number of demand (read+write) MSHR hits 113911336Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_hits::cpu0.data 9784 # number of demand (read+write) MSHR hits 114011336Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_hits::total 9799 # number of demand (read+write) MSHR hits 114111336Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker 1 # number of overall MSHR hits 114211336Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 3 # number of overall MSHR hits 114311336Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_hits::cpu0.inst 11 # number of overall MSHR hits 114411336Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_hits::cpu0.data 9784 # number of overall MSHR hits 114511336Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_hits::total 9799 # number of overall MSHR hits 114611336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 12511 # number of ReadReq MSHR misses 114711336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 8833 # number of ReadReq MSHR misses 114811336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_misses::total 21344 # number of ReadReq MSHR misses 114911336Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackDirty_mshr_misses::writebacks 2 # number of WritebackDirty MSHR misses 115011336Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackDirty_mshr_misses::total 2 # number of WritebackDirty MSHR misses 115111336Sandreas.hansson@arm.comsystem.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 812970 # number of HardPFReq MSHR misses 115211336Sandreas.hansson@arm.comsystem.cpu0.l2cache.HardPFReq_mshr_misses::total 812970 # number of HardPFReq MSHR misses 115311336Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 265863 # number of UpgradeReq MSHR misses 115411336Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_mshr_misses::total 265863 # number of UpgradeReq MSHR misses 115511336Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 207797 # number of SCUpgradeReq MSHR misses 115611336Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 207797 # number of SCUpgradeReq MSHR misses 115711245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 9 # number of SCUpgradeFailReq MSHR misses 115811245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 9 # number of SCUpgradeFailReq MSHR misses 115911336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 287049 # number of ReadExReq MSHR misses 116011336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_misses::total 287049 # number of ReadExReq MSHR misses 116111336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 775241 # number of ReadCleanReq MSHR misses 116211336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_misses::total 775241 # number of ReadCleanReq MSHR misses 116311336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 1065190 # number of ReadSharedReq MSHR misses 116411336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_misses::total 1065190 # number of ReadSharedReq MSHR misses 116511336Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data 607025 # number of InvalidateReq MSHR misses 116611336Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_misses::total 607025 # number of InvalidateReq MSHR misses 116711336Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 12511 # number of demand (read+write) MSHR misses 116811336Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 8833 # number of demand (read+write) MSHR misses 116911336Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_misses::cpu0.inst 775241 # number of demand (read+write) MSHR misses 117011336Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_misses::cpu0.data 1352239 # number of demand (read+write) MSHR misses 117111336Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_misses::total 2148824 # number of demand (read+write) MSHR misses 117211336Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 12511 # number of overall MSHR misses 117311336Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 8833 # number of overall MSHR misses 117411336Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_misses::cpu0.inst 775241 # number of overall MSHR misses 117511336Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_misses::cpu0.data 1352239 # number of overall MSHR misses 117611336Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 812970 # number of overall MSHR misses 117711336Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_misses::total 2961794 # number of overall MSHR misses 117811138Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 52309 # number of ReadReq MSHR uncacheable 117911336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 19530 # number of ReadReq MSHR uncacheable 118011336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable::total 71839 # number of ReadReq MSHR uncacheable 118111336Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 21048 # number of WriteReq MSHR uncacheable 118211336Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteReq_mshr_uncacheable::total 21048 # number of WriteReq MSHR uncacheable 118311138Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 52309 # number of overall MSHR uncacheable misses 118411336Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 40578 # number of overall MSHR uncacheable misses 118511336Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_uncacheable_misses::total 92887 # number of overall MSHR uncacheable misses 118611336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 480468000 # number of ReadReq MSHR miss cycles 118711336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 377798500 # number of ReadReq MSHR miss cycles 118811336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_latency::total 858266500 # number of ReadReq MSHR miss cycles 118911336Sandreas.hansson@arm.comsystem.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 44849426201 # number of HardPFReq MSHR miss cycles 119011336Sandreas.hansson@arm.comsystem.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 44849426201 # number of HardPFReq MSHR miss cycles 119111336Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 7795522498 # number of UpgradeReq MSHR miss cycles 119211336Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 7795522498 # number of UpgradeReq MSHR miss cycles 119311336Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 4002040000 # number of SCUpgradeReq MSHR miss cycles 119411336Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 4002040000 # number of SCUpgradeReq MSHR miss cycles 119511336Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 4147498 # number of SCUpgradeFailReq MSHR miss cycles 119611336Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 4147498 # number of SCUpgradeFailReq MSHR miss cycles 119711336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 15893166999 # number of ReadExReq MSHR miss cycles 119811336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 15893166999 # number of ReadExReq MSHR miss cycles 119911336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 25527386000 # number of ReadCleanReq MSHR miss cycles 120011336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 25527386000 # number of ReadCleanReq MSHR miss cycles 120111336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 38109816995 # number of ReadSharedReq MSHR miss cycles 120211336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 38109816995 # number of ReadSharedReq MSHR miss cycles 120311336Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 64173364000 # number of InvalidateReq MSHR miss cycles 120411336Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 64173364000 # number of InvalidateReq MSHR miss cycles 120511336Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 480468000 # number of demand (read+write) MSHR miss cycles 120611336Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 377798500 # number of demand (read+write) MSHR miss cycles 120711336Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 25527386000 # number of demand (read+write) MSHR miss cycles 120811336Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 54002983994 # number of demand (read+write) MSHR miss cycles 120911336Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_latency::total 80388636494 # number of demand (read+write) MSHR miss cycles 121011336Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 480468000 # number of overall MSHR miss cycles 121111336Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 377798500 # number of overall MSHR miss cycles 121211336Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 25527386000 # number of overall MSHR miss cycles 121311336Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 54002983994 # number of overall MSHR miss cycles 121411336Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 44849426201 # number of overall MSHR miss cycles 121511336Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::total 125238062695 # number of overall MSHR miss cycles 121611201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 6996155000 # number of ReadReq MSHR uncacheable cycles 121711336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 3644540000 # number of ReadReq MSHR uncacheable cycles 121811336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 10640695000 # number of ReadReq MSHR uncacheable cycles 121911336Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 3813756000 # number of WriteReq MSHR uncacheable cycles 122011336Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 3813756000 # number of WriteReq MSHR uncacheable cycles 122111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 6996155000 # number of overall MSHR uncacheable cycles 122211336Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 7458296000 # number of overall MSHR uncacheable cycles 122311336Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_uncacheable_latency::total 14454451000 # number of overall MSHR uncacheable cycles 122411336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.023171 # mshr miss rate for ReadReq accesses 122511336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.049164 # mshr miss rate for ReadReq accesses 122611336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.029661 # mshr miss rate for ReadReq accesses 122711336Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackDirty_mshr_miss_rate::writebacks 0.000001 # mshr miss rate for WritebackDirty accesses 122811336Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackDirty_mshr_miss_rate::total 0.000001 # mshr miss rate for WritebackDirty accesses 122910585Sandreas.hansson@arm.comsystem.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 123010585Sandreas.hansson@arm.comsystem.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 123111336Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.998145 # mshr miss rate for UpgradeReq accesses 123211336Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.998145 # mshr miss rate for UpgradeReq accesses 123311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses 123411201Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 123510636Snilay@cs.wisc.edusystem.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses 123610585Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 123711336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.239883 # mshr miss rate for ReadExReq accesses 123811336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.239883 # mshr miss rate for ReadExReq accesses 123911336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.080799 # mshr miss rate for ReadCleanReq accesses 124011336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.080799 # mshr miss rate for ReadCleanReq accesses 124111336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.270086 # mshr miss rate for ReadSharedReq accesses 124211336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.270086 # mshr miss rate for ReadSharedReq accesses 124311336Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.755217 # mshr miss rate for InvalidateReq accesses 124411336Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.755217 # mshr miss rate for InvalidateReq accesses 124511336Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.023171 # mshr miss rate for demand accesses 124611336Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.049164 # mshr miss rate for demand accesses 124711336Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.080799 # mshr miss rate for demand accesses 124811336Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.263055 # mshr miss rate for demand accesses 124911336Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_rate::total 0.139040 # mshr miss rate for demand accesses 125011336Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.023171 # mshr miss rate for overall accesses 125111336Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.049164 # mshr miss rate for overall accesses 125211336Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.080799 # mshr miss rate for overall accesses 125311336Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.263055 # mshr miss rate for overall accesses 125410585Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses 125511336Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_rate::total 0.191643 # mshr miss rate for overall accesses 125611336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 38403.644793 # average ReadReq mshr miss latency 125711336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 42771.255519 # average ReadReq mshr miss latency 125811336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 40211.136619 # average ReadReq mshr miss latency 125911336Sandreas.hansson@arm.comsystem.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 55167.381577 # average HardPFReq mshr miss latency 126011336Sandreas.hansson@arm.comsystem.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 55167.381577 # average HardPFReq mshr miss latency 126111336Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 29321.577271 # average UpgradeReq mshr miss latency 126211336Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 29321.577271 # average UpgradeReq mshr miss latency 126311336Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 19259.373331 # average SCUpgradeReq mshr miss latency 126411336Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19259.373331 # average SCUpgradeReq mshr miss latency 126511336Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 460833.111111 # average SCUpgradeFailReq mshr miss latency 126611336Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 460833.111111 # average SCUpgradeFailReq mshr miss latency 126711336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 55367.435521 # average ReadExReq mshr miss latency 126811336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 55367.435521 # average ReadExReq mshr miss latency 126911336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 32928.322934 # average ReadCleanReq mshr miss latency 127011336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 32928.322934 # average ReadCleanReq mshr miss latency 127111336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 35777.482886 # average ReadSharedReq mshr miss latency 127211336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 35777.482886 # average ReadSharedReq mshr miss latency 127311336Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 105717.827108 # average InvalidateReq mshr miss latency 127411336Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 105717.827108 # average InvalidateReq mshr miss latency 127511336Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 38403.644793 # average overall mshr miss latency 127611336Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 42771.255519 # average overall mshr miss latency 127711336Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 32928.322934 # average overall mshr miss latency 127811336Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 39935.975810 # average overall mshr miss latency 127911336Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_mshr_miss_latency::total 37410.526173 # average overall mshr miss latency 128011336Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 38403.644793 # average overall mshr miss latency 128111336Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 42771.255519 # average overall mshr miss latency 128211336Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 32928.322934 # average overall mshr miss latency 128311336Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 39935.975810 # average overall mshr miss latency 128411336Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 55167.381577 # average overall mshr miss latency 128511336Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::total 42284.528463 # average overall mshr miss latency 128611201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 133746.678392 # average ReadReq mshr uncacheable latency 128711336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 186612.391193 # average ReadReq mshr uncacheable latency 128811336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 148118.640293 # average ReadReq mshr uncacheable latency 128911336Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 181193.272520 # average WriteReq mshr uncacheable latency 129011336Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 181193.272520 # average WriteReq mshr uncacheable latency 129111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 133746.678392 # average overall mshr uncacheable latency 129211336Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 183801.468776 # average overall mshr uncacheable latency 129311336Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 155613.282806 # average overall mshr uncacheable latency 129410585Sandreas.hansson@arm.comsystem.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 129511336Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_filter.tot_requests 31782914 # Total number of requests made to the snoop filter. 129611336Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_filter.hit_single_requests 16244108 # Number of requests hitting in the snoop filter with a single holder of the requested data. 129711336Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_filter.hit_multi_requests 2495 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 129811336Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_filter.tot_snoops 2292721 # Total number of snoops made to the snoop filter. 129911336Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_filter.hit_single_snoops 2292254 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 130011336Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 467 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 130111336Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadReq 871142 # Transaction distribution 130211336Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadResp 14502039 # Transaction distribution 130311336Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::WriteReq 21048 # Transaction distribution 130411336Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::WriteResp 21048 # Transaction distribution 130511336Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::WritebackDirty 5574338 # Transaction distribution 130611336Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::WritebackClean 11577498 # Transaction distribution 130711336Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::CleanEvict 3160606 # Transaction distribution 130811336Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::HardPFReq 1056652 # Transaction distribution 130911336Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::UpgradeReq 471328 # Transaction distribution 131011336Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::SCUpgradeReq 370548 # Transaction distribution 131111336Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::UpgradeResp 537517 # Transaction distribution 131211336Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 70 # Transaction distribution 131311336Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::UpgradeFailResp 116 # Transaction distribution 131411336Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadExReq 1276044 # Transaction distribution 131511336Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadExResp 1205760 # Transaction distribution 131611336Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadCleanReq 9594650 # Transaction distribution 131711336Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadSharedReq 5010763 # Transaction distribution 131811336Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::InvalidateReq 810566 # Transaction distribution 131911336Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::InvalidateResp 803776 # Transaction distribution 132011336Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 28888045 # Packet count per connected master and slave (bytes) 132111336Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 18933308 # Packet count per connected master and slave (bytes) 132211336Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 377591 # Packet count per connected master and slave (bytes) 132311336Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1141314 # Packet count per connected master and slave (bytes) 132411336Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count::total 49340258 # Packet count per connected master and slave (bytes) 132511336Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 1231429504 # Cumulative packet size per connected master and slave (bytes) 132611336Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 710021103 # Cumulative packet size per connected master and slave (bytes) 132711336Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1437320 # Cumulative packet size per connected master and slave (bytes) 132811336Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4319512 # Cumulative packet size per connected master and slave (bytes) 132911336Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size::total 1947207439 # Cumulative packet size per connected master and slave (bytes) 133011336Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoops 7690219 # Total snoops (count) 133111336Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::samples 24350841 # Request fanout histogram 133211336Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::mean 0.107639 # Request fanout histogram 133311336Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::stdev 0.309986 # Request fanout histogram 133410585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 133511336Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::0 21730213 89.24% 89.24% # Request fanout histogram 133611336Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::1 2620161 10.76% 100.00% # Request fanout histogram 133711336Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::2 467 0.00% 100.00% # Request fanout histogram 133810585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 133911138Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 134010827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 134111336Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::total 24350841 # Request fanout histogram 134211336Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.reqLayer0.occupancy 31629791489 # Layer occupancy (ticks) 134311201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 134411336Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoopLayer0.occupancy 184209930 # Layer occupancy (ticks) 134510585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 134611336Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.respLayer0.occupancy 14474040275 # Layer occupancy (ticks) 134710585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 134811336Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.respLayer1.occupancy 8384067550 # Layer occupancy (ticks) 134910585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 135011336Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.respLayer2.occupancy 198003844 # Layer occupancy (ticks) 135110585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 135211336Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.respLayer3.occupancy 601473802 # Layer occupancy (ticks) 135310585Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 135411336Sandreas.hansson@arm.comsystem.cpu1.branchPred.lookups 133924240 # Number of BP lookups 135511336Sandreas.hansson@arm.comsystem.cpu1.branchPred.condPredicted 95730476 # Number of conditional branches predicted 135611336Sandreas.hansson@arm.comsystem.cpu1.branchPred.condIncorrect 5982653 # Number of conditional branches incorrect 135711336Sandreas.hansson@arm.comsystem.cpu1.branchPred.BTBLookups 100302023 # Number of BTB lookups 135811336Sandreas.hansson@arm.comsystem.cpu1.branchPred.BTBHits 73831862 # Number of BTB hits 135910585Sandreas.hansson@arm.comsystem.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 136011336Sandreas.hansson@arm.comsystem.cpu1.branchPred.BTBHitPct 73.609544 # BTB Hit Percentage 136111336Sandreas.hansson@arm.comsystem.cpu1.branchPred.usedRAS 15419194 # Number of times the RAS was used to get a target. 136211336Sandreas.hansson@arm.comsystem.cpu1.branchPred.RASInCorrect 1021732 # Number of incorrect RAS predictions. 136310628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 136410628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 136510628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 136610628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 136710628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 136810628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 136910628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 137010628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 137110585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 137210585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 137310585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 137410585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 137510585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 137610585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 137710585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 137810585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 137910585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 138010585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 138110585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 138210585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 138310585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 138410585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 138510585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 138610585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 138710585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 138810585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 138910585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 139010585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 139110585Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 139211336Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walks 293746 # Table walker walks requested 139311336Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksLong 293746 # Table walker walks initiated with long descriptors 139411336Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksLongTerminationLevel::Level2 11413 # Level at which table walker walks with long descriptors terminate 139511336Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksLongTerminationLevel::Level3 90757 # Level at which table walker walks with long descriptors terminate 139611336Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkWaitTime::samples 293746 # Table walker wait (enqueue to first request) latency 139711336Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkWaitTime::0 293746 100.00% 100.00% # Table walker wait (enqueue to first request) latency 139811336Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkWaitTime::total 293746 # Table walker wait (enqueue to first request) latency 139911336Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::samples 102170 # Table walker service (enqueue to completion) latency 140011336Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::mean 23413.986493 # Table walker service (enqueue to completion) latency 140111336Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::gmean 21412.179846 # Table walker service (enqueue to completion) latency 140211336Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::stdev 20342.964000 # Table walker service (enqueue to completion) latency 140311336Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::0-65535 100862 98.72% 98.72% # Table walker service (enqueue to completion) latency 140411336Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::65536-131071 167 0.16% 98.88% # Table walker service (enqueue to completion) latency 140511336Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::131072-196607 952 0.93% 99.82% # Table walker service (enqueue to completion) latency 140611336Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::196608-262143 45 0.04% 99.86% # Table walker service (enqueue to completion) latency 140711336Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::262144-327679 52 0.05% 99.91% # Table walker service (enqueue to completion) latency 140811336Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::327680-393215 35 0.03% 99.94% # Table walker service (enqueue to completion) latency 140911336Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::393216-458751 35 0.03% 99.98% # Table walker service (enqueue to completion) latency 141011336Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::458752-524287 12 0.01% 99.99% # Table walker service (enqueue to completion) latency 141111245Sandreas.sandberg@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::524288-589823 6 0.01% 100.00% # Table walker service (enqueue to completion) latency 141211336Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::589824-655359 3 0.00% 100.00% # Table walker service (enqueue to completion) latency 141311245Sandreas.sandberg@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 141411336Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::total 102170 # Table walker service (enqueue to completion) latency 141511201Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksPending::samples 527505760 # Table walker pending requests distribution 141611201Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksPending::0 527505760 100.00% 100.00% # Table walker pending requests distribution 141711201Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksPending::total 527505760 # Table walker pending requests distribution 141811336Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkPageSizes::4K 90757 88.83% 88.83% # Table walker page sizes translated 141911336Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkPageSizes::2M 11413 11.17% 100.00% # Table walker page sizes translated 142011336Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkPageSizes::total 102170 # Table walker page sizes translated 142111336Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 293746 # Table walker requests started/completed, data/inst 142210628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 142311336Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Requested::total 293746 # Table walker requests started/completed, data/inst 142411336Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 102170 # Table walker requests started/completed, data/inst 142510628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 142611336Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Completed::total 102170 # Table walker requests started/completed, data/inst 142711336Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin::total 395916 # Table walker requests started/completed, data/inst 142810585Sandreas.hansson@arm.comsystem.cpu1.dtb.inst_hits 0 # ITB inst hits 142910585Sandreas.hansson@arm.comsystem.cpu1.dtb.inst_misses 0 # ITB inst misses 143011336Sandreas.hansson@arm.comsystem.cpu1.dtb.read_hits 86040245 # DTB read hits 143111336Sandreas.hansson@arm.comsystem.cpu1.dtb.read_misses 244355 # DTB read misses 143211336Sandreas.hansson@arm.comsystem.cpu1.dtb.write_hits 75067998 # DTB write hits 143311336Sandreas.hansson@arm.comsystem.cpu1.dtb.write_misses 49391 # DTB write misses 143410585Sandreas.hansson@arm.comsystem.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed 143510585Sandreas.hansson@arm.comsystem.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 143611336Sandreas.hansson@arm.comsystem.cpu1.dtb.flush_tlb_mva_asid 42784 # Number of times TLB was flushed by MVA & ASID 143711336Sandreas.hansson@arm.comsystem.cpu1.dtb.flush_tlb_asid 1060 # Number of times TLB was flushed by ASID 143811336Sandreas.hansson@arm.comsystem.cpu1.dtb.flush_entries 37937 # Number of entries that have been flushed from TLB 143911336Sandreas.hansson@arm.comsystem.cpu1.dtb.align_faults 1338 # Number of TLB faults due to alignment restrictions 144011336Sandreas.hansson@arm.comsystem.cpu1.dtb.prefetch_faults 8312 # Number of TLB faults due to prefetch 144110585Sandreas.hansson@arm.comsystem.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 144211336Sandreas.hansson@arm.comsystem.cpu1.dtb.perms_faults 11189 # Number of TLB faults due to permissions restrictions 144311336Sandreas.hansson@arm.comsystem.cpu1.dtb.read_accesses 86284600 # DTB read accesses 144411336Sandreas.hansson@arm.comsystem.cpu1.dtb.write_accesses 75117389 # DTB write accesses 144510585Sandreas.hansson@arm.comsystem.cpu1.dtb.inst_accesses 0 # ITB inst accesses 144611336Sandreas.hansson@arm.comsystem.cpu1.dtb.hits 161108243 # DTB hits 144711336Sandreas.hansson@arm.comsystem.cpu1.dtb.misses 293746 # DTB misses 144811336Sandreas.hansson@arm.comsystem.cpu1.dtb.accesses 161401989 # DTB accesses 144910628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 145010628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 145110628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 145210628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 145310628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 145410628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 145510628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 145610628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 145710585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 145810585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 145910585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 146010585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 146110585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 146210585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 146310585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 146410585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 146510585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 146610585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 146710585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 146810585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 146910585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 147010585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 147110585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 147210585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 147310585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 147410585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 147510585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 147610585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 147710585Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 147811336Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walks 65124 # Table walker walks requested 147911336Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksLong 65124 # Table walker walks initiated with long descriptors 148011336Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksLongTerminationLevel::Level2 508 # Level at which table walker walks with long descriptors terminate 148111336Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksLongTerminationLevel::Level3 55766 # Level at which table walker walks with long descriptors terminate 148211336Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkWaitTime::samples 65124 # Table walker wait (enqueue to first request) latency 148311336Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkWaitTime::0 65124 100.00% 100.00% # Table walker wait (enqueue to first request) latency 148411336Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkWaitTime::total 65124 # Table walker wait (enqueue to first request) latency 148511336Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::samples 56274 # Table walker service (enqueue to completion) latency 148611336Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::mean 26926.564666 # Table walker service (enqueue to completion) latency 148711336Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::gmean 23857.779953 # Table walker service (enqueue to completion) latency 148811336Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::stdev 24945.648372 # Table walker service (enqueue to completion) latency 148911336Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::0-65535 54940 97.63% 97.63% # Table walker service (enqueue to completion) latency 149011336Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::65536-131071 10 0.02% 97.65% # Table walker service (enqueue to completion) latency 149111336Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::131072-196607 1199 2.13% 99.78% # Table walker service (enqueue to completion) latency 149211336Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::196608-262143 37 0.07% 99.84% # Table walker service (enqueue to completion) latency 149311336Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::262144-327679 49 0.09% 99.93% # Table walker service (enqueue to completion) latency 149411336Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::327680-393215 24 0.04% 99.97% # Table walker service (enqueue to completion) latency 149511336Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::393216-458751 8 0.01% 99.99% # Table walker service (enqueue to completion) latency 149611336Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::458752-524287 3 0.01% 99.99% # Table walker service (enqueue to completion) latency 149711336Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 149811336Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 149911336Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::total 56274 # Table walker service (enqueue to completion) latency 150011201Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksPending::samples 526611260 # Table walker pending requests distribution 150111201Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksPending::0 526611260 100.00% 100.00% # Table walker pending requests distribution 150211201Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksPending::total 526611260 # Table walker pending requests distribution 150311336Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkPageSizes::4K 55766 99.10% 99.10% # Table walker page sizes translated 150411336Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkPageSizes::2M 508 0.90% 100.00% # Table walker page sizes translated 150511336Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkPageSizes::total 56274 # Table walker page sizes translated 150610628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 150711336Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 65124 # Table walker requests started/completed, data/inst 150811336Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Requested::total 65124 # Table walker requests started/completed, data/inst 150910628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 151011336Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 56274 # Table walker requests started/completed, data/inst 151111336Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Completed::total 56274 # Table walker requests started/completed, data/inst 151211336Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin::total 121398 # Table walker requests started/completed, data/inst 151311336Sandreas.hansson@arm.comsystem.cpu1.itb.inst_hits 239249458 # ITB inst hits 151411336Sandreas.hansson@arm.comsystem.cpu1.itb.inst_misses 65124 # ITB inst misses 151510585Sandreas.hansson@arm.comsystem.cpu1.itb.read_hits 0 # DTB read hits 151610585Sandreas.hansson@arm.comsystem.cpu1.itb.read_misses 0 # DTB read misses 151710585Sandreas.hansson@arm.comsystem.cpu1.itb.write_hits 0 # DTB write hits 151810585Sandreas.hansson@arm.comsystem.cpu1.itb.write_misses 0 # DTB write misses 151910585Sandreas.hansson@arm.comsystem.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed 152010585Sandreas.hansson@arm.comsystem.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 152111336Sandreas.hansson@arm.comsystem.cpu1.itb.flush_tlb_mva_asid 42784 # Number of times TLB was flushed by MVA & ASID 152211336Sandreas.hansson@arm.comsystem.cpu1.itb.flush_tlb_asid 1060 # Number of times TLB was flushed by ASID 152311336Sandreas.hansson@arm.comsystem.cpu1.itb.flush_entries 26970 # Number of entries that have been flushed from TLB 152410585Sandreas.hansson@arm.comsystem.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 152510585Sandreas.hansson@arm.comsystem.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 152610585Sandreas.hansson@arm.comsystem.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 152711336Sandreas.hansson@arm.comsystem.cpu1.itb.perms_faults 220780 # Number of TLB faults due to permissions restrictions 152810585Sandreas.hansson@arm.comsystem.cpu1.itb.read_accesses 0 # DTB read accesses 152910585Sandreas.hansson@arm.comsystem.cpu1.itb.write_accesses 0 # DTB write accesses 153011336Sandreas.hansson@arm.comsystem.cpu1.itb.inst_accesses 239314582 # ITB inst accesses 153111336Sandreas.hansson@arm.comsystem.cpu1.itb.hits 239249458 # DTB hits 153211336Sandreas.hansson@arm.comsystem.cpu1.itb.misses 65124 # DTB misses 153311336Sandreas.hansson@arm.comsystem.cpu1.itb.accesses 239314582 # DTB accesses 153411336Sandreas.hansson@arm.comsystem.cpu1.numCycles 947127317 # number of cpu cycles simulated 153510585Sandreas.hansson@arm.comsystem.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 153610585Sandreas.hansson@arm.comsystem.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 153711336Sandreas.hansson@arm.comsystem.cpu1.committedInsts 437680583 # Number of instructions committed 153811336Sandreas.hansson@arm.comsystem.cpu1.committedOps 515109454 # Number of ops (including micro ops) committed 153911336Sandreas.hansson@arm.comsystem.cpu1.discardedOps 47548266 # Number of ops (including micro ops) which were discarded before commit 154011336Sandreas.hansson@arm.comsystem.cpu1.numFetchSuspends 4998 # Number of times Execute suspended instruction fetching 154111336Sandreas.hansson@arm.comsystem.cpu1.quiesceCycles 93977493591 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 154211245Sandreas.sandberg@arm.comsystem.cpu1.cpi 2.163969 # CPI: cycles per instruction 154311245Sandreas.sandberg@arm.comsystem.cpu1.ipc 0.462114 # IPC: instructions per cycle 154410585Sandreas.hansson@arm.comsystem.cpu1.kern.inst.arm 0 # number of arm instructions executed 154511336Sandreas.hansson@arm.comsystem.cpu1.kern.inst.quiesce 13761 # number of quiesce instructions executed 154611336Sandreas.hansson@arm.comsystem.cpu1.tickCycles 715510770 # Number of cycles that the object actually ticked 154711336Sandreas.hansson@arm.comsystem.cpu1.idleCycles 231616547 # Total number of cycles that the object has spent stopped 154811336Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.replacements 5225400 # number of replacements 154911336Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.tagsinuse 442.020428 # Cycle average of tags in use 155011336Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.total_refs 153149767 # Total number of references to valid blocks. 155111336Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.sampled_refs 5225912 # Sample count of references to valid blocks. 155211336Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.avg_refs 29.305845 # Average number of references to valid blocks. 155311336Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.warmup_cycle 8545383120500 # Cycle when the warmup percentage was hit. 155411336Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_blocks::cpu1.data 442.020428 # Average occupied blocks per requestor 155511336Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_percent::cpu1.data 0.863321 # Average percentage of cache occupancy 155611336Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_percent::total 0.863321 # Average percentage of cache occupancy 155711167Sjthestness@gmail.comsystem.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 155811336Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::0 73 # Occupied blocks per task id 155911336Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::1 408 # Occupied blocks per task id 156011336Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::2 31 # Occupied blocks per task id 156111167Sjthestness@gmail.comsystem.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 156211336Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.tag_accesses 324837482 # Number of tag accesses 156311336Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.data_accesses 324837482 # Number of data accesses 156411336Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_hits::cpu1.data 78835589 # number of ReadReq hits 156511336Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_hits::total 78835589 # number of ReadReq hits 156611336Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_hits::cpu1.data 69932856 # number of WriteReq hits 156711336Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_hits::total 69932856 # number of WriteReq hits 156811336Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_hits::cpu1.data 235045 # number of SoftPFReq hits 156911336Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_hits::total 235045 # number of SoftPFReq hits 157011336Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_hits::cpu1.data 136840 # number of WriteLineReq hits 157111336Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_hits::total 136840 # number of WriteLineReq hits 157211336Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1777859 # number of LoadLockedReq hits 157311336Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_hits::total 1777859 # number of LoadLockedReq hits 157411336Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_hits::cpu1.data 1734680 # number of StoreCondReq hits 157511336Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_hits::total 1734680 # number of StoreCondReq hits 157611336Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_hits::cpu1.data 148768445 # number of demand (read+write) hits 157711336Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_hits::total 148768445 # number of demand (read+write) hits 157811336Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_hits::cpu1.data 149003490 # number of overall hits 157911336Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_hits::total 149003490 # number of overall hits 158011336Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_misses::cpu1.data 3368921 # number of ReadReq misses 158111336Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_misses::total 3368921 # number of ReadReq misses 158211336Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_misses::cpu1.data 2278073 # number of WriteReq misses 158311336Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_misses::total 2278073 # number of WriteReq misses 158411336Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_misses::cpu1.data 647676 # number of SoftPFReq misses 158511336Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_misses::total 647676 # number of SoftPFReq misses 158611336Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_misses::cpu1.data 450910 # number of WriteLineReq misses 158711336Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_misses::total 450910 # number of WriteLineReq misses 158811336Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_misses::cpu1.data 159516 # number of LoadLockedReq misses 158911336Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_misses::total 159516 # number of LoadLockedReq misses 159011336Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_misses::cpu1.data 201171 # number of StoreCondReq misses 159111336Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_misses::total 201171 # number of StoreCondReq misses 159211336Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_misses::cpu1.data 5646994 # number of demand (read+write) misses 159311336Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_misses::total 5646994 # number of demand (read+write) misses 159411336Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_misses::cpu1.data 6294670 # number of overall misses 159511336Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_misses::total 6294670 # number of overall misses 159611336Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_miss_latency::cpu1.data 55794276000 # number of ReadReq miss cycles 159711336Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_miss_latency::total 55794276000 # number of ReadReq miss cycles 159811336Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_miss_latency::cpu1.data 51841670500 # number of WriteReq miss cycles 159911336Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_miss_latency::total 51841670500 # number of WriteReq miss cycles 160011336Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 21264976000 # number of WriteLineReq miss cycles 160111336Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_miss_latency::total 21264976000 # number of WriteLineReq miss cycles 160211336Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2730537500 # number of LoadLockedReq miss cycles 160311336Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_latency::total 2730537500 # number of LoadLockedReq miss cycles 160411336Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 5515974000 # number of StoreCondReq miss cycles 160511336Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_miss_latency::total 5515974000 # number of StoreCondReq miss cycles 160611336Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 4942500 # number of StoreCondFailReq miss cycles 160711336Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondFailReq_miss_latency::total 4942500 # number of StoreCondFailReq miss cycles 160811336Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_miss_latency::cpu1.data 107635946500 # number of demand (read+write) miss cycles 160911336Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_miss_latency::total 107635946500 # number of demand (read+write) miss cycles 161011336Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_miss_latency::cpu1.data 107635946500 # number of overall miss cycles 161111336Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_miss_latency::total 107635946500 # number of overall miss cycles 161211336Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_accesses::cpu1.data 82204510 # number of ReadReq accesses(hits+misses) 161311336Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_accesses::total 82204510 # number of ReadReq accesses(hits+misses) 161411336Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_accesses::cpu1.data 72210929 # number of WriteReq accesses(hits+misses) 161511336Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_accesses::total 72210929 # number of WriteReq accesses(hits+misses) 161611336Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_accesses::cpu1.data 882721 # number of SoftPFReq accesses(hits+misses) 161711336Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_accesses::total 882721 # number of SoftPFReq accesses(hits+misses) 161811336Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_accesses::cpu1.data 587750 # number of WriteLineReq accesses(hits+misses) 161911336Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_accesses::total 587750 # number of WriteLineReq accesses(hits+misses) 162011336Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1937375 # number of LoadLockedReq accesses(hits+misses) 162111336Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_accesses::total 1937375 # number of LoadLockedReq accesses(hits+misses) 162211336Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1935851 # number of StoreCondReq accesses(hits+misses) 162311336Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_accesses::total 1935851 # number of StoreCondReq accesses(hits+misses) 162411336Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_accesses::cpu1.data 154415439 # number of demand (read+write) accesses 162511336Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_accesses::total 154415439 # number of demand (read+write) accesses 162611336Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_accesses::cpu1.data 155298160 # number of overall (read+write) accesses 162711336Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_accesses::total 155298160 # number of overall (read+write) accesses 162811336Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.040982 # miss rate for ReadReq accesses 162911336Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_miss_rate::total 0.040982 # miss rate for ReadReq accesses 163011336Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.031547 # miss rate for WriteReq accesses 163111336Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_miss_rate::total 0.031547 # miss rate for WriteReq accesses 163211336Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.733727 # miss rate for SoftPFReq accesses 163311336Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_miss_rate::total 0.733727 # miss rate for SoftPFReq accesses 163411336Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.767180 # miss rate for WriteLineReq accesses 163511336Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_miss_rate::total 0.767180 # miss rate for WriteLineReq accesses 163611336Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.082336 # miss rate for LoadLockedReq accesses 163711336Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_rate::total 0.082336 # miss rate for LoadLockedReq accesses 163811336Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.103919 # miss rate for StoreCondReq accesses 163911336Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_miss_rate::total 0.103919 # miss rate for StoreCondReq accesses 164011336Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_miss_rate::cpu1.data 0.036570 # miss rate for demand accesses 164111336Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_miss_rate::total 0.036570 # miss rate for demand accesses 164211336Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_miss_rate::cpu1.data 0.040533 # miss rate for overall accesses 164311336Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_miss_rate::total 0.040533 # miss rate for overall accesses 164411336Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16561.467603 # average ReadReq miss latency 164511336Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_avg_miss_latency::total 16561.467603 # average ReadReq miss latency 164611336Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 22756.808276 # average WriteReq miss latency 164711336Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_avg_miss_latency::total 22756.808276 # average WriteReq miss latency 164811336Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 47160.133951 # average WriteLineReq miss latency 164911336Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_avg_miss_latency::total 47160.133951 # average WriteLineReq miss latency 165011336Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 17117.640237 # average LoadLockedReq miss latency 165111336Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 17117.640237 # average LoadLockedReq miss latency 165211336Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 27419.329824 # average StoreCondReq miss latency 165311336Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_avg_miss_latency::total 27419.329824 # average StoreCondReq miss latency 165410636Snilay@cs.wisc.edusystem.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 165510585Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 165611336Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19060.750994 # average overall miss latency 165711336Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_avg_miss_latency::total 19060.750994 # average overall miss latency 165811336Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17099.537625 # average overall miss latency 165911336Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_avg_miss_latency::total 17099.537625 # average overall miss latency 166010585Sandreas.hansson@arm.comsystem.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 166110585Sandreas.hansson@arm.comsystem.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 166210585Sandreas.hansson@arm.comsystem.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 166310585Sandreas.hansson@arm.comsystem.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 166410585Sandreas.hansson@arm.comsystem.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 166510585Sandreas.hansson@arm.comsystem.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 166610585Sandreas.hansson@arm.comsystem.cpu1.dcache.fast_writes 0 # number of fast writes performed 166710585Sandreas.hansson@arm.comsystem.cpu1.dcache.cache_copies 0 # number of cache copies performed 166811336Sandreas.hansson@arm.comsystem.cpu1.dcache.writebacks::writebacks 5225429 # number of writebacks 166911336Sandreas.hansson@arm.comsystem.cpu1.dcache.writebacks::total 5225429 # number of writebacks 167011336Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 382545 # number of ReadReq MSHR hits 167111336Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_hits::total 382545 # number of ReadReq MSHR hits 167211336Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 937825 # number of WriteReq MSHR hits 167311336Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_hits::total 937825 # number of WriteReq MSHR hits 167411336Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 58 # number of WriteLineReq MSHR hits 167511336Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_hits::total 58 # number of WriteLineReq MSHR hits 167611336Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 41578 # number of LoadLockedReq MSHR hits 167711336Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_hits::total 41578 # number of LoadLockedReq MSHR hits 167811336Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data 34 # number of StoreCondReq MSHR hits 167911336Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_hits::total 34 # number of StoreCondReq MSHR hits 168011336Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_hits::cpu1.data 1320370 # number of demand (read+write) MSHR hits 168111336Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_hits::total 1320370 # number of demand (read+write) MSHR hits 168211336Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_hits::cpu1.data 1320370 # number of overall MSHR hits 168311336Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_hits::total 1320370 # number of overall MSHR hits 168411336Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2986376 # number of ReadReq MSHR misses 168511336Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_misses::total 2986376 # number of ReadReq MSHR misses 168611336Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1340248 # number of WriteReq MSHR misses 168711336Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_misses::total 1340248 # number of WriteReq MSHR misses 168811336Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 647394 # number of SoftPFReq MSHR misses 168911336Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_mshr_misses::total 647394 # number of SoftPFReq MSHR misses 169011336Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 450852 # number of WriteLineReq MSHR misses 169111336Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_misses::total 450852 # number of WriteLineReq MSHR misses 169211336Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 117938 # number of LoadLockedReq MSHR misses 169311336Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_misses::total 117938 # number of LoadLockedReq MSHR misses 169411336Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 201137 # number of StoreCondReq MSHR misses 169511336Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_misses::total 201137 # number of StoreCondReq MSHR misses 169611336Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_misses::cpu1.data 4326624 # number of demand (read+write) MSHR misses 169711336Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_misses::total 4326624 # number of demand (read+write) MSHR misses 169811336Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_misses::cpu1.data 4974018 # number of overall MSHR misses 169911336Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_misses::total 4974018 # number of overall MSHR misses 170011336Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 19129 # number of ReadReq MSHR uncacheable 170111336Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_uncacheable::total 19129 # number of ReadReq MSHR uncacheable 170211336Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 17467 # number of WriteReq MSHR uncacheable 170311336Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_uncacheable::total 17467 # number of WriteReq MSHR uncacheable 170411336Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 36596 # number of overall MSHR uncacheable misses 170511336Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_uncacheable_misses::total 36596 # number of overall MSHR uncacheable misses 170611336Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 44483005500 # number of ReadReq MSHR miss cycles 170711336Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_miss_latency::total 44483005500 # number of ReadReq MSHR miss cycles 170811336Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 30789351000 # number of WriteReq MSHR miss cycles 170911336Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_miss_latency::total 30789351000 # number of WriteReq MSHR miss cycles 171011336Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 15729879000 # number of SoftPFReq MSHR miss cycles 171111336Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 15729879000 # number of SoftPFReq MSHR miss cycles 171211336Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 20808027500 # number of WriteLineReq MSHR miss cycles 171311336Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 20808027500 # number of WriteLineReq MSHR miss cycles 171411336Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1765421000 # number of LoadLockedReq MSHR miss cycles 171511336Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1765421000 # number of LoadLockedReq MSHR miss cycles 171611336Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 5312775000 # number of StoreCondReq MSHR miss cycles 171711336Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 5312775000 # number of StoreCondReq MSHR miss cycles 171811336Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 4745500 # number of StoreCondFailReq MSHR miss cycles 171911336Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 4745500 # number of StoreCondFailReq MSHR miss cycles 172011336Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 75272356500 # number of demand (read+write) MSHR miss cycles 172111336Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_miss_latency::total 75272356500 # number of demand (read+write) MSHR miss cycles 172211336Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 91002235500 # number of overall MSHR miss cycles 172311336Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_miss_latency::total 91002235500 # number of overall MSHR miss cycles 172411336Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3151598000 # number of ReadReq MSHR uncacheable cycles 172511336Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 3151598000 # number of ReadReq MSHR uncacheable cycles 172611336Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2962839500 # number of WriteReq MSHR uncacheable cycles 172711336Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 2962839500 # number of WriteReq MSHR uncacheable cycles 172811336Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 6114437500 # number of overall MSHR uncacheable cycles 172911336Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_uncacheable_latency::total 6114437500 # number of overall MSHR uncacheable cycles 173011336Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036329 # mshr miss rate for ReadReq accesses 173111336Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036329 # mshr miss rate for ReadReq accesses 173211336Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018560 # mshr miss rate for WriteReq accesses 173311336Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018560 # mshr miss rate for WriteReq accesses 173411336Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.733407 # mshr miss rate for SoftPFReq accesses 173511336Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.733407 # mshr miss rate for SoftPFReq accesses 173611336Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.767081 # mshr miss rate for WriteLineReq accesses 173711336Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.767081 # mshr miss rate for WriteLineReq accesses 173811336Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.060875 # mshr miss rate for LoadLockedReq accesses 173911336Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.060875 # mshr miss rate for LoadLockedReq accesses 174011336Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.103901 # mshr miss rate for StoreCondReq accesses 174111336Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.103901 # mshr miss rate for StoreCondReq accesses 174211336Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.028019 # mshr miss rate for demand accesses 174311336Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_miss_rate::total 0.028019 # mshr miss rate for demand accesses 174411336Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.032029 # mshr miss rate for overall accesses 174511336Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_miss_rate::total 0.032029 # mshr miss rate for overall accesses 174611336Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14895.313082 # average ReadReq mshr miss latency 174711336Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14895.313082 # average ReadReq mshr miss latency 174811336Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 22972.875916 # average WriteReq mshr miss latency 174911336Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 22972.875916 # average WriteReq mshr miss latency 175011336Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 24297.227036 # average SoftPFReq mshr miss latency 175111336Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 24297.227036 # average SoftPFReq mshr miss latency 175211336Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 46152.678706 # average WriteLineReq mshr miss latency 175311336Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 46152.678706 # average WriteLineReq mshr miss latency 175411336Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14969.060015 # average LoadLockedReq mshr miss latency 175511336Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14969.060015 # average LoadLockedReq mshr miss latency 175611336Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 26413.713041 # average StoreCondReq mshr miss latency 175711336Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 26413.713041 # average StoreCondReq mshr miss latency 175810636Snilay@cs.wisc.edusystem.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 175910585Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 176011336Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17397.480461 # average overall mshr miss latency 176111336Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_avg_mshr_miss_latency::total 17397.480461 # average overall mshr miss latency 176211336Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18295.517929 # average overall mshr miss latency 176311336Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_avg_mshr_miss_latency::total 18295.517929 # average overall mshr miss latency 176411336Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 164754.979351 # average ReadReq mshr uncacheable latency 176511336Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 164754.979351 # average ReadReq mshr uncacheable latency 176611336Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 169624.978531 # average WriteReq mshr uncacheable latency 176711336Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 169624.978531 # average WriteReq mshr uncacheable latency 176811336Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 167079.393923 # average overall mshr uncacheable latency 176911336Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 167079.393923 # average overall mshr uncacheable latency 177010585Sandreas.hansson@arm.comsystem.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 177111336Sandreas.hansson@arm.comsystem.cpu1.icache.tags.replacements 9231311 # number of replacements 177211336Sandreas.hansson@arm.comsystem.cpu1.icache.tags.tagsinuse 506.694166 # Cycle average of tags in use 177311336Sandreas.hansson@arm.comsystem.cpu1.icache.tags.total_refs 229790487 # Total number of references to valid blocks. 177411336Sandreas.hansson@arm.comsystem.cpu1.icache.tags.sampled_refs 9231823 # Sample count of references to valid blocks. 177511336Sandreas.hansson@arm.comsystem.cpu1.icache.tags.avg_refs 24.891128 # Average number of references to valid blocks. 177611336Sandreas.hansson@arm.comsystem.cpu1.icache.tags.warmup_cycle 8386495264000 # Cycle when the warmup percentage was hit. 177711336Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_blocks::cpu1.inst 506.694166 # Average occupied blocks per requestor 177811336Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_percent::cpu1.inst 0.989637 # Average percentage of cache occupancy 177911336Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_percent::total 0.989637 # Average percentage of cache occupancy 178010585Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 178111336Sandreas.hansson@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::0 100 # Occupied blocks per task id 178211336Sandreas.hansson@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::1 336 # Occupied blocks per task id 178311336Sandreas.hansson@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::2 76 # Occupied blocks per task id 178410585Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 178511336Sandreas.hansson@arm.comsystem.cpu1.icache.tags.tag_accesses 487276445 # Number of tag accesses 178611336Sandreas.hansson@arm.comsystem.cpu1.icache.tags.data_accesses 487276445 # Number of data accesses 178711336Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_hits::cpu1.inst 229790487 # number of ReadReq hits 178811336Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_hits::total 229790487 # number of ReadReq hits 178911336Sandreas.hansson@arm.comsystem.cpu1.icache.demand_hits::cpu1.inst 229790487 # number of demand (read+write) hits 179011336Sandreas.hansson@arm.comsystem.cpu1.icache.demand_hits::total 229790487 # number of demand (read+write) hits 179111336Sandreas.hansson@arm.comsystem.cpu1.icache.overall_hits::cpu1.inst 229790487 # number of overall hits 179211336Sandreas.hansson@arm.comsystem.cpu1.icache.overall_hits::total 229790487 # number of overall hits 179311336Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_misses::cpu1.inst 9231824 # number of ReadReq misses 179411336Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_misses::total 9231824 # number of ReadReq misses 179511336Sandreas.hansson@arm.comsystem.cpu1.icache.demand_misses::cpu1.inst 9231824 # number of demand (read+write) misses 179611336Sandreas.hansson@arm.comsystem.cpu1.icache.demand_misses::total 9231824 # number of demand (read+write) misses 179711336Sandreas.hansson@arm.comsystem.cpu1.icache.overall_misses::cpu1.inst 9231824 # number of overall misses 179811336Sandreas.hansson@arm.comsystem.cpu1.icache.overall_misses::total 9231824 # number of overall misses 179911336Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_miss_latency::cpu1.inst 94524443000 # number of ReadReq miss cycles 180011336Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_miss_latency::total 94524443000 # number of ReadReq miss cycles 180111336Sandreas.hansson@arm.comsystem.cpu1.icache.demand_miss_latency::cpu1.inst 94524443000 # number of demand (read+write) miss cycles 180211336Sandreas.hansson@arm.comsystem.cpu1.icache.demand_miss_latency::total 94524443000 # number of demand (read+write) miss cycles 180311336Sandreas.hansson@arm.comsystem.cpu1.icache.overall_miss_latency::cpu1.inst 94524443000 # number of overall miss cycles 180411336Sandreas.hansson@arm.comsystem.cpu1.icache.overall_miss_latency::total 94524443000 # number of overall miss cycles 180511336Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_accesses::cpu1.inst 239022311 # number of ReadReq accesses(hits+misses) 180611336Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_accesses::total 239022311 # number of ReadReq accesses(hits+misses) 180711336Sandreas.hansson@arm.comsystem.cpu1.icache.demand_accesses::cpu1.inst 239022311 # number of demand (read+write) accesses 180811336Sandreas.hansson@arm.comsystem.cpu1.icache.demand_accesses::total 239022311 # number of demand (read+write) accesses 180911336Sandreas.hansson@arm.comsystem.cpu1.icache.overall_accesses::cpu1.inst 239022311 # number of overall (read+write) accesses 181011336Sandreas.hansson@arm.comsystem.cpu1.icache.overall_accesses::total 239022311 # number of overall (read+write) accesses 181111336Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.038623 # miss rate for ReadReq accesses 181211336Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_miss_rate::total 0.038623 # miss rate for ReadReq accesses 181311336Sandreas.hansson@arm.comsystem.cpu1.icache.demand_miss_rate::cpu1.inst 0.038623 # miss rate for demand accesses 181411336Sandreas.hansson@arm.comsystem.cpu1.icache.demand_miss_rate::total 0.038623 # miss rate for demand accesses 181511336Sandreas.hansson@arm.comsystem.cpu1.icache.overall_miss_rate::cpu1.inst 0.038623 # miss rate for overall accesses 181611336Sandreas.hansson@arm.comsystem.cpu1.icache.overall_miss_rate::total 0.038623 # miss rate for overall accesses 181711336Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10238.978018 # average ReadReq miss latency 181811336Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_avg_miss_latency::total 10238.978018 # average ReadReq miss latency 181911336Sandreas.hansson@arm.comsystem.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10238.978018 # average overall miss latency 182011336Sandreas.hansson@arm.comsystem.cpu1.icache.demand_avg_miss_latency::total 10238.978018 # average overall miss latency 182111336Sandreas.hansson@arm.comsystem.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10238.978018 # average overall miss latency 182211336Sandreas.hansson@arm.comsystem.cpu1.icache.overall_avg_miss_latency::total 10238.978018 # average overall miss latency 182310585Sandreas.hansson@arm.comsystem.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 182410585Sandreas.hansson@arm.comsystem.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 182510585Sandreas.hansson@arm.comsystem.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 182610585Sandreas.hansson@arm.comsystem.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 182710585Sandreas.hansson@arm.comsystem.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 182810585Sandreas.hansson@arm.comsystem.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 182910585Sandreas.hansson@arm.comsystem.cpu1.icache.fast_writes 0 # number of fast writes performed 183010585Sandreas.hansson@arm.comsystem.cpu1.icache.cache_copies 0 # number of cache copies performed 183111336Sandreas.hansson@arm.comsystem.cpu1.icache.writebacks::writebacks 9231311 # number of writebacks 183211336Sandreas.hansson@arm.comsystem.cpu1.icache.writebacks::total 9231311 # number of writebacks 183311336Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 9231824 # number of ReadReq MSHR misses 183411336Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_misses::total 9231824 # number of ReadReq MSHR misses 183511336Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_misses::cpu1.inst 9231824 # number of demand (read+write) MSHR misses 183611336Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_misses::total 9231824 # number of demand (read+write) MSHR misses 183711336Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_misses::cpu1.inst 9231824 # number of overall MSHR misses 183811336Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_misses::total 9231824 # number of overall MSHR misses 183911138Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 92 # number of ReadReq MSHR uncacheable 184011138Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_uncacheable::total 92 # number of ReadReq MSHR uncacheable 184111138Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 92 # number of overall MSHR uncacheable misses 184211138Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_uncacheable_misses::total 92 # number of overall MSHR uncacheable misses 184311336Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 89908531500 # number of ReadReq MSHR miss cycles 184411336Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_latency::total 89908531500 # number of ReadReq MSHR miss cycles 184511336Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 89908531500 # number of demand (read+write) MSHR miss cycles 184611336Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_miss_latency::total 89908531500 # number of demand (read+write) MSHR miss cycles 184711336Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 89908531500 # number of overall MSHR miss cycles 184811336Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_miss_latency::total 89908531500 # number of overall MSHR miss cycles 184911201Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 12950500 # number of ReadReq MSHR uncacheable cycles 185011201Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 12950500 # number of ReadReq MSHR uncacheable cycles 185111201Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 12950500 # number of overall MSHR uncacheable cycles 185211201Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_uncacheable_latency::total 12950500 # number of overall MSHR uncacheable cycles 185311336Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.038623 # mshr miss rate for ReadReq accesses 185411336Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_rate::total 0.038623 # mshr miss rate for ReadReq accesses 185511336Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.038623 # mshr miss rate for demand accesses 185611336Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_miss_rate::total 0.038623 # mshr miss rate for demand accesses 185711336Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.038623 # mshr miss rate for overall accesses 185811336Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_miss_rate::total 0.038623 # mshr miss rate for overall accesses 185911336Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 9738.978072 # average ReadReq mshr miss latency 186011336Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 9738.978072 # average ReadReq mshr miss latency 186111336Sandreas.hansson@arm.comsystem.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 9738.978072 # average overall mshr miss latency 186211336Sandreas.hansson@arm.comsystem.cpu1.icache.demand_avg_mshr_miss_latency::total 9738.978072 # average overall mshr miss latency 186311336Sandreas.hansson@arm.comsystem.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 9738.978072 # average overall mshr miss latency 186411336Sandreas.hansson@arm.comsystem.cpu1.icache.overall_avg_mshr_miss_latency::total 9738.978072 # average overall mshr miss latency 186511201Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 140766.304348 # average ReadReq mshr uncacheable latency 186611201Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 140766.304348 # average ReadReq mshr uncacheable latency 186711201Sandreas.hansson@arm.comsystem.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 140766.304348 # average overall mshr uncacheable latency 186811201Sandreas.hansson@arm.comsystem.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 140766.304348 # average overall mshr uncacheable latency 186910585Sandreas.hansson@arm.comsystem.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 187011336Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.num_hwpf_issued 7101301 # number of hwpf issued 187111336Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.pfIdentified 7101636 # number of prefetch candidates identified 187211336Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.pfBufferHit 296 # number of redundant prefetches already in prefetch queue 187310628Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 187410628Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 187511336Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.pfSpanPage 867300 # number of prefetches not generated due to page crossing 187611336Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.replacements 2326720 # number of replacements 187711336Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.tagsinuse 13467.956369 # Cycle average of tags in use 187811336Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.total_refs 23154784 # Total number of references to valid blocks. 187911336Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.sampled_refs 2342909 # Sample count of references to valid blocks. 188011336Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.avg_refs 9.882921 # Average number of references to valid blocks. 188111336Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.warmup_cycle 9860254327500 # Cycle when the warmup percentage was hit. 188211336Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_blocks::writebacks 12598.584174 # Average occupied blocks per requestor 188311336Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 60.491814 # Average occupied blocks per requestor 188411336Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 58.201363 # Average occupied blocks per requestor 188511336Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 750.679017 # Average occupied blocks per requestor 188611336Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::writebacks 0.768957 # Average percentage of cache occupancy 188711336Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.003692 # Average percentage of cache occupancy 188811336Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.003552 # Average percentage of cache occupancy 188911336Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.045818 # Average percentage of cache occupancy 189011336Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::total 0.822019 # Average percentage of cache occupancy 189111336Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_blocks::1022 1395 # Occupied blocks per task id 189211336Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_blocks::1023 52 # Occupied blocks per task id 189311336Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_blocks::1024 14742 # Occupied blocks per task id 189411336Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1022::1 10 # Occupied blocks per task id 189511336Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1022::2 404 # Occupied blocks per task id 189611336Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1022::3 859 # Occupied blocks per task id 189711336Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1022::4 122 # Occupied blocks per task id 189811336Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::1 2 # Occupied blocks per task id 189911336Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id 190011336Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::3 31 # Occupied blocks per task id 190111336Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::4 3 # Occupied blocks per task id 190211336Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::0 86 # Occupied blocks per task id 190311336Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1149 # Occupied blocks per task id 190411336Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5193 # Occupied blocks per task id 190511336Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::3 7319 # Occupied blocks per task id 190611336Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::4 995 # Occupied blocks per task id 190711336Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_percent::1022 0.085144 # Percentage of cache occupancy per task id 190811336Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_percent::1023 0.003174 # Percentage of cache occupancy per task id 190911336Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_percent::1024 0.899780 # Percentage of cache occupancy per task id 191011336Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.tag_accesses 488472501 # Number of tag accesses 191111336Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.data_accesses 488472501 # Number of data accesses 191211336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 576439 # number of ReadReq hits 191311336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 168221 # number of ReadReq hits 191411336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_hits::total 744660 # number of ReadReq hits 191511336Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackDirty_hits::writebacks 3264846 # number of WritebackDirty hits 191611336Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackDirty_hits::total 3264846 # number of WritebackDirty hits 191711336Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackClean_hits::writebacks 11189694 # number of WritebackClean hits 191811336Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackClean_hits::total 11189694 # number of WritebackClean hits 191911336Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_hits::cpu1.data 575 # number of UpgradeReq hits 192011336Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_hits::total 575 # number of UpgradeReq hits 192111336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_hits::cpu1.data 867363 # number of ReadExReq hits 192211336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_hits::total 867363 # number of ReadExReq hits 192311336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 8545306 # number of ReadCleanReq hits 192411336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_hits::total 8545306 # number of ReadCleanReq hits 192511336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 2781382 # number of ReadSharedReq hits 192611336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_hits::total 2781382 # number of ReadSharedReq hits 192711336Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_hits::cpu1.data 181539 # number of InvalidateReq hits 192811336Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_hits::total 181539 # number of InvalidateReq hits 192911336Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.dtb.walker 576439 # number of demand (read+write) hits 193011336Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.itb.walker 168221 # number of demand (read+write) hits 193111336Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.inst 8545306 # number of demand (read+write) hits 193211336Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.data 3648745 # number of demand (read+write) hits 193311336Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::total 12938711 # number of demand (read+write) hits 193411336Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.dtb.walker 576439 # number of overall hits 193511336Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.itb.walker 168221 # number of overall hits 193611336Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.inst 8545306 # number of overall hits 193711336Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.data 3648745 # number of overall hits 193811336Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::total 12938711 # number of overall hits 193911336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 12346 # number of ReadReq misses 194011336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 8532 # number of ReadReq misses 194111336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_misses::total 20878 # number of ReadReq misses 194211336Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackDirty_misses::writebacks 1 # number of WritebackDirty misses 194311336Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackDirty_misses::total 1 # number of WritebackDirty misses 194411336Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_misses::cpu1.data 223343 # number of UpgradeReq misses 194511336Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_misses::total 223343 # number of UpgradeReq misses 194611336Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 201132 # number of SCUpgradeReq misses 194711336Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_misses::total 201132 # number of SCUpgradeReq misses 194811336Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 5 # number of SCUpgradeFailReq misses 194911336Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_misses::total 5 # number of SCUpgradeFailReq misses 195011336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_misses::cpu1.data 251639 # number of ReadExReq misses 195111336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_misses::total 251639 # number of ReadExReq misses 195211336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 686518 # number of ReadCleanReq misses 195311336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_misses::total 686518 # number of ReadCleanReq misses 195411336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 970013 # number of ReadSharedReq misses 195511336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_misses::total 970013 # number of ReadSharedReq misses 195611336Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_misses::cpu1.data 267232 # number of InvalidateReq misses 195711336Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_misses::total 267232 # number of InvalidateReq misses 195811336Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.dtb.walker 12346 # number of demand (read+write) misses 195911336Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.itb.walker 8532 # number of demand (read+write) misses 196011336Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.inst 686518 # number of demand (read+write) misses 196111336Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.data 1221652 # number of demand (read+write) misses 196211336Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::total 1929048 # number of demand (read+write) misses 196311336Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.dtb.walker 12346 # number of overall misses 196411336Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.itb.walker 8532 # number of overall misses 196511336Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.inst 686518 # number of overall misses 196611336Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.data 1221652 # number of overall misses 196711336Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::total 1929048 # number of overall misses 196811336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 599407500 # number of ReadReq miss cycles 196911336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 460132500 # number of ReadReq miss cycles 197011336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_latency::total 1059540000 # number of ReadReq miss cycles 197111336Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 3297082000 # number of UpgradeReq miss cycles 197211336Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_miss_latency::total 3297082000 # number of UpgradeReq miss cycles 197311336Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 1852998500 # number of SCUpgradeReq miss cycles 197411336Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_miss_latency::total 1852998500 # number of SCUpgradeReq miss cycles 197511336Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 4653499 # number of SCUpgradeFailReq miss cycles 197611336Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 4653499 # number of SCUpgradeFailReq miss cycles 197711336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 14739798000 # number of ReadExReq miss cycles 197811336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_miss_latency::total 14739798000 # number of ReadExReq miss cycles 197911336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 24441807000 # number of ReadCleanReq miss cycles 198011336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_miss_latency::total 24441807000 # number of ReadCleanReq miss cycles 198111336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 37974197490 # number of ReadSharedReq miss cycles 198211336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_miss_latency::total 37974197490 # number of ReadSharedReq miss cycles 198311336Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 18803051000 # number of InvalidateReq miss cycles 198411336Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_miss_latency::total 18803051000 # number of InvalidateReq miss cycles 198511336Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 599407500 # number of demand (read+write) miss cycles 198611336Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 460132500 # number of demand (read+write) miss cycles 198711336Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_latency::cpu1.inst 24441807000 # number of demand (read+write) miss cycles 198811336Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_latency::cpu1.data 52713995490 # number of demand (read+write) miss cycles 198911336Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_latency::total 78215342490 # number of demand (read+write) miss cycles 199011336Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 599407500 # number of overall miss cycles 199111336Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 460132500 # number of overall miss cycles 199211336Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_latency::cpu1.inst 24441807000 # number of overall miss cycles 199311336Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_latency::cpu1.data 52713995490 # number of overall miss cycles 199411336Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_latency::total 78215342490 # number of overall miss cycles 199511336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 588785 # number of ReadReq accesses(hits+misses) 199611336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 176753 # number of ReadReq accesses(hits+misses) 199711336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_accesses::total 765538 # number of ReadReq accesses(hits+misses) 199811336Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackDirty_accesses::writebacks 3264847 # number of WritebackDirty accesses(hits+misses) 199911336Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackDirty_accesses::total 3264847 # number of WritebackDirty accesses(hits+misses) 200011336Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackClean_accesses::writebacks 11189694 # number of WritebackClean accesses(hits+misses) 200111336Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackClean_accesses::total 11189694 # number of WritebackClean accesses(hits+misses) 200211336Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 223918 # number of UpgradeReq accesses(hits+misses) 200311336Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_accesses::total 223918 # number of UpgradeReq accesses(hits+misses) 200411336Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 201132 # number of SCUpgradeReq accesses(hits+misses) 200511336Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_accesses::total 201132 # number of SCUpgradeReq accesses(hits+misses) 200611336Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 5 # number of SCUpgradeFailReq accesses(hits+misses) 200711336Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_accesses::total 5 # number of SCUpgradeFailReq accesses(hits+misses) 200811336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1119002 # number of ReadExReq accesses(hits+misses) 200911336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_accesses::total 1119002 # number of ReadExReq accesses(hits+misses) 201011336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 9231824 # number of ReadCleanReq accesses(hits+misses) 201111336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_accesses::total 9231824 # number of ReadCleanReq accesses(hits+misses) 201211336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 3751395 # number of ReadSharedReq accesses(hits+misses) 201311336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_accesses::total 3751395 # number of ReadSharedReq accesses(hits+misses) 201411336Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 448771 # number of InvalidateReq accesses(hits+misses) 201511336Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_accesses::total 448771 # number of InvalidateReq accesses(hits+misses) 201611336Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 588785 # number of demand (read+write) accesses 201711336Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.itb.walker 176753 # number of demand (read+write) accesses 201811336Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.inst 9231824 # number of demand (read+write) accesses 201911336Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.data 4870397 # number of demand (read+write) accesses 202011336Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::total 14867759 # number of demand (read+write) accesses 202111336Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 588785 # number of overall (read+write) accesses 202211336Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.itb.walker 176753 # number of overall (read+write) accesses 202311336Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.inst 9231824 # number of overall (read+write) accesses 202411336Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.data 4870397 # number of overall (read+write) accesses 202511336Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_accesses::total 14867759 # number of overall (read+write) accesses 202611336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.020969 # miss rate for ReadReq accesses 202711336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.048271 # miss rate for ReadReq accesses 202811336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::total 0.027272 # miss rate for ReadReq accesses 202911336Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackDirty_miss_rate::writebacks 0.000000 # miss rate for WritebackDirty accesses 203011336Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackDirty_miss_rate::total 0.000000 # miss rate for WritebackDirty accesses 203111336Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.997432 # miss rate for UpgradeReq accesses 203211336Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_miss_rate::total 0.997432 # miss rate for UpgradeReq accesses 203311201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses 203411201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 203510636Snilay@cs.wisc.edusystem.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses 203610585Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 203711336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.224878 # miss rate for ReadExReq accesses 203811336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_miss_rate::total 0.224878 # miss rate for ReadExReq accesses 203911336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.074364 # miss rate for ReadCleanReq accesses 204011336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.074364 # miss rate for ReadCleanReq accesses 204111336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.258574 # miss rate for ReadSharedReq accesses 204211336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.258574 # miss rate for ReadSharedReq accesses 204311336Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.595475 # miss rate for InvalidateReq accesses 204411336Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_miss_rate::total 0.595475 # miss rate for InvalidateReq accesses 204511336Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.020969 # miss rate for demand accesses 204611336Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.048271 # miss rate for demand accesses 204711336Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.074364 # miss rate for demand accesses 204811336Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.data 0.250832 # miss rate for demand accesses 204911336Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_rate::total 0.129747 # miss rate for demand accesses 205011336Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.020969 # miss rate for overall accesses 205111336Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.048271 # miss rate for overall accesses 205211336Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.074364 # miss rate for overall accesses 205311336Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.data 0.250832 # miss rate for overall accesses 205411336Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::total 0.129747 # miss rate for overall accesses 205511336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 48550.745181 # average ReadReq miss latency 205611336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 53930.203938 # average ReadReq miss latency 205711336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_miss_latency::total 50749.113900 # average ReadReq miss latency 205811336Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 14762.414761 # average UpgradeReq miss latency 205911336Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 14762.414761 # average UpgradeReq miss latency 206011336Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 9212.847782 # average SCUpgradeReq miss latency 206111336Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 9212.847782 # average SCUpgradeReq miss latency 206211336Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 930699.800000 # average SCUpgradeFailReq miss latency 206311336Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 930699.800000 # average SCUpgradeFailReq miss latency 206411336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 58575.173165 # average ReadExReq miss latency 206511336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_avg_miss_latency::total 58575.173165 # average ReadExReq miss latency 206611336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 35602.572693 # average ReadCleanReq miss latency 206711336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 35602.572693 # average ReadCleanReq miss latency 206811336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 39148.132540 # average ReadSharedReq miss latency 206911336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 39148.132540 # average ReadSharedReq miss latency 207011336Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 70362.273231 # average InvalidateReq miss latency 207111336Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 70362.273231 # average InvalidateReq miss latency 207211336Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 48550.745181 # average overall miss latency 207311336Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 53930.203938 # average overall miss latency 207411336Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 35602.572693 # average overall miss latency 207511336Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 43149.764000 # average overall miss latency 207611336Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_miss_latency::total 40546.084125 # average overall miss latency 207711336Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 48550.745181 # average overall miss latency 207811336Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 53930.203938 # average overall miss latency 207911336Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 35602.572693 # average overall miss latency 208011336Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 43149.764000 # average overall miss latency 208111336Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_miss_latency::total 40546.084125 # average overall miss latency 208210628Sandreas.hansson@arm.comsystem.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 208310585Sandreas.hansson@arm.comsystem.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 208410628Sandreas.hansson@arm.comsystem.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 208510585Sandreas.hansson@arm.comsystem.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 208610628Sandreas.hansson@arm.comsystem.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 208710585Sandreas.hansson@arm.comsystem.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 208810585Sandreas.hansson@arm.comsystem.cpu1.l2cache.fast_writes 0 # number of fast writes performed 208910585Sandreas.hansson@arm.comsystem.cpu1.l2cache.cache_copies 0 # number of cache copies performed 209011336Sandreas.hansson@arm.comsystem.cpu1.l2cache.writebacks::writebacks 1166062 # number of writebacks 209111336Sandreas.hansson@arm.comsystem.cpu1.l2cache.writebacks::total 1166062 # number of writebacks 209211336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 2 # number of ReadReq MSHR hits 209311336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_hits::total 2 # number of ReadReq MSHR hits 209411336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 8177 # number of ReadExReq MSHR hits 209511336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_hits::total 8177 # number of ReadExReq MSHR hits 209611336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst 4 # number of ReadCleanReq MSHR hits 209711336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_mshr_hits::total 4 # number of ReadCleanReq MSHR hits 209811336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 786 # number of ReadSharedReq MSHR hits 209911336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_hits::total 786 # number of ReadSharedReq MSHR hits 210011336Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_hits::cpu1.data 3 # number of InvalidateReq MSHR hits 210111336Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_hits::total 3 # number of InvalidateReq MSHR hits 210211336Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 2 # number of demand (read+write) MSHR hits 210311336Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_hits::cpu1.inst 4 # number of demand (read+write) MSHR hits 210411336Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_hits::cpu1.data 8963 # number of demand (read+write) MSHR hits 210511336Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_hits::total 8969 # number of demand (read+write) MSHR hits 210611336Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 2 # number of overall MSHR hits 210711336Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_hits::cpu1.inst 4 # number of overall MSHR hits 210811336Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_hits::cpu1.data 8963 # number of overall MSHR hits 210911336Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_hits::total 8969 # number of overall MSHR hits 211011336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 12346 # number of ReadReq MSHR misses 211111336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 8530 # number of ReadReq MSHR misses 211211336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_misses::total 20876 # number of ReadReq MSHR misses 211311336Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackDirty_mshr_misses::writebacks 1 # number of WritebackDirty MSHR misses 211411336Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackDirty_mshr_misses::total 1 # number of WritebackDirty MSHR misses 211511336Sandreas.hansson@arm.comsystem.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 757140 # number of HardPFReq MSHR misses 211611336Sandreas.hansson@arm.comsystem.cpu1.l2cache.HardPFReq_mshr_misses::total 757140 # number of HardPFReq MSHR misses 211711336Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 223343 # number of UpgradeReq MSHR misses 211811336Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_mshr_misses::total 223343 # number of UpgradeReq MSHR misses 211911336Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 201132 # number of SCUpgradeReq MSHR misses 212011336Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 201132 # number of SCUpgradeReq MSHR misses 212111336Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 5 # number of SCUpgradeFailReq MSHR misses 212211336Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 5 # number of SCUpgradeFailReq MSHR misses 212311336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 243462 # number of ReadExReq MSHR misses 212411336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_misses::total 243462 # number of ReadExReq MSHR misses 212511336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 686514 # number of ReadCleanReq MSHR misses 212611336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_mshr_misses::total 686514 # number of ReadCleanReq MSHR misses 212711336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 969227 # number of ReadSharedReq MSHR misses 212811336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_misses::total 969227 # number of ReadSharedReq MSHR misses 212911336Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data 267229 # number of InvalidateReq MSHR misses 213011336Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_misses::total 267229 # number of InvalidateReq MSHR misses 213111336Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 12346 # number of demand (read+write) MSHR misses 213211336Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 8530 # number of demand (read+write) MSHR misses 213311336Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_misses::cpu1.inst 686514 # number of demand (read+write) MSHR misses 213411336Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_misses::cpu1.data 1212689 # number of demand (read+write) MSHR misses 213511336Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_misses::total 1920079 # number of demand (read+write) MSHR misses 213611336Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 12346 # number of overall MSHR misses 213711336Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 8530 # number of overall MSHR misses 213811336Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_misses::cpu1.inst 686514 # number of overall MSHR misses 213911336Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_misses::cpu1.data 1212689 # number of overall MSHR misses 214011336Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 757140 # number of overall MSHR misses 214111336Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_misses::total 2677219 # number of overall MSHR misses 214211138Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 92 # number of ReadReq MSHR uncacheable 214311336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 19129 # number of ReadReq MSHR uncacheable 214411336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable::total 19221 # number of ReadReq MSHR uncacheable 214511336Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 17467 # number of WriteReq MSHR uncacheable 214611336Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteReq_mshr_uncacheable::total 17467 # number of WriteReq MSHR uncacheable 214711138Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 92 # number of overall MSHR uncacheable misses 214811336Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 36596 # number of overall MSHR uncacheable misses 214911336Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_uncacheable_misses::total 36688 # number of overall MSHR uncacheable misses 215011336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 525331500 # number of ReadReq MSHR miss cycles 215111336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 408923500 # number of ReadReq MSHR miss cycles 215211336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_latency::total 934255000 # number of ReadReq MSHR miss cycles 215311336Sandreas.hansson@arm.comsystem.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 45309762891 # number of HardPFReq MSHR miss cycles 215411336Sandreas.hansson@arm.comsystem.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 45309762891 # number of HardPFReq MSHR miss cycles 215511336Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 7082960998 # number of UpgradeReq MSHR miss cycles 215611336Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 7082960998 # number of UpgradeReq MSHR miss cycles 215711336Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 3799999000 # number of SCUpgradeReq MSHR miss cycles 215811336Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 3799999000 # number of SCUpgradeReq MSHR miss cycles 215911336Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 4287499 # number of SCUpgradeFailReq MSHR miss cycles 216011336Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 4287499 # number of SCUpgradeFailReq MSHR miss cycles 216111336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 11990250000 # number of ReadExReq MSHR miss cycles 216211336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 11990250000 # number of ReadExReq MSHR miss cycles 216311336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 20322650500 # number of ReadCleanReq MSHR miss cycles 216411336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 20322650500 # number of ReadCleanReq MSHR miss cycles 216511336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 32101541990 # number of ReadSharedReq MSHR miss cycles 216611336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 32101541990 # number of ReadSharedReq MSHR miss cycles 216711336Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 17199481500 # number of InvalidateReq MSHR miss cycles 216811336Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 17199481500 # number of InvalidateReq MSHR miss cycles 216911336Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 525331500 # number of demand (read+write) MSHR miss cycles 217011336Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 408923500 # number of demand (read+write) MSHR miss cycles 217111336Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 20322650500 # number of demand (read+write) MSHR miss cycles 217211336Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 44091791990 # number of demand (read+write) MSHR miss cycles 217311336Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_latency::total 65348697490 # number of demand (read+write) MSHR miss cycles 217411336Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 525331500 # number of overall MSHR miss cycles 217511336Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 408923500 # number of overall MSHR miss cycles 217611336Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 20322650500 # number of overall MSHR miss cycles 217711336Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 44091791990 # number of overall MSHR miss cycles 217811336Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 45309762891 # number of overall MSHR miss cycles 217911336Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_latency::total 110658460381 # number of overall MSHR miss cycles 218011201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 12214500 # number of ReadReq MSHR uncacheable cycles 218111336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 2998478000 # number of ReadReq MSHR uncacheable cycles 218211336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 3010692500 # number of ReadReq MSHR uncacheable cycles 218311336Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 2831799500 # number of WriteReq MSHR uncacheable cycles 218411336Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 2831799500 # number of WriteReq MSHR uncacheable cycles 218511201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 12214500 # number of overall MSHR uncacheable cycles 218611336Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 5830277500 # number of overall MSHR uncacheable cycles 218711336Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_uncacheable_latency::total 5842492000 # number of overall MSHR uncacheable cycles 218811336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.020969 # mshr miss rate for ReadReq accesses 218911336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.048259 # mshr miss rate for ReadReq accesses 219011336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.027270 # mshr miss rate for ReadReq accesses 219111336Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackDirty_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for WritebackDirty accesses 219211336Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackDirty_mshr_miss_rate::total 0.000000 # mshr miss rate for WritebackDirty accesses 219310585Sandreas.hansson@arm.comsystem.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 219410585Sandreas.hansson@arm.comsystem.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 219511336Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.997432 # mshr miss rate for UpgradeReq accesses 219611336Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.997432 # mshr miss rate for UpgradeReq accesses 219711201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses 219811201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 219910636Snilay@cs.wisc.edusystem.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses 220010585Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 220111336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.217571 # mshr miss rate for ReadExReq accesses 220211336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.217571 # mshr miss rate for ReadExReq accesses 220311336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.074364 # mshr miss rate for ReadCleanReq accesses 220411336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.074364 # mshr miss rate for ReadCleanReq accesses 220511336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.258364 # mshr miss rate for ReadSharedReq accesses 220611336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.258364 # mshr miss rate for ReadSharedReq accesses 220711336Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.595469 # mshr miss rate for InvalidateReq accesses 220811336Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.595469 # mshr miss rate for InvalidateReq accesses 220911336Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.020969 # mshr miss rate for demand accesses 221011336Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.048259 # mshr miss rate for demand accesses 221111336Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.074364 # mshr miss rate for demand accesses 221211336Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.248992 # mshr miss rate for demand accesses 221311336Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_rate::total 0.129144 # mshr miss rate for demand accesses 221411336Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.020969 # mshr miss rate for overall accesses 221511336Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.048259 # mshr miss rate for overall accesses 221611336Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.074364 # mshr miss rate for overall accesses 221711336Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.248992 # mshr miss rate for overall accesses 221810585Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses 221911336Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_rate::total 0.180069 # mshr miss rate for overall accesses 222011336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 42550.745181 # average ReadReq mshr miss latency 222111336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 47939.449004 # average ReadReq mshr miss latency 222211336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 44752.586702 # average ReadReq mshr miss latency 222311336Sandreas.hansson@arm.comsystem.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 59843.308887 # average HardPFReq mshr miss latency 222411336Sandreas.hansson@arm.comsystem.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 59843.308887 # average HardPFReq mshr miss latency 222511336Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 31713.378069 # average UpgradeReq mshr miss latency 222611336Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31713.378069 # average UpgradeReq mshr miss latency 222711336Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18893.060279 # average SCUpgradeReq mshr miss latency 222811336Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18893.060279 # average SCUpgradeReq mshr miss latency 222911336Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 857499.800000 # average SCUpgradeFailReq mshr miss latency 223011336Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 857499.800000 # average SCUpgradeFailReq mshr miss latency 223111336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 49248.958770 # average ReadExReq mshr miss latency 223211336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 49248.958770 # average ReadExReq mshr miss latency 223311336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 29602.674527 # average ReadCleanReq mshr miss latency 223411336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 29602.674527 # average ReadCleanReq mshr miss latency 223511336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 33120.767364 # average ReadSharedReq mshr miss latency 223611336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 33120.767364 # average ReadSharedReq mshr miss latency 223711336Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 64362.331558 # average InvalidateReq mshr miss latency 223811336Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 64362.331558 # average InvalidateReq mshr miss latency 223911336Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 42550.745181 # average overall mshr miss latency 224011336Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 47939.449004 # average overall mshr miss latency 224111336Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 29602.674527 # average overall mshr miss latency 224211336Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 36358.697069 # average overall mshr miss latency 224311336Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_mshr_miss_latency::total 34034.379570 # average overall mshr miss latency 224411336Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 42550.745181 # average overall mshr miss latency 224511336Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 47939.449004 # average overall mshr miss latency 224611336Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 29602.674527 # average overall mshr miss latency 224711336Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 36358.697069 # average overall mshr miss latency 224811336Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 59843.308887 # average overall mshr miss latency 224911336Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::total 41333.361365 # average overall mshr miss latency 225011201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 132766.304348 # average ReadReq mshr uncacheable latency 225111336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 156750.379006 # average ReadReq mshr uncacheable latency 225211336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 156635.580875 # average ReadReq mshr uncacheable latency 225311336Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 162122.831625 # average WriteReq mshr uncacheable latency 225411336Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 162122.831625 # average WriteReq mshr uncacheable latency 225511201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 132766.304348 # average overall mshr uncacheable latency 225611336Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 159314.610886 # average overall mshr uncacheable latency 225711336Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 159248.037505 # average overall mshr uncacheable latency 225810585Sandreas.hansson@arm.comsystem.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 225911336Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_filter.tot_requests 29757775 # Total number of requests made to the snoop filter. 226011336Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_filter.hit_single_requests 15206900 # Number of requests hitting in the snoop filter with a single holder of the requested data. 226111336Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_filter.hit_multi_requests 2197 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 226211336Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_filter.tot_snoops 2096240 # Total number of snoops made to the snoop filter. 226311336Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_filter.hit_single_snoops 2095918 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 226411336Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 322 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 226511336Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadReq 863744 # Transaction distribution 226611336Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadResp 13939008 # Transaction distribution 226711336Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution 226811336Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::WriteReq 17467 # Transaction distribution 226911336Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::WriteResp 17467 # Transaction distribution 227011336Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::WritebackDirty 4436321 # Transaction distribution 227111336Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::WritebackClean 11191891 # Transaction distribution 227211336Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::CleanEvict 2888082 # Transaction distribution 227311336Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::HardPFReq 986942 # Transaction distribution 227411336Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution 227511336Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::UpgradeReq 436269 # Transaction distribution 227611336Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::SCUpgradeReq 365311 # Transaction distribution 227711336Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::UpgradeResp 490098 # Transaction distribution 227811336Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 60 # Transaction distribution 227911336Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::UpgradeFailResp 116 # Transaction distribution 228011336Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadExReq 1199193 # Transaction distribution 228111336Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadExResp 1126648 # Transaction distribution 228211336Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadCleanReq 9231824 # Transaction distribution 228311336Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadSharedReq 4839539 # Transaction distribution 228411336Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::InvalidateReq 455831 # Transaction distribution 228511336Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::InvalidateResp 448771 # Transaction distribution 228611336Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 27695142 # Packet count per connected master and slave (bytes) 228711336Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16951918 # Packet count per connected master and slave (bytes) 228811336Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 371352 # Packet count per connected master and slave (bytes) 228911336Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1238709 # Packet count per connected master and slave (bytes) 229011336Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count::total 46257121 # Packet count per connected master and slave (bytes) 229111336Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1181646464 # Cumulative packet size per connected master and slave (bytes) 229211336Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 652642726 # Cumulative packet size per connected master and slave (bytes) 229311336Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1414024 # Cumulative packet size per connected master and slave (bytes) 229411336Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4710280 # Cumulative packet size per connected master and slave (bytes) 229511336Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size::total 1840413494 # Cumulative packet size per connected master and slave (bytes) 229611336Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoops 6842316 # Total snoops (count) 229711336Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::samples 22455736 # Request fanout histogram 229811336Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::mean 0.107935 # Request fanout histogram 229911336Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::stdev 0.310344 # Request fanout histogram 230010585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 230111336Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::0 20032307 89.21% 89.21% # Request fanout histogram 230211336Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::1 2423107 10.79% 100.00% # Request fanout histogram 230311336Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::2 322 0.00% 100.00% # Request fanout histogram 230410585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 230511138Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 230610827Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 230711336Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::total 22455736 # Request fanout histogram 230811336Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.reqLayer0.occupancy 29622476486 # Layer occupancy (ticks) 230911201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 231011336Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoopLayer0.occupancy 182393833 # Layer occupancy (ticks) 231110585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 231211336Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.respLayer0.occupancy 13851399924 # Layer occupancy (ticks) 231310585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 231411336Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.respLayer1.occupancy 7774596662 # Layer occupancy (ticks) 231510585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 231611336Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.respLayer2.occupancy 194664868 # Layer occupancy (ticks) 231710585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 231811336Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.respLayer3.occupancy 650073200 # Layer occupancy (ticks) 231910585Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 232011336Sandreas.hansson@arm.comsystem.iobus.trans_dist::ReadReq 40417 # Transaction distribution 232111336Sandreas.hansson@arm.comsystem.iobus.trans_dist::ReadResp 40417 # Transaction distribution 232211336Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteReq 136988 # Transaction distribution 232311336Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteResp 136988 # Transaction distribution 232411336Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47856 # Packet count per connected master and slave (bytes) 232510585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 232611245Sandreas.sandberg@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 232710585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) 232810585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) 232910585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 233010585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 233110585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 233210585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 233310585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) 233410585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 233511201Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29808 # Packet count per connected master and slave (bytes) 233610585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) 233711336Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::total 122998 # Packet count per connected master and slave (bytes) 233811336Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231732 # Packet count per connected master and slave (bytes) 233911336Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.realview.ide.dma::total 231732 # Packet count per connected master and slave (bytes) 234010585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) 234110585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) 234211336Sandreas.hansson@arm.comsystem.iobus.pkt_count::total 354810 # Packet count per connected master and slave (bytes) 234311336Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47876 # Cumulative packet size per connected master and slave (bytes) 234410585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) 234511245Sandreas.sandberg@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) 234610585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) 234710585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) 234810585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 234910585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 235010585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 235110585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 235210585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) 235310585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 235411201Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17703 # Cumulative packet size per connected master and slave (bytes) 235510585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) 235611336Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::total 156013 # Cumulative packet size per connected master and slave (bytes) 235711336Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7355280 # Cumulative packet size per connected master and slave (bytes) 235811336Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.realview.ide.dma::total 7355280 # Cumulative packet size per connected master and slave (bytes) 235910585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 236010585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) 236111336Sandreas.hansson@arm.comsystem.iobus.pkt_size::total 7513379 # Cumulative packet size per connected master and slave (bytes) 236211336Sandreas.hansson@arm.comsystem.iobus.reqLayer0.occupancy 47192501 # Layer occupancy (ticks) 236310585Sandreas.hansson@arm.comsystem.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 236411336Sandreas.hansson@arm.comsystem.iobus.reqLayer1.occupancy 12000 # Layer occupancy (ticks) 236510585Sandreas.hansson@arm.comsystem.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 236611336Sandreas.hansson@arm.comsystem.iobus.reqLayer2.occupancy 324000 # Layer occupancy (ticks) 236710585Sandreas.hansson@arm.comsystem.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 236811245Sandreas.sandberg@arm.comsystem.iobus.reqLayer3.occupancy 9500 # Layer occupancy (ticks) 236910585Sandreas.hansson@arm.comsystem.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 237011336Sandreas.hansson@arm.comsystem.iobus.reqLayer4.occupancy 9500 # Layer occupancy (ticks) 237111245Sandreas.sandberg@arm.comsystem.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 237211336Sandreas.hansson@arm.comsystem.iobus.reqLayer10.occupancy 10000 # Layer occupancy (ticks) 237310585Sandreas.hansson@arm.comsystem.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 237411336Sandreas.hansson@arm.comsystem.iobus.reqLayer13.occupancy 10500 # Layer occupancy (ticks) 237510585Sandreas.hansson@arm.comsystem.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 237611336Sandreas.hansson@arm.comsystem.iobus.reqLayer14.occupancy 9000 # Layer occupancy (ticks) 237710585Sandreas.hansson@arm.comsystem.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 237811336Sandreas.hansson@arm.comsystem.iobus.reqLayer15.occupancy 9500 # Layer occupancy (ticks) 237910585Sandreas.hansson@arm.comsystem.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 238011201Sandreas.hansson@arm.comsystem.iobus.reqLayer16.occupancy 15500 # Layer occupancy (ticks) 238110585Sandreas.hansson@arm.comsystem.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 238211336Sandreas.hansson@arm.comsystem.iobus.reqLayer17.occupancy 9500 # Layer occupancy (ticks) 238310585Sandreas.hansson@arm.comsystem.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 238411336Sandreas.hansson@arm.comsystem.iobus.reqLayer23.occupancy 26190001 # Layer occupancy (ticks) 238510585Sandreas.hansson@arm.comsystem.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 238611336Sandreas.hansson@arm.comsystem.iobus.reqLayer24.occupancy 36429000 # Layer occupancy (ticks) 238710585Sandreas.hansson@arm.comsystem.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 238811336Sandreas.hansson@arm.comsystem.iobus.reqLayer25.occupancy 568769538 # Layer occupancy (ticks) 238910585Sandreas.hansson@arm.comsystem.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 239011336Sandreas.hansson@arm.comsystem.iobus.respLayer0.occupancy 92997000 # Layer occupancy (ticks) 239110585Sandreas.hansson@arm.comsystem.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 239211336Sandreas.hansson@arm.comsystem.iobus.respLayer3.occupancy 148172000 # Layer occupancy (ticks) 239310585Sandreas.hansson@arm.comsystem.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 239410892Sandreas.hansson@arm.comsystem.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) 239510585Sandreas.hansson@arm.comsystem.iobus.respLayer4.utilization 0.0 # Layer utilization (%) 239611336Sandreas.hansson@arm.comsystem.iocache.tags.replacements 115847 # number of replacements 239711336Sandreas.hansson@arm.comsystem.iocache.tags.tagsinuse 11.301670 # Cycle average of tags in use 239811336Sandreas.hansson@arm.comsystem.iocache.tags.total_refs 3 # Total number of references to valid blocks. 239911336Sandreas.hansson@arm.comsystem.iocache.tags.sampled_refs 115863 # Sample count of references to valid blocks. 240011336Sandreas.hansson@arm.comsystem.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. 240111336Sandreas.hansson@arm.comsystem.iocache.tags.warmup_cycle 9145489939000 # Cycle when the warmup percentage was hit. 240211336Sandreas.hansson@arm.comsystem.iocache.tags.occ_blocks::realview.ethernet 3.832621 # Average occupied blocks per requestor 240311336Sandreas.hansson@arm.comsystem.iocache.tags.occ_blocks::realview.ide 7.469049 # Average occupied blocks per requestor 240411336Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::realview.ethernet 0.239539 # Average percentage of cache occupancy 240511336Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::realview.ide 0.466816 # Average percentage of cache occupancy 240611336Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::total 0.706354 # Average percentage of cache occupancy 240710585Sandreas.hansson@arm.comsystem.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 240810827Sandreas.hansson@arm.comsystem.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 240910585Sandreas.hansson@arm.comsystem.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 241011336Sandreas.hansson@arm.comsystem.iocache.tags.tag_accesses 1043151 # Number of tag accesses 241111336Sandreas.hansson@arm.comsystem.iocache.tags.data_accesses 1043151 # Number of data accesses 241210585Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses 241311336Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::realview.ide 8882 # number of ReadReq misses 241411336Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::total 8919 # number of ReadReq misses 241510585Sandreas.hansson@arm.comsystem.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 241610585Sandreas.hansson@arm.comsystem.iocache.WriteReq_misses::total 3 # number of WriteReq misses 241711336Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_misses::realview.ide 106984 # number of WriteLineReq misses 241811336Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_misses::total 106984 # number of WriteLineReq misses 241910585Sandreas.hansson@arm.comsystem.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses 242011336Sandreas.hansson@arm.comsystem.iocache.demand_misses::realview.ide 8882 # number of demand (read+write) misses 242111336Sandreas.hansson@arm.comsystem.iocache.demand_misses::total 8922 # number of demand (read+write) misses 242210585Sandreas.hansson@arm.comsystem.iocache.overall_misses::realview.ethernet 40 # number of overall misses 242311336Sandreas.hansson@arm.comsystem.iocache.overall_misses::realview.ide 8882 # number of overall misses 242411336Sandreas.hansson@arm.comsystem.iocache.overall_misses::total 8922 # number of overall misses 242511336Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_latency::realview.ethernet 5198000 # number of ReadReq miss cycles 242611336Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_latency::realview.ide 1701700997 # number of ReadReq miss cycles 242711336Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_latency::total 1706898997 # number of ReadReq miss cycles 242810726Sandreas.hansson@arm.comsystem.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles 242910726Sandreas.hansson@arm.comsystem.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles 243011336Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_latency::realview.ide 13567134541 # number of WriteLineReq miss cycles 243111336Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_latency::total 13567134541 # number of WriteLineReq miss cycles 243211336Sandreas.hansson@arm.comsystem.iocache.demand_miss_latency::realview.ethernet 5567000 # number of demand (read+write) miss cycles 243311336Sandreas.hansson@arm.comsystem.iocache.demand_miss_latency::realview.ide 1701700997 # number of demand (read+write) miss cycles 243411336Sandreas.hansson@arm.comsystem.iocache.demand_miss_latency::total 1707267997 # number of demand (read+write) miss cycles 243511336Sandreas.hansson@arm.comsystem.iocache.overall_miss_latency::realview.ethernet 5567000 # number of overall miss cycles 243611336Sandreas.hansson@arm.comsystem.iocache.overall_miss_latency::realview.ide 1701700997 # number of overall miss cycles 243711336Sandreas.hansson@arm.comsystem.iocache.overall_miss_latency::total 1707267997 # number of overall miss cycles 243810585Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) 243911336Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::realview.ide 8882 # number of ReadReq accesses(hits+misses) 244011336Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::total 8919 # number of ReadReq accesses(hits+misses) 244110585Sandreas.hansson@arm.comsystem.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 244210585Sandreas.hansson@arm.comsystem.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 244311201Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_accesses::realview.ide 106984 # number of WriteLineReq accesses(hits+misses) 244411201Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_accesses::total 106984 # number of WriteLineReq accesses(hits+misses) 244510585Sandreas.hansson@arm.comsystem.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses 244611336Sandreas.hansson@arm.comsystem.iocache.demand_accesses::realview.ide 8882 # number of demand (read+write) accesses 244711336Sandreas.hansson@arm.comsystem.iocache.demand_accesses::total 8922 # number of demand (read+write) accesses 244810585Sandreas.hansson@arm.comsystem.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses 244911336Sandreas.hansson@arm.comsystem.iocache.overall_accesses::realview.ide 8882 # number of overall (read+write) accesses 245011336Sandreas.hansson@arm.comsystem.iocache.overall_accesses::total 8922 # number of overall (read+write) accesses 245110585Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 245210585Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 245310585Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 245410585Sandreas.hansson@arm.comsystem.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 245510585Sandreas.hansson@arm.comsystem.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 245611336Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 245711336Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 245810585Sandreas.hansson@arm.comsystem.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses 245910585Sandreas.hansson@arm.comsystem.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 246010585Sandreas.hansson@arm.comsystem.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 246110585Sandreas.hansson@arm.comsystem.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses 246210585Sandreas.hansson@arm.comsystem.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 246310585Sandreas.hansson@arm.comsystem.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 246411336Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_miss_latency::realview.ethernet 140486.486486 # average ReadReq miss latency 246511336Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_miss_latency::realview.ide 191589.844292 # average ReadReq miss latency 246611336Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_miss_latency::total 191377.844714 # average ReadReq miss latency 246710726Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency 246810726Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency 246911336Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_avg_miss_latency::realview.ide 126814.612849 # average WriteLineReq miss latency 247011336Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_avg_miss_latency::total 126814.612849 # average WriteLineReq miss latency 247111336Sandreas.hansson@arm.comsystem.iocache.demand_avg_miss_latency::realview.ethernet 139175 # average overall miss latency 247211336Sandreas.hansson@arm.comsystem.iocache.demand_avg_miss_latency::realview.ide 191589.844292 # average overall miss latency 247311336Sandreas.hansson@arm.comsystem.iocache.demand_avg_miss_latency::total 191354.852836 # average overall miss latency 247411336Sandreas.hansson@arm.comsystem.iocache.overall_avg_miss_latency::realview.ethernet 139175 # average overall miss latency 247511336Sandreas.hansson@arm.comsystem.iocache.overall_avg_miss_latency::realview.ide 191589.844292 # average overall miss latency 247611336Sandreas.hansson@arm.comsystem.iocache.overall_avg_miss_latency::total 191354.852836 # average overall miss latency 247711336Sandreas.hansson@arm.comsystem.iocache.blocked_cycles::no_mshrs 34809 # number of cycles access was blocked 247810585Sandreas.hansson@arm.comsystem.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 247911336Sandreas.hansson@arm.comsystem.iocache.blocked::no_mshrs 3501 # number of cycles access was blocked 248010585Sandreas.hansson@arm.comsystem.iocache.blocked::no_targets 0 # number of cycles access was blocked 248111336Sandreas.hansson@arm.comsystem.iocache.avg_blocked_cycles::no_mshrs 9.942588 # average number of cycles each access was blocked 248210585Sandreas.hansson@arm.comsystem.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 248310585Sandreas.hansson@arm.comsystem.iocache.fast_writes 0 # number of fast writes performed 248410585Sandreas.hansson@arm.comsystem.iocache.cache_copies 0 # number of cache copies performed 248511336Sandreas.hansson@arm.comsystem.iocache.writebacks::writebacks 106950 # number of writebacks 248611336Sandreas.hansson@arm.comsystem.iocache.writebacks::total 106950 # number of writebacks 248710585Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses 248811336Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_misses::realview.ide 8882 # number of ReadReq MSHR misses 248911336Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_misses::total 8919 # number of ReadReq MSHR misses 249010585Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses 249110585Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses 249211336Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_misses::realview.ide 106984 # number of WriteLineReq MSHR misses 249311336Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_misses::total 106984 # number of WriteLineReq MSHR misses 249410585Sandreas.hansson@arm.comsystem.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses 249511336Sandreas.hansson@arm.comsystem.iocache.demand_mshr_misses::realview.ide 8882 # number of demand (read+write) MSHR misses 249611336Sandreas.hansson@arm.comsystem.iocache.demand_mshr_misses::total 8922 # number of demand (read+write) MSHR misses 249710585Sandreas.hansson@arm.comsystem.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses 249811336Sandreas.hansson@arm.comsystem.iocache.overall_mshr_misses::realview.ide 8882 # number of overall MSHR misses 249911336Sandreas.hansson@arm.comsystem.iocache.overall_mshr_misses::total 8922 # number of overall MSHR misses 250011336Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3348000 # number of ReadReq MSHR miss cycles 250111336Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_latency::realview.ide 1257600997 # number of ReadReq MSHR miss cycles 250211336Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_latency::total 1260948997 # number of ReadReq MSHR miss cycles 250310892Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles 250410892Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles 250511336Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8211460570 # number of WriteLineReq MSHR miss cycles 250611336Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_miss_latency::total 8211460570 # number of WriteLineReq MSHR miss cycles 250711336Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_latency::realview.ethernet 3567000 # number of demand (read+write) MSHR miss cycles 250811336Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_latency::realview.ide 1257600997 # number of demand (read+write) MSHR miss cycles 250911336Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_latency::total 1261167997 # number of demand (read+write) MSHR miss cycles 251011336Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_latency::realview.ethernet 3567000 # number of overall MSHR miss cycles 251111336Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_latency::realview.ide 1257600997 # number of overall MSHR miss cycles 251211336Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_latency::total 1261167997 # number of overall MSHR miss cycles 251310585Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses 251410585Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 251510585Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 251610585Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses 251710585Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 251811336Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 251911336Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 252010585Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses 252110585Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 252210585Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 252310585Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses 252410585Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 252510585Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 252611336Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90486.486486 # average ReadReq mshr miss latency 252711336Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 141589.844292 # average ReadReq mshr miss latency 252811336Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::total 141377.844714 # average ReadReq mshr miss latency 252910892Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency 253010892Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency 253111336Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 76754.099398 # average WriteLineReq mshr miss latency 253211336Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_avg_mshr_miss_latency::total 76754.099398 # average WriteLineReq mshr miss latency 253311336Sandreas.hansson@arm.comsystem.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89175 # average overall mshr miss latency 253411336Sandreas.hansson@arm.comsystem.iocache.demand_avg_mshr_miss_latency::realview.ide 141589.844292 # average overall mshr miss latency 253511336Sandreas.hansson@arm.comsystem.iocache.demand_avg_mshr_miss_latency::total 141354.852836 # average overall mshr miss latency 253611336Sandreas.hansson@arm.comsystem.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89175 # average overall mshr miss latency 253711336Sandreas.hansson@arm.comsystem.iocache.overall_avg_mshr_miss_latency::realview.ide 141589.844292 # average overall mshr miss latency 253811336Sandreas.hansson@arm.comsystem.iocache.overall_avg_mshr_miss_latency::total 141354.852836 # average overall mshr miss latency 253910585Sandreas.hansson@arm.comsystem.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 254011336Sandreas.hansson@arm.comsystem.l2c.tags.replacements 1465460 # number of replacements 254111336Sandreas.hansson@arm.comsystem.l2c.tags.tagsinuse 62985.288046 # Cycle average of tags in use 254211336Sandreas.hansson@arm.comsystem.l2c.tags.total_refs 6746847 # Total number of references to valid blocks. 254311336Sandreas.hansson@arm.comsystem.l2c.tags.sampled_refs 1525111 # Sample count of references to valid blocks. 254411336Sandreas.hansson@arm.comsystem.l2c.tags.avg_refs 4.423840 # Average number of references to valid blocks. 254510892Sandreas.hansson@arm.comsystem.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 254611336Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::writebacks 21606.771340 # Average occupied blocks per requestor 254711336Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.dtb.walker 163.937701 # Average occupied blocks per requestor 254811336Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.itb.walker 223.248695 # Average occupied blocks per requestor 254911336Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.inst 5669.657556 # Average occupied blocks per requestor 255011336Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.data 6460.370404 # Average occupied blocks per requestor 255111336Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 9729.240754 # Average occupied blocks per requestor 255211336Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.dtb.walker 163.294328 # Average occupied blocks per requestor 255311336Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.itb.walker 204.500397 # Average occupied blocks per requestor 255411336Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.inst 3331.837675 # Average occupied blocks per requestor 255511336Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.data 6323.626930 # Average occupied blocks per requestor 255611336Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 9108.802265 # Average occupied blocks per requestor 255711336Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::writebacks 0.329693 # Average percentage of cache occupancy 255811336Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.dtb.walker 0.002501 # Average percentage of cache occupancy 255911336Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.itb.walker 0.003407 # Average percentage of cache occupancy 256011336Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.inst 0.086512 # Average percentage of cache occupancy 256111336Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.data 0.098577 # Average percentage of cache occupancy 256211336Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.148456 # Average percentage of cache occupancy 256311336Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu1.dtb.walker 0.002492 # Average percentage of cache occupancy 256411336Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu1.itb.walker 0.003120 # Average percentage of cache occupancy 256511336Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu1.inst 0.050840 # Average percentage of cache occupancy 256611336Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu1.data 0.096491 # Average percentage of cache occupancy 256711336Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.138989 # Average percentage of cache occupancy 256811336Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::total 0.961079 # Average percentage of cache occupancy 256911336Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_blocks::1022 9038 # Occupied blocks per task id 257011336Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_blocks::1023 217 # Occupied blocks per task id 257111336Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_blocks::1024 50396 # Occupied blocks per task id 257211336Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1022::1 130 # Occupied blocks per task id 257311336Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1022::2 134 # Occupied blocks per task id 257411336Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1022::3 1705 # Occupied blocks per task id 257511336Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1022::4 7069 # Occupied blocks per task id 257611336Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id 257711336Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1023::2 6 # Occupied blocks per task id 257811336Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1023::3 23 # Occupied blocks per task id 257911336Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1023::4 187 # Occupied blocks per task id 258011336Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id 258111336Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::1 313 # Occupied blocks per task id 258211336Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::2 2486 # Occupied blocks per task id 258311336Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::3 12173 # Occupied blocks per task id 258411336Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::4 35392 # Occupied blocks per task id 258511336Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_percent::1022 0.137909 # Percentage of cache occupancy per task id 258611336Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_percent::1023 0.003311 # Percentage of cache occupancy per task id 258711336Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_percent::1024 0.768982 # Percentage of cache occupancy per task id 258811336Sandreas.hansson@arm.comsystem.l2c.tags.tag_accesses 82649960 # Number of tag accesses 258911336Sandreas.hansson@arm.comsystem.l2c.tags.data_accesses 82649960 # Number of data accesses 259011336Sandreas.hansson@arm.comsystem.l2c.WritebackDirty_hits::writebacks 2868119 # number of WritebackDirty hits 259111336Sandreas.hansson@arm.comsystem.l2c.WritebackDirty_hits::total 2868119 # number of WritebackDirty hits 259211336Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_hits::cpu0.data 181384 # number of UpgradeReq hits 259311336Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_hits::cpu1.data 131978 # number of UpgradeReq hits 259411336Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_hits::total 313362 # number of UpgradeReq hits 259511336Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_hits::cpu0.data 45809 # number of SCUpgradeReq hits 259611336Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_hits::cpu1.data 40059 # number of SCUpgradeReq hits 259711336Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_hits::total 85868 # number of SCUpgradeReq hits 259811336Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::cpu0.data 200580 # number of ReadExReq hits 259911336Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::cpu1.data 165707 # number of ReadExReq hits 260011336Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::total 366287 # number of ReadExReq hits 260111336Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.dtb.walker 7480 # number of ReadSharedReq hits 260211336Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.itb.walker 5183 # number of ReadSharedReq hits 260311336Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.inst 699361 # number of ReadSharedReq hits 260411336Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.data 660994 # number of ReadSharedReq hits 260511336Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 342500 # number of ReadSharedReq hits 260611336Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.dtb.walker 6176 # number of ReadSharedReq hits 260711336Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.itb.walker 4038 # number of ReadSharedReq hits 260811336Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.inst 639412 # number of ReadSharedReq hits 260911336Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.data 580820 # number of ReadSharedReq hits 261011336Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 295958 # number of ReadSharedReq hits 261111336Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::total 3241922 # number of ReadSharedReq hits 261211336Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.dtb.walker 7480 # number of demand (read+write) hits 261311336Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.itb.walker 5183 # number of demand (read+write) hits 261411336Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.inst 699361 # number of demand (read+write) hits 261511336Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.data 861574 # number of demand (read+write) hits 261611336Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.l2cache.prefetcher 342500 # number of demand (read+write) hits 261711336Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.dtb.walker 6176 # number of demand (read+write) hits 261811336Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.itb.walker 4038 # number of demand (read+write) hits 261911336Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.inst 639412 # number of demand (read+write) hits 262011336Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.data 746527 # number of demand (read+write) hits 262111336Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.l2cache.prefetcher 295958 # number of demand (read+write) hits 262211336Sandreas.hansson@arm.comsystem.l2c.demand_hits::total 3608209 # number of demand (read+write) hits 262311336Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.dtb.walker 7480 # number of overall hits 262411336Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.itb.walker 5183 # number of overall hits 262511336Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.inst 699361 # number of overall hits 262611336Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.data 861574 # number of overall hits 262711336Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.l2cache.prefetcher 342500 # number of overall hits 262811336Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.dtb.walker 6176 # number of overall hits 262911336Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.itb.walker 4038 # number of overall hits 263011336Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.inst 639412 # number of overall hits 263111336Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.data 746527 # number of overall hits 263211336Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.l2cache.prefetcher 295958 # number of overall hits 263311336Sandreas.hansson@arm.comsystem.l2c.overall_hits::total 3608209 # number of overall hits 263411336Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_misses::cpu0.data 61552 # number of UpgradeReq misses 263511336Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_misses::cpu1.data 61783 # number of UpgradeReq misses 263611336Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_misses::total 123335 # number of UpgradeReq misses 263711336Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_misses::cpu0.data 12334 # number of SCUpgradeReq misses 263811336Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_misses::cpu1.data 11273 # number of SCUpgradeReq misses 263911336Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_misses::total 23607 # number of SCUpgradeReq misses 264011336Sandreas.hansson@arm.comsystem.l2c.ReadExReq_misses::cpu0.data 493827 # number of ReadExReq misses 264111336Sandreas.hansson@arm.comsystem.l2c.ReadExReq_misses::cpu1.data 156178 # number of ReadExReq misses 264211336Sandreas.hansson@arm.comsystem.l2c.ReadExReq_misses::total 650005 # number of ReadExReq misses 264311336Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.dtb.walker 2015 # number of ReadSharedReq misses 264411336Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.itb.walker 1763 # number of ReadSharedReq misses 264511336Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.inst 75880 # number of ReadSharedReq misses 264611336Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.data 147884 # number of ReadSharedReq misses 264711336Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 232018 # number of ReadSharedReq misses 264811336Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.dtb.walker 2405 # number of ReadSharedReq misses 264911336Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.itb.walker 2064 # number of ReadSharedReq misses 265011336Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.inst 47101 # number of ReadSharedReq misses 265111336Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.data 114695 # number of ReadSharedReq misses 265211336Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 237376 # number of ReadSharedReq misses 265311336Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::total 863201 # number of ReadSharedReq misses 265411336Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.dtb.walker 2015 # number of demand (read+write) misses 265511336Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.itb.walker 1763 # number of demand (read+write) misses 265611336Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.inst 75880 # number of demand (read+write) misses 265711336Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.data 641711 # number of demand (read+write) misses 265811336Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.l2cache.prefetcher 232018 # number of demand (read+write) misses 265911336Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.dtb.walker 2405 # number of demand (read+write) misses 266011336Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.itb.walker 2064 # number of demand (read+write) misses 266111336Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.inst 47101 # number of demand (read+write) misses 266211336Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.data 270873 # number of demand (read+write) misses 266311336Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.l2cache.prefetcher 237376 # number of demand (read+write) misses 266411336Sandreas.hansson@arm.comsystem.l2c.demand_misses::total 1513206 # number of demand (read+write) misses 266511336Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.dtb.walker 2015 # number of overall misses 266611336Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.itb.walker 1763 # number of overall misses 266711336Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.inst 75880 # number of overall misses 266811336Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.data 641711 # number of overall misses 266911336Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.l2cache.prefetcher 232018 # number of overall misses 267011336Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.dtb.walker 2405 # number of overall misses 267111336Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.itb.walker 2064 # number of overall misses 267211336Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.inst 47101 # number of overall misses 267311336Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.data 270873 # number of overall misses 267411336Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.l2cache.prefetcher 237376 # number of overall misses 267511336Sandreas.hansson@arm.comsystem.l2c.overall_misses::total 1513206 # number of overall misses 267611336Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_latency::cpu0.data 1080728500 # number of UpgradeReq miss cycles 267711336Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_latency::cpu1.data 1074141000 # number of UpgradeReq miss cycles 267811336Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_latency::total 2154869500 # number of UpgradeReq miss cycles 267911336Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_latency::cpu0.data 192695000 # number of SCUpgradeReq miss cycles 268011336Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_latency::cpu1.data 205559500 # number of SCUpgradeReq miss cycles 268111336Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_latency::total 398254500 # number of SCUpgradeReq miss cycles 268211336Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_latency::cpu0.data 68952537500 # number of ReadExReq miss cycles 268311336Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_latency::cpu1.data 21260978999 # number of ReadExReq miss cycles 268411336Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_latency::total 90213516499 # number of ReadExReq miss cycles 268511336Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 283038500 # number of ReadSharedReq miss cycles 268611336Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 248472000 # number of ReadSharedReq miss cycles 268711336Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu0.inst 10197968500 # number of ReadSharedReq miss cycles 268811336Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu0.data 20619201500 # number of ReadSharedReq miss cycles 268911336Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 38762108448 # number of ReadSharedReq miss cycles 269011336Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 338612000 # number of ReadSharedReq miss cycles 269111336Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 290311500 # number of ReadSharedReq miss cycles 269211336Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu1.inst 6337057500 # number of ReadSharedReq miss cycles 269311336Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu1.data 16104459500 # number of ReadSharedReq miss cycles 269411336Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 39857778585 # number of ReadSharedReq miss cycles 269511336Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::total 133039008033 # number of ReadSharedReq miss cycles 269611336Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu0.dtb.walker 283038500 # number of demand (read+write) miss cycles 269711336Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu0.itb.walker 248472000 # number of demand (read+write) miss cycles 269811336Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu0.inst 10197968500 # number of demand (read+write) miss cycles 269911336Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu0.data 89571739000 # number of demand (read+write) miss cycles 270011336Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 38762108448 # number of demand (read+write) miss cycles 270111336Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu1.dtb.walker 338612000 # number of demand (read+write) miss cycles 270211336Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu1.itb.walker 290311500 # number of demand (read+write) miss cycles 270311336Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu1.inst 6337057500 # number of demand (read+write) miss cycles 270411336Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu1.data 37365438499 # number of demand (read+write) miss cycles 270511336Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 39857778585 # number of demand (read+write) miss cycles 270611336Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::total 223252524532 # number of demand (read+write) miss cycles 270711336Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu0.dtb.walker 283038500 # number of overall miss cycles 270811336Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu0.itb.walker 248472000 # number of overall miss cycles 270911336Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu0.inst 10197968500 # number of overall miss cycles 271011336Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu0.data 89571739000 # number of overall miss cycles 271111336Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 38762108448 # number of overall miss cycles 271211336Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu1.dtb.walker 338612000 # number of overall miss cycles 271311336Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu1.itb.walker 290311500 # number of overall miss cycles 271411336Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu1.inst 6337057500 # number of overall miss cycles 271511336Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu1.data 37365438499 # number of overall miss cycles 271611336Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 39857778585 # number of overall miss cycles 271711336Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::total 223252524532 # number of overall miss cycles 271811336Sandreas.hansson@arm.comsystem.l2c.WritebackDirty_accesses::writebacks 2868119 # number of WritebackDirty accesses(hits+misses) 271911336Sandreas.hansson@arm.comsystem.l2c.WritebackDirty_accesses::total 2868119 # number of WritebackDirty accesses(hits+misses) 272011336Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_accesses::cpu0.data 242936 # number of UpgradeReq accesses(hits+misses) 272111336Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_accesses::cpu1.data 193761 # number of UpgradeReq accesses(hits+misses) 272211336Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_accesses::total 436697 # number of UpgradeReq accesses(hits+misses) 272311336Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_accesses::cpu0.data 58143 # number of SCUpgradeReq accesses(hits+misses) 272411336Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_accesses::cpu1.data 51332 # number of SCUpgradeReq accesses(hits+misses) 272511336Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_accesses::total 109475 # number of SCUpgradeReq accesses(hits+misses) 272611336Sandreas.hansson@arm.comsystem.l2c.ReadExReq_accesses::cpu0.data 694407 # number of ReadExReq accesses(hits+misses) 272711336Sandreas.hansson@arm.comsystem.l2c.ReadExReq_accesses::cpu1.data 321885 # number of ReadExReq accesses(hits+misses) 272811336Sandreas.hansson@arm.comsystem.l2c.ReadExReq_accesses::total 1016292 # number of ReadExReq accesses(hits+misses) 272911336Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 9495 # number of ReadSharedReq accesses(hits+misses) 273011336Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.itb.walker 6946 # number of ReadSharedReq accesses(hits+misses) 273111336Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.inst 775241 # number of ReadSharedReq accesses(hits+misses) 273211336Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.data 808878 # number of ReadSharedReq accesses(hits+misses) 273311336Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 574518 # number of ReadSharedReq accesses(hits+misses) 273411336Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 8581 # number of ReadSharedReq accesses(hits+misses) 273511336Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.itb.walker 6102 # number of ReadSharedReq accesses(hits+misses) 273611336Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.inst 686513 # number of ReadSharedReq accesses(hits+misses) 273711336Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.data 695515 # number of ReadSharedReq accesses(hits+misses) 273811336Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 533334 # number of ReadSharedReq accesses(hits+misses) 273911336Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::total 4105123 # number of ReadSharedReq accesses(hits+misses) 274011336Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.dtb.walker 9495 # number of demand (read+write) accesses 274111336Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.itb.walker 6946 # number of demand (read+write) accesses 274211336Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.inst 775241 # number of demand (read+write) accesses 274311336Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.data 1503285 # number of demand (read+write) accesses 274411336Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.l2cache.prefetcher 574518 # number of demand (read+write) accesses 274511336Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.dtb.walker 8581 # number of demand (read+write) accesses 274611336Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.itb.walker 6102 # number of demand (read+write) accesses 274711336Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.inst 686513 # number of demand (read+write) accesses 274811336Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.data 1017400 # number of demand (read+write) accesses 274911336Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.l2cache.prefetcher 533334 # number of demand (read+write) accesses 275011336Sandreas.hansson@arm.comsystem.l2c.demand_accesses::total 5121415 # number of demand (read+write) accesses 275111336Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.dtb.walker 9495 # number of overall (read+write) accesses 275211336Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.itb.walker 6946 # number of overall (read+write) accesses 275311336Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.inst 775241 # number of overall (read+write) accesses 275411336Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.data 1503285 # number of overall (read+write) accesses 275511336Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.l2cache.prefetcher 574518 # number of overall (read+write) accesses 275611336Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.dtb.walker 8581 # number of overall (read+write) accesses 275711336Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.itb.walker 6102 # number of overall (read+write) accesses 275811336Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.inst 686513 # number of overall (read+write) accesses 275911336Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.data 1017400 # number of overall (read+write) accesses 276011336Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.l2cache.prefetcher 533334 # number of overall (read+write) accesses 276111336Sandreas.hansson@arm.comsystem.l2c.overall_accesses::total 5121415 # number of overall (read+write) accesses 276211336Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_rate::cpu0.data 0.253367 # miss rate for UpgradeReq accesses 276311336Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_rate::cpu1.data 0.318862 # miss rate for UpgradeReq accesses 276411336Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_rate::total 0.282427 # miss rate for UpgradeReq accesses 276511336Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.212132 # miss rate for SCUpgradeReq accesses 276611336Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.219610 # miss rate for SCUpgradeReq accesses 276711336Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_rate::total 0.215638 # miss rate for SCUpgradeReq accesses 276811336Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_rate::cpu0.data 0.711149 # miss rate for ReadExReq accesses 276911336Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_rate::cpu1.data 0.485198 # miss rate for ReadExReq accesses 277011336Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_rate::total 0.639585 # miss rate for ReadExReq accesses 277111336Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.212217 # miss rate for ReadSharedReq accesses 277211336Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.253815 # miss rate for ReadSharedReq accesses 277311336Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.097879 # miss rate for ReadSharedReq accesses 277411336Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.data 0.182826 # miss rate for ReadSharedReq accesses 277511336Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.403848 # miss rate for ReadSharedReq accesses 277611336Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.280270 # miss rate for ReadSharedReq accesses 277711336Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.338250 # miss rate for ReadSharedReq accesses 277811336Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.068609 # miss rate for ReadSharedReq accesses 277911336Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.data 0.164907 # miss rate for ReadSharedReq accesses 278011336Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.445079 # miss rate for ReadSharedReq accesses 278111336Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::total 0.210274 # miss rate for ReadSharedReq accesses 278211336Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.dtb.walker 0.212217 # miss rate for demand accesses 278311336Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.itb.walker 0.253815 # miss rate for demand accesses 278411336Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.inst 0.097879 # miss rate for demand accesses 278511336Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.data 0.426872 # miss rate for demand accesses 278611336Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.403848 # miss rate for demand accesses 278711336Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.dtb.walker 0.280270 # miss rate for demand accesses 278811336Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.itb.walker 0.338250 # miss rate for demand accesses 278911336Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.inst 0.068609 # miss rate for demand accesses 279011336Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.data 0.266240 # miss rate for demand accesses 279111336Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.445079 # miss rate for demand accesses 279211336Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::total 0.295466 # miss rate for demand accesses 279311336Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.dtb.walker 0.212217 # miss rate for overall accesses 279411336Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.itb.walker 0.253815 # miss rate for overall accesses 279511336Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.inst 0.097879 # miss rate for overall accesses 279611336Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.data 0.426872 # miss rate for overall accesses 279711336Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.403848 # miss rate for overall accesses 279811336Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.dtb.walker 0.280270 # miss rate for overall accesses 279911336Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.itb.walker 0.338250 # miss rate for overall accesses 280011336Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.inst 0.068609 # miss rate for overall accesses 280111336Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.data 0.266240 # miss rate for overall accesses 280211336Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.445079 # miss rate for overall accesses 280311336Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::total 0.295466 # miss rate for overall accesses 280411336Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_avg_miss_latency::cpu0.data 17557.975370 # average UpgradeReq miss latency 280511336Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_avg_miss_latency::cpu1.data 17385.704806 # average UpgradeReq miss latency 280611336Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_avg_miss_latency::total 17471.678761 # average UpgradeReq miss latency 280711336Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 15623.074428 # average SCUpgradeReq miss latency 280811336Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 18234.675774 # average SCUpgradeReq miss latency 280911336Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_avg_miss_latency::total 16870.186809 # average SCUpgradeReq miss latency 281011336Sandreas.hansson@arm.comsystem.l2c.ReadExReq_avg_miss_latency::cpu0.data 139628.933817 # average ReadExReq miss latency 281111336Sandreas.hansson@arm.comsystem.l2c.ReadExReq_avg_miss_latency::cpu1.data 136132.995678 # average ReadExReq miss latency 281211336Sandreas.hansson@arm.comsystem.l2c.ReadExReq_avg_miss_latency::total 138788.957776 # average ReadExReq miss latency 281311336Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 140465.756824 # average ReadSharedReq miss latency 281411336Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 140937.039138 # average ReadSharedReq miss latency 281511336Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 134396.000264 # average ReadSharedReq miss latency 281611336Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 139428.210625 # average ReadSharedReq miss latency 281711336Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 167065.091708 # average ReadSharedReq miss latency 281811336Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 140795.010395 # average ReadSharedReq miss latency 281911336Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 140654.796512 # average ReadSharedReq miss latency 282011336Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 134541.888707 # average ReadSharedReq miss latency 282111336Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 140411.173111 # average ReadSharedReq miss latency 282211336Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 167909.892260 # average ReadSharedReq miss latency 282311336Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::total 154122.861342 # average ReadSharedReq miss latency 282411336Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu0.dtb.walker 140465.756824 # average overall miss latency 282511336Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu0.itb.walker 140937.039138 # average overall miss latency 282611336Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu0.inst 134396.000264 # average overall miss latency 282711336Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu0.data 139582.676625 # average overall miss latency 282811336Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 167065.091708 # average overall miss latency 282911336Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu1.dtb.walker 140795.010395 # average overall miss latency 283011336Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu1.itb.walker 140654.796512 # average overall miss latency 283111336Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu1.inst 134541.888707 # average overall miss latency 283211336Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu1.data 137944.492434 # average overall miss latency 283311336Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 167909.892260 # average overall miss latency 283411336Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::total 147536.108456 # average overall miss latency 283511336Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu0.dtb.walker 140465.756824 # average overall miss latency 283611336Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu0.itb.walker 140937.039138 # average overall miss latency 283711336Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu0.inst 134396.000264 # average overall miss latency 283811336Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu0.data 139582.676625 # average overall miss latency 283911336Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 167065.091708 # average overall miss latency 284011336Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu1.dtb.walker 140795.010395 # average overall miss latency 284111336Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu1.itb.walker 140654.796512 # average overall miss latency 284211336Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu1.inst 134541.888707 # average overall miss latency 284311336Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu1.data 137944.492434 # average overall miss latency 284411336Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 167909.892260 # average overall miss latency 284511336Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::total 147536.108456 # average overall miss latency 284611336Sandreas.hansson@arm.comsystem.l2c.blocked_cycles::no_mshrs 2227 # number of cycles access was blocked 284710515SAli.Saidi@ARM.comsystem.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 284811336Sandreas.hansson@arm.comsystem.l2c.blocked::no_mshrs 45 # number of cycles access was blocked 284910515SAli.Saidi@ARM.comsystem.l2c.blocked::no_targets 0 # number of cycles access was blocked 285011336Sandreas.hansson@arm.comsystem.l2c.avg_blocked_cycles::no_mshrs 49.488889 # average number of cycles each access was blocked 285110515SAli.Saidi@ARM.comsystem.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 285210515SAli.Saidi@ARM.comsystem.l2c.fast_writes 0 # number of fast writes performed 285310515SAli.Saidi@ARM.comsystem.l2c.cache_copies 0 # number of cache copies performed 285411336Sandreas.hansson@arm.comsystem.l2c.writebacks::writebacks 1132908 # number of writebacks 285511336Sandreas.hansson@arm.comsystem.l2c.writebacks::total 1132908 # number of writebacks 285611336Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_hits::cpu1.data 1 # number of ReadExReq MSHR hits 285711336Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_hits::total 1 # number of ReadExReq MSHR hits 285811336Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_hits::cpu0.inst 168 # number of ReadSharedReq MSHR hits 285911336Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_hits::cpu0.data 25 # number of ReadSharedReq MSHR hits 286011336Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_hits::cpu1.inst 159 # number of ReadSharedReq MSHR hits 286111336Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_hits::cpu1.data 10 # number of ReadSharedReq MSHR hits 286211336Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_hits::cpu1.l2cache.prefetcher 1 # number of ReadSharedReq MSHR hits 286311336Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_hits::total 363 # number of ReadSharedReq MSHR hits 286411336Sandreas.hansson@arm.comsystem.l2c.demand_mshr_hits::cpu0.inst 168 # number of demand (read+write) MSHR hits 286511336Sandreas.hansson@arm.comsystem.l2c.demand_mshr_hits::cpu0.data 25 # number of demand (read+write) MSHR hits 286611336Sandreas.hansson@arm.comsystem.l2c.demand_mshr_hits::cpu1.inst 159 # number of demand (read+write) MSHR hits 286711336Sandreas.hansson@arm.comsystem.l2c.demand_mshr_hits::cpu1.data 11 # number of demand (read+write) MSHR hits 286811336Sandreas.hansson@arm.comsystem.l2c.demand_mshr_hits::cpu1.l2cache.prefetcher 1 # number of demand (read+write) MSHR hits 286911336Sandreas.hansson@arm.comsystem.l2c.demand_mshr_hits::total 364 # number of demand (read+write) MSHR hits 287011336Sandreas.hansson@arm.comsystem.l2c.overall_mshr_hits::cpu0.inst 168 # number of overall MSHR hits 287111336Sandreas.hansson@arm.comsystem.l2c.overall_mshr_hits::cpu0.data 25 # number of overall MSHR hits 287211336Sandreas.hansson@arm.comsystem.l2c.overall_mshr_hits::cpu1.inst 159 # number of overall MSHR hits 287311336Sandreas.hansson@arm.comsystem.l2c.overall_mshr_hits::cpu1.data 11 # number of overall MSHR hits 287411336Sandreas.hansson@arm.comsystem.l2c.overall_mshr_hits::cpu1.l2cache.prefetcher 1 # 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mshr miss rate for ReadSharedReq accesses 300311336Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.403848 # mshr miss rate for ReadSharedReq accesses 300411336Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.280270 # mshr miss rate for ReadSharedReq accesses 300511336Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.338250 # mshr miss rate for ReadSharedReq accesses 300611336Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.068377 # mshr miss rate for ReadSharedReq accesses 300711336Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.164892 # mshr miss rate for ReadSharedReq accesses 300811336Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.445078 # mshr miss rate for ReadSharedReq accesses 300911336Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::total 0.210186 # mshr miss rate for ReadSharedReq accesses 301011336Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.212217 # mshr miss rate for demand accesses 301111336Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.253815 # mshr miss rate for demand accesses 301211336Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu0.inst 0.097663 # mshr miss rate for demand accesses 301311336Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu0.data 0.426856 # mshr miss rate for demand accesses 301411336Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.403848 # mshr miss rate for demand accesses 301511336Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.280270 # mshr miss rate for demand accesses 301611336Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.338250 # mshr miss rate for demand accesses 301711336Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu1.inst 0.068377 # mshr miss rate for demand accesses 301811336Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu1.data 0.266230 # mshr miss rate for demand accesses 301911336Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.445078 # mshr miss rate for demand accesses 302011336Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::total 0.295395 # mshr miss rate for demand accesses 302111336Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.212217 # mshr miss rate for overall accesses 302211336Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.253815 # mshr miss rate for overall accesses 302311336Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu0.inst 0.097663 # mshr miss rate for overall accesses 302411336Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu0.data 0.426856 # mshr miss rate for overall accesses 302511336Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.403848 # mshr miss rate for overall accesses 302611336Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.280270 # mshr miss rate for overall accesses 302711336Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.338250 # mshr miss rate for overall accesses 302811336Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu1.inst 0.068377 # mshr miss rate for overall accesses 302911336Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu1.data 0.266230 # mshr miss rate for overall accesses 303011336Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.445078 # mshr miss rate for overall accesses 303111336Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::total 0.295395 # mshr miss rate for overall accesses 303211336Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 70665.648541 # average UpgradeReq mshr miss latency 303311336Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 70510.844375 # average UpgradeReq mshr miss latency 303411336Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_avg_mshr_miss_latency::total 70588.101488 # average UpgradeReq mshr miss latency 303511336Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 73697.624453 # average SCUpgradeReq mshr miss latency 303611336Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 73499.423401 # average SCUpgradeReq mshr miss latency 303711336Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 73602.977930 # average SCUpgradeReq mshr miss latency 303811336Sandreas.hansson@arm.comsystem.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 129628.448141 # average ReadExReq mshr miss latency 303911336Sandreas.hansson@arm.comsystem.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 126131.309034 # average ReadExReq mshr miss latency 304011336Sandreas.hansson@arm.comsystem.l2c.ReadExReq_avg_mshr_miss_latency::total 128788.187628 # average ReadExReq mshr miss latency 304111336Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 130465.013896 # average ReadSharedReq mshr miss latency 304211336Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 130935.623936 # average ReadSharedReq mshr miss latency 304311336Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 124440.857896 # average ReadSharedReq mshr miss latency 304411336Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 129429.419995 # average ReadSharedReq mshr miss latency 304511336Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 157062.022343 # average ReadSharedReq mshr miss latency 304611336Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 130793.143035 # average ReadSharedReq mshr miss latency 304711336Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 130652.621124 # average ReadSharedReq mshr miss latency 304811336Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 124595.578948 # average ReadSharedReq mshr miss latency 304911336Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 130411.611492 # average ReadSharedReq mshr miss latency 305011336Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 157907.439107 # average ReadSharedReq mshr miss latency 305111336Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::total 144136.486641 # average ReadSharedReq mshr miss latency 305211336Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 130465.013896 # average overall mshr miss latency 305311336Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 130935.623936 # average overall mshr miss latency 305411336Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.inst 124440.857896 # average overall mshr miss latency 305511336Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.data 129582.587544 # average overall mshr miss latency 305611336Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 157062.022343 # average overall mshr miss latency 305711336Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 130793.143035 # average overall mshr miss latency 305811336Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 130652.621124 # average overall mshr miss latency 305911336Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.inst 124595.578948 # average overall mshr miss latency 306011336Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.data 127943.621161 # average overall mshr miss latency 306111336Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 157907.439107 # average overall mshr miss latency 306211336Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::total 137541.973961 # average overall mshr miss latency 306311336Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 130465.013896 # average overall mshr miss latency 306411336Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 130935.623936 # average overall mshr miss latency 306511336Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.inst 124440.857896 # average overall mshr miss latency 306611336Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.data 129582.587544 # average overall mshr miss latency 306711336Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 157062.022343 # average overall mshr miss latency 306811336Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 130793.143035 # average overall mshr miss latency 306911336Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 130652.621124 # average overall mshr miss latency 307011336Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.inst 124595.578948 # average overall mshr miss latency 307111336Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.data 127943.621161 # average overall mshr miss latency 307211336Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 157907.439107 # average overall mshr miss latency 307311336Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::total 137541.973961 # average overall mshr miss latency 307411201Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 112746.678392 # average ReadReq mshr uncacheable latency 307511336Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 168601.820174 # average ReadReq mshr uncacheable latency 307611201Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 111728.260870 # average ReadReq mshr uncacheable latency 307711336Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 138760.548387 # average ReadReq mshr uncacheable latency 307811336Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::total 130189.676437 # average ReadReq mshr uncacheable latency 307911336Sandreas.hansson@arm.comsystem.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 164179.590555 # average WriteReq mshr uncacheable latency 308011336Sandreas.hansson@arm.comsystem.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 145115.792122 # average WriteReq mshr uncacheable latency 308111336Sandreas.hansson@arm.comsystem.l2c.WriteReq_avg_mshr_uncacheable_latency::total 155533.936466 # average WriteReq mshr uncacheable latency 308211201Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 112746.678392 # average overall mshr uncacheable latency 308311336Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 166307.988812 # average overall mshr uncacheable latency 308411201Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 111728.260870 # average overall mshr uncacheable latency 308511336Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 141794.024977 # average overall mshr uncacheable latency 308611336Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_uncacheable_latency::total 137723.145408 # average overall mshr uncacheable latency 308710515SAli.Saidi@ARM.comsystem.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 308811336Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadReq 91058 # Transaction distribution 308911336Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadResp 962815 # Transaction distribution 309011336Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteReq 38515 # Transaction distribution 309111336Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteResp 38515 # Transaction distribution 309211336Sandreas.hansson@arm.comsystem.membus.trans_dist::WritebackDirty 1239858 # Transaction distribution 309311336Sandreas.hansson@arm.comsystem.membus.trans_dist::CleanEvict 269903 # Transaction distribution 309411336Sandreas.hansson@arm.comsystem.membus.trans_dist::UpgradeReq 432314 # Transaction distribution 309511336Sandreas.hansson@arm.comsystem.membus.trans_dist::SCUpgradeReq 322959 # Transaction distribution 309611336Sandreas.hansson@arm.comsystem.membus.trans_dist::UpgradeResp 23 # Transaction distribution 309711245Sandreas.sandberg@arm.comsystem.membus.trans_dist::SCUpgradeFailReq 3 # Transaction distribution 309811336Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExReq 660243 # Transaction distribution 309911336Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExResp 640684 # Transaction distribution 310011336Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadSharedReq 871757 # Transaction distribution 310111336Sandreas.hansson@arm.comsystem.membus.trans_dist::InvalidateReq 106984 # Transaction distribution 310211336Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122998 # Packet count per connected master and slave (bytes) 310310585Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 52 # Packet count per connected master and slave (bytes) 310411336Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 26126 # Packet count per connected master and slave (bytes) 310511336Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5285035 # Packet count per connected master and slave (bytes) 310611336Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::total 5434211 # Packet count per connected master and slave (bytes) 310711336Sandreas.hansson@arm.comsystem.membus.pkt_count_system.iocache.mem_side::system.physmem.port 238560 # Packet count per connected master and slave (bytes) 310811336Sandreas.hansson@arm.comsystem.membus.pkt_count_system.iocache.mem_side::total 238560 # Packet count per connected master and slave (bytes) 310911336Sandreas.hansson@arm.comsystem.membus.pkt_count::total 5672771 # Packet count per connected master and slave (bytes) 311011336Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 156013 # Cumulative packet size per connected master and slave (bytes) 311110585Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1324 # Cumulative packet size per connected master and slave (bytes) 311211336Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 52252 # Cumulative packet size per connected master and slave (bytes) 311311336Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.physmem.port 172058368 # Cumulative packet size per connected master and slave (bytes) 311411336Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::total 172267957 # Cumulative packet size per connected master and slave (bytes) 311511336Sandreas.hansson@arm.comsystem.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7280448 # Cumulative packet size per connected master and slave (bytes) 311611336Sandreas.hansson@arm.comsystem.membus.pkt_size_system.iocache.mem_side::total 7280448 # Cumulative packet size per connected master and slave (bytes) 311711336Sandreas.hansson@arm.comsystem.membus.pkt_size::total 179548405 # Cumulative packet size per connected master and slave (bytes) 311811336Sandreas.hansson@arm.comsystem.membus.snoops 621430 # Total snoops (count) 311911336Sandreas.hansson@arm.comsystem.membus.snoop_fanout::samples 4033661 # Request fanout histogram 312010585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::mean 1 # Request fanout histogram 312110585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::stdev 0 # Request fanout histogram 312210585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 312310585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 312411336Sandreas.hansson@arm.comsystem.membus.snoop_fanout::1 4033661 100.00% 100.00% # Request fanout histogram 312510585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 312610585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 312710585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::min_value 1 # Request fanout histogram 312810585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::max_value 1 # Request fanout histogram 312911336Sandreas.hansson@arm.comsystem.membus.snoop_fanout::total 4033661 # Request fanout histogram 313011336Sandreas.hansson@arm.comsystem.membus.reqLayer0.occupancy 110232498 # Layer occupancy (ticks) 313110585Sandreas.hansson@arm.comsystem.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 313210892Sandreas.hansson@arm.comsystem.membus.reqLayer1.occupancy 33984 # Layer occupancy (ticks) 313310585Sandreas.hansson@arm.comsystem.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 313411336Sandreas.hansson@arm.comsystem.membus.reqLayer2.occupancy 21930998 # Layer occupancy (ticks) 313510585Sandreas.hansson@arm.comsystem.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 313611336Sandreas.hansson@arm.comsystem.membus.reqLayer5.occupancy 8790771874 # Layer occupancy (ticks) 313710585Sandreas.hansson@arm.comsystem.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 313811336Sandreas.hansson@arm.comsystem.membus.respLayer2.occupancy 8289711005 # Layer occupancy (ticks) 313910585Sandreas.hansson@arm.comsystem.membus.respLayer2.utilization 0.0 # Layer utilization (%) 314011336Sandreas.hansson@arm.comsystem.membus.respLayer3.occupancy 45511990 # Layer occupancy (ticks) 314110585Sandreas.hansson@arm.comsystem.membus.respLayer3.utilization 0.0 # Layer utilization (%) 314211239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 314311239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 314411239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 314511239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 314611239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 314711239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_sys.clock 16667 # Clock period in ticks 314810515SAli.Saidi@ARM.comsystem.realview.ethernet.txBytes 966 # Bytes Transmitted 314910515SAli.Saidi@ARM.comsystem.realview.ethernet.txPackets 3 # Number of Packets Transmitted 315010515SAli.Saidi@ARM.comsystem.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device 315110515SAli.Saidi@ARM.comsystem.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device 315210515SAli.Saidi@ARM.comsystem.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 315310515SAli.Saidi@ARM.comsystem.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 315410515SAli.Saidi@ARM.comsystem.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 315510515SAli.Saidi@ARM.comsystem.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 315610515SAli.Saidi@ARM.comsystem.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 315711201Sandreas.hansson@arm.comsystem.realview.ethernet.totBandwidth 163 # Total Bandwidth (bits/s) 315810515SAli.Saidi@ARM.comsystem.realview.ethernet.totPackets 3 # Total Packets 315910515SAli.Saidi@ARM.comsystem.realview.ethernet.totBytes 966 # Total Bytes 316010515SAli.Saidi@ARM.comsystem.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) 316111201Sandreas.hansson@arm.comsystem.realview.ethernet.txBandwidth 163 # Transmit Bandwidth (bits/s) 316210515SAli.Saidi@ARM.comsystem.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) 316310515SAli.Saidi@ARM.comsystem.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 316410515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post 316510515SAli.Saidi@ARM.comsystem.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 316610515SAli.Saidi@ARM.comsystem.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 316710515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post 316810515SAli.Saidi@ARM.comsystem.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 316910515SAli.Saidi@ARM.comsystem.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 317010515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post 317110515SAli.Saidi@ARM.comsystem.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 317210515SAli.Saidi@ARM.comsystem.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 317310515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post 317410515SAli.Saidi@ARM.comsystem.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 317510515SAli.Saidi@ARM.comsystem.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 317610515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post 317710515SAli.Saidi@ARM.comsystem.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 317810515SAli.Saidi@ARM.comsystem.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 317910515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post 318010515SAli.Saidi@ARM.comsystem.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 318110515SAli.Saidi@ARM.comsystem.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 318210515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 318310515SAli.Saidi@ARM.comsystem.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 318410515SAli.Saidi@ARM.comsystem.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 318510515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 318610515SAli.Saidi@ARM.comsystem.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 318710515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 318810515SAli.Saidi@ARM.comsystem.realview.ethernet.postedInterrupts 13 # number of posts to CPU 318910515SAli.Saidi@ARM.comsystem.realview.ethernet.droppedPackets 0 # number of packets dropped 319011239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 319111239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 319211239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 319311239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks 319411336Sandreas.hansson@arm.comsystem.toL2Bus.snoop_filter.tot_requests 12834320 # Total number of requests made to the snoop filter. 319511336Sandreas.hansson@arm.comsystem.toL2Bus.snoop_filter.hit_single_requests 6946519 # Number of requests hitting in the snoop filter with a single holder of the requested data. 319611336Sandreas.hansson@arm.comsystem.toL2Bus.snoop_filter.hit_multi_requests 2149909 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 319711336Sandreas.hansson@arm.comsystem.toL2Bus.snoop_filter.tot_snoops 154845 # Total number of snoops made to the snoop filter. 319811336Sandreas.hansson@arm.comsystem.toL2Bus.snoop_filter.hit_single_snoops 139190 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 319911336Sandreas.hansson@arm.comsystem.toL2Bus.snoop_filter.hit_multi_snoops 15655 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 320011336Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadReq 91060 # Transaction distribution 320111336Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadResp 4987176 # Transaction distribution 320211336Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::WriteReq 38515 # Transaction distribution 320311336Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::WriteResp 38515 # Transaction distribution 320411336Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::WritebackDirty 4108038 # Transaction distribution 320511336Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::CleanEvict 3110241 # Transaction distribution 320611336Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::UpgradeReq 736356 # Transaction distribution 320711336Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::SCUpgradeReq 408827 # Transaction distribution 320811336Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::UpgradeResp 1145183 # Transaction distribution 320911336Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::SCUpgradeFailReq 116 # Transaction distribution 321011336Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::UpgradeFailResp 116 # Transaction distribution 321111336Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadExReq 1157626 # Transaction distribution 321211336Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadExResp 1157626 # Transaction distribution 321311336Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadSharedReq 4903350 # Transaction distribution 321411336Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::InvalidateReq 106984 # Transaction distribution 321511336Sandreas.hansson@arm.comsystem.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 10442900 # Packet count per connected master and slave (bytes) 321611336Sandreas.hansson@arm.comsystem.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8319786 # Packet count per connected master and slave (bytes) 321711336Sandreas.hansson@arm.comsystem.toL2Bus.pkt_count::total 18762686 # Packet count per connected master and slave (bytes) 321811336Sandreas.hansson@arm.comsystem.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 296101599 # Cumulative packet size per connected master and slave (bytes) 321911336Sandreas.hansson@arm.comsystem.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 218919254 # Cumulative packet size per connected master and slave (bytes) 322011336Sandreas.hansson@arm.comsystem.toL2Bus.pkt_size::total 515020853 # Cumulative packet size per connected master and slave (bytes) 322111336Sandreas.hansson@arm.comsystem.toL2Bus.snoops 3228731 # Total snoops (count) 322211336Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::samples 9024232 # Request fanout histogram 322311336Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::mean 0.357725 # Request fanout histogram 322411336Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::stdev 0.482936 # Request fanout histogram 322510515SAli.Saidi@ARM.comsystem.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 322611336Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::0 5811691 64.40% 64.40% # Request fanout histogram 322711336Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::1 3196886 35.43% 99.83% # Request fanout histogram 322811336Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::2 15655 0.17% 100.00% # Request fanout histogram 322910515SAli.Saidi@ARM.comsystem.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 323011138Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 323110515SAli.Saidi@ARM.comsystem.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 323211336Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::total 9024232 # Request fanout histogram 323311336Sandreas.hansson@arm.comsystem.toL2Bus.reqLayer0.occupancy 9776043593 # Layer occupancy (ticks) 323410515SAli.Saidi@ARM.comsystem.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 323511336Sandreas.hansson@arm.comsystem.toL2Bus.snoopLayer0.occupancy 2607881 # Layer occupancy (ticks) 323610515SAli.Saidi@ARM.comsystem.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 323711336Sandreas.hansson@arm.comsystem.toL2Bus.respLayer0.occupancy 5412935477 # Layer occupancy (ticks) 323810515SAli.Saidi@ARM.comsystem.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 323911336Sandreas.hansson@arm.comsystem.toL2Bus.respLayer1.occupancy 4393187885 # Layer occupancy (ticks) 324010515SAli.Saidi@ARM.comsystem.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 324110515SAli.Saidi@ARM.com 324210515SAli.Saidi@ARM.com---------- End Simulation Statistics ---------- 3243