---------- Begin Simulation Statistics ---------- sim_seconds 47.461935 # Number of seconds simulated sim_ticks 47461934895000 # Number of ticks simulated final_tick 47461934895000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks host_inst_rate 231788 # Simulator instruction rate (inst/s) host_op_rate 272612 # Simulator op (including micro ops) rate (op/s) host_tick_rate 12136870284 # Simulator tick rate (ticks/s) host_mem_usage 762440 # Number of bytes of host memory used host_seconds 3910.56 # Real time elapsed on the host sim_insts 906421729 # Number of instructions simulated sim_ops 1066065309 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0.dtb.walker 128960 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 112832 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.inst 8192640 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.data 40731208 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.l2cache.prefetcher 14846528 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 153920 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.itb.walker 132096 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.inst 3008640 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.data 17045264 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.l2cache.prefetcher 15179584 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 435648 # Number of bytes read from this memory system.physmem.bytes_read::total 99967320 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu0.inst 8192640 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::cpu1.inst 3008640 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 11201280 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 79350912 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory system.physmem.bytes_written::total 79371496 # Number of bytes written to this memory system.physmem.num_reads::cpu0.dtb.walker 2015 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 1763 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.inst 128010 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.data 636438 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.l2cache.prefetcher 231977 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 2405 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.itb.walker 2064 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.inst 47010 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.data 266345 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.l2cache.prefetcher 237181 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 6807 # Number of read requests responded to by this memory system.physmem.num_reads::total 1562015 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 1239858 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory system.physmem.num_writes::total 1242432 # Number of write requests responded to by this memory system.physmem.bw_read::cpu0.dtb.walker 2717 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 2377 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.inst 172615 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.data 858187 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.l2cache.prefetcher 312809 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 3243 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.itb.walker 2783 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.inst 63391 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.data 359135 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.l2cache.prefetcher 319826 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 9179 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 2106263 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu0.inst 172615 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu1.inst 63391 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 236006 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_write::writebacks 1671885 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 434 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::total 1672319 # Write bandwidth from this memory (bytes/s) system.physmem.bw_total::writebacks 1671885 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 2717 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 2377 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.inst 172615 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.data 858620 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.l2cache.prefetcher 312809 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 3243 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.itb.walker 2783 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.inst 63391 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.data 359136 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.l2cache.prefetcher 319826 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 9179 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 3778582 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 1562015 # Number of read requests accepted system.physmem.writeReqs 1242432 # Number of write requests accepted system.physmem.readBursts 1562015 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 1242432 # Number of DRAM write bursts, including those merged in the write queue system.physmem.bytesReadDRAM 99934848 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 34112 # Total number of bytes read from write queue system.physmem.bytesWritten 79370432 # Total number of bytes written to DRAM system.physmem.bytesReadSys 99967320 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 79371496 # Total written bytes from the system interface side system.physmem.servicedByWrQ 533 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 2246 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 93757 # Per bank write bursts system.physmem.perBankRdBursts::1 100629 # Per bank write bursts system.physmem.perBankRdBursts::2 93977 # Per bank write bursts system.physmem.perBankRdBursts::3 99615 # Per bank write bursts system.physmem.perBankRdBursts::4 97211 # Per bank write bursts system.physmem.perBankRdBursts::5 108899 # Per bank write bursts system.physmem.perBankRdBursts::6 95410 # Per bank write bursts system.physmem.perBankRdBursts::7 95079 # Per bank write bursts system.physmem.perBankRdBursts::8 84413 # Per bank write bursts system.physmem.perBankRdBursts::9 140545 # Per bank write bursts system.physmem.perBankRdBursts::10 87149 # Per bank write bursts system.physmem.perBankRdBursts::11 92128 # Per bank write bursts system.physmem.perBankRdBursts::12 89605 # Per bank write bursts system.physmem.perBankRdBursts::13 97795 # Per bank write bursts system.physmem.perBankRdBursts::14 91413 # Per bank write bursts system.physmem.perBankRdBursts::15 93857 # Per bank write bursts system.physmem.perBankWrBursts::0 74634 # Per bank write bursts system.physmem.perBankWrBursts::1 80843 # Per bank write bursts system.physmem.perBankWrBursts::2 76779 # Per bank write bursts system.physmem.perBankWrBursts::3 81501 # Per bank write bursts system.physmem.perBankWrBursts::4 79021 # Per bank write bursts system.physmem.perBankWrBursts::5 86869 # Per bank write bursts system.physmem.perBankWrBursts::6 77167 # Per bank write bursts system.physmem.perBankWrBursts::7 78926 # Per bank write bursts system.physmem.perBankWrBursts::8 71646 # Per bank write bursts system.physmem.perBankWrBursts::9 75252 # Per bank write bursts system.physmem.perBankWrBursts::10 73334 # Per bank write bursts system.physmem.perBankWrBursts::11 76259 # Per bank write bursts system.physmem.perBankWrBursts::12 74746 # Per bank write bursts system.physmem.perBankWrBursts::13 79667 # Per bank write bursts system.physmem.perBankWrBursts::14 75302 # Per bank write bursts system.physmem.perBankWrBursts::15 78217 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 64 # Number of times write queue was full causing retry system.physmem.totGap 47461932782500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 25 # Read request sizes (log2) system.physmem.readPktSize::4 5 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) system.physmem.readPktSize::6 1561985 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 2 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 1239858 # Write request sizes (log2) system.physmem.rdQLenPdf::0 973357 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 368872 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 48939 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 35383 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 30040 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 27781 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 24940 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 22435 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 19175 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 4270 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 1963 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 1251 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 910 # What read queue length does an incoming req see system.physmem.rdQLenPdf::13 672 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 409 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 353 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 290 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 241 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 109 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 70 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 9 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 7 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::15 20126 # What write queue length does an incoming req see system.physmem.wrQLenPdf::16 23872 # What write queue length does an incoming req see system.physmem.wrQLenPdf::17 45415 # What write queue length does an incoming req see system.physmem.wrQLenPdf::18 56281 # What write queue length does an incoming req see system.physmem.wrQLenPdf::19 64128 # What write queue length does an incoming req see system.physmem.wrQLenPdf::20 66477 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 70043 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 73662 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 76578 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 77244 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 79843 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 84567 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 82434 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 83310 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 91239 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 81410 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 76067 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 73611 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 3385 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 1421 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 940 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 727 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 640 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 568 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 422 # What write queue length does an incoming req see system.physmem.wrQLenPdf::40 365 # What write queue length does an incoming req see system.physmem.wrQLenPdf::41 390 # What write queue length does an incoming req see system.physmem.wrQLenPdf::42 333 # What write queue length does an incoming req see system.physmem.wrQLenPdf::43 338 # What write queue length does an incoming req see system.physmem.wrQLenPdf::44 374 # What write queue length does an incoming req see system.physmem.wrQLenPdf::45 362 # What write queue length does an incoming req see system.physmem.wrQLenPdf::46 231 # What write queue length does an incoming req see system.physmem.wrQLenPdf::47 275 # What write queue length does an incoming req see system.physmem.wrQLenPdf::48 228 # What write queue length does an incoming req see system.physmem.wrQLenPdf::49 247 # What write queue length does an incoming req see system.physmem.wrQLenPdf::50 311 # What write queue length does an incoming req see system.physmem.wrQLenPdf::51 204 # What write queue length does an incoming req see system.physmem.wrQLenPdf::52 261 # What write queue length does an incoming req see system.physmem.wrQLenPdf::53 236 # What write queue length does an incoming req see system.physmem.wrQLenPdf::54 227 # What write queue length does an incoming req see system.physmem.wrQLenPdf::55 124 # What write queue length does an incoming req see system.physmem.wrQLenPdf::56 170 # What write queue length does an incoming req see system.physmem.wrQLenPdf::57 185 # What write queue length does an incoming req see system.physmem.wrQLenPdf::58 133 # What write queue length does an incoming req see system.physmem.wrQLenPdf::59 155 # What write queue length does an incoming req see system.physmem.wrQLenPdf::60 142 # What write queue length does an incoming req see system.physmem.wrQLenPdf::61 234 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 86 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 150 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 991222 # Bytes accessed per row activation system.physmem.bytesPerActivate::mean 180.892514 # Bytes accessed per row activation system.physmem.bytesPerActivate::gmean 111.543893 # Bytes accessed per row activation system.physmem.bytesPerActivate::stdev 240.536828 # Bytes accessed per row activation system.physmem.bytesPerActivate::0-127 614355 61.98% 61.98% # Bytes accessed per row activation system.physmem.bytesPerActivate::128-255 184510 18.61% 80.59% # Bytes accessed per row activation system.physmem.bytesPerActivate::256-383 61267 6.18% 86.77% # Bytes accessed per row activation system.physmem.bytesPerActivate::384-511 32396 3.27% 90.04% # Bytes accessed per row activation system.physmem.bytesPerActivate::512-639 21556 2.17% 92.22% # Bytes accessed per row activation system.physmem.bytesPerActivate::640-767 13955 1.41% 93.63% # Bytes accessed per row activation system.physmem.bytesPerActivate::768-895 9658 0.97% 94.60% # Bytes accessed per row activation system.physmem.bytesPerActivate::896-1023 9476 0.96% 95.56% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 44049 4.44% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 991222 # Bytes accessed per row activation system.physmem.rdPerTurnAround::samples 69967 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::mean 22.317164 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::stdev 326.421262 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::0-4095 69964 100.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::4096-8191 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::24576-28671 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::81920-86015 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::total 69967 # Reads before turning the bus around for writes system.physmem.wrPerTurnAround::samples 69967 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::mean 17.724970 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::gmean 17.179434 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::stdev 7.169336 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::16-19 65865 94.14% 94.14% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::20-23 2036 2.91% 97.05% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::24-27 254 0.36% 97.41% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::28-31 187 0.27% 97.68% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::32-35 141 0.20% 97.88% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::36-39 122 0.17% 98.05% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::40-43 214 0.31% 98.36% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::44-47 78 0.11% 98.47% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::48-51 271 0.39% 98.86% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::52-55 64 0.09% 98.95% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::56-59 34 0.05% 99.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::60-63 49 0.07% 99.07% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::64-67 243 0.35% 99.42% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::68-71 32 0.05% 99.46% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::72-75 40 0.06% 99.52% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::76-79 104 0.15% 99.67% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::80-83 171 0.24% 99.91% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::84-87 3 0.00% 99.92% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::88-91 3 0.00% 99.92% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::92-95 3 0.00% 99.92% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::96-99 1 0.00% 99.93% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::100-103 3 0.00% 99.93% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::104-107 1 0.00% 99.93% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::108-111 1 0.00% 99.93% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::112-115 3 0.00% 99.94% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::128-131 14 0.02% 99.96% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::132-135 3 0.00% 99.96% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::136-139 1 0.00% 99.96% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::144-147 14 0.02% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::152-155 1 0.00% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::156-159 2 0.00% 99.99% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::160-163 2 0.00% 99.99% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::164-167 1 0.00% 99.99% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::168-171 1 0.00% 99.99% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::172-175 1 0.00% 99.99% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::176-179 2 0.00% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::180-183 1 0.00% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::184-187 1 0.00% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 69967 # Writes before turning the bus around for reads system.physmem.totQLat 43176438588 # Total ticks spent queuing system.physmem.totMemAccLat 72454226088 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 7807410000 # Total ticks spent in databus transfers system.physmem.avgQLat 27650.94 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst system.physmem.avgMemAccLat 46400.94 # Average memory access latency per DRAM burst system.physmem.avgRdBW 2.11 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 1.67 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 2.11 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 1.67 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing system.physmem.avgWrQLen 25.42 # Average write queue length when enqueuing system.physmem.readRowHits 1247973 # Number of row buffer hits during reads system.physmem.writeRowHits 562447 # Number of row buffer hits during writes system.physmem.readRowHitRate 79.92 # Row buffer hit rate for reads system.physmem.writeRowHitRate 45.35 # Row buffer hit rate for writes system.physmem.avgGap 16923811.64 # Average gap between requests system.physmem.pageHitRate 64.62 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 3897081720 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 2126383875 # Energy for precharge commands per rank (pJ) system.physmem_0.readEnergy 6119692800 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 4119595200 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 3099982404480 # Energy for refresh commands per rank (pJ) system.physmem_0.actBackEnergy 1216381568355 # Energy for active background per rank (pJ) system.physmem_0.preBackEnergy 27410155454250 # Energy for precharge background per rank (pJ) system.physmem_0.totalEnergy 31742782180680 # Total energy per rank (pJ) system.physmem_0.averagePower 668.805156 # Core power per rank (mW) system.physmem_0.memoryStateTime::IDLE 45598728268843 # Time in different power states system.physmem_0.memoryStateTime::REF 1584858080000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_0.memoryStateTime::ACT 278346651157 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_1.actEnergy 3596556600 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 1962406875 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 6059788800 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 3916661040 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 3099982404480 # Energy for refresh commands per rank (pJ) system.physmem_1.actBackEnergy 1207691479170 # Energy for active background per rank (pJ) system.physmem_1.preBackEnergy 27417778331250 # Energy for precharge background per rank (pJ) system.physmem_1.totalEnergy 31740987628215 # Total energy per rank (pJ) system.physmem_1.averagePower 668.767346 # Core power per rank (mW) system.physmem_1.memoryStateTime::IDLE 45611421903472 # Time in different power states system.physmem_1.memoryStateTime::REF 1584858080000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 265649419028 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 704 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 576 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 1324 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu0.inst 704 # Number of instructions bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu1.inst 576 # Number of instructions bytes read from this memory system.realview.nvmem.bytes_inst_read::total 1280 # Number of instructions bytes read from this memory system.realview.nvmem.num_reads::cpu0.inst 11 # Number of read requests responded to by this memory system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory system.realview.nvmem.num_reads::cpu1.inst 9 # Number of read requests responded to by this memory system.realview.nvmem.num_reads::cpu1.data 1 # Number of read requests responded to by this memory system.realview.nvmem.num_reads::total 26 # Number of read requests responded to by this memory system.realview.nvmem.bw_read::cpu0.inst 15 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_read::cpu1.inst 12 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_read::cpu1.data 0 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_read::total 28 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_inst_read::cpu0.inst 15 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_inst_read::cpu1.inst 12 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_inst_read::total 27 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.inst 15 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.inst 12 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 28 # Total bandwidth to/from this memory (bytes/s) system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 1671 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6846976 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1674 # Number of DMA write transactions. system.cpu0.branchPred.lookups 141158417 # Number of BP lookups system.cpu0.branchPred.condPredicted 100207840 # Number of conditional branches predicted system.cpu0.branchPred.condIncorrect 6289341 # Number of conditional branches incorrect system.cpu0.branchPred.BTBLookups 105574499 # Number of BTB lookups system.cpu0.branchPred.BTBHits 76948344 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu0.branchPred.BTBHitPct 72.885351 # BTB Hit Percentage system.cpu0.branchPred.usedRAS 16552897 # Number of times the RAS was used to get a target. system.cpu0.branchPred.RASInCorrect 1094870 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.walker.walks 283140 # Table walker walks requested system.cpu0.dtb.walker.walksLong 283140 # Table walker walks initiated with long descriptors system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 9717 # Level at which table walker walks with long descriptors terminate system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 79661 # Level at which table walker walks with long descriptors terminate system.cpu0.dtb.walker.walkWaitTime::samples 283140 # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walkWaitTime::0 283140 100.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walkWaitTime::total 283140 # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walkCompletionTime::samples 89378 # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::mean 23531.797534 # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::gmean 21398.159545 # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::stdev 20518.573843 # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::0-65535 88174 98.65% 98.65% # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::65536-131071 214 0.24% 98.89% # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::131072-196607 839 0.94% 99.83% # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::196608-262143 33 0.04% 99.87% # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::262144-327679 38 0.04% 99.91% # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::327680-393215 25 0.03% 99.94% # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::393216-458751 35 0.04% 99.98% # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::458752-524287 10 0.01% 99.99% # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::524288-589823 8 0.01% 100.00% # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::720896-786431 1 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::total 89378 # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walksPending::samples -909613592 # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::0 -909613592 100.00% 100.00% # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::total -909613592 # Table walker pending requests distribution system.cpu0.dtb.walker.walkPageSizes::4K 79661 89.13% 89.13% # Table walker page sizes translated system.cpu0.dtb.walker.walkPageSizes::2M 9717 10.87% 100.00% # Table walker page sizes translated system.cpu0.dtb.walker.walkPageSizes::total 89378 # Table walker page sizes translated system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 283140 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 283140 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 89378 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 89378 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin::total 372518 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses system.cpu0.dtb.read_hits 90921588 # DTB read hits system.cpu0.dtb.read_misses 233548 # DTB read misses system.cpu0.dtb.write_hits 80603054 # DTB write hits system.cpu0.dtb.write_misses 49592 # DTB write misses system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 42784 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 1060 # Number of times TLB was flushed by ASID system.cpu0.dtb.flush_entries 38267 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 2134 # Number of TLB faults due to alignment restrictions system.cpu0.dtb.prefetch_faults 9015 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 11497 # Number of TLB faults due to permissions restrictions system.cpu0.dtb.read_accesses 91155136 # DTB read accesses system.cpu0.dtb.write_accesses 80652646 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses system.cpu0.dtb.hits 171524642 # DTB hits system.cpu0.dtb.misses 283140 # DTB misses system.cpu0.dtb.accesses 171807782 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.itb.walker.walks 66290 # Table walker walks requested system.cpu0.itb.walker.walksLong 66290 # Table walker walks initiated with long descriptors system.cpu0.itb.walker.walksLongTerminationLevel::Level2 665 # Level at which table walker walks with long descriptors terminate system.cpu0.itb.walker.walksLongTerminationLevel::Level3 56612 # Level at which table walker walks with long descriptors terminate system.cpu0.itb.walker.walkWaitTime::samples 66290 # Table walker wait (enqueue to first request) latency system.cpu0.itb.walker.walkWaitTime::0 66290 100.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu0.itb.walker.walkWaitTime::total 66290 # Table walker wait (enqueue to first request) latency system.cpu0.itb.walker.walkCompletionTime::samples 57277 # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::mean 26707.997975 # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::gmean 23913.035188 # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::stdev 23204.196076 # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::0-65535 56118 97.98% 97.98% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::65536-131071 13 0.02% 98.00% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::131072-196607 1037 1.81% 99.81% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::196608-262143 26 0.05% 99.86% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::262144-327679 46 0.08% 99.94% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::327680-393215 23 0.04% 99.98% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::393216-458751 11 0.02% 99.99% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::458752-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::total 57277 # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walksPending::samples -910742092 # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::0 -910742092 100.00% 100.00% # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::total -910742092 # Table walker pending requests distribution system.cpu0.itb.walker.walkPageSizes::4K 56612 98.84% 98.84% # Table walker page sizes translated system.cpu0.itb.walker.walkPageSizes::2M 665 1.16% 100.00% # Table walker page sizes translated system.cpu0.itb.walker.walkPageSizes::total 57277 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 66290 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Requested::total 66290 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 57277 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::total 57277 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin::total 123567 # Table walker requests started/completed, data/inst system.cpu0.itb.inst_hits 252665762 # ITB inst hits system.cpu0.itb.inst_misses 66290 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 42784 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 1060 # Number of times TLB was flushed by ASID system.cpu0.itb.flush_entries 27416 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 203450 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses system.cpu0.itb.inst_accesses 252732052 # ITB inst accesses system.cpu0.itb.hits 252665762 # DTB hits system.cpu0.itb.misses 66290 # DTB misses system.cpu0.itb.accesses 252732052 # DTB accesses system.cpu0.numCycles 1081051562 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.committedInsts 468741146 # Number of instructions committed system.cpu0.committedOps 550955855 # Number of ops (including micro ops) committed system.cpu0.discardedOps 47157402 # Number of ops (including micro ops) which were discarded before commit system.cpu0.numFetchSuspends 5078 # Number of times Execute suspended instruction fetching system.cpu0.quiesceCycles 93843643871 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt system.cpu0.cpi 2.306287 # CPI: cycles per instruction system.cpu0.ipc 0.433597 # IPC: instructions per cycle system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 5324 # number of quiesce instructions executed system.cpu0.tickCycles 755067683 # Number of cycles that the object actually ticked system.cpu0.idleCycles 325983879 # Total number of cycles that the object has spent stopped system.cpu0.dcache.tags.replacements 5850262 # number of replacements system.cpu0.dcache.tags.tagsinuse 501.214442 # Cycle average of tags in use system.cpu0.dcache.tags.total_refs 162710873 # Total number of references to valid blocks. system.cpu0.dcache.tags.sampled_refs 5850774 # Sample count of references to valid blocks. system.cpu0.dcache.tags.avg_refs 27.810145 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 7690769000 # Cycle when the warmup percentage was hit. system.cpu0.dcache.tags.occ_blocks::cpu0.data 501.214442 # Average occupied blocks per requestor system.cpu0.dcache.tags.occ_percent::cpu0.data 0.978934 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.978934 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::0 158 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::1 332 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 22 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu0.dcache.tags.tag_accesses 346062459 # Number of tag accesses system.cpu0.dcache.tags.data_accesses 346062459 # Number of data accesses system.cpu0.dcache.ReadReq_hits::cpu0.data 83268986 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::total 83268986 # number of ReadReq hits system.cpu0.dcache.WriteReq_hits::cpu0.data 74755135 # number of WriteReq hits system.cpu0.dcache.WriteReq_hits::total 74755135 # number of WriteReq hits system.cpu0.dcache.SoftPFReq_hits::cpu0.data 273368 # number of SoftPFReq hits system.cpu0.dcache.SoftPFReq_hits::total 273368 # number of SoftPFReq hits system.cpu0.dcache.WriteLineReq_hits::cpu0.data 183787 # number of WriteLineReq hits system.cpu0.dcache.WriteLineReq_hits::total 183787 # number of WriteLineReq hits system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1841830 # number of LoadLockedReq hits system.cpu0.dcache.LoadLockedReq_hits::total 1841830 # number of LoadLockedReq hits system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1806426 # number of StoreCondReq hits system.cpu0.dcache.StoreCondReq_hits::total 1806426 # number of StoreCondReq hits system.cpu0.dcache.demand_hits::cpu0.data 158024121 # number of demand (read+write) hits system.cpu0.dcache.demand_hits::total 158024121 # number of demand (read+write) hits system.cpu0.dcache.overall_hits::cpu0.data 158297489 # number of overall hits system.cpu0.dcache.overall_hits::total 158297489 # number of overall hits system.cpu0.dcache.ReadReq_misses::cpu0.data 3569470 # number of ReadReq misses system.cpu0.dcache.ReadReq_misses::total 3569470 # number of ReadReq misses system.cpu0.dcache.WriteReq_misses::cpu0.data 2481271 # number of WriteReq misses system.cpu0.dcache.WriteReq_misses::total 2481271 # number of WriteReq misses system.cpu0.dcache.SoftPFReq_misses::cpu0.data 690957 # number of SoftPFReq misses system.cpu0.dcache.SoftPFReq_misses::total 690957 # number of SoftPFReq misses system.cpu0.dcache.WriteLineReq_misses::cpu0.data 806074 # number of WriteLineReq misses system.cpu0.dcache.WriteLineReq_misses::total 806074 # number of WriteLineReq misses system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 173924 # number of LoadLockedReq misses system.cpu0.dcache.LoadLockedReq_misses::total 173924 # number of LoadLockedReq misses system.cpu0.dcache.StoreCondReq_misses::cpu0.data 207838 # number of StoreCondReq misses system.cpu0.dcache.StoreCondReq_misses::total 207838 # number of StoreCondReq misses system.cpu0.dcache.demand_misses::cpu0.data 6050741 # number of demand (read+write) misses system.cpu0.dcache.demand_misses::total 6050741 # number of demand (read+write) misses system.cpu0.dcache.overall_misses::cpu0.data 6741698 # number of overall misses system.cpu0.dcache.overall_misses::total 6741698 # number of overall misses system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 62945089000 # number of ReadReq miss cycles system.cpu0.dcache.ReadReq_miss_latency::total 62945089000 # number of ReadReq miss cycles system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 62898003000 # number of WriteReq miss cycles system.cpu0.dcache.WriteReq_miss_latency::total 62898003000 # number of WriteReq miss cycles system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 71296883500 # number of WriteLineReq miss cycles system.cpu0.dcache.WriteLineReq_miss_latency::total 71296883500 # number of WriteLineReq miss cycles system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2825966000 # number of LoadLockedReq miss cycles system.cpu0.dcache.LoadLockedReq_miss_latency::total 2825966000 # number of LoadLockedReq miss cycles system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 5775275000 # number of StoreCondReq miss cycles system.cpu0.dcache.StoreCondReq_miss_latency::total 5775275000 # number of StoreCondReq miss cycles system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 4714000 # number of StoreCondFailReq miss cycles system.cpu0.dcache.StoreCondFailReq_miss_latency::total 4714000 # number of StoreCondFailReq miss cycles system.cpu0.dcache.demand_miss_latency::cpu0.data 125843092000 # number of demand (read+write) miss cycles system.cpu0.dcache.demand_miss_latency::total 125843092000 # number of demand (read+write) miss cycles system.cpu0.dcache.overall_miss_latency::cpu0.data 125843092000 # number of overall miss cycles system.cpu0.dcache.overall_miss_latency::total 125843092000 # number of overall miss cycles system.cpu0.dcache.ReadReq_accesses::cpu0.data 86838456 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.ReadReq_accesses::total 86838456 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::cpu0.data 77236406 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::total 77236406 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 964325 # number of SoftPFReq accesses(hits+misses) system.cpu0.dcache.SoftPFReq_accesses::total 964325 # number of SoftPFReq accesses(hits+misses) system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 989861 # number of WriteLineReq accesses(hits+misses) system.cpu0.dcache.WriteLineReq_accesses::total 989861 # number of WriteLineReq accesses(hits+misses) system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2015754 # number of LoadLockedReq accesses(hits+misses) system.cpu0.dcache.LoadLockedReq_accesses::total 2015754 # number of LoadLockedReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2014264 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::total 2014264 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.demand_accesses::cpu0.data 164074862 # number of demand (read+write) accesses system.cpu0.dcache.demand_accesses::total 164074862 # number of demand (read+write) accesses system.cpu0.dcache.overall_accesses::cpu0.data 165039187 # number of overall (read+write) accesses system.cpu0.dcache.overall_accesses::total 165039187 # number of overall (read+write) accesses system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.041105 # miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_miss_rate::total 0.041105 # miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.032126 # miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_miss_rate::total 0.032126 # miss rate for WriteReq accesses system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.716519 # miss rate for SoftPFReq accesses system.cpu0.dcache.SoftPFReq_miss_rate::total 0.716519 # miss rate for SoftPFReq accesses system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.814330 # miss rate for WriteLineReq accesses system.cpu0.dcache.WriteLineReq_miss_rate::total 0.814330 # miss rate for WriteLineReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.086282 # miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.086282 # miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.103183 # miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::total 0.103183 # miss rate for StoreCondReq accesses system.cpu0.dcache.demand_miss_rate::cpu0.data 0.036878 # miss rate for demand accesses system.cpu0.dcache.demand_miss_rate::total 0.036878 # miss rate for demand accesses system.cpu0.dcache.overall_miss_rate::cpu0.data 0.040849 # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::total 0.040849 # miss rate for overall accesses system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 17634.295568 # average ReadReq miss latency system.cpu0.dcache.ReadReq_avg_miss_latency::total 17634.295568 # average ReadReq miss latency system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 25349.106567 # average WriteReq miss latency system.cpu0.dcache.WriteReq_avg_miss_latency::total 25349.106567 # average WriteReq miss latency system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 88449.551158 # average WriteLineReq miss latency system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 88449.551158 # average WriteLineReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16248.280858 # average LoadLockedReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16248.280858 # average LoadLockedReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 27787.387292 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 27787.387292 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 20797.963754 # average overall miss latency system.cpu0.dcache.demand_avg_miss_latency::total 20797.963754 # average overall miss latency system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 18666.379301 # average overall miss latency system.cpu0.dcache.overall_avg_miss_latency::total 18666.379301 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed system.cpu0.dcache.writebacks::writebacks 5850286 # number of writebacks system.cpu0.dcache.writebacks::total 5850286 # number of writebacks system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 444097 # number of ReadReq MSHR hits system.cpu0.dcache.ReadReq_mshr_hits::total 444097 # number of ReadReq MSHR hits system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1026850 # number of WriteReq MSHR hits system.cpu0.dcache.WriteReq_mshr_hits::total 1026850 # number of WriteReq MSHR hits system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 104 # number of WriteLineReq MSHR hits system.cpu0.dcache.WriteLineReq_mshr_hits::total 104 # number of WriteLineReq MSHR hits system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 44524 # number of LoadLockedReq MSHR hits system.cpu0.dcache.LoadLockedReq_mshr_hits::total 44524 # number of LoadLockedReq MSHR hits system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data 32 # number of StoreCondReq MSHR hits system.cpu0.dcache.StoreCondReq_mshr_hits::total 32 # number of StoreCondReq MSHR hits system.cpu0.dcache.demand_mshr_hits::cpu0.data 1470947 # number of demand (read+write) MSHR hits system.cpu0.dcache.demand_mshr_hits::total 1470947 # number of demand (read+write) MSHR hits system.cpu0.dcache.overall_mshr_hits::cpu0.data 1470947 # number of overall MSHR hits system.cpu0.dcache.overall_mshr_hits::total 1470947 # number of overall MSHR hits system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3125373 # number of ReadReq MSHR misses system.cpu0.dcache.ReadReq_mshr_misses::total 3125373 # number of ReadReq MSHR misses system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1454421 # number of WriteReq MSHR misses system.cpu0.dcache.WriteReq_mshr_misses::total 1454421 # number of WriteReq MSHR misses system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 689314 # number of SoftPFReq MSHR misses system.cpu0.dcache.SoftPFReq_mshr_misses::total 689314 # number of SoftPFReq MSHR misses system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 805970 # number of WriteLineReq MSHR misses system.cpu0.dcache.WriteLineReq_mshr_misses::total 805970 # number of WriteLineReq MSHR misses system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 129400 # number of LoadLockedReq MSHR misses system.cpu0.dcache.LoadLockedReq_mshr_misses::total 129400 # number of LoadLockedReq MSHR misses system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 207806 # number of StoreCondReq MSHR misses system.cpu0.dcache.StoreCondReq_mshr_misses::total 207806 # number of StoreCondReq MSHR misses system.cpu0.dcache.demand_mshr_misses::cpu0.data 4579794 # number of demand (read+write) MSHR misses system.cpu0.dcache.demand_mshr_misses::total 4579794 # number of demand (read+write) MSHR misses system.cpu0.dcache.overall_mshr_misses::cpu0.data 5269108 # number of overall MSHR misses system.cpu0.dcache.overall_mshr_misses::total 5269108 # number of overall MSHR misses system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 19530 # number of ReadReq MSHR uncacheable system.cpu0.dcache.ReadReq_mshr_uncacheable::total 19530 # number of ReadReq MSHR uncacheable system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 21048 # number of WriteReq MSHR uncacheable system.cpu0.dcache.WriteReq_mshr_uncacheable::total 21048 # number of WriteReq MSHR uncacheable system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 40578 # number of overall MSHR uncacheable misses system.cpu0.dcache.overall_mshr_uncacheable_misses::total 40578 # number of overall MSHR uncacheable misses system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 49230560000 # number of ReadReq MSHR miss cycles system.cpu0.dcache.ReadReq_mshr_miss_latency::total 49230560000 # number of ReadReq MSHR miss cycles system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 36276054500 # number of WriteReq MSHR miss cycles system.cpu0.dcache.WriteReq_mshr_miss_latency::total 36276054500 # number of WriteReq MSHR miss cycles system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 18434925500 # number of SoftPFReq MSHR miss cycles system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 18434925500 # number of SoftPFReq MSHR miss cycles system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 70481228500 # number of WriteLineReq MSHR miss cycles system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 70481228500 # number of WriteLineReq MSHR miss cycles system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1893845500 # number of LoadLockedReq MSHR miss cycles system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1893845500 # number of LoadLockedReq MSHR miss cycles system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 5565229000 # number of StoreCondReq MSHR miss cycles system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 5565229000 # number of StoreCondReq MSHR miss cycles system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 4561000 # number of StoreCondFailReq MSHR miss cycles system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 4561000 # number of StoreCondFailReq MSHR miss cycles system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 85506614500 # number of demand (read+write) MSHR miss cycles system.cpu0.dcache.demand_mshr_miss_latency::total 85506614500 # number of demand (read+write) MSHR miss cycles system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 103941540000 # number of overall MSHR miss cycles system.cpu0.dcache.overall_mshr_miss_latency::total 103941540000 # number of overall MSHR miss cycles system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3800939500 # number of ReadReq MSHR uncacheable cycles system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 3800939500 # number of ReadReq MSHR uncacheable cycles system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 3971667500 # number of WriteReq MSHR uncacheable cycles system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 3971667500 # number of WriteReq MSHR uncacheable cycles system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 7772607000 # number of overall MSHR uncacheable cycles system.cpu0.dcache.overall_mshr_uncacheable_latency::total 7772607000 # number of overall MSHR uncacheable cycles system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.035991 # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.035991 # mshr miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018831 # mshr miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018831 # mshr miss rate for WriteReq accesses system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.714815 # mshr miss rate for SoftPFReq accesses system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.714815 # mshr miss rate for SoftPFReq accesses system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.814225 # mshr miss rate for WriteLineReq accesses system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.814225 # mshr miss rate for WriteLineReq accesses system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.064194 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.064194 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.103167 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.103167 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027913 # mshr miss rate for demand accesses system.cpu0.dcache.demand_mshr_miss_rate::total 0.027913 # mshr miss rate for demand accesses system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.031926 # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::total 0.031926 # mshr miss rate for overall accesses system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15751.899053 # average ReadReq mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15751.899053 # average ReadReq mshr miss latency system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 24941.921562 # average WriteReq mshr miss latency system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 24941.921562 # average WriteReq mshr miss latency system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 26743.872169 # average SoftPFReq mshr miss latency system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 26743.872169 # average SoftPFReq mshr miss latency system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 87448.947852 # average WriteLineReq mshr miss latency system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 87448.947852 # average WriteLineReq mshr miss latency system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14635.591190 # average LoadLockedReq mshr miss latency system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14635.591190 # average LoadLockedReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 26780.886981 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 26780.886981 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18670.406245 # average overall mshr miss latency system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18670.406245 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19726.591294 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19726.591294 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 194620.558116 # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 194620.558116 # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 188695.719308 # average WriteReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 188695.719308 # average WriteReq mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 191547.316280 # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 191547.316280 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.icache.tags.replacements 9594128 # number of replacements system.cpu0.icache.tags.tagsinuse 511.890921 # Cycle average of tags in use system.cpu0.icache.tags.total_refs 242861120 # Total number of references to valid blocks. system.cpu0.icache.tags.sampled_refs 9594640 # Sample count of references to valid blocks. system.cpu0.icache.tags.avg_refs 25.312166 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 40343615000 # Cycle when the warmup percentage was hit. system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.890921 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999787 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.999787 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::0 74 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::1 191 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::2 247 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu0.icache.tags.tag_accesses 514506190 # Number of tag accesses system.cpu0.icache.tags.data_accesses 514506190 # Number of data accesses system.cpu0.icache.ReadReq_hits::cpu0.inst 242861120 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::total 242861120 # number of ReadReq hits system.cpu0.icache.demand_hits::cpu0.inst 242861120 # number of demand (read+write) hits system.cpu0.icache.demand_hits::total 242861120 # number of demand (read+write) hits system.cpu0.icache.overall_hits::cpu0.inst 242861120 # number of overall hits system.cpu0.icache.overall_hits::total 242861120 # number of overall hits system.cpu0.icache.ReadReq_misses::cpu0.inst 9594650 # number of ReadReq misses system.cpu0.icache.ReadReq_misses::total 9594650 # number of ReadReq misses system.cpu0.icache.demand_misses::cpu0.inst 9594650 # number of demand (read+write) misses system.cpu0.icache.demand_misses::total 9594650 # number of demand (read+write) misses system.cpu0.icache.overall_misses::cpu0.inst 9594650 # number of overall misses system.cpu0.icache.overall_misses::total 9594650 # number of overall misses system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 102613134000 # number of ReadReq miss cycles system.cpu0.icache.ReadReq_miss_latency::total 102613134000 # number of ReadReq miss cycles system.cpu0.icache.demand_miss_latency::cpu0.inst 102613134000 # number of demand (read+write) miss cycles system.cpu0.icache.demand_miss_latency::total 102613134000 # number of demand (read+write) miss cycles system.cpu0.icache.overall_miss_latency::cpu0.inst 102613134000 # number of overall miss cycles system.cpu0.icache.overall_miss_latency::total 102613134000 # number of overall miss cycles system.cpu0.icache.ReadReq_accesses::cpu0.inst 252455770 # number of ReadReq accesses(hits+misses) system.cpu0.icache.ReadReq_accesses::total 252455770 # number of ReadReq accesses(hits+misses) system.cpu0.icache.demand_accesses::cpu0.inst 252455770 # number of demand (read+write) accesses system.cpu0.icache.demand_accesses::total 252455770 # number of demand (read+write) accesses system.cpu0.icache.overall_accesses::cpu0.inst 252455770 # number of overall (read+write) accesses system.cpu0.icache.overall_accesses::total 252455770 # number of overall (read+write) accesses system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.038005 # miss rate for ReadReq accesses system.cpu0.icache.ReadReq_miss_rate::total 0.038005 # miss rate for ReadReq accesses system.cpu0.icache.demand_miss_rate::cpu0.inst 0.038005 # miss rate for demand accesses system.cpu0.icache.demand_miss_rate::total 0.038005 # miss rate for demand accesses system.cpu0.icache.overall_miss_rate::cpu0.inst 0.038005 # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::total 0.038005 # miss rate for overall accesses system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10694.828264 # average ReadReq miss latency system.cpu0.icache.ReadReq_avg_miss_latency::total 10694.828264 # average ReadReq miss latency system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10694.828264 # average overall miss latency system.cpu0.icache.demand_avg_miss_latency::total 10694.828264 # average overall miss latency system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10694.828264 # average overall miss latency system.cpu0.icache.overall_avg_miss_latency::total 10694.828264 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed system.cpu0.icache.writebacks::writebacks 9594128 # number of writebacks system.cpu0.icache.writebacks::total 9594128 # number of writebacks system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 9594650 # number of ReadReq MSHR misses system.cpu0.icache.ReadReq_mshr_misses::total 9594650 # number of ReadReq MSHR misses system.cpu0.icache.demand_mshr_misses::cpu0.inst 9594650 # number of demand (read+write) MSHR misses system.cpu0.icache.demand_mshr_misses::total 9594650 # number of demand (read+write) MSHR misses system.cpu0.icache.overall_mshr_misses::cpu0.inst 9594650 # number of overall MSHR misses system.cpu0.icache.overall_mshr_misses::total 9594650 # number of overall MSHR misses system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 52309 # number of ReadReq MSHR uncacheable system.cpu0.icache.ReadReq_mshr_uncacheable::total 52309 # number of ReadReq MSHR uncacheable system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 52309 # number of overall MSHR uncacheable misses system.cpu0.icache.overall_mshr_uncacheable_misses::total 52309 # number of overall MSHR uncacheable misses system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 97815809000 # number of ReadReq MSHR miss cycles system.cpu0.icache.ReadReq_mshr_miss_latency::total 97815809000 # number of ReadReq MSHR miss cycles system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 97815809000 # number of demand (read+write) MSHR miss cycles system.cpu0.icache.demand_mshr_miss_latency::total 97815809000 # number of demand (read+write) MSHR miss cycles system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 97815809000 # number of overall MSHR miss cycles system.cpu0.icache.overall_mshr_miss_latency::total 97815809000 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 7414627000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 7414627000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 7414627000 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 7414627000 # number of overall MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.038005 # mshr miss rate for ReadReq accesses system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.038005 # mshr miss rate for ReadReq accesses system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.038005 # mshr miss rate for demand accesses system.cpu0.icache.demand_mshr_miss_rate::total 0.038005 # mshr miss rate for demand accesses system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.038005 # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_miss_rate::total 0.038005 # mshr miss rate for overall accesses system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10194.828264 # average ReadReq mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10194.828264 # average ReadReq mshr miss latency system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10194.828264 # average overall mshr miss latency system.cpu0.icache.demand_avg_mshr_miss_latency::total 10194.828264 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10194.828264 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_miss_latency::total 10194.828264 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 141746.678392 # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 141746.678392 # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 141746.678392 # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 141746.678392 # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.l2cache.prefetcher.num_hwpf_issued 8065650 # number of hwpf issued system.cpu0.l2cache.prefetcher.pfIdentified 8066797 # number of prefetch candidates identified system.cpu0.l2cache.prefetcher.pfBufferHit 1004 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size system.cpu0.l2cache.prefetcher.pfSpanPage 1049003 # number of prefetches not generated due to page crossing system.cpu0.l2cache.tags.replacements 2949800 # number of replacements system.cpu0.l2cache.tags.tagsinuse 16165.081558 # Cycle average of tags in use system.cpu0.l2cache.tags.total_refs 23810069 # Total number of references to valid blocks. system.cpu0.l2cache.tags.sampled_refs 2965603 # Sample count of references to valid blocks. system.cpu0.l2cache.tags.avg_refs 8.028745 # Average number of references to valid blocks. system.cpu0.l2cache.tags.warmup_cycle 9049945000 # Cycle when the warmup percentage was hit. system.cpu0.l2cache.tags.occ_blocks::writebacks 15191.178363 # Average occupied blocks per requestor system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 63.510017 # Average occupied blocks per requestor system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 64.560721 # Average occupied blocks per requestor system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 845.832457 # Average occupied blocks per requestor system.cpu0.l2cache.tags.occ_percent::writebacks 0.927196 # Average percentage of cache occupancy system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003876 # Average percentage of cache occupancy system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.003940 # Average percentage of cache occupancy system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.051626 # Average percentage of cache occupancy system.cpu0.l2cache.tags.occ_percent::total 0.986638 # Average percentage of cache occupancy system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1186 # Occupied blocks per task id system.cpu0.l2cache.tags.occ_task_id_blocks::1023 68 # Occupied blocks per task id system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14549 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 43 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 162 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 909 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 72 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 45 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 19 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 3 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 130 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 878 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5504 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7511 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 526 # Occupied blocks per task id system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.072388 # Percentage of cache occupancy per task id system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.004150 # Percentage of cache occupancy per task id system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.888000 # Percentage of cache occupancy per task id system.cpu0.l2cache.tags.tag_accesses 520895158 # Number of tag accesses system.cpu0.l2cache.tags.data_accesses 520895158 # Number of data accesses system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 527427 # number of ReadReq hits system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 170829 # number of ReadReq hits system.cpu0.l2cache.ReadReq_hits::total 698256 # number of ReadReq hits system.cpu0.l2cache.WritebackDirty_hits::writebacks 3866912 # number of WritebackDirty hits system.cpu0.l2cache.WritebackDirty_hits::total 3866912 # number of WritebackDirty hits system.cpu0.l2cache.WritebackClean_hits::writebacks 11575004 # number of WritebackClean hits system.cpu0.l2cache.WritebackClean_hits::total 11575004 # number of WritebackClean hits system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 494 # number of UpgradeReq hits system.cpu0.l2cache.UpgradeReq_hits::total 494 # number of UpgradeReq hits system.cpu0.l2cache.ReadExReq_hits::cpu0.data 901398 # number of ReadExReq hits system.cpu0.l2cache.ReadExReq_hits::total 901398 # number of ReadExReq hits system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 8819397 # number of ReadCleanReq hits system.cpu0.l2cache.ReadCleanReq_hits::total 8819397 # number of ReadCleanReq hits system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 2877090 # number of ReadSharedReq hits system.cpu0.l2cache.ReadSharedReq_hits::total 2877090 # number of ReadSharedReq hits system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 196747 # number of InvalidateReq hits system.cpu0.l2cache.InvalidateReq_hits::total 196747 # number of InvalidateReq hits system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 527427 # number of demand (read+write) hits system.cpu0.l2cache.demand_hits::cpu0.itb.walker 170829 # number of demand (read+write) hits system.cpu0.l2cache.demand_hits::cpu0.inst 8819397 # number of demand (read+write) hits system.cpu0.l2cache.demand_hits::cpu0.data 3778488 # number of demand (read+write) hits system.cpu0.l2cache.demand_hits::total 13296141 # number of demand (read+write) hits system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 527427 # number of overall hits system.cpu0.l2cache.overall_hits::cpu0.itb.walker 170829 # number of overall hits system.cpu0.l2cache.overall_hits::cpu0.inst 8819397 # number of overall hits system.cpu0.l2cache.overall_hits::cpu0.data 3778488 # number of overall hits system.cpu0.l2cache.overall_hits::total 13296141 # number of overall hits system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 12512 # number of ReadReq misses system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 8836 # number of ReadReq misses system.cpu0.l2cache.ReadReq_misses::total 21348 # number of ReadReq misses system.cpu0.l2cache.WritebackDirty_misses::writebacks 2 # number of WritebackDirty misses system.cpu0.l2cache.WritebackDirty_misses::total 2 # number of WritebackDirty misses system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 265863 # number of UpgradeReq misses system.cpu0.l2cache.UpgradeReq_misses::total 265863 # number of UpgradeReq misses system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 207797 # number of SCUpgradeReq misses system.cpu0.l2cache.SCUpgradeReq_misses::total 207797 # number of SCUpgradeReq misses system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 9 # number of SCUpgradeFailReq misses system.cpu0.l2cache.SCUpgradeFailReq_misses::total 9 # number of SCUpgradeFailReq misses system.cpu0.l2cache.ReadExReq_misses::cpu0.data 295222 # number of ReadExReq misses system.cpu0.l2cache.ReadExReq_misses::total 295222 # number of ReadExReq misses system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 775252 # number of ReadCleanReq misses system.cpu0.l2cache.ReadCleanReq_misses::total 775252 # number of ReadCleanReq misses system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 1066801 # number of ReadSharedReq misses system.cpu0.l2cache.ReadSharedReq_misses::total 1066801 # number of ReadSharedReq misses system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 607029 # number of InvalidateReq misses system.cpu0.l2cache.InvalidateReq_misses::total 607029 # number of InvalidateReq misses system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 12512 # number of demand (read+write) misses system.cpu0.l2cache.demand_misses::cpu0.itb.walker 8836 # number of demand (read+write) misses system.cpu0.l2cache.demand_misses::cpu0.inst 775252 # number of demand (read+write) misses system.cpu0.l2cache.demand_misses::cpu0.data 1362023 # number of demand (read+write) misses system.cpu0.l2cache.demand_misses::total 2158623 # number of demand (read+write) misses system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 12512 # number of overall misses system.cpu0.l2cache.overall_misses::cpu0.itb.walker 8836 # number of overall misses system.cpu0.l2cache.overall_misses::cpu0.inst 775252 # number of overall misses system.cpu0.l2cache.overall_misses::cpu0.data 1362023 # number of overall misses system.cpu0.l2cache.overall_misses::total 2158623 # number of overall misses system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 555558000 # number of ReadReq miss cycles system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 430868000 # number of ReadReq miss cycles system.cpu0.l2cache.ReadReq_miss_latency::total 986426000 # number of ReadReq miss cycles system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 3493305000 # number of UpgradeReq miss cycles system.cpu0.l2cache.UpgradeReq_miss_latency::total 3493305000 # number of UpgradeReq miss cycles system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 1939943000 # number of SCUpgradeReq miss cycles system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 1939943000 # number of SCUpgradeReq miss cycles system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 4477498 # number of SCUpgradeFailReq miss cycles system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 4477498 # number of SCUpgradeFailReq miss cycles system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 18708847499 # number of ReadExReq miss cycles system.cpu0.l2cache.ReadExReq_miss_latency::total 18708847499 # number of ReadExReq miss cycles system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 30179302500 # number of ReadCleanReq miss cycles system.cpu0.l2cache.ReadCleanReq_miss_latency::total 30179302500 # number of ReadCleanReq miss cycles system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 44632390995 # number of ReadSharedReq miss cycles system.cpu0.l2cache.ReadSharedReq_miss_latency::total 44632390995 # number of ReadSharedReq miss cycles system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data 67815733000 # number of InvalidateReq miss cycles system.cpu0.l2cache.InvalidateReq_miss_latency::total 67815733000 # number of InvalidateReq miss cycles system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 555558000 # number of demand (read+write) miss cycles system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 430868000 # number of demand (read+write) miss cycles system.cpu0.l2cache.demand_miss_latency::cpu0.inst 30179302500 # number of demand (read+write) miss cycles system.cpu0.l2cache.demand_miss_latency::cpu0.data 63341238494 # number of demand (read+write) miss cycles system.cpu0.l2cache.demand_miss_latency::total 94506966994 # number of demand (read+write) miss cycles system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 555558000 # number of overall miss cycles system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 430868000 # number of overall miss cycles system.cpu0.l2cache.overall_miss_latency::cpu0.inst 30179302500 # number of overall miss cycles system.cpu0.l2cache.overall_miss_latency::cpu0.data 63341238494 # number of overall miss cycles system.cpu0.l2cache.overall_miss_latency::total 94506966994 # number of overall miss cycles system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 539939 # number of ReadReq accesses(hits+misses) system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 179665 # number of ReadReq accesses(hits+misses) system.cpu0.l2cache.ReadReq_accesses::total 719604 # number of ReadReq accesses(hits+misses) system.cpu0.l2cache.WritebackDirty_accesses::writebacks 3866914 # number of WritebackDirty accesses(hits+misses) system.cpu0.l2cache.WritebackDirty_accesses::total 3866914 # number of WritebackDirty accesses(hits+misses) system.cpu0.l2cache.WritebackClean_accesses::writebacks 11575004 # number of WritebackClean accesses(hits+misses) system.cpu0.l2cache.WritebackClean_accesses::total 11575004 # number of WritebackClean accesses(hits+misses) system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 266357 # number of UpgradeReq accesses(hits+misses) system.cpu0.l2cache.UpgradeReq_accesses::total 266357 # number of UpgradeReq accesses(hits+misses) system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 207797 # number of SCUpgradeReq accesses(hits+misses) system.cpu0.l2cache.SCUpgradeReq_accesses::total 207797 # number of SCUpgradeReq accesses(hits+misses) system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 9 # number of SCUpgradeFailReq accesses(hits+misses) system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 9 # number of SCUpgradeFailReq accesses(hits+misses) system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1196620 # number of ReadExReq accesses(hits+misses) system.cpu0.l2cache.ReadExReq_accesses::total 1196620 # number of ReadExReq accesses(hits+misses) system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 9594649 # number of ReadCleanReq accesses(hits+misses) system.cpu0.l2cache.ReadCleanReq_accesses::total 9594649 # number of ReadCleanReq accesses(hits+misses) system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 3943891 # number of ReadSharedReq accesses(hits+misses) system.cpu0.l2cache.ReadSharedReq_accesses::total 3943891 # number of ReadSharedReq accesses(hits+misses) system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 803776 # number of InvalidateReq accesses(hits+misses) system.cpu0.l2cache.InvalidateReq_accesses::total 803776 # number of InvalidateReq accesses(hits+misses) system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 539939 # number of demand (read+write) accesses system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 179665 # number of demand (read+write) accesses system.cpu0.l2cache.demand_accesses::cpu0.inst 9594649 # number of demand (read+write) accesses system.cpu0.l2cache.demand_accesses::cpu0.data 5140511 # number of demand (read+write) accesses system.cpu0.l2cache.demand_accesses::total 15454764 # number of demand (read+write) accesses system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 539939 # number of overall (read+write) accesses system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 179665 # number of overall (read+write) accesses system.cpu0.l2cache.overall_accesses::cpu0.inst 9594649 # number of overall (read+write) accesses system.cpu0.l2cache.overall_accesses::cpu0.data 5140511 # number of overall (read+write) accesses system.cpu0.l2cache.overall_accesses::total 15454764 # number of overall (read+write) accesses system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.023173 # miss rate for ReadReq accesses system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.049180 # miss rate for ReadReq accesses system.cpu0.l2cache.ReadReq_miss_rate::total 0.029666 # miss rate for ReadReq accesses system.cpu0.l2cache.WritebackDirty_miss_rate::writebacks 0.000001 # miss rate for WritebackDirty accesses system.cpu0.l2cache.WritebackDirty_miss_rate::total 0.000001 # miss rate for WritebackDirty accesses system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.998145 # miss rate for UpgradeReq accesses system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.998145 # miss rate for UpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.246713 # miss rate for ReadExReq accesses system.cpu0.l2cache.ReadExReq_miss_rate::total 0.246713 # miss rate for ReadExReq accesses system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.080800 # miss rate for ReadCleanReq accesses system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.080800 # miss rate for ReadCleanReq accesses system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.270495 # miss rate for ReadSharedReq accesses system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.270495 # miss rate for ReadSharedReq accesses system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.755222 # miss rate for InvalidateReq accesses system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.755222 # miss rate for InvalidateReq accesses system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.023173 # miss rate for demand accesses system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.049180 # miss rate for demand accesses system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.080800 # miss rate for demand accesses system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.264959 # miss rate for demand accesses system.cpu0.l2cache.demand_miss_rate::total 0.139674 # miss rate for demand accesses system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.023173 # miss rate for overall accesses system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.049180 # miss rate for overall accesses system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.080800 # miss rate for overall accesses system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.264959 # miss rate for overall accesses system.cpu0.l2cache.overall_miss_rate::total 0.139674 # miss rate for overall accesses system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 44402.014066 # average ReadReq miss latency system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 48762.788592 # average ReadReq miss latency system.cpu0.l2cache.ReadReq_avg_miss_latency::total 46206.951471 # average ReadReq miss latency system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 13139.492897 # average UpgradeReq miss latency system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 13139.492897 # average UpgradeReq miss latency system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 9335.760382 # average SCUpgradeReq miss latency system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 9335.760382 # average SCUpgradeReq miss latency system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 497499.777778 # average SCUpgradeFailReq miss latency system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 497499.777778 # average SCUpgradeFailReq miss latency system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 63372.131816 # average ReadExReq miss latency system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 63372.131816 # average ReadExReq miss latency system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 38928.377482 # average ReadCleanReq miss latency system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 38928.377482 # average ReadCleanReq miss latency system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 41837.597635 # average ReadSharedReq miss latency system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 41837.597635 # average ReadSharedReq miss latency system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 111717.451720 # average InvalidateReq miss latency system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 111717.451720 # average InvalidateReq miss latency system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 44402.014066 # average overall miss latency system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 48762.788592 # average overall miss latency system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 38928.377482 # average overall miss latency system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 46505.263490 # average overall miss latency system.cpu0.l2cache.demand_avg_miss_latency::total 43781.135934 # average overall miss latency system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 44402.014066 # average overall miss latency system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 48762.788592 # average overall miss latency system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 38928.377482 # average overall miss latency system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 46505.263490 # average overall miss latency system.cpu0.l2cache.overall_avg_miss_latency::total 43781.135934 # average overall miss latency system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.l2cache.fast_writes 0 # number of fast writes performed system.cpu0.l2cache.cache_copies 0 # number of cache copies performed system.cpu0.l2cache.writebacks::writebacks 1702054 # number of writebacks system.cpu0.l2cache.writebacks::total 1702054 # number of writebacks system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker 1 # number of ReadReq MSHR hits system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 3 # number of ReadReq MSHR hits system.cpu0.l2cache.ReadReq_mshr_hits::total 4 # number of ReadReq MSHR hits system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 8173 # number of ReadExReq MSHR hits system.cpu0.l2cache.ReadExReq_mshr_hits::total 8173 # number of ReadExReq MSHR hits system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 11 # number of ReadCleanReq MSHR hits system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 11 # number of ReadCleanReq MSHR hits system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 1611 # number of ReadSharedReq MSHR hits system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 1611 # number of ReadSharedReq MSHR hits system.cpu0.l2cache.InvalidateReq_mshr_hits::cpu0.data 4 # number of InvalidateReq MSHR hits system.cpu0.l2cache.InvalidateReq_mshr_hits::total 4 # number of InvalidateReq MSHR hits system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker 1 # number of demand (read+write) MSHR hits system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 3 # number of demand (read+write) MSHR hits system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 11 # number of demand (read+write) MSHR hits system.cpu0.l2cache.demand_mshr_hits::cpu0.data 9784 # number of demand (read+write) MSHR hits system.cpu0.l2cache.demand_mshr_hits::total 9799 # number of demand (read+write) MSHR hits system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker 1 # number of overall MSHR hits system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 3 # number of overall MSHR hits system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 11 # number of overall MSHR hits system.cpu0.l2cache.overall_mshr_hits::cpu0.data 9784 # number of overall MSHR hits system.cpu0.l2cache.overall_mshr_hits::total 9799 # number of overall MSHR hits system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 12511 # number of ReadReq MSHR misses system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 8833 # number of ReadReq MSHR misses system.cpu0.l2cache.ReadReq_mshr_misses::total 21344 # number of ReadReq MSHR misses system.cpu0.l2cache.WritebackDirty_mshr_misses::writebacks 2 # number of WritebackDirty MSHR misses system.cpu0.l2cache.WritebackDirty_mshr_misses::total 2 # number of WritebackDirty MSHR misses system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 812970 # number of HardPFReq MSHR misses system.cpu0.l2cache.HardPFReq_mshr_misses::total 812970 # number of HardPFReq MSHR misses system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 265863 # number of UpgradeReq MSHR misses system.cpu0.l2cache.UpgradeReq_mshr_misses::total 265863 # number of UpgradeReq MSHR misses system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 207797 # number of SCUpgradeReq MSHR misses system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 207797 # number of SCUpgradeReq MSHR misses system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 9 # number of SCUpgradeFailReq MSHR misses system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 9 # number of SCUpgradeFailReq MSHR misses system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 287049 # number of ReadExReq MSHR misses system.cpu0.l2cache.ReadExReq_mshr_misses::total 287049 # number of ReadExReq MSHR misses system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 775241 # number of ReadCleanReq MSHR misses system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 775241 # number of ReadCleanReq MSHR misses system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 1065190 # number of ReadSharedReq MSHR misses system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 1065190 # number of ReadSharedReq MSHR misses system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data 607025 # number of InvalidateReq MSHR misses system.cpu0.l2cache.InvalidateReq_mshr_misses::total 607025 # number of InvalidateReq MSHR misses system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 12511 # number of demand (read+write) MSHR misses system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 8833 # number of demand (read+write) MSHR misses system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 775241 # number of demand (read+write) MSHR misses system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1352239 # number of demand (read+write) MSHR misses system.cpu0.l2cache.demand_mshr_misses::total 2148824 # number of demand (read+write) MSHR misses system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 12511 # number of overall MSHR misses system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 8833 # number of overall MSHR misses system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 775241 # number of overall MSHR misses system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1352239 # number of overall MSHR misses system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 812970 # number of overall MSHR misses system.cpu0.l2cache.overall_mshr_misses::total 2961794 # number of overall MSHR misses system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 52309 # number of ReadReq MSHR uncacheable system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 19530 # number of ReadReq MSHR uncacheable system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 71839 # number of ReadReq MSHR uncacheable system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 21048 # number of WriteReq MSHR uncacheable system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 21048 # number of WriteReq MSHR uncacheable system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 52309 # number of overall MSHR uncacheable misses system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 40578 # number of overall MSHR uncacheable misses system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 92887 # number of overall MSHR uncacheable misses system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 480468000 # number of ReadReq MSHR miss cycles system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 377798500 # number of ReadReq MSHR miss cycles system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 858266500 # number of ReadReq MSHR miss cycles system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 44849426201 # number of HardPFReq MSHR miss cycles system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 44849426201 # number of HardPFReq MSHR miss cycles system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 7795522498 # number of UpgradeReq MSHR miss cycles system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 7795522498 # number of UpgradeReq MSHR miss cycles system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 4002040000 # number of SCUpgradeReq MSHR miss cycles system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 4002040000 # number of SCUpgradeReq MSHR miss cycles system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 4147498 # number of SCUpgradeFailReq MSHR miss cycles system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 4147498 # number of SCUpgradeFailReq MSHR miss cycles system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 15893166999 # number of ReadExReq MSHR miss cycles system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 15893166999 # number of ReadExReq MSHR miss cycles system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 25527386000 # number of ReadCleanReq MSHR miss cycles system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 25527386000 # number of ReadCleanReq MSHR miss cycles system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 38109816995 # number of ReadSharedReq MSHR miss cycles system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 38109816995 # number of ReadSharedReq MSHR miss cycles system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 64173364000 # number of InvalidateReq MSHR miss cycles system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 64173364000 # number of InvalidateReq MSHR miss cycles system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 480468000 # number of demand (read+write) MSHR miss cycles system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 377798500 # number of demand (read+write) MSHR miss cycles system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 25527386000 # number of demand (read+write) MSHR miss cycles system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 54002983994 # number of demand (read+write) MSHR miss cycles system.cpu0.l2cache.demand_mshr_miss_latency::total 80388636494 # number of demand (read+write) MSHR miss cycles system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 480468000 # number of overall MSHR miss cycles system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 377798500 # number of overall MSHR miss cycles system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 25527386000 # number of overall MSHR miss cycles system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 54002983994 # number of overall MSHR miss cycles system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 44849426201 # number of overall MSHR miss cycles system.cpu0.l2cache.overall_mshr_miss_latency::total 125238062695 # number of overall MSHR miss cycles system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 6996155000 # number of ReadReq MSHR uncacheable cycles system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 3644540000 # number of ReadReq MSHR uncacheable cycles system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 10640695000 # number of ReadReq MSHR uncacheable cycles system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 3813756000 # number of WriteReq MSHR uncacheable cycles system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 3813756000 # number of WriteReq MSHR uncacheable cycles system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 6996155000 # number of overall MSHR uncacheable cycles system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 7458296000 # number of overall MSHR uncacheable cycles system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 14454451000 # number of overall MSHR uncacheable cycles system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.023171 # mshr miss rate for ReadReq accesses system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.049164 # mshr miss rate for ReadReq accesses system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.029661 # mshr miss rate for ReadReq accesses system.cpu0.l2cache.WritebackDirty_mshr_miss_rate::writebacks 0.000001 # mshr miss rate for WritebackDirty accesses system.cpu0.l2cache.WritebackDirty_mshr_miss_rate::total 0.000001 # mshr miss rate for WritebackDirty accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.998145 # mshr miss rate for UpgradeReq accesses system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.998145 # mshr miss rate for UpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.239883 # mshr miss rate for ReadExReq accesses system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.239883 # mshr miss rate for ReadExReq accesses system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.080799 # mshr miss rate for ReadCleanReq accesses system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.080799 # mshr miss rate for ReadCleanReq accesses system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.270086 # mshr miss rate for ReadSharedReq accesses system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.270086 # mshr miss rate for ReadSharedReq accesses system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.755217 # mshr miss rate for InvalidateReq accesses system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.755217 # mshr miss rate for InvalidateReq accesses system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.023171 # mshr miss rate for demand accesses system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.049164 # mshr miss rate for demand accesses system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.080799 # mshr miss rate for demand accesses system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.263055 # mshr miss rate for demand accesses system.cpu0.l2cache.demand_mshr_miss_rate::total 0.139040 # mshr miss rate for demand accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.023171 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.049164 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.080799 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.263055 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::total 0.191643 # mshr miss rate for overall accesses system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 38403.644793 # average ReadReq mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 42771.255519 # average ReadReq mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 40211.136619 # average ReadReq mshr miss latency system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 55167.381577 # average HardPFReq mshr miss latency system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 55167.381577 # average HardPFReq mshr miss latency system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 29321.577271 # average UpgradeReq mshr miss latency system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 29321.577271 # average UpgradeReq mshr miss latency system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 19259.373331 # average SCUpgradeReq mshr miss latency system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19259.373331 # average SCUpgradeReq mshr miss latency system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 460833.111111 # average SCUpgradeFailReq mshr miss latency system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 460833.111111 # average SCUpgradeFailReq mshr miss latency system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 55367.435521 # average ReadExReq mshr miss latency system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 55367.435521 # average ReadExReq mshr miss latency system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 32928.322934 # average ReadCleanReq mshr miss latency system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 32928.322934 # average ReadCleanReq mshr miss latency system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 35777.482886 # average ReadSharedReq mshr miss latency system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 35777.482886 # average ReadSharedReq mshr miss latency system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 105717.827108 # average InvalidateReq mshr miss latency system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 105717.827108 # average InvalidateReq mshr miss latency system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 38403.644793 # average overall mshr miss latency system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 42771.255519 # average overall mshr miss latency system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 32928.322934 # average overall mshr miss latency system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 39935.975810 # average overall mshr miss latency system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 37410.526173 # average overall mshr miss latency system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 38403.644793 # average overall mshr miss latency system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 42771.255519 # average overall mshr miss latency system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 32928.322934 # average overall mshr miss latency system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 39935.975810 # average overall mshr miss latency system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 55167.381577 # average overall mshr miss latency system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 42284.528463 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 133746.678392 # average ReadReq mshr uncacheable latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 186612.391193 # average ReadReq mshr uncacheable latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 148118.640293 # average ReadReq mshr uncacheable latency system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 181193.272520 # average WriteReq mshr uncacheable latency system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 181193.272520 # average WriteReq mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 133746.678392 # average overall mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 183801.468776 # average overall mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 155613.282806 # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.toL2Bus.snoop_filter.tot_requests 31782914 # Total number of requests made to the snoop filter. system.cpu0.toL2Bus.snoop_filter.hit_single_requests 16244108 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 2495 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu0.toL2Bus.snoop_filter.tot_snoops 2292721 # Total number of snoops made to the snoop filter. system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 2292254 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 467 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu0.toL2Bus.trans_dist::ReadReq 871142 # Transaction distribution system.cpu0.toL2Bus.trans_dist::ReadResp 14502039 # Transaction distribution system.cpu0.toL2Bus.trans_dist::WriteReq 21048 # Transaction distribution system.cpu0.toL2Bus.trans_dist::WriteResp 21048 # Transaction distribution system.cpu0.toL2Bus.trans_dist::WritebackDirty 5574338 # Transaction distribution system.cpu0.toL2Bus.trans_dist::WritebackClean 11577498 # Transaction distribution system.cpu0.toL2Bus.trans_dist::CleanEvict 3160606 # Transaction distribution system.cpu0.toL2Bus.trans_dist::HardPFReq 1056652 # Transaction distribution system.cpu0.toL2Bus.trans_dist::UpgradeReq 471328 # Transaction distribution system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 370548 # Transaction distribution system.cpu0.toL2Bus.trans_dist::UpgradeResp 537517 # Transaction distribution system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 70 # Transaction distribution system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 116 # Transaction distribution system.cpu0.toL2Bus.trans_dist::ReadExReq 1276044 # Transaction distribution system.cpu0.toL2Bus.trans_dist::ReadExResp 1205760 # Transaction distribution system.cpu0.toL2Bus.trans_dist::ReadCleanReq 9594650 # Transaction distribution system.cpu0.toL2Bus.trans_dist::ReadSharedReq 5010763 # Transaction distribution system.cpu0.toL2Bus.trans_dist::InvalidateReq 810566 # Transaction distribution system.cpu0.toL2Bus.trans_dist::InvalidateResp 803776 # Transaction distribution system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 28888045 # Packet count per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 18933308 # Packet count per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 377591 # Packet count per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1141314 # Packet count per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_count::total 49340258 # Packet count per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 1231429504 # Cumulative packet size per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 710021103 # Cumulative packet size per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1437320 # Cumulative packet size per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4319512 # Cumulative packet size per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_size::total 1947207439 # Cumulative packet size per connected master and slave (bytes) system.cpu0.toL2Bus.snoops 7690219 # Total snoops (count) system.cpu0.toL2Bus.snoop_fanout::samples 24350841 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::mean 0.107639 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::stdev 0.309986 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::0 21730213 89.24% 89.24% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::1 2620161 10.76% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::2 467 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::total 24350841 # Request fanout histogram system.cpu0.toL2Bus.reqLayer0.occupancy 31629791489 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.cpu0.toL2Bus.snoopLayer0.occupancy 184209930 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) system.cpu0.toL2Bus.respLayer0.occupancy 14474040275 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu0.toL2Bus.respLayer1.occupancy 8384067550 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu0.toL2Bus.respLayer2.occupancy 198003844 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) system.cpu0.toL2Bus.respLayer3.occupancy 601473802 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu1.branchPred.lookups 133924240 # Number of BP lookups system.cpu1.branchPred.condPredicted 95730476 # Number of conditional branches predicted system.cpu1.branchPred.condIncorrect 5982653 # Number of conditional branches incorrect system.cpu1.branchPred.BTBLookups 100302023 # Number of BTB lookups system.cpu1.branchPred.BTBHits 73831862 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu1.branchPred.BTBHitPct 73.609544 # BTB Hit Percentage system.cpu1.branchPred.usedRAS 15419194 # Number of times the RAS was used to get a target. system.cpu1.branchPred.RASInCorrect 1021732 # Number of incorrect RAS predictions. system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.walker.walks 293746 # Table walker walks requested system.cpu1.dtb.walker.walksLong 293746 # Table walker walks initiated with long descriptors system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 11413 # Level at which table walker walks with long descriptors terminate system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 90757 # Level at which table walker walks with long descriptors terminate system.cpu1.dtb.walker.walkWaitTime::samples 293746 # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walkWaitTime::0 293746 100.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walkWaitTime::total 293746 # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walkCompletionTime::samples 102170 # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::mean 23413.986493 # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::gmean 21412.179846 # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::stdev 20342.964000 # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::0-65535 100862 98.72% 98.72% # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::65536-131071 167 0.16% 98.88% # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::131072-196607 952 0.93% 99.82% # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::196608-262143 45 0.04% 99.86% # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::262144-327679 52 0.05% 99.91% # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::327680-393215 35 0.03% 99.94% # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::393216-458751 35 0.03% 99.98% # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::458752-524287 12 0.01% 99.99% # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::524288-589823 6 0.01% 100.00% # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::589824-655359 3 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::total 102170 # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walksPending::samples 527505760 # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::0 527505760 100.00% 100.00% # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::total 527505760 # Table walker pending requests distribution system.cpu1.dtb.walker.walkPageSizes::4K 90757 88.83% 88.83% # Table walker page sizes translated system.cpu1.dtb.walker.walkPageSizes::2M 11413 11.17% 100.00% # Table walker page sizes translated system.cpu1.dtb.walker.walkPageSizes::total 102170 # Table walker page sizes translated system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 293746 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 293746 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 102170 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 102170 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin::total 395916 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses system.cpu1.dtb.read_hits 86040245 # DTB read hits system.cpu1.dtb.read_misses 244355 # DTB read misses system.cpu1.dtb.write_hits 75067998 # DTB write hits system.cpu1.dtb.write_misses 49391 # DTB write misses system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 42784 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 1060 # Number of times TLB was flushed by ASID system.cpu1.dtb.flush_entries 37937 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 1338 # Number of TLB faults due to alignment restrictions system.cpu1.dtb.prefetch_faults 8312 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 11189 # Number of TLB faults due to permissions restrictions system.cpu1.dtb.read_accesses 86284600 # DTB read accesses system.cpu1.dtb.write_accesses 75117389 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses system.cpu1.dtb.hits 161108243 # DTB hits system.cpu1.dtb.misses 293746 # DTB misses system.cpu1.dtb.accesses 161401989 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.itb.walker.walks 65124 # Table walker walks requested system.cpu1.itb.walker.walksLong 65124 # Table walker walks initiated with long descriptors system.cpu1.itb.walker.walksLongTerminationLevel::Level2 508 # Level at which table walker walks with long descriptors terminate system.cpu1.itb.walker.walksLongTerminationLevel::Level3 55766 # Level at which table walker walks with long descriptors terminate system.cpu1.itb.walker.walkWaitTime::samples 65124 # Table walker wait (enqueue to first request) latency system.cpu1.itb.walker.walkWaitTime::0 65124 100.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu1.itb.walker.walkWaitTime::total 65124 # Table walker wait (enqueue to first request) latency system.cpu1.itb.walker.walkCompletionTime::samples 56274 # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::mean 26926.564666 # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::gmean 23857.779953 # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::stdev 24945.648372 # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::0-65535 54940 97.63% 97.63% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::65536-131071 10 0.02% 97.65% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::131072-196607 1199 2.13% 99.78% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::196608-262143 37 0.07% 99.84% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::262144-327679 49 0.09% 99.93% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::327680-393215 24 0.04% 99.97% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::393216-458751 8 0.01% 99.99% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::458752-524287 3 0.01% 99.99% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::total 56274 # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walksPending::samples 526611260 # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::0 526611260 100.00% 100.00% # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::total 526611260 # Table walker pending requests distribution system.cpu1.itb.walker.walkPageSizes::4K 55766 99.10% 99.10% # Table walker page sizes translated system.cpu1.itb.walker.walkPageSizes::2M 508 0.90% 100.00% # Table walker page sizes translated system.cpu1.itb.walker.walkPageSizes::total 56274 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 65124 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Requested::total 65124 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 56274 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::total 56274 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin::total 121398 # Table walker requests started/completed, data/inst system.cpu1.itb.inst_hits 239249458 # ITB inst hits system.cpu1.itb.inst_misses 65124 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 42784 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 1060 # Number of times TLB was flushed by ASID system.cpu1.itb.flush_entries 26970 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 220780 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses system.cpu1.itb.inst_accesses 239314582 # ITB inst accesses system.cpu1.itb.hits 239249458 # DTB hits system.cpu1.itb.misses 65124 # DTB misses system.cpu1.itb.accesses 239314582 # DTB accesses system.cpu1.numCycles 947127317 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.committedInsts 437680583 # Number of instructions committed system.cpu1.committedOps 515109454 # Number of ops (including micro ops) committed system.cpu1.discardedOps 47548266 # Number of ops (including micro ops) which were discarded before commit system.cpu1.numFetchSuspends 4998 # Number of times Execute suspended instruction fetching system.cpu1.quiesceCycles 93977493591 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt system.cpu1.cpi 2.163969 # CPI: cycles per instruction system.cpu1.ipc 0.462114 # IPC: instructions per cycle system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 13761 # number of quiesce instructions executed system.cpu1.tickCycles 715510770 # Number of cycles that the object actually ticked system.cpu1.idleCycles 231616547 # Total number of cycles that the object has spent stopped system.cpu1.dcache.tags.replacements 5225400 # number of replacements system.cpu1.dcache.tags.tagsinuse 442.020428 # Cycle average of tags in use system.cpu1.dcache.tags.total_refs 153149767 # Total number of references to valid blocks. system.cpu1.dcache.tags.sampled_refs 5225912 # Sample count of references to valid blocks. system.cpu1.dcache.tags.avg_refs 29.305845 # Average number of references to valid blocks. system.cpu1.dcache.tags.warmup_cycle 8545383120500 # Cycle when the warmup percentage was hit. system.cpu1.dcache.tags.occ_blocks::cpu1.data 442.020428 # Average occupied blocks per requestor system.cpu1.dcache.tags.occ_percent::cpu1.data 0.863321 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_percent::total 0.863321 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::0 73 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::1 408 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::2 31 # Occupied blocks per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu1.dcache.tags.tag_accesses 324837482 # Number of tag accesses system.cpu1.dcache.tags.data_accesses 324837482 # Number of data accesses system.cpu1.dcache.ReadReq_hits::cpu1.data 78835589 # number of ReadReq hits system.cpu1.dcache.ReadReq_hits::total 78835589 # number of ReadReq hits system.cpu1.dcache.WriteReq_hits::cpu1.data 69932856 # number of WriteReq hits system.cpu1.dcache.WriteReq_hits::total 69932856 # number of WriteReq hits system.cpu1.dcache.SoftPFReq_hits::cpu1.data 235045 # number of SoftPFReq hits system.cpu1.dcache.SoftPFReq_hits::total 235045 # number of SoftPFReq hits system.cpu1.dcache.WriteLineReq_hits::cpu1.data 136840 # number of WriteLineReq hits system.cpu1.dcache.WriteLineReq_hits::total 136840 # number of WriteLineReq hits system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1777859 # number of LoadLockedReq hits system.cpu1.dcache.LoadLockedReq_hits::total 1777859 # number of LoadLockedReq hits system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1734680 # number of StoreCondReq hits system.cpu1.dcache.StoreCondReq_hits::total 1734680 # number of StoreCondReq hits system.cpu1.dcache.demand_hits::cpu1.data 148768445 # number of demand (read+write) hits system.cpu1.dcache.demand_hits::total 148768445 # number of demand (read+write) hits system.cpu1.dcache.overall_hits::cpu1.data 149003490 # number of overall hits system.cpu1.dcache.overall_hits::total 149003490 # number of overall hits system.cpu1.dcache.ReadReq_misses::cpu1.data 3368921 # number of ReadReq misses system.cpu1.dcache.ReadReq_misses::total 3368921 # number of ReadReq misses system.cpu1.dcache.WriteReq_misses::cpu1.data 2278073 # number of WriteReq misses system.cpu1.dcache.WriteReq_misses::total 2278073 # number of WriteReq misses system.cpu1.dcache.SoftPFReq_misses::cpu1.data 647676 # number of SoftPFReq misses system.cpu1.dcache.SoftPFReq_misses::total 647676 # number of SoftPFReq misses system.cpu1.dcache.WriteLineReq_misses::cpu1.data 450910 # number of WriteLineReq misses system.cpu1.dcache.WriteLineReq_misses::total 450910 # number of WriteLineReq misses system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 159516 # number of LoadLockedReq misses system.cpu1.dcache.LoadLockedReq_misses::total 159516 # number of LoadLockedReq misses system.cpu1.dcache.StoreCondReq_misses::cpu1.data 201171 # number of StoreCondReq misses system.cpu1.dcache.StoreCondReq_misses::total 201171 # number of StoreCondReq misses system.cpu1.dcache.demand_misses::cpu1.data 5646994 # number of demand (read+write) misses system.cpu1.dcache.demand_misses::total 5646994 # number of demand (read+write) misses system.cpu1.dcache.overall_misses::cpu1.data 6294670 # number of overall misses system.cpu1.dcache.overall_misses::total 6294670 # number of overall misses system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 55794276000 # number of ReadReq miss cycles system.cpu1.dcache.ReadReq_miss_latency::total 55794276000 # number of ReadReq miss cycles system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 51841670500 # number of WriteReq miss cycles system.cpu1.dcache.WriteReq_miss_latency::total 51841670500 # number of WriteReq miss cycles system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 21264976000 # number of WriteLineReq miss cycles system.cpu1.dcache.WriteLineReq_miss_latency::total 21264976000 # number of WriteLineReq miss cycles system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2730537500 # number of LoadLockedReq miss cycles system.cpu1.dcache.LoadLockedReq_miss_latency::total 2730537500 # number of LoadLockedReq miss cycles system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 5515974000 # number of StoreCondReq miss cycles system.cpu1.dcache.StoreCondReq_miss_latency::total 5515974000 # number of StoreCondReq miss cycles system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 4942500 # number of StoreCondFailReq miss cycles system.cpu1.dcache.StoreCondFailReq_miss_latency::total 4942500 # number of StoreCondFailReq miss cycles system.cpu1.dcache.demand_miss_latency::cpu1.data 107635946500 # number of demand (read+write) miss cycles system.cpu1.dcache.demand_miss_latency::total 107635946500 # number of demand (read+write) miss cycles system.cpu1.dcache.overall_miss_latency::cpu1.data 107635946500 # number of overall miss cycles system.cpu1.dcache.overall_miss_latency::total 107635946500 # number of overall miss cycles system.cpu1.dcache.ReadReq_accesses::cpu1.data 82204510 # number of ReadReq accesses(hits+misses) system.cpu1.dcache.ReadReq_accesses::total 82204510 # number of ReadReq accesses(hits+misses) system.cpu1.dcache.WriteReq_accesses::cpu1.data 72210929 # number of WriteReq accesses(hits+misses) system.cpu1.dcache.WriteReq_accesses::total 72210929 # number of WriteReq accesses(hits+misses) system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 882721 # number of SoftPFReq accesses(hits+misses) system.cpu1.dcache.SoftPFReq_accesses::total 882721 # number of SoftPFReq accesses(hits+misses) system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 587750 # number of WriteLineReq accesses(hits+misses) system.cpu1.dcache.WriteLineReq_accesses::total 587750 # number of WriteLineReq accesses(hits+misses) system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1937375 # number of LoadLockedReq accesses(hits+misses) system.cpu1.dcache.LoadLockedReq_accesses::total 1937375 # number of LoadLockedReq accesses(hits+misses) system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1935851 # number of StoreCondReq accesses(hits+misses) system.cpu1.dcache.StoreCondReq_accesses::total 1935851 # number of StoreCondReq accesses(hits+misses) system.cpu1.dcache.demand_accesses::cpu1.data 154415439 # number of demand (read+write) accesses system.cpu1.dcache.demand_accesses::total 154415439 # number of demand (read+write) accesses system.cpu1.dcache.overall_accesses::cpu1.data 155298160 # number of overall (read+write) accesses system.cpu1.dcache.overall_accesses::total 155298160 # number of overall (read+write) accesses system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.040982 # miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_miss_rate::total 0.040982 # miss rate for ReadReq accesses system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.031547 # miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_miss_rate::total 0.031547 # miss rate for WriteReq accesses system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.733727 # miss rate for SoftPFReq accesses system.cpu1.dcache.SoftPFReq_miss_rate::total 0.733727 # miss rate for SoftPFReq accesses system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.767180 # miss rate for WriteLineReq accesses system.cpu1.dcache.WriteLineReq_miss_rate::total 0.767180 # miss rate for WriteLineReq accesses system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.082336 # miss rate for LoadLockedReq accesses system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.082336 # miss rate for LoadLockedReq accesses system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.103919 # miss rate for StoreCondReq accesses system.cpu1.dcache.StoreCondReq_miss_rate::total 0.103919 # miss rate for StoreCondReq accesses system.cpu1.dcache.demand_miss_rate::cpu1.data 0.036570 # miss rate for demand accesses system.cpu1.dcache.demand_miss_rate::total 0.036570 # miss rate for demand accesses system.cpu1.dcache.overall_miss_rate::cpu1.data 0.040533 # miss rate for overall accesses system.cpu1.dcache.overall_miss_rate::total 0.040533 # miss rate for overall accesses system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16561.467603 # average ReadReq miss latency system.cpu1.dcache.ReadReq_avg_miss_latency::total 16561.467603 # average ReadReq miss latency system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 22756.808276 # average WriteReq miss latency system.cpu1.dcache.WriteReq_avg_miss_latency::total 22756.808276 # average WriteReq miss latency system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 47160.133951 # average WriteLineReq miss latency system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 47160.133951 # average WriteLineReq miss latency system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 17117.640237 # average LoadLockedReq miss latency system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 17117.640237 # average LoadLockedReq miss latency system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 27419.329824 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 27419.329824 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19060.750994 # average overall miss latency system.cpu1.dcache.demand_avg_miss_latency::total 19060.750994 # average overall miss latency system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17099.537625 # average overall miss latency system.cpu1.dcache.overall_avg_miss_latency::total 17099.537625 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed system.cpu1.dcache.writebacks::writebacks 5225429 # number of writebacks system.cpu1.dcache.writebacks::total 5225429 # number of writebacks system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 382545 # number of ReadReq MSHR hits system.cpu1.dcache.ReadReq_mshr_hits::total 382545 # number of ReadReq MSHR hits system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 937825 # number of WriteReq MSHR hits system.cpu1.dcache.WriteReq_mshr_hits::total 937825 # number of WriteReq MSHR hits system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 58 # number of WriteLineReq MSHR hits system.cpu1.dcache.WriteLineReq_mshr_hits::total 58 # number of WriteLineReq MSHR hits system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 41578 # number of LoadLockedReq MSHR hits system.cpu1.dcache.LoadLockedReq_mshr_hits::total 41578 # number of LoadLockedReq MSHR hits system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data 34 # number of StoreCondReq MSHR hits system.cpu1.dcache.StoreCondReq_mshr_hits::total 34 # number of StoreCondReq MSHR hits system.cpu1.dcache.demand_mshr_hits::cpu1.data 1320370 # number of demand (read+write) MSHR hits system.cpu1.dcache.demand_mshr_hits::total 1320370 # number of demand (read+write) MSHR hits system.cpu1.dcache.overall_mshr_hits::cpu1.data 1320370 # number of overall MSHR hits system.cpu1.dcache.overall_mshr_hits::total 1320370 # number of overall MSHR hits system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2986376 # number of ReadReq MSHR misses system.cpu1.dcache.ReadReq_mshr_misses::total 2986376 # number of ReadReq MSHR misses system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1340248 # number of WriteReq MSHR misses system.cpu1.dcache.WriteReq_mshr_misses::total 1340248 # number of WriteReq MSHR misses system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 647394 # number of SoftPFReq MSHR misses system.cpu1.dcache.SoftPFReq_mshr_misses::total 647394 # number of SoftPFReq MSHR misses system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 450852 # number of WriteLineReq MSHR misses system.cpu1.dcache.WriteLineReq_mshr_misses::total 450852 # number of WriteLineReq MSHR misses system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 117938 # number of LoadLockedReq MSHR misses system.cpu1.dcache.LoadLockedReq_mshr_misses::total 117938 # number of LoadLockedReq MSHR misses system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 201137 # number of StoreCondReq MSHR misses system.cpu1.dcache.StoreCondReq_mshr_misses::total 201137 # number of StoreCondReq MSHR misses system.cpu1.dcache.demand_mshr_misses::cpu1.data 4326624 # number of demand (read+write) MSHR misses system.cpu1.dcache.demand_mshr_misses::total 4326624 # number of demand (read+write) MSHR misses system.cpu1.dcache.overall_mshr_misses::cpu1.data 4974018 # number of overall MSHR misses system.cpu1.dcache.overall_mshr_misses::total 4974018 # number of overall MSHR misses system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 19129 # number of ReadReq MSHR uncacheable system.cpu1.dcache.ReadReq_mshr_uncacheable::total 19129 # number of ReadReq MSHR uncacheable system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 17467 # number of WriteReq MSHR uncacheable system.cpu1.dcache.WriteReq_mshr_uncacheable::total 17467 # number of WriteReq MSHR uncacheable system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 36596 # number of overall MSHR uncacheable misses system.cpu1.dcache.overall_mshr_uncacheable_misses::total 36596 # number of overall MSHR uncacheable misses system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 44483005500 # number of ReadReq MSHR miss cycles system.cpu1.dcache.ReadReq_mshr_miss_latency::total 44483005500 # number of ReadReq MSHR miss cycles system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 30789351000 # number of WriteReq MSHR miss cycles system.cpu1.dcache.WriteReq_mshr_miss_latency::total 30789351000 # number of WriteReq MSHR miss cycles system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 15729879000 # number of SoftPFReq MSHR miss cycles system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 15729879000 # number of SoftPFReq MSHR miss cycles system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 20808027500 # number of WriteLineReq MSHR miss cycles system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 20808027500 # number of WriteLineReq MSHR miss cycles system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1765421000 # number of LoadLockedReq MSHR miss cycles system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1765421000 # number of LoadLockedReq MSHR miss cycles system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 5312775000 # number of StoreCondReq MSHR miss cycles system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 5312775000 # number of StoreCondReq MSHR miss cycles system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 4745500 # number of StoreCondFailReq MSHR miss cycles system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 4745500 # number of StoreCondFailReq MSHR miss cycles system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 75272356500 # number of demand (read+write) MSHR miss cycles system.cpu1.dcache.demand_mshr_miss_latency::total 75272356500 # number of demand (read+write) MSHR miss cycles system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 91002235500 # number of overall MSHR miss cycles system.cpu1.dcache.overall_mshr_miss_latency::total 91002235500 # number of overall MSHR miss cycles system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3151598000 # number of ReadReq MSHR uncacheable cycles system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 3151598000 # number of ReadReq MSHR uncacheable cycles system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2962839500 # number of WriteReq MSHR uncacheable cycles system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 2962839500 # number of WriteReq MSHR uncacheable cycles system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 6114437500 # number of overall MSHR uncacheable cycles system.cpu1.dcache.overall_mshr_uncacheable_latency::total 6114437500 # number of overall MSHR uncacheable cycles system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036329 # mshr miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036329 # mshr miss rate for ReadReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018560 # mshr miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018560 # mshr miss rate for WriteReq accesses system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.733407 # mshr miss rate for SoftPFReq accesses system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.733407 # mshr miss rate for SoftPFReq accesses system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.767081 # mshr miss rate for WriteLineReq accesses system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.767081 # mshr miss rate for WriteLineReq accesses system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.060875 # mshr miss rate for LoadLockedReq accesses system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.060875 # mshr miss rate for LoadLockedReq accesses system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.103901 # mshr miss rate for StoreCondReq accesses system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.103901 # mshr miss rate for StoreCondReq accesses system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.028019 # mshr miss rate for demand accesses system.cpu1.dcache.demand_mshr_miss_rate::total 0.028019 # mshr miss rate for demand accesses system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.032029 # mshr miss rate for overall accesses system.cpu1.dcache.overall_mshr_miss_rate::total 0.032029 # mshr miss rate for overall accesses system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14895.313082 # average ReadReq mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14895.313082 # average ReadReq mshr miss latency system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 22972.875916 # average WriteReq mshr miss latency system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 22972.875916 # average WriteReq mshr miss latency system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 24297.227036 # average SoftPFReq mshr miss latency system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 24297.227036 # average SoftPFReq mshr miss latency system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 46152.678706 # average WriteLineReq mshr miss latency system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 46152.678706 # average WriteLineReq mshr miss latency system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14969.060015 # average LoadLockedReq mshr miss latency system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14969.060015 # average LoadLockedReq mshr miss latency system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 26413.713041 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 26413.713041 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17397.480461 # average overall mshr miss latency system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17397.480461 # average overall mshr miss latency system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18295.517929 # average overall mshr miss latency system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18295.517929 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 164754.979351 # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 164754.979351 # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 169624.978531 # average WriteReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 169624.978531 # average WriteReq mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 167079.393923 # average overall mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 167079.393923 # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.icache.tags.replacements 9231311 # number of replacements system.cpu1.icache.tags.tagsinuse 506.694166 # Cycle average of tags in use system.cpu1.icache.tags.total_refs 229790487 # Total number of references to valid blocks. system.cpu1.icache.tags.sampled_refs 9231823 # Sample count of references to valid blocks. system.cpu1.icache.tags.avg_refs 24.891128 # Average number of references to valid blocks. system.cpu1.icache.tags.warmup_cycle 8386495264000 # Cycle when the warmup percentage was hit. system.cpu1.icache.tags.occ_blocks::cpu1.inst 506.694166 # Average occupied blocks per requestor system.cpu1.icache.tags.occ_percent::cpu1.inst 0.989637 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_percent::total 0.989637 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::0 100 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::1 336 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::2 76 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu1.icache.tags.tag_accesses 487276445 # Number of tag accesses system.cpu1.icache.tags.data_accesses 487276445 # Number of data accesses system.cpu1.icache.ReadReq_hits::cpu1.inst 229790487 # number of ReadReq hits system.cpu1.icache.ReadReq_hits::total 229790487 # number of ReadReq hits system.cpu1.icache.demand_hits::cpu1.inst 229790487 # number of demand (read+write) hits system.cpu1.icache.demand_hits::total 229790487 # number of demand (read+write) hits system.cpu1.icache.overall_hits::cpu1.inst 229790487 # number of overall hits system.cpu1.icache.overall_hits::total 229790487 # number of overall hits system.cpu1.icache.ReadReq_misses::cpu1.inst 9231824 # number of ReadReq misses system.cpu1.icache.ReadReq_misses::total 9231824 # number of ReadReq misses system.cpu1.icache.demand_misses::cpu1.inst 9231824 # number of demand (read+write) misses system.cpu1.icache.demand_misses::total 9231824 # number of demand (read+write) misses system.cpu1.icache.overall_misses::cpu1.inst 9231824 # number of overall misses system.cpu1.icache.overall_misses::total 9231824 # number of overall misses system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 94524443000 # number of ReadReq miss cycles system.cpu1.icache.ReadReq_miss_latency::total 94524443000 # number of ReadReq miss cycles system.cpu1.icache.demand_miss_latency::cpu1.inst 94524443000 # number of demand (read+write) miss cycles system.cpu1.icache.demand_miss_latency::total 94524443000 # number of demand (read+write) miss cycles system.cpu1.icache.overall_miss_latency::cpu1.inst 94524443000 # number of overall miss cycles system.cpu1.icache.overall_miss_latency::total 94524443000 # number of overall miss cycles system.cpu1.icache.ReadReq_accesses::cpu1.inst 239022311 # number of ReadReq accesses(hits+misses) system.cpu1.icache.ReadReq_accesses::total 239022311 # number of ReadReq accesses(hits+misses) system.cpu1.icache.demand_accesses::cpu1.inst 239022311 # number of demand (read+write) accesses system.cpu1.icache.demand_accesses::total 239022311 # number of demand (read+write) accesses system.cpu1.icache.overall_accesses::cpu1.inst 239022311 # number of overall (read+write) accesses system.cpu1.icache.overall_accesses::total 239022311 # number of overall (read+write) accesses system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.038623 # miss rate for ReadReq accesses system.cpu1.icache.ReadReq_miss_rate::total 0.038623 # miss rate for ReadReq accesses system.cpu1.icache.demand_miss_rate::cpu1.inst 0.038623 # miss rate for demand accesses system.cpu1.icache.demand_miss_rate::total 0.038623 # miss rate for demand accesses system.cpu1.icache.overall_miss_rate::cpu1.inst 0.038623 # miss rate for overall accesses system.cpu1.icache.overall_miss_rate::total 0.038623 # miss rate for overall accesses system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10238.978018 # average ReadReq miss latency system.cpu1.icache.ReadReq_avg_miss_latency::total 10238.978018 # average ReadReq miss latency system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10238.978018 # average overall miss latency system.cpu1.icache.demand_avg_miss_latency::total 10238.978018 # average overall miss latency system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10238.978018 # average overall miss latency system.cpu1.icache.overall_avg_miss_latency::total 10238.978018 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed system.cpu1.icache.writebacks::writebacks 9231311 # number of writebacks system.cpu1.icache.writebacks::total 9231311 # number of writebacks system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 9231824 # number of ReadReq MSHR misses system.cpu1.icache.ReadReq_mshr_misses::total 9231824 # number of ReadReq MSHR misses system.cpu1.icache.demand_mshr_misses::cpu1.inst 9231824 # number of demand (read+write) MSHR misses system.cpu1.icache.demand_mshr_misses::total 9231824 # number of demand (read+write) MSHR misses system.cpu1.icache.overall_mshr_misses::cpu1.inst 9231824 # number of overall MSHR misses system.cpu1.icache.overall_mshr_misses::total 9231824 # number of overall MSHR misses system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 92 # number of ReadReq MSHR uncacheable system.cpu1.icache.ReadReq_mshr_uncacheable::total 92 # number of ReadReq MSHR uncacheable system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 92 # number of overall MSHR uncacheable misses system.cpu1.icache.overall_mshr_uncacheable_misses::total 92 # number of overall MSHR uncacheable misses system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 89908531500 # number of ReadReq MSHR miss cycles system.cpu1.icache.ReadReq_mshr_miss_latency::total 89908531500 # number of ReadReq MSHR miss cycles system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 89908531500 # number of demand (read+write) MSHR miss cycles system.cpu1.icache.demand_mshr_miss_latency::total 89908531500 # number of demand (read+write) MSHR miss cycles system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 89908531500 # number of overall MSHR miss cycles system.cpu1.icache.overall_mshr_miss_latency::total 89908531500 # number of overall MSHR miss cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 12950500 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 12950500 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 12950500 # number of overall MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::total 12950500 # number of overall MSHR uncacheable cycles system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.038623 # mshr miss rate for ReadReq accesses system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.038623 # mshr miss rate for ReadReq accesses system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.038623 # mshr miss rate for demand accesses system.cpu1.icache.demand_mshr_miss_rate::total 0.038623 # mshr miss rate for demand accesses system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.038623 # mshr miss rate for overall accesses system.cpu1.icache.overall_mshr_miss_rate::total 0.038623 # mshr miss rate for overall accesses system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 9738.978072 # average ReadReq mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 9738.978072 # average ReadReq mshr miss latency system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 9738.978072 # average overall mshr miss latency system.cpu1.icache.demand_avg_mshr_miss_latency::total 9738.978072 # average overall mshr miss latency system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 9738.978072 # average overall mshr miss latency system.cpu1.icache.overall_avg_mshr_miss_latency::total 9738.978072 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 140766.304348 # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 140766.304348 # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 140766.304348 # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 140766.304348 # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.l2cache.prefetcher.num_hwpf_issued 7101301 # number of hwpf issued system.cpu1.l2cache.prefetcher.pfIdentified 7101636 # number of prefetch candidates identified system.cpu1.l2cache.prefetcher.pfBufferHit 296 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size system.cpu1.l2cache.prefetcher.pfSpanPage 867300 # number of prefetches not generated due to page crossing system.cpu1.l2cache.tags.replacements 2326720 # number of replacements system.cpu1.l2cache.tags.tagsinuse 13467.956369 # Cycle average of tags in use system.cpu1.l2cache.tags.total_refs 23154784 # Total number of references to valid blocks. system.cpu1.l2cache.tags.sampled_refs 2342909 # Sample count of references to valid blocks. system.cpu1.l2cache.tags.avg_refs 9.882921 # Average number of references to valid blocks. system.cpu1.l2cache.tags.warmup_cycle 9860254327500 # Cycle when the warmup percentage was hit. system.cpu1.l2cache.tags.occ_blocks::writebacks 12598.584174 # Average occupied blocks per requestor system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 60.491814 # Average occupied blocks per requestor system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 58.201363 # Average occupied blocks per requestor system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 750.679017 # Average occupied blocks per requestor system.cpu1.l2cache.tags.occ_percent::writebacks 0.768957 # Average percentage of cache occupancy system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.003692 # Average percentage of cache occupancy system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.003552 # Average percentage of cache occupancy system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.045818 # Average percentage of cache occupancy system.cpu1.l2cache.tags.occ_percent::total 0.822019 # Average percentage of cache occupancy system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1395 # Occupied blocks per task id system.cpu1.l2cache.tags.occ_task_id_blocks::1023 52 # Occupied blocks per task id system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14742 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 10 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 404 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 859 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 122 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 2 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 31 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 3 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 86 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1149 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5193 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 7319 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 995 # Occupied blocks per task id system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.085144 # Percentage of cache occupancy per task id system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.003174 # Percentage of cache occupancy per task id system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.899780 # Percentage of cache occupancy per task id system.cpu1.l2cache.tags.tag_accesses 488472501 # Number of tag accesses system.cpu1.l2cache.tags.data_accesses 488472501 # Number of data accesses system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 576439 # number of ReadReq hits system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 168221 # number of ReadReq hits system.cpu1.l2cache.ReadReq_hits::total 744660 # number of ReadReq hits system.cpu1.l2cache.WritebackDirty_hits::writebacks 3264846 # number of WritebackDirty hits system.cpu1.l2cache.WritebackDirty_hits::total 3264846 # number of WritebackDirty hits system.cpu1.l2cache.WritebackClean_hits::writebacks 11189694 # number of WritebackClean hits system.cpu1.l2cache.WritebackClean_hits::total 11189694 # number of WritebackClean hits system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 575 # number of UpgradeReq hits system.cpu1.l2cache.UpgradeReq_hits::total 575 # number of UpgradeReq hits system.cpu1.l2cache.ReadExReq_hits::cpu1.data 867363 # number of ReadExReq hits system.cpu1.l2cache.ReadExReq_hits::total 867363 # number of ReadExReq hits system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 8545306 # number of ReadCleanReq hits system.cpu1.l2cache.ReadCleanReq_hits::total 8545306 # number of ReadCleanReq hits system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 2781382 # number of ReadSharedReq hits system.cpu1.l2cache.ReadSharedReq_hits::total 2781382 # number of ReadSharedReq hits system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 181539 # number of InvalidateReq hits system.cpu1.l2cache.InvalidateReq_hits::total 181539 # number of InvalidateReq hits system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 576439 # number of demand (read+write) hits system.cpu1.l2cache.demand_hits::cpu1.itb.walker 168221 # number of demand (read+write) hits system.cpu1.l2cache.demand_hits::cpu1.inst 8545306 # number of demand (read+write) hits system.cpu1.l2cache.demand_hits::cpu1.data 3648745 # number of demand (read+write) hits system.cpu1.l2cache.demand_hits::total 12938711 # number of demand (read+write) hits system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 576439 # number of overall hits system.cpu1.l2cache.overall_hits::cpu1.itb.walker 168221 # number of overall hits system.cpu1.l2cache.overall_hits::cpu1.inst 8545306 # number of overall hits system.cpu1.l2cache.overall_hits::cpu1.data 3648745 # number of overall hits system.cpu1.l2cache.overall_hits::total 12938711 # number of overall hits system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 12346 # number of ReadReq misses system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 8532 # number of ReadReq misses system.cpu1.l2cache.ReadReq_misses::total 20878 # number of ReadReq misses system.cpu1.l2cache.WritebackDirty_misses::writebacks 1 # number of WritebackDirty misses system.cpu1.l2cache.WritebackDirty_misses::total 1 # number of WritebackDirty misses system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 223343 # number of UpgradeReq misses system.cpu1.l2cache.UpgradeReq_misses::total 223343 # number of UpgradeReq misses system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 201132 # number of SCUpgradeReq misses system.cpu1.l2cache.SCUpgradeReq_misses::total 201132 # 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number of WritebackClean accesses(hits+misses) system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 223918 # number of UpgradeReq accesses(hits+misses) system.cpu1.l2cache.UpgradeReq_accesses::total 223918 # number of UpgradeReq accesses(hits+misses) system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 201132 # number of SCUpgradeReq accesses(hits+misses) system.cpu1.l2cache.SCUpgradeReq_accesses::total 201132 # number of SCUpgradeReq accesses(hits+misses) system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 5 # number of SCUpgradeFailReq accesses(hits+misses) system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 5 # number of SCUpgradeFailReq accesses(hits+misses) system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1119002 # number of ReadExReq accesses(hits+misses) system.cpu1.l2cache.ReadExReq_accesses::total 1119002 # number of ReadExReq accesses(hits+misses) system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 9231824 # number of ReadCleanReq accesses(hits+misses) system.cpu1.l2cache.ReadCleanReq_accesses::total 9231824 # number of ReadCleanReq accesses(hits+misses) system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 3751395 # number of ReadSharedReq accesses(hits+misses) system.cpu1.l2cache.ReadSharedReq_accesses::total 3751395 # number of ReadSharedReq accesses(hits+misses) system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 448771 # number of InvalidateReq accesses(hits+misses) system.cpu1.l2cache.InvalidateReq_accesses::total 448771 # number of InvalidateReq accesses(hits+misses) system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 588785 # number of demand (read+write) accesses system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 176753 # number of demand (read+write) accesses system.cpu1.l2cache.demand_accesses::cpu1.inst 9231824 # number of demand (read+write) accesses system.cpu1.l2cache.demand_accesses::cpu1.data 4870397 # number of demand (read+write) accesses system.cpu1.l2cache.demand_accesses::total 14867759 # number of demand (read+write) accesses system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 588785 # 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number of overall MSHR misses system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 92 # number of ReadReq MSHR uncacheable system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 19129 # number of ReadReq MSHR uncacheable system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 19221 # number of ReadReq MSHR uncacheable system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 17467 # number of WriteReq MSHR uncacheable system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 17467 # number of WriteReq MSHR uncacheable system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 92 # number of overall MSHR uncacheable misses system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 36596 # number of overall MSHR uncacheable misses system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 36688 # number of overall MSHR uncacheable misses system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 525331500 # number of ReadReq MSHR miss cycles system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 408923500 # number of ReadReq MSHR miss cycles system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 934255000 # number of ReadReq MSHR miss cycles system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 45309762891 # number of HardPFReq MSHR miss cycles system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 45309762891 # number of HardPFReq MSHR miss cycles system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 7082960998 # number of UpgradeReq MSHR miss cycles system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 7082960998 # number of UpgradeReq MSHR miss cycles system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 3799999000 # number of SCUpgradeReq MSHR miss cycles system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 3799999000 # number of SCUpgradeReq MSHR miss cycles system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 4287499 # number of SCUpgradeFailReq MSHR miss cycles system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 4287499 # number of SCUpgradeFailReq MSHR miss cycles system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 11990250000 # number of ReadExReq MSHR miss cycles system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 11990250000 # number of ReadExReq MSHR miss cycles system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 20322650500 # number of ReadCleanReq MSHR miss cycles system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 20322650500 # number of ReadCleanReq MSHR miss cycles system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 32101541990 # number of ReadSharedReq MSHR miss cycles system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 32101541990 # number of ReadSharedReq MSHR miss cycles system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 17199481500 # number of InvalidateReq MSHR miss cycles system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 17199481500 # number of InvalidateReq MSHR miss cycles system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 525331500 # number of demand (read+write) MSHR miss cycles system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 408923500 # number of demand (read+write) MSHR miss cycles system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 20322650500 # number of demand (read+write) MSHR miss cycles system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 44091791990 # number of demand (read+write) MSHR miss cycles system.cpu1.l2cache.demand_mshr_miss_latency::total 65348697490 # number of demand (read+write) MSHR miss cycles system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 525331500 # number of overall MSHR miss cycles system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 408923500 # number of overall MSHR miss cycles system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 20322650500 # number of overall MSHR miss cycles system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 44091791990 # number of overall MSHR miss cycles system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 45309762891 # number of overall MSHR miss cycles system.cpu1.l2cache.overall_mshr_miss_latency::total 110658460381 # number of overall MSHR miss cycles system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 12214500 # number of ReadReq MSHR uncacheable cycles system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 2998478000 # number of ReadReq MSHR uncacheable cycles system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 3010692500 # number of ReadReq MSHR uncacheable cycles system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 2831799500 # number of WriteReq MSHR uncacheable cycles system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 2831799500 # number of WriteReq MSHR uncacheable cycles system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 12214500 # number of overall MSHR uncacheable cycles system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 5830277500 # number of overall MSHR uncacheable cycles system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 5842492000 # number of overall MSHR uncacheable cycles system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.020969 # mshr miss rate for ReadReq accesses system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.048259 # mshr miss rate for ReadReq accesses system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.027270 # mshr miss rate for ReadReq accesses system.cpu1.l2cache.WritebackDirty_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for WritebackDirty accesses system.cpu1.l2cache.WritebackDirty_mshr_miss_rate::total 0.000000 # mshr miss rate for WritebackDirty accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.997432 # mshr miss rate for UpgradeReq accesses system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.997432 # mshr miss rate for UpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.217571 # mshr miss rate for ReadExReq accesses system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.217571 # mshr miss rate for ReadExReq accesses system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.074364 # mshr miss rate for ReadCleanReq accesses system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.074364 # mshr miss rate for ReadCleanReq accesses system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.258364 # mshr miss rate for ReadSharedReq accesses system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.258364 # mshr miss rate for ReadSharedReq accesses system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.595469 # mshr miss rate for InvalidateReq accesses system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.595469 # mshr miss rate for InvalidateReq accesses system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.020969 # mshr miss rate for demand accesses system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.048259 # mshr miss rate for demand accesses system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.074364 # mshr miss rate for demand accesses system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.248992 # mshr miss rate for demand accesses system.cpu1.l2cache.demand_mshr_miss_rate::total 0.129144 # mshr miss rate for demand accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.020969 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.048259 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.074364 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.248992 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::total 0.180069 # mshr miss rate for overall accesses system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 42550.745181 # average ReadReq mshr miss latency system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 47939.449004 # average ReadReq mshr miss latency system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 44752.586702 # average ReadReq mshr miss latency system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 59843.308887 # average HardPFReq mshr miss latency system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 59843.308887 # average HardPFReq mshr miss latency system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 31713.378069 # average UpgradeReq mshr miss latency system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31713.378069 # average UpgradeReq mshr miss latency system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18893.060279 # average SCUpgradeReq mshr miss latency system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18893.060279 # average SCUpgradeReq mshr miss latency system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 857499.800000 # average SCUpgradeFailReq mshr miss latency system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 857499.800000 # average SCUpgradeFailReq mshr miss latency system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 49248.958770 # average ReadExReq mshr miss latency system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 49248.958770 # average ReadExReq mshr miss latency system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 29602.674527 # average ReadCleanReq mshr miss latency system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 29602.674527 # average ReadCleanReq mshr miss latency system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 33120.767364 # average ReadSharedReq mshr miss latency system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 33120.767364 # average ReadSharedReq mshr miss latency system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 64362.331558 # average InvalidateReq mshr miss latency system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 64362.331558 # average InvalidateReq mshr miss latency system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 42550.745181 # average overall mshr miss latency system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 47939.449004 # average overall mshr miss latency system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 29602.674527 # average overall mshr miss latency system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 36358.697069 # average overall mshr miss latency system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 34034.379570 # average overall mshr miss latency system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 42550.745181 # average overall mshr miss latency system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 47939.449004 # average overall mshr miss latency system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 29602.674527 # average overall mshr miss latency system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 36358.697069 # average overall mshr miss latency system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 59843.308887 # average overall mshr miss latency system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 41333.361365 # average overall mshr miss latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 132766.304348 # average ReadReq mshr uncacheable latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 156750.379006 # average ReadReq mshr uncacheable latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 156635.580875 # average ReadReq mshr uncacheable latency system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 162122.831625 # average WriteReq mshr uncacheable latency system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 162122.831625 # average WriteReq mshr uncacheable latency system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 132766.304348 # average overall mshr uncacheable latency system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 159314.610886 # average overall mshr uncacheable latency system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 159248.037505 # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.toL2Bus.snoop_filter.tot_requests 29757775 # Total number of requests made to the snoop filter. system.cpu1.toL2Bus.snoop_filter.hit_single_requests 15206900 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 2197 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu1.toL2Bus.snoop_filter.tot_snoops 2096240 # Total number of snoops made to the snoop filter. system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 2095918 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 322 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu1.toL2Bus.trans_dist::ReadReq 863744 # Transaction distribution system.cpu1.toL2Bus.trans_dist::ReadResp 13939008 # Transaction distribution system.cpu1.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution system.cpu1.toL2Bus.trans_dist::WriteReq 17467 # Transaction distribution system.cpu1.toL2Bus.trans_dist::WriteResp 17467 # Transaction distribution system.cpu1.toL2Bus.trans_dist::WritebackDirty 4436321 # Transaction distribution system.cpu1.toL2Bus.trans_dist::WritebackClean 11191891 # Transaction distribution system.cpu1.toL2Bus.trans_dist::CleanEvict 2888082 # Transaction distribution system.cpu1.toL2Bus.trans_dist::HardPFReq 986942 # Transaction distribution system.cpu1.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution system.cpu1.toL2Bus.trans_dist::UpgradeReq 436269 # Transaction distribution system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 365311 # Transaction distribution system.cpu1.toL2Bus.trans_dist::UpgradeResp 490098 # Transaction distribution system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 60 # Transaction distribution system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 116 # Transaction distribution system.cpu1.toL2Bus.trans_dist::ReadExReq 1199193 # Transaction distribution system.cpu1.toL2Bus.trans_dist::ReadExResp 1126648 # Transaction distribution system.cpu1.toL2Bus.trans_dist::ReadCleanReq 9231824 # Transaction distribution system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4839539 # Transaction distribution system.cpu1.toL2Bus.trans_dist::InvalidateReq 455831 # Transaction distribution system.cpu1.toL2Bus.trans_dist::InvalidateResp 448771 # Transaction distribution system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 27695142 # Packet count per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16951918 # Packet count per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 371352 # Packet count per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1238709 # Packet count per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_count::total 46257121 # Packet count per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1181646464 # Cumulative packet size per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 652642726 # Cumulative packet size per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1414024 # Cumulative packet size per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4710280 # Cumulative packet size per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_size::total 1840413494 # Cumulative packet size per connected master and slave (bytes) system.cpu1.toL2Bus.snoops 6842316 # Total snoops (count) system.cpu1.toL2Bus.snoop_fanout::samples 22455736 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::mean 0.107935 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::stdev 0.310344 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::0 20032307 89.21% 89.21% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::1 2423107 10.79% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::2 322 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::total 22455736 # Request fanout histogram system.cpu1.toL2Bus.reqLayer0.occupancy 29622476486 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.cpu1.toL2Bus.snoopLayer0.occupancy 182393833 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) system.cpu1.toL2Bus.respLayer0.occupancy 13851399924 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu1.toL2Bus.respLayer1.occupancy 7774596662 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu1.toL2Bus.respLayer2.occupancy 194664868 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) system.cpu1.toL2Bus.respLayer3.occupancy 650073200 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.trans_dist::ReadReq 40417 # Transaction distribution system.iobus.trans_dist::ReadResp 40417 # Transaction distribution system.iobus.trans_dist::WriteReq 136988 # Transaction distribution system.iobus.trans_dist::WriteResp 136988 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47856 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29808 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 122998 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231732 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::total 231732 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::total 354810 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47876 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17703 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 156013 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7355280 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::total 7355280 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 7513379 # Cumulative packet size per connected master and slave (bytes) system.iobus.reqLayer0.occupancy 47192501 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 12000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 324000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer3.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer10.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer13.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer14.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer15.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer16.occupancy 15500 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer23.occupancy 26190001 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer24.occupancy 36429000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer25.occupancy 568769538 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 92997000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer3.occupancy 148172000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 115847 # number of replacements system.iocache.tags.tagsinuse 11.301670 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 115863 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. system.iocache.tags.warmup_cycle 9145489939000 # Cycle when the warmup percentage was hit. system.iocache.tags.occ_blocks::realview.ethernet 3.832621 # Average occupied blocks per requestor system.iocache.tags.occ_blocks::realview.ide 7.469049 # Average occupied blocks per requestor system.iocache.tags.occ_percent::realview.ethernet 0.239539 # Average percentage of cache occupancy system.iocache.tags.occ_percent::realview.ide 0.466816 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.706354 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 1043151 # Number of tag accesses system.iocache.tags.data_accesses 1043151 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses system.iocache.ReadReq_misses::realview.ide 8882 # number of ReadReq misses system.iocache.ReadReq_misses::total 8919 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteLineReq_misses::realview.ide 106984 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 106984 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses system.iocache.demand_misses::realview.ide 8882 # number of demand (read+write) misses system.iocache.demand_misses::total 8922 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses system.iocache.overall_misses::realview.ide 8882 # number of overall misses system.iocache.overall_misses::total 8922 # number of overall misses system.iocache.ReadReq_miss_latency::realview.ethernet 5198000 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::realview.ide 1701700997 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 1706898997 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles system.iocache.WriteLineReq_miss_latency::realview.ide 13567134541 # number of WriteLineReq miss cycles system.iocache.WriteLineReq_miss_latency::total 13567134541 # number of WriteLineReq miss cycles system.iocache.demand_miss_latency::realview.ethernet 5567000 # number of demand (read+write) miss cycles system.iocache.demand_miss_latency::realview.ide 1701700997 # number of demand (read+write) miss cycles system.iocache.demand_miss_latency::total 1707267997 # number of demand (read+write) miss cycles system.iocache.overall_miss_latency::realview.ethernet 5567000 # number of overall miss cycles system.iocache.overall_miss_latency::realview.ide 1701700997 # number of overall miss cycles system.iocache.overall_miss_latency::total 1707267997 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::realview.ide 8882 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 8919 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 106984 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106984 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses system.iocache.demand_accesses::realview.ide 8882 # number of demand (read+write) accesses system.iocache.demand_accesses::total 8922 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses system.iocache.overall_accesses::realview.ide 8882 # number of overall (read+write) accesses system.iocache.overall_accesses::total 8922 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140486.486486 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::realview.ide 191589.844292 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total 191377.844714 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency system.iocache.WriteLineReq_avg_miss_latency::realview.ide 126814.612849 # average WriteLineReq miss latency system.iocache.WriteLineReq_avg_miss_latency::total 126814.612849 # average WriteLineReq miss latency system.iocache.demand_avg_miss_latency::realview.ethernet 139175 # average overall miss latency system.iocache.demand_avg_miss_latency::realview.ide 191589.844292 # average overall miss latency system.iocache.demand_avg_miss_latency::total 191354.852836 # average overall miss latency system.iocache.overall_avg_miss_latency::realview.ethernet 139175 # average overall miss latency system.iocache.overall_avg_miss_latency::realview.ide 191589.844292 # average overall miss latency system.iocache.overall_avg_miss_latency::total 191354.852836 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 34809 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 3501 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked system.iocache.avg_blocked_cycles::no_mshrs 9.942588 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 106950 # number of writebacks system.iocache.writebacks::total 106950 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses system.iocache.ReadReq_mshr_misses::realview.ide 8882 # number of ReadReq MSHR misses system.iocache.ReadReq_mshr_misses::total 8919 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 106984 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 106984 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses system.iocache.demand_mshr_misses::realview.ide 8882 # number of demand (read+write) MSHR misses system.iocache.demand_mshr_misses::total 8922 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses system.iocache.overall_mshr_misses::realview.ide 8882 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 8922 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3348000 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::realview.ide 1257600997 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 1260948997 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8211460570 # number of WriteLineReq MSHR miss cycles system.iocache.WriteLineReq_mshr_miss_latency::total 8211460570 # number of WriteLineReq MSHR miss cycles system.iocache.demand_mshr_miss_latency::realview.ethernet 3567000 # number of demand (read+write) MSHR miss cycles system.iocache.demand_mshr_miss_latency::realview.ide 1257600997 # number of demand (read+write) MSHR miss cycles system.iocache.demand_mshr_miss_latency::total 1261167997 # number of demand (read+write) MSHR miss cycles system.iocache.overall_mshr_miss_latency::realview.ethernet 3567000 # number of overall MSHR miss cycles system.iocache.overall_mshr_miss_latency::realview.ide 1257600997 # number of overall MSHR miss cycles system.iocache.overall_mshr_miss_latency::total 1261167997 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90486.486486 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 141589.844292 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::total 141377.844714 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 76754.099398 # average WriteLineReq mshr miss latency system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76754.099398 # average WriteLineReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89175 # average overall mshr miss latency system.iocache.demand_avg_mshr_miss_latency::realview.ide 141589.844292 # average overall mshr miss latency system.iocache.demand_avg_mshr_miss_latency::total 141354.852836 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89175 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::realview.ide 141589.844292 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::total 141354.852836 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.l2c.tags.replacements 1465460 # number of replacements system.l2c.tags.tagsinuse 62985.288046 # Cycle average of tags in use system.l2c.tags.total_refs 6746847 # Total number of references to valid blocks. system.l2c.tags.sampled_refs 1525111 # Sample count of references to valid blocks. system.l2c.tags.avg_refs 4.423840 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.l2c.tags.occ_blocks::writebacks 21606.771340 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.dtb.walker 163.937701 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.itb.walker 223.248695 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.inst 5669.657556 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.data 6460.370404 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 9729.240754 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1.dtb.walker 163.294328 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1.itb.walker 204.500397 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1.inst 3331.837675 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1.data 6323.626930 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 9108.802265 # Average occupied blocks per requestor system.l2c.tags.occ_percent::writebacks 0.329693 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002501 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.003407 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.inst 0.086512 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.data 0.098577 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.148456 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002492 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.itb.walker 0.003120 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.inst 0.050840 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.data 0.096491 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.138989 # Average percentage of cache occupancy system.l2c.tags.occ_percent::total 0.961079 # Average percentage of cache occupancy system.l2c.tags.occ_task_id_blocks::1022 9038 # Occupied blocks per task id system.l2c.tags.occ_task_id_blocks::1023 217 # Occupied blocks per task id system.l2c.tags.occ_task_id_blocks::1024 50396 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1022::1 130 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1022::2 134 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1022::3 1705 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1022::4 7069 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1023::2 6 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1023::3 23 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1023::4 187 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::1 313 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::2 2486 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::3 12173 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::4 35392 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1022 0.137909 # Percentage of cache occupancy per task id system.l2c.tags.occ_task_id_percent::1023 0.003311 # Percentage of cache occupancy per task id system.l2c.tags.occ_task_id_percent::1024 0.768982 # Percentage of cache occupancy per task id system.l2c.tags.tag_accesses 82649960 # Number of tag accesses system.l2c.tags.data_accesses 82649960 # Number of data accesses system.l2c.WritebackDirty_hits::writebacks 2868119 # number of WritebackDirty hits system.l2c.WritebackDirty_hits::total 2868119 # number of WritebackDirty hits system.l2c.UpgradeReq_hits::cpu0.data 181384 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu1.data 131978 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 313362 # number of UpgradeReq hits system.l2c.SCUpgradeReq_hits::cpu0.data 45809 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::cpu1.data 40059 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::total 85868 # number of SCUpgradeReq hits system.l2c.ReadExReq_hits::cpu0.data 200580 # number of ReadExReq hits system.l2c.ReadExReq_hits::cpu1.data 165707 # number of ReadExReq hits system.l2c.ReadExReq_hits::total 366287 # number of ReadExReq hits system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 7480 # number of ReadSharedReq hits system.l2c.ReadSharedReq_hits::cpu0.itb.walker 5183 # number of ReadSharedReq hits system.l2c.ReadSharedReq_hits::cpu0.inst 699361 # number of ReadSharedReq hits system.l2c.ReadSharedReq_hits::cpu0.data 660994 # number of ReadSharedReq hits system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 342500 # number of ReadSharedReq hits system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 6176 # number of ReadSharedReq hits system.l2c.ReadSharedReq_hits::cpu1.itb.walker 4038 # number of ReadSharedReq hits system.l2c.ReadSharedReq_hits::cpu1.inst 639412 # number of ReadSharedReq hits system.l2c.ReadSharedReq_hits::cpu1.data 580820 # number of ReadSharedReq hits system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 295958 # number of ReadSharedReq hits system.l2c.ReadSharedReq_hits::total 3241922 # number of ReadSharedReq hits system.l2c.demand_hits::cpu0.dtb.walker 7480 # number of demand (read+write) hits system.l2c.demand_hits::cpu0.itb.walker 5183 # number of demand (read+write) hits system.l2c.demand_hits::cpu0.inst 699361 # number of demand (read+write) hits system.l2c.demand_hits::cpu0.data 861574 # number of demand (read+write) hits system.l2c.demand_hits::cpu0.l2cache.prefetcher 342500 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.dtb.walker 6176 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.itb.walker 4038 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.inst 639412 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.data 746527 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.l2cache.prefetcher 295958 # number of demand (read+write) hits system.l2c.demand_hits::total 3608209 # number of demand (read+write) hits system.l2c.overall_hits::cpu0.dtb.walker 7480 # number of overall hits system.l2c.overall_hits::cpu0.itb.walker 5183 # number of overall hits system.l2c.overall_hits::cpu0.inst 699361 # number of overall hits system.l2c.overall_hits::cpu0.data 861574 # number of overall hits system.l2c.overall_hits::cpu0.l2cache.prefetcher 342500 # number of overall hits system.l2c.overall_hits::cpu1.dtb.walker 6176 # number of overall hits system.l2c.overall_hits::cpu1.itb.walker 4038 # number of overall hits system.l2c.overall_hits::cpu1.inst 639412 # number of overall hits system.l2c.overall_hits::cpu1.data 746527 # number of overall hits system.l2c.overall_hits::cpu1.l2cache.prefetcher 295958 # number of overall hits system.l2c.overall_hits::total 3608209 # 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average ReadSharedReq mshr miss latency system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 124440.857896 # average ReadSharedReq mshr miss latency system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 129429.419995 # average ReadSharedReq mshr miss latency system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 157062.022343 # average ReadSharedReq mshr miss latency system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 130793.143035 # average ReadSharedReq mshr miss latency system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 130652.621124 # average ReadSharedReq mshr miss latency system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 124595.578948 # average ReadSharedReq mshr miss latency system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 130411.611492 # average ReadSharedReq mshr miss latency system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 157907.439107 # average ReadSharedReq mshr miss latency system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 144136.486641 # average ReadSharedReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 130465.013896 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 130935.623936 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 124440.857896 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.data 129582.587544 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 157062.022343 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 130793.143035 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 130652.621124 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 124595.578948 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.data 127943.621161 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 157907.439107 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::total 137541.973961 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 130465.013896 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 130935.623936 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 124440.857896 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.data 129582.587544 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 157062.022343 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 130793.143035 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 130652.621124 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 124595.578948 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.data 127943.621161 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 157907.439107 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::total 137541.973961 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 112746.678392 # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 168601.820174 # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 111728.260870 # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 138760.548387 # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 130189.676437 # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 164179.590555 # average WriteReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 145115.792122 # average WriteReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 155533.936466 # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 112746.678392 # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 166307.988812 # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 111728.260870 # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 141794.024977 # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total 137723.145408 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 91058 # Transaction distribution system.membus.trans_dist::ReadResp 962815 # Transaction distribution system.membus.trans_dist::WriteReq 38515 # Transaction distribution system.membus.trans_dist::WriteResp 38515 # Transaction distribution system.membus.trans_dist::WritebackDirty 1239858 # Transaction distribution system.membus.trans_dist::CleanEvict 269903 # Transaction distribution system.membus.trans_dist::UpgradeReq 432314 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 322959 # Transaction distribution system.membus.trans_dist::UpgradeResp 23 # Transaction distribution system.membus.trans_dist::SCUpgradeFailReq 3 # Transaction distribution system.membus.trans_dist::ReadExReq 660243 # Transaction distribution system.membus.trans_dist::ReadExResp 640684 # Transaction distribution system.membus.trans_dist::ReadSharedReq 871757 # Transaction distribution system.membus.trans_dist::InvalidateReq 106984 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122998 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 52 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 26126 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5285035 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::total 5434211 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 238560 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 238560 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 5672771 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 156013 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1324 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 52252 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 172058368 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::total 172267957 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7280448 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 7280448 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 179548405 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 621430 # Total snoops (count) system.membus.snoop_fanout::samples 4033661 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::1 4033661 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram system.membus.snoop_fanout::total 4033661 # Request fanout histogram system.membus.reqLayer0.occupancy 110232498 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 33984 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) system.membus.reqLayer2.occupancy 21930998 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer5.occupancy 8790771874 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) system.membus.respLayer2.occupancy 8289711005 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.membus.respLayer3.occupancy 45511990 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA system.realview.ethernet.totBandwidth 163 # Total Bandwidth (bits/s) system.realview.ethernet.totPackets 3 # Total Packets system.realview.ethernet.totBytes 966 # Total Bytes system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) system.realview.ethernet.txBandwidth 163 # Transmit Bandwidth (bits/s) system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks system.toL2Bus.snoop_filter.tot_requests 12834320 # Total number of requests made to the snoop filter. system.toL2Bus.snoop_filter.hit_single_requests 6946519 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_requests 2149909 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.toL2Bus.snoop_filter.tot_snoops 154845 # Total number of snoops made to the snoop filter. system.toL2Bus.snoop_filter.hit_single_snoops 139190 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 15655 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.toL2Bus.trans_dist::ReadReq 91060 # Transaction distribution system.toL2Bus.trans_dist::ReadResp 4987176 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 38515 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 38515 # Transaction distribution system.toL2Bus.trans_dist::WritebackDirty 4108038 # Transaction distribution system.toL2Bus.trans_dist::CleanEvict 3110241 # Transaction distribution system.toL2Bus.trans_dist::UpgradeReq 736356 # Transaction distribution system.toL2Bus.trans_dist::SCUpgradeReq 408827 # Transaction distribution system.toL2Bus.trans_dist::UpgradeResp 1145183 # Transaction distribution system.toL2Bus.trans_dist::SCUpgradeFailReq 116 # Transaction distribution system.toL2Bus.trans_dist::UpgradeFailResp 116 # Transaction distribution system.toL2Bus.trans_dist::ReadExReq 1157626 # Transaction distribution system.toL2Bus.trans_dist::ReadExResp 1157626 # Transaction distribution system.toL2Bus.trans_dist::ReadSharedReq 4903350 # Transaction distribution system.toL2Bus.trans_dist::InvalidateReq 106984 # Transaction distribution system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 10442900 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8319786 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count::total 18762686 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 296101599 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 218919254 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size::total 515020853 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.snoops 3228731 # Total snoops (count) system.toL2Bus.snoop_fanout::samples 9024232 # Request fanout histogram system.toL2Bus.snoop_fanout::mean 0.357725 # Request fanout histogram system.toL2Bus.snoop_fanout::stdev 0.482936 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 5811691 64.40% 64.40% # Request fanout histogram system.toL2Bus.snoop_fanout::1 3196886 35.43% 99.83% # Request fanout histogram system.toL2Bus.snoop_fanout::2 15655 0.17% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram system.toL2Bus.snoop_fanout::total 9024232 # Request fanout histogram system.toL2Bus.reqLayer0.occupancy 9776043593 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) system.toL2Bus.snoopLayer0.occupancy 2607881 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) system.toL2Bus.respLayer0.occupancy 5412935477 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.toL2Bus.respLayer1.occupancy 4393187885 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ----------