stats.txt revision 11336
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 47.461935 # Number of seconds simulated 4sim_ticks 47461934895000 # Number of ticks simulated 5final_tick 47461934895000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 231788 # Simulator instruction rate (inst/s) 8host_op_rate 272612 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 12136870284 # Simulator tick rate (ticks/s) 10host_mem_usage 762440 # Number of bytes of host memory used 11host_seconds 3910.56 # Real time elapsed on the host 12sim_insts 906421729 # Number of instructions simulated 13sim_ops 1066065309 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu0.dtb.walker 128960 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.itb.walker 112832 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.inst 8192640 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.data 40731208 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu0.l2cache.prefetcher 14846528 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu1.dtb.walker 153920 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.itb.walker 132096 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu1.inst 3008640 # Number of bytes read from this memory 24system.physmem.bytes_read::cpu1.data 17045264 # Number of bytes read from this memory 25system.physmem.bytes_read::cpu1.l2cache.prefetcher 15179584 # Number of bytes read from this memory 26system.physmem.bytes_read::realview.ide 435648 # Number of bytes read from this memory 27system.physmem.bytes_read::total 99967320 # Number of bytes read from this memory 28system.physmem.bytes_inst_read::cpu0.inst 8192640 # Number of instructions bytes read from this memory 29system.physmem.bytes_inst_read::cpu1.inst 3008640 # Number of instructions bytes read from this memory 30system.physmem.bytes_inst_read::total 11201280 # Number of instructions bytes read from this memory 31system.physmem.bytes_written::writebacks 79350912 # Number of bytes written to this memory 32system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory 33system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory 34system.physmem.bytes_written::total 79371496 # Number of bytes written to this memory 35system.physmem.num_reads::cpu0.dtb.walker 2015 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu0.itb.walker 1763 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu0.inst 128010 # Number of read requests responded to by this memory 38system.physmem.num_reads::cpu0.data 636438 # Number of read requests responded to by this memory 39system.physmem.num_reads::cpu0.l2cache.prefetcher 231977 # Number of read requests responded to by this memory 40system.physmem.num_reads::cpu1.dtb.walker 2405 # Number of read requests responded to by this memory 41system.physmem.num_reads::cpu1.itb.walker 2064 # Number of read requests responded to by this memory 42system.physmem.num_reads::cpu1.inst 47010 # Number of read requests responded to by this memory 43system.physmem.num_reads::cpu1.data 266345 # Number of read requests responded to by this memory 44system.physmem.num_reads::cpu1.l2cache.prefetcher 237181 # Number of read requests responded to by this memory 45system.physmem.num_reads::realview.ide 6807 # Number of read requests responded to by this memory 46system.physmem.num_reads::total 1562015 # Number of read requests responded to by this memory 47system.physmem.num_writes::writebacks 1239858 # Number of write requests responded to by this memory 48system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory 49system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory 50system.physmem.num_writes::total 1242432 # Number of write requests responded to by this memory 51system.physmem.bw_read::cpu0.dtb.walker 2717 # Total read bandwidth from this memory (bytes/s) 52system.physmem.bw_read::cpu0.itb.walker 2377 # Total read bandwidth from this memory (bytes/s) 53system.physmem.bw_read::cpu0.inst 172615 # Total read bandwidth from this memory (bytes/s) 54system.physmem.bw_read::cpu0.data 858187 # Total read bandwidth from this memory (bytes/s) 55system.physmem.bw_read::cpu0.l2cache.prefetcher 312809 # Total read bandwidth from this memory (bytes/s) 56system.physmem.bw_read::cpu1.dtb.walker 3243 # Total read bandwidth from this memory (bytes/s) 57system.physmem.bw_read::cpu1.itb.walker 2783 # Total read bandwidth from this memory (bytes/s) 58system.physmem.bw_read::cpu1.inst 63391 # Total read bandwidth from this memory (bytes/s) 59system.physmem.bw_read::cpu1.data 359135 # Total read bandwidth from this memory (bytes/s) 60system.physmem.bw_read::cpu1.l2cache.prefetcher 319826 # Total read bandwidth from this memory (bytes/s) 61system.physmem.bw_read::realview.ide 9179 # Total read bandwidth from this memory (bytes/s) 62system.physmem.bw_read::total 2106263 # Total read bandwidth from this memory (bytes/s) 63system.physmem.bw_inst_read::cpu0.inst 172615 # Instruction read bandwidth from this memory (bytes/s) 64system.physmem.bw_inst_read::cpu1.inst 63391 # Instruction read bandwidth from this memory (bytes/s) 65system.physmem.bw_inst_read::total 236006 # Instruction read bandwidth from this memory (bytes/s) 66system.physmem.bw_write::writebacks 1671885 # Write bandwidth from this memory (bytes/s) 67system.physmem.bw_write::cpu0.data 434 # Write bandwidth from this memory (bytes/s) 68system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) 69system.physmem.bw_write::total 1672319 # Write bandwidth from this memory (bytes/s) 70system.physmem.bw_total::writebacks 1671885 # Total bandwidth to/from this memory (bytes/s) 71system.physmem.bw_total::cpu0.dtb.walker 2717 # Total bandwidth to/from this memory (bytes/s) 72system.physmem.bw_total::cpu0.itb.walker 2377 # Total bandwidth to/from this memory (bytes/s) 73system.physmem.bw_total::cpu0.inst 172615 # Total bandwidth to/from this memory (bytes/s) 74system.physmem.bw_total::cpu0.data 858620 # Total bandwidth to/from this memory (bytes/s) 75system.physmem.bw_total::cpu0.l2cache.prefetcher 312809 # Total bandwidth to/from this memory (bytes/s) 76system.physmem.bw_total::cpu1.dtb.walker 3243 # Total bandwidth to/from this memory (bytes/s) 77system.physmem.bw_total::cpu1.itb.walker 2783 # Total bandwidth to/from this memory (bytes/s) 78system.physmem.bw_total::cpu1.inst 63391 # Total bandwidth to/from this memory (bytes/s) 79system.physmem.bw_total::cpu1.data 359136 # Total bandwidth to/from this memory (bytes/s) 80system.physmem.bw_total::cpu1.l2cache.prefetcher 319826 # Total bandwidth to/from this memory (bytes/s) 81system.physmem.bw_total::realview.ide 9179 # Total bandwidth to/from this memory (bytes/s) 82system.physmem.bw_total::total 3778582 # Total bandwidth to/from this memory (bytes/s) 83system.physmem.readReqs 1562015 # Number of read requests accepted 84system.physmem.writeReqs 1242432 # Number of write requests accepted 85system.physmem.readBursts 1562015 # Number of DRAM read bursts, including those serviced by the write queue 86system.physmem.writeBursts 1242432 # Number of DRAM write bursts, including those merged in the write queue 87system.physmem.bytesReadDRAM 99934848 # Total number of bytes read from DRAM 88system.physmem.bytesReadWrQ 34112 # Total number of bytes read from write queue 89system.physmem.bytesWritten 79370432 # Total number of bytes written to DRAM 90system.physmem.bytesReadSys 99967320 # Total read bytes from the system interface side 91system.physmem.bytesWrittenSys 79371496 # Total written bytes from the system interface side 92system.physmem.servicedByWrQ 533 # Number of DRAM read bursts serviced by the write queue 93system.physmem.mergedWrBursts 2246 # Number of DRAM write bursts merged with an existing one 94system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 95system.physmem.perBankRdBursts::0 93757 # Per bank write bursts 96system.physmem.perBankRdBursts::1 100629 # Per bank write bursts 97system.physmem.perBankRdBursts::2 93977 # Per bank write bursts 98system.physmem.perBankRdBursts::3 99615 # Per bank write bursts 99system.physmem.perBankRdBursts::4 97211 # Per bank write bursts 100system.physmem.perBankRdBursts::5 108899 # Per bank write bursts 101system.physmem.perBankRdBursts::6 95410 # Per bank write bursts 102system.physmem.perBankRdBursts::7 95079 # Per bank write bursts 103system.physmem.perBankRdBursts::8 84413 # Per bank write bursts 104system.physmem.perBankRdBursts::9 140545 # Per bank write bursts 105system.physmem.perBankRdBursts::10 87149 # Per bank write bursts 106system.physmem.perBankRdBursts::11 92128 # Per bank write bursts 107system.physmem.perBankRdBursts::12 89605 # Per bank write bursts 108system.physmem.perBankRdBursts::13 97795 # Per bank write bursts 109system.physmem.perBankRdBursts::14 91413 # Per bank write bursts 110system.physmem.perBankRdBursts::15 93857 # Per bank write bursts 111system.physmem.perBankWrBursts::0 74634 # Per bank write bursts 112system.physmem.perBankWrBursts::1 80843 # Per bank write bursts 113system.physmem.perBankWrBursts::2 76779 # Per bank write bursts 114system.physmem.perBankWrBursts::3 81501 # Per bank write bursts 115system.physmem.perBankWrBursts::4 79021 # Per bank write bursts 116system.physmem.perBankWrBursts::5 86869 # Per bank write bursts 117system.physmem.perBankWrBursts::6 77167 # Per bank write bursts 118system.physmem.perBankWrBursts::7 78926 # Per bank write bursts 119system.physmem.perBankWrBursts::8 71646 # Per bank write bursts 120system.physmem.perBankWrBursts::9 75252 # Per bank write bursts 121system.physmem.perBankWrBursts::10 73334 # Per bank write bursts 122system.physmem.perBankWrBursts::11 76259 # Per bank write bursts 123system.physmem.perBankWrBursts::12 74746 # Per bank write bursts 124system.physmem.perBankWrBursts::13 79667 # Per bank write bursts 125system.physmem.perBankWrBursts::14 75302 # Per bank write bursts 126system.physmem.perBankWrBursts::15 78217 # Per bank write bursts 127system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 128system.physmem.numWrRetry 64 # Number of times write queue was full causing retry 129system.physmem.totGap 47461932782500 # Total gap between requests 130system.physmem.readPktSize::0 0 # Read request sizes (log2) 131system.physmem.readPktSize::1 0 # Read request sizes (log2) 132system.physmem.readPktSize::2 0 # Read request sizes (log2) 133system.physmem.readPktSize::3 25 # Read request sizes (log2) 134system.physmem.readPktSize::4 5 # Read request sizes (log2) 135system.physmem.readPktSize::5 0 # Read request sizes (log2) 136system.physmem.readPktSize::6 1561985 # Read request sizes (log2) 137system.physmem.writePktSize::0 0 # Write request sizes (log2) 138system.physmem.writePktSize::1 0 # Write request sizes (log2) 139system.physmem.writePktSize::2 2 # Write request sizes (log2) 140system.physmem.writePktSize::3 2572 # Write request sizes (log2) 141system.physmem.writePktSize::4 0 # Write request sizes (log2) 142system.physmem.writePktSize::5 0 # Write request sizes (log2) 143system.physmem.writePktSize::6 1239858 # Write request sizes (log2) 144system.physmem.rdQLenPdf::0 973357 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::1 368872 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::2 48939 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::3 35383 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::4 30040 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::5 27781 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::6 24940 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::7 22435 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::8 19175 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::9 4270 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::10 1963 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::11 1251 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::12 910 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::13 672 # What read queue length does an incoming req see 158system.physmem.rdQLenPdf::14 409 # What read queue length does an incoming req see 159system.physmem.rdQLenPdf::15 353 # What read queue length does an incoming req see 160system.physmem.rdQLenPdf::16 290 # What read queue length does an incoming req see 161system.physmem.rdQLenPdf::17 241 # What read queue length does an incoming req see 162system.physmem.rdQLenPdf::18 109 # What read queue length does an incoming req see 163system.physmem.rdQLenPdf::19 70 # What read queue length does an incoming req see 164system.physmem.rdQLenPdf::20 9 # What read queue length does an incoming req see 165system.physmem.rdQLenPdf::21 7 # What read queue length does an incoming req see 166system.physmem.rdQLenPdf::22 3 # What read queue length does an incoming req see 167system.physmem.rdQLenPdf::23 2 # What read queue length does an incoming req see 168system.physmem.rdQLenPdf::24 1 # What read queue length does an incoming req see 169system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 170system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 171system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 172system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 173system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 174system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 175system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 176system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::15 20126 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::16 23872 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::17 45415 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::18 56281 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::19 64128 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::20 66477 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::21 70043 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::22 73662 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::23 76578 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::24 77244 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::25 79843 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::26 84567 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::27 82434 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::28 83310 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::29 91239 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::30 81410 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::31 76067 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::32 73611 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::33 3385 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::34 1421 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::35 940 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::36 727 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::37 640 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::38 568 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::39 422 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::40 365 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::41 390 # What write queue length does an incoming req see 218system.physmem.wrQLenPdf::42 333 # What write queue length does an incoming req see 219system.physmem.wrQLenPdf::43 338 # What write queue length does an incoming req see 220system.physmem.wrQLenPdf::44 374 # What write queue length does an incoming req see 221system.physmem.wrQLenPdf::45 362 # What write queue length does an incoming req see 222system.physmem.wrQLenPdf::46 231 # What write queue length does an incoming req see 223system.physmem.wrQLenPdf::47 275 # What write queue length does an incoming req see 224system.physmem.wrQLenPdf::48 228 # What write queue length does an incoming req see 225system.physmem.wrQLenPdf::49 247 # What write queue length does an incoming req see 226system.physmem.wrQLenPdf::50 311 # What write queue length does an incoming req see 227system.physmem.wrQLenPdf::51 204 # What write queue length does an incoming req see 228system.physmem.wrQLenPdf::52 261 # What write queue length does an incoming req see 229system.physmem.wrQLenPdf::53 236 # What write queue length does an incoming req see 230system.physmem.wrQLenPdf::54 227 # What write queue length does an incoming req see 231system.physmem.wrQLenPdf::55 124 # What write queue length does an incoming req see 232system.physmem.wrQLenPdf::56 170 # What write queue length does an incoming req see 233system.physmem.wrQLenPdf::57 185 # What write queue length does an incoming req see 234system.physmem.wrQLenPdf::58 133 # What write queue length does an incoming req see 235system.physmem.wrQLenPdf::59 155 # What write queue length does an incoming req see 236system.physmem.wrQLenPdf::60 142 # What write queue length does an incoming req see 237system.physmem.wrQLenPdf::61 234 # What write queue length does an incoming req see 238system.physmem.wrQLenPdf::62 86 # What write queue length does an incoming req see 239system.physmem.wrQLenPdf::63 150 # What write queue length does an incoming req see 240system.physmem.bytesPerActivate::samples 991222 # Bytes accessed per row activation 241system.physmem.bytesPerActivate::mean 180.892514 # Bytes accessed per row activation 242system.physmem.bytesPerActivate::gmean 111.543893 # Bytes accessed per row activation 243system.physmem.bytesPerActivate::stdev 240.536828 # Bytes accessed per row activation 244system.physmem.bytesPerActivate::0-127 614355 61.98% 61.98% # Bytes accessed per row activation 245system.physmem.bytesPerActivate::128-255 184510 18.61% 80.59% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::256-383 61267 6.18% 86.77% # Bytes accessed per row activation 247system.physmem.bytesPerActivate::384-511 32396 3.27% 90.04% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::512-639 21556 2.17% 92.22% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::640-767 13955 1.41% 93.63% # Bytes accessed per row activation 250system.physmem.bytesPerActivate::768-895 9658 0.97% 94.60% # Bytes accessed per row activation 251system.physmem.bytesPerActivate::896-1023 9476 0.96% 95.56% # Bytes accessed per row activation 252system.physmem.bytesPerActivate::1024-1151 44049 4.44% 100.00% # Bytes accessed per row activation 253system.physmem.bytesPerActivate::total 991222 # Bytes accessed per row activation 254system.physmem.rdPerTurnAround::samples 69967 # Reads before turning the bus around for writes 255system.physmem.rdPerTurnAround::mean 22.317164 # Reads before turning the bus around for writes 256system.physmem.rdPerTurnAround::stdev 326.421262 # Reads before turning the bus around for writes 257system.physmem.rdPerTurnAround::0-4095 69964 100.00% 100.00% # Reads before turning the bus around for writes 258system.physmem.rdPerTurnAround::4096-8191 1 0.00% 100.00% # Reads before turning the bus around for writes 259system.physmem.rdPerTurnAround::24576-28671 1 0.00% 100.00% # Reads before turning the bus around for writes 260system.physmem.rdPerTurnAround::81920-86015 1 0.00% 100.00% # Reads before turning the bus around for writes 261system.physmem.rdPerTurnAround::total 69967 # Reads before turning the bus around for writes 262system.physmem.wrPerTurnAround::samples 69967 # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::mean 17.724970 # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::gmean 17.179434 # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::stdev 7.169336 # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::16-19 65865 94.14% 94.14% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::20-23 2036 2.91% 97.05% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::24-27 254 0.36% 97.41% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::28-31 187 0.27% 97.68% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::32-35 141 0.20% 97.88% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::36-39 122 0.17% 98.05% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::40-43 214 0.31% 98.36% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::44-47 78 0.11% 98.47% # Writes before turning the bus around for reads 274system.physmem.wrPerTurnAround::48-51 271 0.39% 98.86% # Writes before turning the bus around for reads 275system.physmem.wrPerTurnAround::52-55 64 0.09% 98.95% # Writes before turning the bus around for reads 276system.physmem.wrPerTurnAround::56-59 34 0.05% 99.00% # Writes before turning the bus around for reads 277system.physmem.wrPerTurnAround::60-63 49 0.07% 99.07% # Writes before turning the bus around for reads 278system.physmem.wrPerTurnAround::64-67 243 0.35% 99.42% # Writes before turning the bus around for reads 279system.physmem.wrPerTurnAround::68-71 32 0.05% 99.46% # Writes before turning the bus around for reads 280system.physmem.wrPerTurnAround::72-75 40 0.06% 99.52% # Writes before turning the bus around for reads 281system.physmem.wrPerTurnAround::76-79 104 0.15% 99.67% # Writes before turning the bus around for reads 282system.physmem.wrPerTurnAround::80-83 171 0.24% 99.91% # Writes before turning the bus around for reads 283system.physmem.wrPerTurnAround::84-87 3 0.00% 99.92% # Writes before turning the bus around for reads 284system.physmem.wrPerTurnAround::88-91 3 0.00% 99.92% # Writes before turning the bus around for reads 285system.physmem.wrPerTurnAround::92-95 3 0.00% 99.92% # Writes before turning the bus around for reads 286system.physmem.wrPerTurnAround::96-99 1 0.00% 99.93% # Writes before turning the bus around for reads 287system.physmem.wrPerTurnAround::100-103 3 0.00% 99.93% # Writes before turning the bus around for reads 288system.physmem.wrPerTurnAround::104-107 1 0.00% 99.93% # Writes before turning the bus around for reads 289system.physmem.wrPerTurnAround::108-111 1 0.00% 99.93% # Writes before turning the bus around for reads 290system.physmem.wrPerTurnAround::112-115 3 0.00% 99.94% # Writes before turning the bus around for reads 291system.physmem.wrPerTurnAround::128-131 14 0.02% 99.96% # Writes before turning the bus around for reads 292system.physmem.wrPerTurnAround::132-135 3 0.00% 99.96% # Writes before turning the bus around for reads 293system.physmem.wrPerTurnAround::136-139 1 0.00% 99.96% # Writes before turning the bus around for reads 294system.physmem.wrPerTurnAround::144-147 14 0.02% 99.98% # Writes before turning the bus around for reads 295system.physmem.wrPerTurnAround::152-155 1 0.00% 99.98% # Writes before turning the bus around for reads 296system.physmem.wrPerTurnAround::156-159 2 0.00% 99.99% # Writes before turning the bus around for reads 297system.physmem.wrPerTurnAround::160-163 2 0.00% 99.99% # Writes before turning the bus around for reads 298system.physmem.wrPerTurnAround::164-167 1 0.00% 99.99% # Writes before turning the bus around for reads 299system.physmem.wrPerTurnAround::168-171 1 0.00% 99.99% # Writes before turning the bus around for reads 300system.physmem.wrPerTurnAround::172-175 1 0.00% 99.99% # Writes before turning the bus around for reads 301system.physmem.wrPerTurnAround::176-179 2 0.00% 100.00% # Writes before turning the bus around for reads 302system.physmem.wrPerTurnAround::180-183 1 0.00% 100.00% # Writes before turning the bus around for reads 303system.physmem.wrPerTurnAround::184-187 1 0.00% 100.00% # Writes before turning the bus around for reads 304system.physmem.wrPerTurnAround::total 69967 # Writes before turning the bus around for reads 305system.physmem.totQLat 43176438588 # Total ticks spent queuing 306system.physmem.totMemAccLat 72454226088 # Total ticks spent from burst creation until serviced by the DRAM 307system.physmem.totBusLat 7807410000 # Total ticks spent in databus transfers 308system.physmem.avgQLat 27650.94 # Average queueing delay per DRAM burst 309system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 310system.physmem.avgMemAccLat 46400.94 # Average memory access latency per DRAM burst 311system.physmem.avgRdBW 2.11 # Average DRAM read bandwidth in MiByte/s 312system.physmem.avgWrBW 1.67 # Average achieved write bandwidth in MiByte/s 313system.physmem.avgRdBWSys 2.11 # Average system read bandwidth in MiByte/s 314system.physmem.avgWrBWSys 1.67 # Average system write bandwidth in MiByte/s 315system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 316system.physmem.busUtil 0.03 # Data bus utilization in percentage 317system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads 318system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes 319system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing 320system.physmem.avgWrQLen 25.42 # Average write queue length when enqueuing 321system.physmem.readRowHits 1247973 # Number of row buffer hits during reads 322system.physmem.writeRowHits 562447 # Number of row buffer hits during writes 323system.physmem.readRowHitRate 79.92 # Row buffer hit rate for reads 324system.physmem.writeRowHitRate 45.35 # Row buffer hit rate for writes 325system.physmem.avgGap 16923811.64 # Average gap between requests 326system.physmem.pageHitRate 64.62 # Row buffer hit rate, read and write combined 327system.physmem_0.actEnergy 3897081720 # Energy for activate commands per rank (pJ) 328system.physmem_0.preEnergy 2126383875 # Energy for precharge commands per rank (pJ) 329system.physmem_0.readEnergy 6119692800 # Energy for read commands per rank (pJ) 330system.physmem_0.writeEnergy 4119595200 # Energy for write commands per rank (pJ) 331system.physmem_0.refreshEnergy 3099982404480 # Energy for refresh commands per rank (pJ) 332system.physmem_0.actBackEnergy 1216381568355 # Energy for active background per rank (pJ) 333system.physmem_0.preBackEnergy 27410155454250 # Energy for precharge background per rank (pJ) 334system.physmem_0.totalEnergy 31742782180680 # Total energy per rank (pJ) 335system.physmem_0.averagePower 668.805156 # Core power per rank (mW) 336system.physmem_0.memoryStateTime::IDLE 45598728268843 # Time in different power states 337system.physmem_0.memoryStateTime::REF 1584858080000 # Time in different power states 338system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 339system.physmem_0.memoryStateTime::ACT 278346651157 # Time in different power states 340system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 341system.physmem_1.actEnergy 3596556600 # Energy for activate commands per rank (pJ) 342system.physmem_1.preEnergy 1962406875 # Energy for precharge commands per rank (pJ) 343system.physmem_1.readEnergy 6059788800 # Energy for read commands per rank (pJ) 344system.physmem_1.writeEnergy 3916661040 # Energy for write commands per rank (pJ) 345system.physmem_1.refreshEnergy 3099982404480 # Energy for refresh commands per rank (pJ) 346system.physmem_1.actBackEnergy 1207691479170 # Energy for active background per rank (pJ) 347system.physmem_1.preBackEnergy 27417778331250 # Energy for precharge background per rank (pJ) 348system.physmem_1.totalEnergy 31740987628215 # Total energy per rank (pJ) 349system.physmem_1.averagePower 668.767346 # Core power per rank (mW) 350system.physmem_1.memoryStateTime::IDLE 45611421903472 # Time in different power states 351system.physmem_1.memoryStateTime::REF 1584858080000 # Time in different power states 352system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 353system.physmem_1.memoryStateTime::ACT 265649419028 # Time in different power states 354system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 355system.realview.nvmem.bytes_read::cpu0.inst 704 # Number of bytes read from this memory 356system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory 357system.realview.nvmem.bytes_read::cpu1.inst 576 # Number of bytes read from this memory 358system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory 359system.realview.nvmem.bytes_read::total 1324 # Number of bytes read from this memory 360system.realview.nvmem.bytes_inst_read::cpu0.inst 704 # Number of instructions bytes read from this memory 361system.realview.nvmem.bytes_inst_read::cpu1.inst 576 # Number of instructions bytes read from this memory 362system.realview.nvmem.bytes_inst_read::total 1280 # Number of instructions bytes read from this memory 363system.realview.nvmem.num_reads::cpu0.inst 11 # Number of read requests responded to by this memory 364system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory 365system.realview.nvmem.num_reads::cpu1.inst 9 # Number of read requests responded to by this memory 366system.realview.nvmem.num_reads::cpu1.data 1 # Number of read requests responded to by this memory 367system.realview.nvmem.num_reads::total 26 # Number of read requests responded to by this memory 368system.realview.nvmem.bw_read::cpu0.inst 15 # Total read bandwidth from this memory (bytes/s) 369system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s) 370system.realview.nvmem.bw_read::cpu1.inst 12 # Total read bandwidth from this memory (bytes/s) 371system.realview.nvmem.bw_read::cpu1.data 0 # Total read bandwidth from this memory (bytes/s) 372system.realview.nvmem.bw_read::total 28 # Total read bandwidth from this memory (bytes/s) 373system.realview.nvmem.bw_inst_read::cpu0.inst 15 # Instruction read bandwidth from this memory (bytes/s) 374system.realview.nvmem.bw_inst_read::cpu1.inst 12 # Instruction read bandwidth from this memory (bytes/s) 375system.realview.nvmem.bw_inst_read::total 27 # Instruction read bandwidth from this memory (bytes/s) 376system.realview.nvmem.bw_total::cpu0.inst 15 # Total bandwidth to/from this memory (bytes/s) 377system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s) 378system.realview.nvmem.bw_total::cpu1.inst 12 # Total bandwidth to/from this memory (bytes/s) 379system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) 380system.realview.nvmem.bw_total::total 28 # Total bandwidth to/from this memory (bytes/s) 381system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 382system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 383system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 384system.cf0.dma_write_full_pages 1671 # Number of full page size DMA writes. 385system.cf0.dma_write_bytes 6846976 # Number of bytes transfered via DMA writes. 386system.cf0.dma_write_txs 1674 # Number of DMA write transactions. 387system.cpu0.branchPred.lookups 141158417 # Number of BP lookups 388system.cpu0.branchPred.condPredicted 100207840 # Number of conditional branches predicted 389system.cpu0.branchPred.condIncorrect 6289341 # Number of conditional branches incorrect 390system.cpu0.branchPred.BTBLookups 105574499 # Number of BTB lookups 391system.cpu0.branchPred.BTBHits 76948344 # Number of BTB hits 392system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 393system.cpu0.branchPred.BTBHitPct 72.885351 # BTB Hit Percentage 394system.cpu0.branchPred.usedRAS 16552897 # Number of times the RAS was used to get a target. 395system.cpu0.branchPred.RASInCorrect 1094870 # Number of incorrect RAS predictions. 396system.cpu_clk_domain.clock 500 # Clock period in ticks 397system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 398system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 399system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 400system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 401system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 402system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 403system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 404system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 405system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 406system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 407system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 408system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 409system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 410system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 411system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 412system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 413system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 414system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 415system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 416system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 417system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 418system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 419system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 420system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 421system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 422system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 423system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 424system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 425system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 426system.cpu0.dtb.walker.walks 283140 # Table walker walks requested 427system.cpu0.dtb.walker.walksLong 283140 # Table walker walks initiated with long descriptors 428system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 9717 # Level at which table walker walks with long descriptors terminate 429system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 79661 # Level at which table walker walks with long descriptors terminate 430system.cpu0.dtb.walker.walkWaitTime::samples 283140 # Table walker wait (enqueue to first request) latency 431system.cpu0.dtb.walker.walkWaitTime::0 283140 100.00% 100.00% # Table walker wait (enqueue to first request) latency 432system.cpu0.dtb.walker.walkWaitTime::total 283140 # Table walker wait (enqueue to first request) latency 433system.cpu0.dtb.walker.walkCompletionTime::samples 89378 # Table walker service (enqueue to completion) latency 434system.cpu0.dtb.walker.walkCompletionTime::mean 23531.797534 # Table walker service (enqueue to completion) latency 435system.cpu0.dtb.walker.walkCompletionTime::gmean 21398.159545 # Table walker service (enqueue to completion) latency 436system.cpu0.dtb.walker.walkCompletionTime::stdev 20518.573843 # Table walker service (enqueue to completion) latency 437system.cpu0.dtb.walker.walkCompletionTime::0-65535 88174 98.65% 98.65% # Table walker service (enqueue to completion) latency 438system.cpu0.dtb.walker.walkCompletionTime::65536-131071 214 0.24% 98.89% # Table walker service (enqueue to completion) latency 439system.cpu0.dtb.walker.walkCompletionTime::131072-196607 839 0.94% 99.83% # Table walker service (enqueue to completion) latency 440system.cpu0.dtb.walker.walkCompletionTime::196608-262143 33 0.04% 99.87% # Table walker service (enqueue to completion) latency 441system.cpu0.dtb.walker.walkCompletionTime::262144-327679 38 0.04% 99.91% # Table walker service (enqueue to completion) latency 442system.cpu0.dtb.walker.walkCompletionTime::327680-393215 25 0.03% 99.94% # Table walker service (enqueue to completion) latency 443system.cpu0.dtb.walker.walkCompletionTime::393216-458751 35 0.04% 99.98% # Table walker service (enqueue to completion) latency 444system.cpu0.dtb.walker.walkCompletionTime::458752-524287 10 0.01% 99.99% # Table walker service (enqueue to completion) latency 445system.cpu0.dtb.walker.walkCompletionTime::524288-589823 8 0.01% 100.00% # Table walker service (enqueue to completion) latency 446system.cpu0.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 447system.cpu0.dtb.walker.walkCompletionTime::720896-786431 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 448system.cpu0.dtb.walker.walkCompletionTime::total 89378 # Table walker service (enqueue to completion) latency 449system.cpu0.dtb.walker.walksPending::samples -909613592 # Table walker pending requests distribution 450system.cpu0.dtb.walker.walksPending::0 -909613592 100.00% 100.00% # Table walker pending requests distribution 451system.cpu0.dtb.walker.walksPending::total -909613592 # Table walker pending requests distribution 452system.cpu0.dtb.walker.walkPageSizes::4K 79661 89.13% 89.13% # Table walker page sizes translated 453system.cpu0.dtb.walker.walkPageSizes::2M 9717 10.87% 100.00% # Table walker page sizes translated 454system.cpu0.dtb.walker.walkPageSizes::total 89378 # Table walker page sizes translated 455system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 283140 # Table walker requests started/completed, data/inst 456system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 457system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 283140 # Table walker requests started/completed, data/inst 458system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 89378 # Table walker requests started/completed, data/inst 459system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 460system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 89378 # Table walker requests started/completed, data/inst 461system.cpu0.dtb.walker.walkRequestOrigin::total 372518 # Table walker requests started/completed, data/inst 462system.cpu0.dtb.inst_hits 0 # ITB inst hits 463system.cpu0.dtb.inst_misses 0 # ITB inst misses 464system.cpu0.dtb.read_hits 90921588 # DTB read hits 465system.cpu0.dtb.read_misses 233548 # DTB read misses 466system.cpu0.dtb.write_hits 80603054 # DTB write hits 467system.cpu0.dtb.write_misses 49592 # DTB write misses 468system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed 469system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 470system.cpu0.dtb.flush_tlb_mva_asid 42784 # Number of times TLB was flushed by MVA & ASID 471system.cpu0.dtb.flush_tlb_asid 1060 # Number of times TLB was flushed by ASID 472system.cpu0.dtb.flush_entries 38267 # Number of entries that have been flushed from TLB 473system.cpu0.dtb.align_faults 2134 # Number of TLB faults due to alignment restrictions 474system.cpu0.dtb.prefetch_faults 9015 # Number of TLB faults due to prefetch 475system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 476system.cpu0.dtb.perms_faults 11497 # Number of TLB faults due to permissions restrictions 477system.cpu0.dtb.read_accesses 91155136 # DTB read accesses 478system.cpu0.dtb.write_accesses 80652646 # DTB write accesses 479system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 480system.cpu0.dtb.hits 171524642 # DTB hits 481system.cpu0.dtb.misses 283140 # DTB misses 482system.cpu0.dtb.accesses 171807782 # DTB accesses 483system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 484system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 485system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 486system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 487system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 488system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 489system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 490system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 491system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 492system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 493system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 494system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 495system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 496system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 497system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 498system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 499system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 500system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 501system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 502system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 503system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 504system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 505system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 506system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 507system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 508system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 509system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 510system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 511system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 512system.cpu0.itb.walker.walks 66290 # Table walker walks requested 513system.cpu0.itb.walker.walksLong 66290 # Table walker walks initiated with long descriptors 514system.cpu0.itb.walker.walksLongTerminationLevel::Level2 665 # Level at which table walker walks with long descriptors terminate 515system.cpu0.itb.walker.walksLongTerminationLevel::Level3 56612 # Level at which table walker walks with long descriptors terminate 516system.cpu0.itb.walker.walkWaitTime::samples 66290 # Table walker wait (enqueue to first request) latency 517system.cpu0.itb.walker.walkWaitTime::0 66290 100.00% 100.00% # Table walker wait (enqueue to first request) latency 518system.cpu0.itb.walker.walkWaitTime::total 66290 # Table walker wait (enqueue to first request) latency 519system.cpu0.itb.walker.walkCompletionTime::samples 57277 # Table walker service (enqueue to completion) latency 520system.cpu0.itb.walker.walkCompletionTime::mean 26707.997975 # Table walker service (enqueue to completion) latency 521system.cpu0.itb.walker.walkCompletionTime::gmean 23913.035188 # Table walker service (enqueue to completion) latency 522system.cpu0.itb.walker.walkCompletionTime::stdev 23204.196076 # Table walker service (enqueue to completion) latency 523system.cpu0.itb.walker.walkCompletionTime::0-65535 56118 97.98% 97.98% # Table walker service (enqueue to completion) latency 524system.cpu0.itb.walker.walkCompletionTime::65536-131071 13 0.02% 98.00% # Table walker service (enqueue to completion) latency 525system.cpu0.itb.walker.walkCompletionTime::131072-196607 1037 1.81% 99.81% # Table walker service (enqueue to completion) latency 526system.cpu0.itb.walker.walkCompletionTime::196608-262143 26 0.05% 99.86% # Table walker service (enqueue to completion) latency 527system.cpu0.itb.walker.walkCompletionTime::262144-327679 46 0.08% 99.94% # Table walker service (enqueue to completion) latency 528system.cpu0.itb.walker.walkCompletionTime::327680-393215 23 0.04% 99.98% # Table walker service (enqueue to completion) latency 529system.cpu0.itb.walker.walkCompletionTime::393216-458751 11 0.02% 99.99% # Table walker service (enqueue to completion) latency 530system.cpu0.itb.walker.walkCompletionTime::458752-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 531system.cpu0.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 532system.cpu0.itb.walker.walkCompletionTime::total 57277 # Table walker service (enqueue to completion) latency 533system.cpu0.itb.walker.walksPending::samples -910742092 # Table walker pending requests distribution 534system.cpu0.itb.walker.walksPending::0 -910742092 100.00% 100.00% # Table walker pending requests distribution 535system.cpu0.itb.walker.walksPending::total -910742092 # Table walker pending requests distribution 536system.cpu0.itb.walker.walkPageSizes::4K 56612 98.84% 98.84% # Table walker page sizes translated 537system.cpu0.itb.walker.walkPageSizes::2M 665 1.16% 100.00% # Table walker page sizes translated 538system.cpu0.itb.walker.walkPageSizes::total 57277 # Table walker page sizes translated 539system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 540system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 66290 # Table walker requests started/completed, data/inst 541system.cpu0.itb.walker.walkRequestOrigin_Requested::total 66290 # Table walker requests started/completed, data/inst 542system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 543system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 57277 # Table walker requests started/completed, data/inst 544system.cpu0.itb.walker.walkRequestOrigin_Completed::total 57277 # Table walker requests started/completed, data/inst 545system.cpu0.itb.walker.walkRequestOrigin::total 123567 # Table walker requests started/completed, data/inst 546system.cpu0.itb.inst_hits 252665762 # ITB inst hits 547system.cpu0.itb.inst_misses 66290 # ITB inst misses 548system.cpu0.itb.read_hits 0 # DTB read hits 549system.cpu0.itb.read_misses 0 # DTB read misses 550system.cpu0.itb.write_hits 0 # DTB write hits 551system.cpu0.itb.write_misses 0 # DTB write misses 552system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed 553system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 554system.cpu0.itb.flush_tlb_mva_asid 42784 # Number of times TLB was flushed by MVA & ASID 555system.cpu0.itb.flush_tlb_asid 1060 # Number of times TLB was flushed by ASID 556system.cpu0.itb.flush_entries 27416 # Number of entries that have been flushed from TLB 557system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 558system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 559system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 560system.cpu0.itb.perms_faults 203450 # Number of TLB faults due to permissions restrictions 561system.cpu0.itb.read_accesses 0 # DTB read accesses 562system.cpu0.itb.write_accesses 0 # DTB write accesses 563system.cpu0.itb.inst_accesses 252732052 # ITB inst accesses 564system.cpu0.itb.hits 252665762 # DTB hits 565system.cpu0.itb.misses 66290 # DTB misses 566system.cpu0.itb.accesses 252732052 # DTB accesses 567system.cpu0.numCycles 1081051562 # number of cpu cycles simulated 568system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 569system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 570system.cpu0.committedInsts 468741146 # Number of instructions committed 571system.cpu0.committedOps 550955855 # Number of ops (including micro ops) committed 572system.cpu0.discardedOps 47157402 # Number of ops (including micro ops) which were discarded before commit 573system.cpu0.numFetchSuspends 5078 # Number of times Execute suspended instruction fetching 574system.cpu0.quiesceCycles 93843643871 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 575system.cpu0.cpi 2.306287 # CPI: cycles per instruction 576system.cpu0.ipc 0.433597 # IPC: instructions per cycle 577system.cpu0.kern.inst.arm 0 # number of arm instructions executed 578system.cpu0.kern.inst.quiesce 5324 # number of quiesce instructions executed 579system.cpu0.tickCycles 755067683 # Number of cycles that the object actually ticked 580system.cpu0.idleCycles 325983879 # Total number of cycles that the object has spent stopped 581system.cpu0.dcache.tags.replacements 5850262 # number of replacements 582system.cpu0.dcache.tags.tagsinuse 501.214442 # Cycle average of tags in use 583system.cpu0.dcache.tags.total_refs 162710873 # Total number of references to valid blocks. 584system.cpu0.dcache.tags.sampled_refs 5850774 # Sample count of references to valid blocks. 585system.cpu0.dcache.tags.avg_refs 27.810145 # Average number of references to valid blocks. 586system.cpu0.dcache.tags.warmup_cycle 7690769000 # Cycle when the warmup percentage was hit. 587system.cpu0.dcache.tags.occ_blocks::cpu0.data 501.214442 # Average occupied blocks per requestor 588system.cpu0.dcache.tags.occ_percent::cpu0.data 0.978934 # Average percentage of cache occupancy 589system.cpu0.dcache.tags.occ_percent::total 0.978934 # Average percentage of cache occupancy 590system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 591system.cpu0.dcache.tags.age_task_id_blocks_1024::0 158 # Occupied blocks per task id 592system.cpu0.dcache.tags.age_task_id_blocks_1024::1 332 # Occupied blocks per task id 593system.cpu0.dcache.tags.age_task_id_blocks_1024::2 22 # Occupied blocks per task id 594system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 595system.cpu0.dcache.tags.tag_accesses 346062459 # Number of tag accesses 596system.cpu0.dcache.tags.data_accesses 346062459 # Number of data accesses 597system.cpu0.dcache.ReadReq_hits::cpu0.data 83268986 # number of ReadReq hits 598system.cpu0.dcache.ReadReq_hits::total 83268986 # number of ReadReq hits 599system.cpu0.dcache.WriteReq_hits::cpu0.data 74755135 # number of WriteReq hits 600system.cpu0.dcache.WriteReq_hits::total 74755135 # number of WriteReq hits 601system.cpu0.dcache.SoftPFReq_hits::cpu0.data 273368 # number of SoftPFReq hits 602system.cpu0.dcache.SoftPFReq_hits::total 273368 # number of SoftPFReq hits 603system.cpu0.dcache.WriteLineReq_hits::cpu0.data 183787 # number of WriteLineReq hits 604system.cpu0.dcache.WriteLineReq_hits::total 183787 # number of WriteLineReq hits 605system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1841830 # number of LoadLockedReq hits 606system.cpu0.dcache.LoadLockedReq_hits::total 1841830 # number of LoadLockedReq hits 607system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1806426 # number of StoreCondReq hits 608system.cpu0.dcache.StoreCondReq_hits::total 1806426 # number of StoreCondReq hits 609system.cpu0.dcache.demand_hits::cpu0.data 158024121 # number of demand (read+write) hits 610system.cpu0.dcache.demand_hits::total 158024121 # number of demand (read+write) hits 611system.cpu0.dcache.overall_hits::cpu0.data 158297489 # number of overall hits 612system.cpu0.dcache.overall_hits::total 158297489 # number of overall hits 613system.cpu0.dcache.ReadReq_misses::cpu0.data 3569470 # number of ReadReq misses 614system.cpu0.dcache.ReadReq_misses::total 3569470 # number of ReadReq misses 615system.cpu0.dcache.WriteReq_misses::cpu0.data 2481271 # number of WriteReq misses 616system.cpu0.dcache.WriteReq_misses::total 2481271 # number of WriteReq misses 617system.cpu0.dcache.SoftPFReq_misses::cpu0.data 690957 # number of SoftPFReq misses 618system.cpu0.dcache.SoftPFReq_misses::total 690957 # number of SoftPFReq misses 619system.cpu0.dcache.WriteLineReq_misses::cpu0.data 806074 # number of WriteLineReq misses 620system.cpu0.dcache.WriteLineReq_misses::total 806074 # number of WriteLineReq misses 621system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 173924 # number of LoadLockedReq misses 622system.cpu0.dcache.LoadLockedReq_misses::total 173924 # number of LoadLockedReq misses 623system.cpu0.dcache.StoreCondReq_misses::cpu0.data 207838 # number of StoreCondReq misses 624system.cpu0.dcache.StoreCondReq_misses::total 207838 # number of StoreCondReq misses 625system.cpu0.dcache.demand_misses::cpu0.data 6050741 # number of demand (read+write) misses 626system.cpu0.dcache.demand_misses::total 6050741 # number of demand (read+write) misses 627system.cpu0.dcache.overall_misses::cpu0.data 6741698 # number of overall misses 628system.cpu0.dcache.overall_misses::total 6741698 # number of overall misses 629system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 62945089000 # number of ReadReq miss cycles 630system.cpu0.dcache.ReadReq_miss_latency::total 62945089000 # number of ReadReq miss cycles 631system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 62898003000 # number of WriteReq miss cycles 632system.cpu0.dcache.WriteReq_miss_latency::total 62898003000 # number of WriteReq miss cycles 633system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 71296883500 # number of WriteLineReq miss cycles 634system.cpu0.dcache.WriteLineReq_miss_latency::total 71296883500 # number of WriteLineReq miss cycles 635system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2825966000 # number of LoadLockedReq miss cycles 636system.cpu0.dcache.LoadLockedReq_miss_latency::total 2825966000 # number of LoadLockedReq miss cycles 637system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 5775275000 # number of StoreCondReq miss cycles 638system.cpu0.dcache.StoreCondReq_miss_latency::total 5775275000 # number of StoreCondReq miss cycles 639system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 4714000 # number of StoreCondFailReq miss cycles 640system.cpu0.dcache.StoreCondFailReq_miss_latency::total 4714000 # number of StoreCondFailReq miss cycles 641system.cpu0.dcache.demand_miss_latency::cpu0.data 125843092000 # number of demand (read+write) miss cycles 642system.cpu0.dcache.demand_miss_latency::total 125843092000 # number of demand (read+write) miss cycles 643system.cpu0.dcache.overall_miss_latency::cpu0.data 125843092000 # number of overall miss cycles 644system.cpu0.dcache.overall_miss_latency::total 125843092000 # number of overall miss cycles 645system.cpu0.dcache.ReadReq_accesses::cpu0.data 86838456 # number of ReadReq accesses(hits+misses) 646system.cpu0.dcache.ReadReq_accesses::total 86838456 # number of ReadReq accesses(hits+misses) 647system.cpu0.dcache.WriteReq_accesses::cpu0.data 77236406 # number of WriteReq accesses(hits+misses) 648system.cpu0.dcache.WriteReq_accesses::total 77236406 # number of WriteReq accesses(hits+misses) 649system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 964325 # number of SoftPFReq accesses(hits+misses) 650system.cpu0.dcache.SoftPFReq_accesses::total 964325 # number of SoftPFReq accesses(hits+misses) 651system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 989861 # number of WriteLineReq accesses(hits+misses) 652system.cpu0.dcache.WriteLineReq_accesses::total 989861 # number of WriteLineReq accesses(hits+misses) 653system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2015754 # number of LoadLockedReq accesses(hits+misses) 654system.cpu0.dcache.LoadLockedReq_accesses::total 2015754 # number of LoadLockedReq accesses(hits+misses) 655system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2014264 # number of StoreCondReq accesses(hits+misses) 656system.cpu0.dcache.StoreCondReq_accesses::total 2014264 # number of StoreCondReq accesses(hits+misses) 657system.cpu0.dcache.demand_accesses::cpu0.data 164074862 # number of demand (read+write) accesses 658system.cpu0.dcache.demand_accesses::total 164074862 # number of demand (read+write) accesses 659system.cpu0.dcache.overall_accesses::cpu0.data 165039187 # number of overall (read+write) accesses 660system.cpu0.dcache.overall_accesses::total 165039187 # number of overall (read+write) accesses 661system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.041105 # miss rate for ReadReq accesses 662system.cpu0.dcache.ReadReq_miss_rate::total 0.041105 # miss rate for ReadReq accesses 663system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.032126 # miss rate for WriteReq accesses 664system.cpu0.dcache.WriteReq_miss_rate::total 0.032126 # miss rate for WriteReq accesses 665system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.716519 # miss rate for SoftPFReq accesses 666system.cpu0.dcache.SoftPFReq_miss_rate::total 0.716519 # miss rate for SoftPFReq accesses 667system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.814330 # miss rate for WriteLineReq accesses 668system.cpu0.dcache.WriteLineReq_miss_rate::total 0.814330 # miss rate for WriteLineReq accesses 669system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.086282 # miss rate for LoadLockedReq accesses 670system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.086282 # miss rate for LoadLockedReq accesses 671system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.103183 # miss rate for StoreCondReq accesses 672system.cpu0.dcache.StoreCondReq_miss_rate::total 0.103183 # miss rate for StoreCondReq accesses 673system.cpu0.dcache.demand_miss_rate::cpu0.data 0.036878 # miss rate for demand accesses 674system.cpu0.dcache.demand_miss_rate::total 0.036878 # miss rate for demand accesses 675system.cpu0.dcache.overall_miss_rate::cpu0.data 0.040849 # miss rate for overall accesses 676system.cpu0.dcache.overall_miss_rate::total 0.040849 # miss rate for overall accesses 677system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 17634.295568 # average ReadReq miss latency 678system.cpu0.dcache.ReadReq_avg_miss_latency::total 17634.295568 # average ReadReq miss latency 679system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 25349.106567 # average WriteReq miss latency 680system.cpu0.dcache.WriteReq_avg_miss_latency::total 25349.106567 # average WriteReq miss latency 681system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 88449.551158 # average WriteLineReq miss latency 682system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 88449.551158 # average WriteLineReq miss latency 683system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16248.280858 # average LoadLockedReq miss latency 684system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16248.280858 # average LoadLockedReq miss latency 685system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 27787.387292 # average StoreCondReq miss latency 686system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 27787.387292 # average StoreCondReq miss latency 687system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency 688system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 689system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 20797.963754 # average overall miss latency 690system.cpu0.dcache.demand_avg_miss_latency::total 20797.963754 # average overall miss latency 691system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 18666.379301 # average overall miss latency 692system.cpu0.dcache.overall_avg_miss_latency::total 18666.379301 # average overall miss latency 693system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 694system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 695system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 696system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 697system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 698system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 699system.cpu0.dcache.fast_writes 0 # number of fast writes performed 700system.cpu0.dcache.cache_copies 0 # number of cache copies performed 701system.cpu0.dcache.writebacks::writebacks 5850286 # number of writebacks 702system.cpu0.dcache.writebacks::total 5850286 # number of writebacks 703system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 444097 # number of ReadReq MSHR hits 704system.cpu0.dcache.ReadReq_mshr_hits::total 444097 # number of ReadReq MSHR hits 705system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1026850 # number of WriteReq MSHR hits 706system.cpu0.dcache.WriteReq_mshr_hits::total 1026850 # number of WriteReq MSHR hits 707system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 104 # number of WriteLineReq MSHR hits 708system.cpu0.dcache.WriteLineReq_mshr_hits::total 104 # number of WriteLineReq MSHR hits 709system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 44524 # number of LoadLockedReq MSHR hits 710system.cpu0.dcache.LoadLockedReq_mshr_hits::total 44524 # number of LoadLockedReq MSHR hits 711system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data 32 # number of StoreCondReq MSHR hits 712system.cpu0.dcache.StoreCondReq_mshr_hits::total 32 # number of StoreCondReq MSHR hits 713system.cpu0.dcache.demand_mshr_hits::cpu0.data 1470947 # number of demand (read+write) MSHR hits 714system.cpu0.dcache.demand_mshr_hits::total 1470947 # number of demand (read+write) MSHR hits 715system.cpu0.dcache.overall_mshr_hits::cpu0.data 1470947 # number of overall MSHR hits 716system.cpu0.dcache.overall_mshr_hits::total 1470947 # number of overall MSHR hits 717system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3125373 # number of ReadReq MSHR misses 718system.cpu0.dcache.ReadReq_mshr_misses::total 3125373 # number of ReadReq MSHR misses 719system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1454421 # number of WriteReq MSHR misses 720system.cpu0.dcache.WriteReq_mshr_misses::total 1454421 # number of WriteReq MSHR misses 721system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 689314 # number of SoftPFReq MSHR misses 722system.cpu0.dcache.SoftPFReq_mshr_misses::total 689314 # number of SoftPFReq MSHR misses 723system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 805970 # number of WriteLineReq MSHR misses 724system.cpu0.dcache.WriteLineReq_mshr_misses::total 805970 # number of WriteLineReq MSHR misses 725system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 129400 # number of LoadLockedReq MSHR misses 726system.cpu0.dcache.LoadLockedReq_mshr_misses::total 129400 # number of LoadLockedReq MSHR misses 727system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 207806 # number of StoreCondReq MSHR misses 728system.cpu0.dcache.StoreCondReq_mshr_misses::total 207806 # number of StoreCondReq MSHR misses 729system.cpu0.dcache.demand_mshr_misses::cpu0.data 4579794 # number of demand (read+write) MSHR misses 730system.cpu0.dcache.demand_mshr_misses::total 4579794 # number of demand (read+write) MSHR misses 731system.cpu0.dcache.overall_mshr_misses::cpu0.data 5269108 # number of overall MSHR misses 732system.cpu0.dcache.overall_mshr_misses::total 5269108 # number of overall MSHR misses 733system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 19530 # number of ReadReq MSHR uncacheable 734system.cpu0.dcache.ReadReq_mshr_uncacheable::total 19530 # number of ReadReq MSHR uncacheable 735system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 21048 # number of WriteReq MSHR uncacheable 736system.cpu0.dcache.WriteReq_mshr_uncacheable::total 21048 # number of WriteReq MSHR uncacheable 737system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 40578 # number of overall MSHR uncacheable misses 738system.cpu0.dcache.overall_mshr_uncacheable_misses::total 40578 # number of overall MSHR uncacheable misses 739system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 49230560000 # number of ReadReq MSHR miss cycles 740system.cpu0.dcache.ReadReq_mshr_miss_latency::total 49230560000 # number of ReadReq MSHR miss cycles 741system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 36276054500 # number of WriteReq MSHR miss cycles 742system.cpu0.dcache.WriteReq_mshr_miss_latency::total 36276054500 # number of WriteReq MSHR miss cycles 743system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 18434925500 # number of SoftPFReq MSHR miss cycles 744system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 18434925500 # number of SoftPFReq MSHR miss cycles 745system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 70481228500 # number of WriteLineReq MSHR miss cycles 746system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 70481228500 # number of WriteLineReq MSHR miss cycles 747system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1893845500 # number of LoadLockedReq MSHR miss cycles 748system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1893845500 # number of LoadLockedReq MSHR miss cycles 749system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 5565229000 # number of StoreCondReq MSHR miss cycles 750system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 5565229000 # number of StoreCondReq MSHR miss cycles 751system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 4561000 # number of StoreCondFailReq MSHR miss cycles 752system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 4561000 # number of StoreCondFailReq MSHR miss cycles 753system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 85506614500 # number of demand (read+write) MSHR miss cycles 754system.cpu0.dcache.demand_mshr_miss_latency::total 85506614500 # number of demand (read+write) MSHR miss cycles 755system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 103941540000 # number of overall MSHR miss cycles 756system.cpu0.dcache.overall_mshr_miss_latency::total 103941540000 # number of overall MSHR miss cycles 757system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3800939500 # number of ReadReq MSHR uncacheable cycles 758system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 3800939500 # number of ReadReq MSHR uncacheable cycles 759system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 3971667500 # number of WriteReq MSHR uncacheable cycles 760system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 3971667500 # number of WriteReq MSHR uncacheable cycles 761system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 7772607000 # number of overall MSHR uncacheable cycles 762system.cpu0.dcache.overall_mshr_uncacheable_latency::total 7772607000 # number of overall MSHR uncacheable cycles 763system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.035991 # mshr miss rate for ReadReq accesses 764system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.035991 # mshr miss rate for ReadReq accesses 765system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018831 # mshr miss rate for WriteReq accesses 766system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018831 # mshr miss rate for WriteReq accesses 767system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.714815 # mshr miss rate for SoftPFReq accesses 768system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.714815 # mshr miss rate for SoftPFReq accesses 769system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.814225 # mshr miss rate for WriteLineReq accesses 770system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.814225 # mshr miss rate for WriteLineReq accesses 771system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.064194 # mshr miss rate for LoadLockedReq accesses 772system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.064194 # mshr miss rate for LoadLockedReq accesses 773system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.103167 # mshr miss rate for StoreCondReq accesses 774system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.103167 # mshr miss rate for StoreCondReq accesses 775system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027913 # mshr miss rate for demand accesses 776system.cpu0.dcache.demand_mshr_miss_rate::total 0.027913 # mshr miss rate for demand accesses 777system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.031926 # mshr miss rate for overall accesses 778system.cpu0.dcache.overall_mshr_miss_rate::total 0.031926 # mshr miss rate for overall accesses 779system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15751.899053 # average ReadReq mshr miss latency 780system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15751.899053 # average ReadReq mshr miss latency 781system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 24941.921562 # average WriteReq mshr miss latency 782system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 24941.921562 # average WriteReq mshr miss latency 783system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 26743.872169 # average SoftPFReq mshr miss latency 784system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 26743.872169 # average SoftPFReq mshr miss latency 785system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 87448.947852 # average WriteLineReq mshr miss latency 786system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 87448.947852 # average WriteLineReq mshr miss latency 787system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14635.591190 # average LoadLockedReq mshr miss latency 788system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14635.591190 # average LoadLockedReq mshr miss latency 789system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 26780.886981 # average StoreCondReq mshr miss latency 790system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 26780.886981 # average StoreCondReq mshr miss latency 791system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 792system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 793system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18670.406245 # average overall mshr miss latency 794system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18670.406245 # average overall mshr miss latency 795system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19726.591294 # average overall mshr miss latency 796system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19726.591294 # average overall mshr miss latency 797system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 194620.558116 # average ReadReq mshr uncacheable latency 798system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 194620.558116 # average ReadReq mshr uncacheable latency 799system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 188695.719308 # average WriteReq mshr uncacheable latency 800system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 188695.719308 # average WriteReq mshr uncacheable latency 801system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 191547.316280 # average overall mshr uncacheable latency 802system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 191547.316280 # average overall mshr uncacheable latency 803system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 804system.cpu0.icache.tags.replacements 9594128 # number of replacements 805system.cpu0.icache.tags.tagsinuse 511.890921 # Cycle average of tags in use 806system.cpu0.icache.tags.total_refs 242861120 # Total number of references to valid blocks. 807system.cpu0.icache.tags.sampled_refs 9594640 # Sample count of references to valid blocks. 808system.cpu0.icache.tags.avg_refs 25.312166 # Average number of references to valid blocks. 809system.cpu0.icache.tags.warmup_cycle 40343615000 # Cycle when the warmup percentage was hit. 810system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.890921 # Average occupied blocks per requestor 811system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999787 # Average percentage of cache occupancy 812system.cpu0.icache.tags.occ_percent::total 0.999787 # Average percentage of cache occupancy 813system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 814system.cpu0.icache.tags.age_task_id_blocks_1024::0 74 # Occupied blocks per task id 815system.cpu0.icache.tags.age_task_id_blocks_1024::1 191 # Occupied blocks per task id 816system.cpu0.icache.tags.age_task_id_blocks_1024::2 247 # Occupied blocks per task id 817system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 818system.cpu0.icache.tags.tag_accesses 514506190 # Number of tag accesses 819system.cpu0.icache.tags.data_accesses 514506190 # Number of data accesses 820system.cpu0.icache.ReadReq_hits::cpu0.inst 242861120 # number of ReadReq hits 821system.cpu0.icache.ReadReq_hits::total 242861120 # number of ReadReq hits 822system.cpu0.icache.demand_hits::cpu0.inst 242861120 # number of demand (read+write) hits 823system.cpu0.icache.demand_hits::total 242861120 # number of demand (read+write) hits 824system.cpu0.icache.overall_hits::cpu0.inst 242861120 # number of overall hits 825system.cpu0.icache.overall_hits::total 242861120 # number of overall hits 826system.cpu0.icache.ReadReq_misses::cpu0.inst 9594650 # number of ReadReq misses 827system.cpu0.icache.ReadReq_misses::total 9594650 # number of ReadReq misses 828system.cpu0.icache.demand_misses::cpu0.inst 9594650 # number of demand (read+write) misses 829system.cpu0.icache.demand_misses::total 9594650 # number of demand (read+write) misses 830system.cpu0.icache.overall_misses::cpu0.inst 9594650 # number of overall misses 831system.cpu0.icache.overall_misses::total 9594650 # number of overall misses 832system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 102613134000 # number of ReadReq miss cycles 833system.cpu0.icache.ReadReq_miss_latency::total 102613134000 # number of ReadReq miss cycles 834system.cpu0.icache.demand_miss_latency::cpu0.inst 102613134000 # number of demand (read+write) miss cycles 835system.cpu0.icache.demand_miss_latency::total 102613134000 # number of demand (read+write) miss cycles 836system.cpu0.icache.overall_miss_latency::cpu0.inst 102613134000 # number of overall miss cycles 837system.cpu0.icache.overall_miss_latency::total 102613134000 # number of overall miss cycles 838system.cpu0.icache.ReadReq_accesses::cpu0.inst 252455770 # number of ReadReq accesses(hits+misses) 839system.cpu0.icache.ReadReq_accesses::total 252455770 # number of ReadReq accesses(hits+misses) 840system.cpu0.icache.demand_accesses::cpu0.inst 252455770 # number of demand (read+write) accesses 841system.cpu0.icache.demand_accesses::total 252455770 # number of demand (read+write) accesses 842system.cpu0.icache.overall_accesses::cpu0.inst 252455770 # number of overall (read+write) accesses 843system.cpu0.icache.overall_accesses::total 252455770 # number of overall (read+write) accesses 844system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.038005 # miss rate for ReadReq accesses 845system.cpu0.icache.ReadReq_miss_rate::total 0.038005 # miss rate for ReadReq accesses 846system.cpu0.icache.demand_miss_rate::cpu0.inst 0.038005 # miss rate for demand accesses 847system.cpu0.icache.demand_miss_rate::total 0.038005 # miss rate for demand accesses 848system.cpu0.icache.overall_miss_rate::cpu0.inst 0.038005 # miss rate for overall accesses 849system.cpu0.icache.overall_miss_rate::total 0.038005 # miss rate for overall accesses 850system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10694.828264 # average ReadReq miss latency 851system.cpu0.icache.ReadReq_avg_miss_latency::total 10694.828264 # average ReadReq miss latency 852system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10694.828264 # average overall miss latency 853system.cpu0.icache.demand_avg_miss_latency::total 10694.828264 # average overall miss latency 854system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10694.828264 # average overall miss latency 855system.cpu0.icache.overall_avg_miss_latency::total 10694.828264 # average overall miss latency 856system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 857system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 858system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 859system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 860system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 861system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 862system.cpu0.icache.fast_writes 0 # number of fast writes performed 863system.cpu0.icache.cache_copies 0 # number of cache copies performed 864system.cpu0.icache.writebacks::writebacks 9594128 # number of writebacks 865system.cpu0.icache.writebacks::total 9594128 # number of writebacks 866system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 9594650 # number of ReadReq MSHR misses 867system.cpu0.icache.ReadReq_mshr_misses::total 9594650 # number of ReadReq MSHR misses 868system.cpu0.icache.demand_mshr_misses::cpu0.inst 9594650 # number of demand (read+write) MSHR misses 869system.cpu0.icache.demand_mshr_misses::total 9594650 # number of demand (read+write) MSHR misses 870system.cpu0.icache.overall_mshr_misses::cpu0.inst 9594650 # number of overall MSHR misses 871system.cpu0.icache.overall_mshr_misses::total 9594650 # number of overall MSHR misses 872system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 52309 # number of ReadReq MSHR uncacheable 873system.cpu0.icache.ReadReq_mshr_uncacheable::total 52309 # number of ReadReq MSHR uncacheable 874system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 52309 # number of overall MSHR uncacheable misses 875system.cpu0.icache.overall_mshr_uncacheable_misses::total 52309 # number of overall MSHR uncacheable misses 876system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 97815809000 # number of ReadReq MSHR miss cycles 877system.cpu0.icache.ReadReq_mshr_miss_latency::total 97815809000 # number of ReadReq MSHR miss cycles 878system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 97815809000 # number of demand (read+write) MSHR miss cycles 879system.cpu0.icache.demand_mshr_miss_latency::total 97815809000 # number of demand (read+write) MSHR miss cycles 880system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 97815809000 # number of overall MSHR miss cycles 881system.cpu0.icache.overall_mshr_miss_latency::total 97815809000 # number of overall MSHR miss cycles 882system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 7414627000 # number of ReadReq MSHR uncacheable cycles 883system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 7414627000 # number of ReadReq MSHR uncacheable cycles 884system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 7414627000 # number of overall MSHR uncacheable cycles 885system.cpu0.icache.overall_mshr_uncacheable_latency::total 7414627000 # number of overall MSHR uncacheable cycles 886system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.038005 # mshr miss rate for ReadReq accesses 887system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.038005 # mshr miss rate for ReadReq accesses 888system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.038005 # mshr miss rate for demand accesses 889system.cpu0.icache.demand_mshr_miss_rate::total 0.038005 # mshr miss rate for demand accesses 890system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.038005 # mshr miss rate for overall accesses 891system.cpu0.icache.overall_mshr_miss_rate::total 0.038005 # mshr miss rate for overall accesses 892system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10194.828264 # average ReadReq mshr miss latency 893system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10194.828264 # average ReadReq mshr miss latency 894system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10194.828264 # average overall mshr miss latency 895system.cpu0.icache.demand_avg_mshr_miss_latency::total 10194.828264 # average overall mshr miss latency 896system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10194.828264 # average overall mshr miss latency 897system.cpu0.icache.overall_avg_mshr_miss_latency::total 10194.828264 # average overall mshr miss latency 898system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 141746.678392 # average ReadReq mshr uncacheable latency 899system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 141746.678392 # average ReadReq mshr uncacheable latency 900system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 141746.678392 # average overall mshr uncacheable latency 901system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 141746.678392 # average overall mshr uncacheable latency 902system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 903system.cpu0.l2cache.prefetcher.num_hwpf_issued 8065650 # number of hwpf issued 904system.cpu0.l2cache.prefetcher.pfIdentified 8066797 # number of prefetch candidates identified 905system.cpu0.l2cache.prefetcher.pfBufferHit 1004 # number of redundant prefetches already in prefetch queue 906system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 907system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 908system.cpu0.l2cache.prefetcher.pfSpanPage 1049003 # number of prefetches not generated due to page crossing 909system.cpu0.l2cache.tags.replacements 2949800 # number of replacements 910system.cpu0.l2cache.tags.tagsinuse 16165.081558 # Cycle average of tags in use 911system.cpu0.l2cache.tags.total_refs 23810069 # Total number of references to valid blocks. 912system.cpu0.l2cache.tags.sampled_refs 2965603 # Sample count of references to valid blocks. 913system.cpu0.l2cache.tags.avg_refs 8.028745 # Average number of references to valid blocks. 914system.cpu0.l2cache.tags.warmup_cycle 9049945000 # Cycle when the warmup percentage was hit. 915system.cpu0.l2cache.tags.occ_blocks::writebacks 15191.178363 # Average occupied blocks per requestor 916system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 63.510017 # Average occupied blocks per requestor 917system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 64.560721 # Average occupied blocks per requestor 918system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 845.832457 # Average occupied blocks per requestor 919system.cpu0.l2cache.tags.occ_percent::writebacks 0.927196 # Average percentage of cache occupancy 920system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003876 # Average percentage of cache occupancy 921system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.003940 # Average percentage of cache occupancy 922system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.051626 # Average percentage of cache occupancy 923system.cpu0.l2cache.tags.occ_percent::total 0.986638 # Average percentage of cache occupancy 924system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1186 # Occupied blocks per task id 925system.cpu0.l2cache.tags.occ_task_id_blocks::1023 68 # Occupied blocks per task id 926system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14549 # Occupied blocks per task id 927system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 43 # Occupied blocks per task id 928system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 162 # Occupied blocks per task id 929system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 909 # Occupied blocks per task id 930system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 72 # Occupied blocks per task id 931system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id 932system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 45 # Occupied blocks per task id 933system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 19 # Occupied blocks per task id 934system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 3 # Occupied blocks per task id 935system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 130 # Occupied blocks per task id 936system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 878 # Occupied blocks per task id 937system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5504 # Occupied blocks per task id 938system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7511 # Occupied blocks per task id 939system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 526 # Occupied blocks per task id 940system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.072388 # Percentage of cache occupancy per task id 941system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.004150 # Percentage of cache occupancy per task id 942system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.888000 # Percentage of cache occupancy per task id 943system.cpu0.l2cache.tags.tag_accesses 520895158 # Number of tag accesses 944system.cpu0.l2cache.tags.data_accesses 520895158 # Number of data accesses 945system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 527427 # number of ReadReq hits 946system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 170829 # number of ReadReq hits 947system.cpu0.l2cache.ReadReq_hits::total 698256 # number of ReadReq hits 948system.cpu0.l2cache.WritebackDirty_hits::writebacks 3866912 # number of WritebackDirty hits 949system.cpu0.l2cache.WritebackDirty_hits::total 3866912 # number of WritebackDirty hits 950system.cpu0.l2cache.WritebackClean_hits::writebacks 11575004 # number of WritebackClean hits 951system.cpu0.l2cache.WritebackClean_hits::total 11575004 # number of WritebackClean hits 952system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 494 # number of UpgradeReq hits 953system.cpu0.l2cache.UpgradeReq_hits::total 494 # number of UpgradeReq hits 954system.cpu0.l2cache.ReadExReq_hits::cpu0.data 901398 # number of ReadExReq hits 955system.cpu0.l2cache.ReadExReq_hits::total 901398 # number of ReadExReq hits 956system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 8819397 # number of ReadCleanReq hits 957system.cpu0.l2cache.ReadCleanReq_hits::total 8819397 # number of ReadCleanReq hits 958system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 2877090 # number of ReadSharedReq hits 959system.cpu0.l2cache.ReadSharedReq_hits::total 2877090 # number of ReadSharedReq hits 960system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 196747 # number of InvalidateReq hits 961system.cpu0.l2cache.InvalidateReq_hits::total 196747 # number of InvalidateReq hits 962system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 527427 # number of demand (read+write) hits 963system.cpu0.l2cache.demand_hits::cpu0.itb.walker 170829 # number of demand (read+write) hits 964system.cpu0.l2cache.demand_hits::cpu0.inst 8819397 # number of demand (read+write) hits 965system.cpu0.l2cache.demand_hits::cpu0.data 3778488 # number of demand (read+write) hits 966system.cpu0.l2cache.demand_hits::total 13296141 # number of demand (read+write) hits 967system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 527427 # number of overall hits 968system.cpu0.l2cache.overall_hits::cpu0.itb.walker 170829 # number of overall hits 969system.cpu0.l2cache.overall_hits::cpu0.inst 8819397 # number of overall hits 970system.cpu0.l2cache.overall_hits::cpu0.data 3778488 # number of overall hits 971system.cpu0.l2cache.overall_hits::total 13296141 # number of overall hits 972system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 12512 # number of ReadReq misses 973system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 8836 # number of ReadReq misses 974system.cpu0.l2cache.ReadReq_misses::total 21348 # number of ReadReq misses 975system.cpu0.l2cache.WritebackDirty_misses::writebacks 2 # number of WritebackDirty misses 976system.cpu0.l2cache.WritebackDirty_misses::total 2 # number of WritebackDirty misses 977system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 265863 # number of UpgradeReq misses 978system.cpu0.l2cache.UpgradeReq_misses::total 265863 # number of UpgradeReq misses 979system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 207797 # number of SCUpgradeReq misses 980system.cpu0.l2cache.SCUpgradeReq_misses::total 207797 # number of SCUpgradeReq misses 981system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 9 # number of SCUpgradeFailReq misses 982system.cpu0.l2cache.SCUpgradeFailReq_misses::total 9 # number of SCUpgradeFailReq misses 983system.cpu0.l2cache.ReadExReq_misses::cpu0.data 295222 # number of ReadExReq misses 984system.cpu0.l2cache.ReadExReq_misses::total 295222 # number of ReadExReq misses 985system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 775252 # number of ReadCleanReq misses 986system.cpu0.l2cache.ReadCleanReq_misses::total 775252 # number of ReadCleanReq misses 987system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 1066801 # number of ReadSharedReq misses 988system.cpu0.l2cache.ReadSharedReq_misses::total 1066801 # number of ReadSharedReq misses 989system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 607029 # number of InvalidateReq misses 990system.cpu0.l2cache.InvalidateReq_misses::total 607029 # number of InvalidateReq misses 991system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 12512 # number of demand (read+write) misses 992system.cpu0.l2cache.demand_misses::cpu0.itb.walker 8836 # number of demand (read+write) misses 993system.cpu0.l2cache.demand_misses::cpu0.inst 775252 # number of demand (read+write) misses 994system.cpu0.l2cache.demand_misses::cpu0.data 1362023 # number of demand (read+write) misses 995system.cpu0.l2cache.demand_misses::total 2158623 # number of demand (read+write) misses 996system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 12512 # number of overall misses 997system.cpu0.l2cache.overall_misses::cpu0.itb.walker 8836 # number of overall misses 998system.cpu0.l2cache.overall_misses::cpu0.inst 775252 # number of overall misses 999system.cpu0.l2cache.overall_misses::cpu0.data 1362023 # number of overall misses 1000system.cpu0.l2cache.overall_misses::total 2158623 # number of overall misses 1001system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 555558000 # number of ReadReq miss cycles 1002system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 430868000 # number of ReadReq miss cycles 1003system.cpu0.l2cache.ReadReq_miss_latency::total 986426000 # number of ReadReq miss cycles 1004system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 3493305000 # number of UpgradeReq miss cycles 1005system.cpu0.l2cache.UpgradeReq_miss_latency::total 3493305000 # number of UpgradeReq miss cycles 1006system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 1939943000 # number of SCUpgradeReq miss cycles 1007system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 1939943000 # number of SCUpgradeReq miss cycles 1008system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 4477498 # number of SCUpgradeFailReq miss cycles 1009system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 4477498 # number of SCUpgradeFailReq miss cycles 1010system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 18708847499 # number of ReadExReq miss cycles 1011system.cpu0.l2cache.ReadExReq_miss_latency::total 18708847499 # number of ReadExReq miss cycles 1012system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 30179302500 # number of ReadCleanReq miss cycles 1013system.cpu0.l2cache.ReadCleanReq_miss_latency::total 30179302500 # number of ReadCleanReq miss cycles 1014system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 44632390995 # number of ReadSharedReq miss cycles 1015system.cpu0.l2cache.ReadSharedReq_miss_latency::total 44632390995 # number of ReadSharedReq miss cycles 1016system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data 67815733000 # number of InvalidateReq miss cycles 1017system.cpu0.l2cache.InvalidateReq_miss_latency::total 67815733000 # number of InvalidateReq miss cycles 1018system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 555558000 # number of demand (read+write) miss cycles 1019system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 430868000 # number of demand (read+write) miss cycles 1020system.cpu0.l2cache.demand_miss_latency::cpu0.inst 30179302500 # number of demand (read+write) miss cycles 1021system.cpu0.l2cache.demand_miss_latency::cpu0.data 63341238494 # number of demand (read+write) miss cycles 1022system.cpu0.l2cache.demand_miss_latency::total 94506966994 # number of demand (read+write) miss cycles 1023system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 555558000 # number of overall miss cycles 1024system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 430868000 # number of overall miss cycles 1025system.cpu0.l2cache.overall_miss_latency::cpu0.inst 30179302500 # number of overall miss cycles 1026system.cpu0.l2cache.overall_miss_latency::cpu0.data 63341238494 # number of overall miss cycles 1027system.cpu0.l2cache.overall_miss_latency::total 94506966994 # number of overall miss cycles 1028system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 539939 # number of ReadReq accesses(hits+misses) 1029system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 179665 # number of ReadReq accesses(hits+misses) 1030system.cpu0.l2cache.ReadReq_accesses::total 719604 # number of ReadReq accesses(hits+misses) 1031system.cpu0.l2cache.WritebackDirty_accesses::writebacks 3866914 # number of WritebackDirty accesses(hits+misses) 1032system.cpu0.l2cache.WritebackDirty_accesses::total 3866914 # number of WritebackDirty accesses(hits+misses) 1033system.cpu0.l2cache.WritebackClean_accesses::writebacks 11575004 # number of WritebackClean accesses(hits+misses) 1034system.cpu0.l2cache.WritebackClean_accesses::total 11575004 # number of WritebackClean accesses(hits+misses) 1035system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 266357 # number of UpgradeReq accesses(hits+misses) 1036system.cpu0.l2cache.UpgradeReq_accesses::total 266357 # number of UpgradeReq accesses(hits+misses) 1037system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 207797 # number of SCUpgradeReq accesses(hits+misses) 1038system.cpu0.l2cache.SCUpgradeReq_accesses::total 207797 # number of SCUpgradeReq accesses(hits+misses) 1039system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 9 # number of SCUpgradeFailReq accesses(hits+misses) 1040system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 9 # number of SCUpgradeFailReq accesses(hits+misses) 1041system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1196620 # number of ReadExReq accesses(hits+misses) 1042system.cpu0.l2cache.ReadExReq_accesses::total 1196620 # number of ReadExReq accesses(hits+misses) 1043system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 9594649 # number of ReadCleanReq accesses(hits+misses) 1044system.cpu0.l2cache.ReadCleanReq_accesses::total 9594649 # number of ReadCleanReq accesses(hits+misses) 1045system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 3943891 # number of ReadSharedReq accesses(hits+misses) 1046system.cpu0.l2cache.ReadSharedReq_accesses::total 3943891 # number of ReadSharedReq accesses(hits+misses) 1047system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 803776 # number of InvalidateReq accesses(hits+misses) 1048system.cpu0.l2cache.InvalidateReq_accesses::total 803776 # number of InvalidateReq accesses(hits+misses) 1049system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 539939 # number of demand (read+write) accesses 1050system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 179665 # number of demand (read+write) accesses 1051system.cpu0.l2cache.demand_accesses::cpu0.inst 9594649 # number of demand (read+write) accesses 1052system.cpu0.l2cache.demand_accesses::cpu0.data 5140511 # number of demand (read+write) accesses 1053system.cpu0.l2cache.demand_accesses::total 15454764 # number of demand (read+write) accesses 1054system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 539939 # number of overall (read+write) accesses 1055system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 179665 # number of overall (read+write) accesses 1056system.cpu0.l2cache.overall_accesses::cpu0.inst 9594649 # number of overall (read+write) accesses 1057system.cpu0.l2cache.overall_accesses::cpu0.data 5140511 # number of overall (read+write) accesses 1058system.cpu0.l2cache.overall_accesses::total 15454764 # number of overall (read+write) accesses 1059system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.023173 # miss rate for ReadReq accesses 1060system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.049180 # miss rate for ReadReq accesses 1061system.cpu0.l2cache.ReadReq_miss_rate::total 0.029666 # miss rate for ReadReq accesses 1062system.cpu0.l2cache.WritebackDirty_miss_rate::writebacks 0.000001 # miss rate for WritebackDirty accesses 1063system.cpu0.l2cache.WritebackDirty_miss_rate::total 0.000001 # miss rate for WritebackDirty accesses 1064system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.998145 # miss rate for UpgradeReq accesses 1065system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.998145 # miss rate for UpgradeReq accesses 1066system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses 1067system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 1068system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses 1069system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 1070system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.246713 # miss rate for ReadExReq accesses 1071system.cpu0.l2cache.ReadExReq_miss_rate::total 0.246713 # miss rate for ReadExReq accesses 1072system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.080800 # miss rate for ReadCleanReq accesses 1073system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.080800 # miss rate for ReadCleanReq accesses 1074system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.270495 # miss rate for ReadSharedReq accesses 1075system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.270495 # miss rate for ReadSharedReq accesses 1076system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.755222 # miss rate for InvalidateReq accesses 1077system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.755222 # miss rate for InvalidateReq accesses 1078system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.023173 # miss rate for demand accesses 1079system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.049180 # miss rate for demand accesses 1080system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.080800 # miss rate for demand accesses 1081system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.264959 # miss rate for demand accesses 1082system.cpu0.l2cache.demand_miss_rate::total 0.139674 # miss rate for demand accesses 1083system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.023173 # miss rate for overall accesses 1084system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.049180 # miss rate for overall accesses 1085system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.080800 # miss rate for overall accesses 1086system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.264959 # miss rate for overall accesses 1087system.cpu0.l2cache.overall_miss_rate::total 0.139674 # miss rate for overall accesses 1088system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 44402.014066 # average ReadReq miss latency 1089system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 48762.788592 # average ReadReq miss latency 1090system.cpu0.l2cache.ReadReq_avg_miss_latency::total 46206.951471 # average ReadReq miss latency 1091system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 13139.492897 # average UpgradeReq miss latency 1092system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 13139.492897 # average UpgradeReq miss latency 1093system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 9335.760382 # average SCUpgradeReq miss latency 1094system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 9335.760382 # average SCUpgradeReq miss latency 1095system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 497499.777778 # average SCUpgradeFailReq miss latency 1096system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 497499.777778 # average SCUpgradeFailReq miss latency 1097system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 63372.131816 # average ReadExReq miss latency 1098system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 63372.131816 # average ReadExReq miss latency 1099system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 38928.377482 # average ReadCleanReq miss latency 1100system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 38928.377482 # average ReadCleanReq miss latency 1101system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 41837.597635 # average ReadSharedReq miss latency 1102system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 41837.597635 # average ReadSharedReq miss latency 1103system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 111717.451720 # average InvalidateReq miss latency 1104system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 111717.451720 # average InvalidateReq miss latency 1105system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 44402.014066 # average overall miss latency 1106system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 48762.788592 # average overall miss latency 1107system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 38928.377482 # average overall miss latency 1108system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 46505.263490 # average overall miss latency 1109system.cpu0.l2cache.demand_avg_miss_latency::total 43781.135934 # average overall miss latency 1110system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 44402.014066 # average overall miss latency 1111system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 48762.788592 # average overall miss latency 1112system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 38928.377482 # average overall miss latency 1113system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 46505.263490 # average overall miss latency 1114system.cpu0.l2cache.overall_avg_miss_latency::total 43781.135934 # average overall miss latency 1115system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1116system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1117system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1118system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1119system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1120system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1121system.cpu0.l2cache.fast_writes 0 # number of fast writes performed 1122system.cpu0.l2cache.cache_copies 0 # number of cache copies performed 1123system.cpu0.l2cache.writebacks::writebacks 1702054 # number of writebacks 1124system.cpu0.l2cache.writebacks::total 1702054 # number of writebacks 1125system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker 1 # number of ReadReq MSHR hits 1126system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 3 # number of ReadReq MSHR hits 1127system.cpu0.l2cache.ReadReq_mshr_hits::total 4 # number of ReadReq MSHR hits 1128system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 8173 # number of ReadExReq MSHR hits 1129system.cpu0.l2cache.ReadExReq_mshr_hits::total 8173 # number of ReadExReq MSHR hits 1130system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 11 # number of ReadCleanReq MSHR hits 1131system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 11 # number of ReadCleanReq MSHR hits 1132system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 1611 # number of ReadSharedReq MSHR hits 1133system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 1611 # number of ReadSharedReq MSHR hits 1134system.cpu0.l2cache.InvalidateReq_mshr_hits::cpu0.data 4 # number of InvalidateReq MSHR hits 1135system.cpu0.l2cache.InvalidateReq_mshr_hits::total 4 # number of InvalidateReq MSHR hits 1136system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker 1 # number of demand (read+write) MSHR hits 1137system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 3 # number of demand (read+write) MSHR hits 1138system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 11 # number of demand (read+write) MSHR hits 1139system.cpu0.l2cache.demand_mshr_hits::cpu0.data 9784 # number of demand (read+write) MSHR hits 1140system.cpu0.l2cache.demand_mshr_hits::total 9799 # number of demand (read+write) MSHR hits 1141system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker 1 # number of overall MSHR hits 1142system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 3 # number of overall MSHR hits 1143system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 11 # number of overall MSHR hits 1144system.cpu0.l2cache.overall_mshr_hits::cpu0.data 9784 # number of overall MSHR hits 1145system.cpu0.l2cache.overall_mshr_hits::total 9799 # number of overall MSHR hits 1146system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 12511 # number of ReadReq MSHR misses 1147system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 8833 # number of ReadReq MSHR misses 1148system.cpu0.l2cache.ReadReq_mshr_misses::total 21344 # number of ReadReq MSHR misses 1149system.cpu0.l2cache.WritebackDirty_mshr_misses::writebacks 2 # number of WritebackDirty MSHR misses 1150system.cpu0.l2cache.WritebackDirty_mshr_misses::total 2 # number of WritebackDirty MSHR misses 1151system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 812970 # number of HardPFReq MSHR misses 1152system.cpu0.l2cache.HardPFReq_mshr_misses::total 812970 # number of HardPFReq MSHR misses 1153system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 265863 # number of UpgradeReq MSHR misses 1154system.cpu0.l2cache.UpgradeReq_mshr_misses::total 265863 # number of UpgradeReq MSHR misses 1155system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 207797 # number of SCUpgradeReq MSHR misses 1156system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 207797 # number of SCUpgradeReq MSHR misses 1157system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 9 # number of SCUpgradeFailReq MSHR misses 1158system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 9 # number of SCUpgradeFailReq MSHR misses 1159system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 287049 # number of ReadExReq MSHR misses 1160system.cpu0.l2cache.ReadExReq_mshr_misses::total 287049 # number of ReadExReq MSHR misses 1161system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 775241 # number of ReadCleanReq MSHR misses 1162system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 775241 # number of ReadCleanReq MSHR misses 1163system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 1065190 # number of ReadSharedReq MSHR misses 1164system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 1065190 # number of ReadSharedReq MSHR misses 1165system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data 607025 # number of InvalidateReq MSHR misses 1166system.cpu0.l2cache.InvalidateReq_mshr_misses::total 607025 # number of InvalidateReq MSHR misses 1167system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 12511 # number of demand (read+write) MSHR misses 1168system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 8833 # number of demand (read+write) MSHR misses 1169system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 775241 # number of demand (read+write) MSHR misses 1170system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1352239 # number of demand (read+write) MSHR misses 1171system.cpu0.l2cache.demand_mshr_misses::total 2148824 # number of demand (read+write) MSHR misses 1172system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 12511 # number of overall MSHR misses 1173system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 8833 # number of overall MSHR misses 1174system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 775241 # number of overall MSHR misses 1175system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1352239 # number of overall MSHR misses 1176system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 812970 # number of overall MSHR misses 1177system.cpu0.l2cache.overall_mshr_misses::total 2961794 # number of overall MSHR misses 1178system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 52309 # number of ReadReq MSHR uncacheable 1179system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 19530 # number of ReadReq MSHR uncacheable 1180system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 71839 # number of ReadReq MSHR uncacheable 1181system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 21048 # number of WriteReq MSHR uncacheable 1182system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 21048 # number of WriteReq MSHR uncacheable 1183system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 52309 # number of overall MSHR uncacheable misses 1184system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 40578 # number of overall MSHR uncacheable misses 1185system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 92887 # number of overall MSHR uncacheable misses 1186system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 480468000 # number of ReadReq MSHR miss cycles 1187system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 377798500 # number of ReadReq MSHR miss cycles 1188system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 858266500 # number of ReadReq MSHR miss cycles 1189system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 44849426201 # number of HardPFReq MSHR miss cycles 1190system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 44849426201 # number of HardPFReq MSHR miss cycles 1191system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 7795522498 # number of UpgradeReq MSHR miss cycles 1192system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 7795522498 # number of UpgradeReq MSHR miss cycles 1193system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 4002040000 # number of SCUpgradeReq MSHR miss cycles 1194system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 4002040000 # number of SCUpgradeReq MSHR miss cycles 1195system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 4147498 # number of SCUpgradeFailReq MSHR miss cycles 1196system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 4147498 # number of SCUpgradeFailReq MSHR miss cycles 1197system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 15893166999 # number of ReadExReq MSHR miss cycles 1198system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 15893166999 # number of ReadExReq MSHR miss cycles 1199system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 25527386000 # number of ReadCleanReq MSHR miss cycles 1200system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 25527386000 # number of ReadCleanReq MSHR miss cycles 1201system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 38109816995 # number of ReadSharedReq MSHR miss cycles 1202system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 38109816995 # number of ReadSharedReq MSHR miss cycles 1203system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 64173364000 # number of InvalidateReq MSHR miss cycles 1204system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 64173364000 # number of InvalidateReq MSHR miss cycles 1205system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 480468000 # number of demand (read+write) MSHR miss cycles 1206system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 377798500 # number of demand (read+write) MSHR miss cycles 1207system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 25527386000 # number of demand (read+write) MSHR miss cycles 1208system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 54002983994 # number of demand (read+write) MSHR miss cycles 1209system.cpu0.l2cache.demand_mshr_miss_latency::total 80388636494 # number of demand (read+write) MSHR miss cycles 1210system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 480468000 # number of overall MSHR miss cycles 1211system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 377798500 # number of overall MSHR miss cycles 1212system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 25527386000 # number of overall MSHR miss cycles 1213system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 54002983994 # number of overall MSHR miss cycles 1214system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 44849426201 # number of overall MSHR miss cycles 1215system.cpu0.l2cache.overall_mshr_miss_latency::total 125238062695 # number of overall MSHR miss cycles 1216system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 6996155000 # number of ReadReq MSHR uncacheable cycles 1217system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 3644540000 # number of ReadReq MSHR uncacheable cycles 1218system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 10640695000 # number of ReadReq MSHR uncacheable cycles 1219system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 3813756000 # number of WriteReq MSHR uncacheable cycles 1220system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 3813756000 # number of WriteReq MSHR uncacheable cycles 1221system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 6996155000 # number of overall MSHR uncacheable cycles 1222system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 7458296000 # number of overall MSHR uncacheable cycles 1223system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 14454451000 # number of overall MSHR uncacheable cycles 1224system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.023171 # mshr miss rate for ReadReq accesses 1225system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.049164 # mshr miss rate for ReadReq accesses 1226system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.029661 # mshr miss rate for ReadReq accesses 1227system.cpu0.l2cache.WritebackDirty_mshr_miss_rate::writebacks 0.000001 # mshr miss rate for WritebackDirty accesses 1228system.cpu0.l2cache.WritebackDirty_mshr_miss_rate::total 0.000001 # mshr miss rate for WritebackDirty accesses 1229system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1230system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 1231system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.998145 # mshr miss rate for UpgradeReq accesses 1232system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.998145 # mshr miss rate for UpgradeReq accesses 1233system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses 1234system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 1235system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses 1236system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 1237system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.239883 # mshr miss rate for ReadExReq accesses 1238system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.239883 # mshr miss rate for ReadExReq accesses 1239system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.080799 # mshr miss rate for ReadCleanReq accesses 1240system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.080799 # mshr miss rate for ReadCleanReq accesses 1241system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.270086 # mshr miss rate for ReadSharedReq accesses 1242system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.270086 # mshr miss rate for ReadSharedReq accesses 1243system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.755217 # mshr miss rate for InvalidateReq accesses 1244system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.755217 # mshr miss rate for InvalidateReq accesses 1245system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.023171 # mshr miss rate for demand accesses 1246system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.049164 # mshr miss rate for demand accesses 1247system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.080799 # mshr miss rate for demand accesses 1248system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.263055 # mshr miss rate for demand accesses 1249system.cpu0.l2cache.demand_mshr_miss_rate::total 0.139040 # mshr miss rate for demand accesses 1250system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.023171 # mshr miss rate for overall accesses 1251system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.049164 # mshr miss rate for overall accesses 1252system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.080799 # mshr miss rate for overall accesses 1253system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.263055 # mshr miss rate for overall accesses 1254system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses 1255system.cpu0.l2cache.overall_mshr_miss_rate::total 0.191643 # mshr miss rate for overall accesses 1256system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 38403.644793 # average ReadReq mshr miss latency 1257system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 42771.255519 # average ReadReq mshr miss latency 1258system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 40211.136619 # average ReadReq mshr miss latency 1259system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 55167.381577 # average HardPFReq mshr miss latency 1260system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 55167.381577 # average HardPFReq mshr miss latency 1261system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 29321.577271 # average UpgradeReq mshr miss latency 1262system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 29321.577271 # average UpgradeReq mshr miss latency 1263system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 19259.373331 # average SCUpgradeReq mshr miss latency 1264system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19259.373331 # average SCUpgradeReq mshr miss latency 1265system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 460833.111111 # average SCUpgradeFailReq mshr miss latency 1266system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 460833.111111 # average SCUpgradeFailReq mshr miss latency 1267system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 55367.435521 # average ReadExReq mshr miss latency 1268system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 55367.435521 # average ReadExReq mshr miss latency 1269system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 32928.322934 # average ReadCleanReq mshr miss latency 1270system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 32928.322934 # average ReadCleanReq mshr miss latency 1271system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 35777.482886 # average ReadSharedReq mshr miss latency 1272system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 35777.482886 # average ReadSharedReq mshr miss latency 1273system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 105717.827108 # average InvalidateReq mshr miss latency 1274system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 105717.827108 # average InvalidateReq mshr miss latency 1275system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 38403.644793 # average overall mshr miss latency 1276system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 42771.255519 # average overall mshr miss latency 1277system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 32928.322934 # average overall mshr miss latency 1278system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 39935.975810 # average overall mshr miss latency 1279system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 37410.526173 # average overall mshr miss latency 1280system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 38403.644793 # average overall mshr miss latency 1281system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 42771.255519 # average overall mshr miss latency 1282system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 32928.322934 # average overall mshr miss latency 1283system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 39935.975810 # average overall mshr miss latency 1284system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 55167.381577 # average overall mshr miss latency 1285system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 42284.528463 # average overall mshr miss latency 1286system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 133746.678392 # average ReadReq mshr uncacheable latency 1287system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 186612.391193 # average ReadReq mshr uncacheable latency 1288system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 148118.640293 # average ReadReq mshr uncacheable latency 1289system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 181193.272520 # average WriteReq mshr uncacheable latency 1290system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 181193.272520 # average WriteReq mshr uncacheable latency 1291system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 133746.678392 # average overall mshr uncacheable latency 1292system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 183801.468776 # average overall mshr uncacheable latency 1293system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 155613.282806 # average overall mshr uncacheable latency 1294system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1295system.cpu0.toL2Bus.snoop_filter.tot_requests 31782914 # Total number of requests made to the snoop filter. 1296system.cpu0.toL2Bus.snoop_filter.hit_single_requests 16244108 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1297system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 2495 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1298system.cpu0.toL2Bus.snoop_filter.tot_snoops 2292721 # Total number of snoops made to the snoop filter. 1299system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 2292254 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1300system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 467 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1301system.cpu0.toL2Bus.trans_dist::ReadReq 871142 # Transaction distribution 1302system.cpu0.toL2Bus.trans_dist::ReadResp 14502039 # Transaction distribution 1303system.cpu0.toL2Bus.trans_dist::WriteReq 21048 # Transaction distribution 1304system.cpu0.toL2Bus.trans_dist::WriteResp 21048 # Transaction distribution 1305system.cpu0.toL2Bus.trans_dist::WritebackDirty 5574338 # Transaction distribution 1306system.cpu0.toL2Bus.trans_dist::WritebackClean 11577498 # Transaction distribution 1307system.cpu0.toL2Bus.trans_dist::CleanEvict 3160606 # Transaction distribution 1308system.cpu0.toL2Bus.trans_dist::HardPFReq 1056652 # Transaction distribution 1309system.cpu0.toL2Bus.trans_dist::UpgradeReq 471328 # Transaction distribution 1310system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 370548 # Transaction distribution 1311system.cpu0.toL2Bus.trans_dist::UpgradeResp 537517 # Transaction distribution 1312system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 70 # Transaction distribution 1313system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 116 # Transaction distribution 1314system.cpu0.toL2Bus.trans_dist::ReadExReq 1276044 # Transaction distribution 1315system.cpu0.toL2Bus.trans_dist::ReadExResp 1205760 # Transaction distribution 1316system.cpu0.toL2Bus.trans_dist::ReadCleanReq 9594650 # Transaction distribution 1317system.cpu0.toL2Bus.trans_dist::ReadSharedReq 5010763 # Transaction distribution 1318system.cpu0.toL2Bus.trans_dist::InvalidateReq 810566 # Transaction distribution 1319system.cpu0.toL2Bus.trans_dist::InvalidateResp 803776 # Transaction distribution 1320system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 28888045 # Packet count per connected master and slave (bytes) 1321system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 18933308 # Packet count per connected master and slave (bytes) 1322system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 377591 # Packet count per connected master and slave (bytes) 1323system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1141314 # Packet count per connected master and slave (bytes) 1324system.cpu0.toL2Bus.pkt_count::total 49340258 # Packet count per connected master and slave (bytes) 1325system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 1231429504 # Cumulative packet size per connected master and slave (bytes) 1326system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 710021103 # Cumulative packet size per connected master and slave (bytes) 1327system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1437320 # Cumulative packet size per connected master and slave (bytes) 1328system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4319512 # Cumulative packet size per connected master and slave (bytes) 1329system.cpu0.toL2Bus.pkt_size::total 1947207439 # Cumulative packet size per connected master and slave (bytes) 1330system.cpu0.toL2Bus.snoops 7690219 # Total snoops (count) 1331system.cpu0.toL2Bus.snoop_fanout::samples 24350841 # Request fanout histogram 1332system.cpu0.toL2Bus.snoop_fanout::mean 0.107639 # Request fanout histogram 1333system.cpu0.toL2Bus.snoop_fanout::stdev 0.309986 # Request fanout histogram 1334system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1335system.cpu0.toL2Bus.snoop_fanout::0 21730213 89.24% 89.24% # Request fanout histogram 1336system.cpu0.toL2Bus.snoop_fanout::1 2620161 10.76% 100.00% # Request fanout histogram 1337system.cpu0.toL2Bus.snoop_fanout::2 467 0.00% 100.00% # Request fanout histogram 1338system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1339system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1340system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 1341system.cpu0.toL2Bus.snoop_fanout::total 24350841 # Request fanout histogram 1342system.cpu0.toL2Bus.reqLayer0.occupancy 31629791489 # Layer occupancy (ticks) 1343system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 1344system.cpu0.toL2Bus.snoopLayer0.occupancy 184209930 # Layer occupancy (ticks) 1345system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1346system.cpu0.toL2Bus.respLayer0.occupancy 14474040275 # Layer occupancy (ticks) 1347system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 1348system.cpu0.toL2Bus.respLayer1.occupancy 8384067550 # Layer occupancy (ticks) 1349system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 1350system.cpu0.toL2Bus.respLayer2.occupancy 198003844 # Layer occupancy (ticks) 1351system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1352system.cpu0.toL2Bus.respLayer3.occupancy 601473802 # Layer occupancy (ticks) 1353system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1354system.cpu1.branchPred.lookups 133924240 # Number of BP lookups 1355system.cpu1.branchPred.condPredicted 95730476 # Number of conditional branches predicted 1356system.cpu1.branchPred.condIncorrect 5982653 # Number of conditional branches incorrect 1357system.cpu1.branchPred.BTBLookups 100302023 # Number of BTB lookups 1358system.cpu1.branchPred.BTBHits 73831862 # Number of BTB hits 1359system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 1360system.cpu1.branchPred.BTBHitPct 73.609544 # BTB Hit Percentage 1361system.cpu1.branchPred.usedRAS 15419194 # Number of times the RAS was used to get a target. 1362system.cpu1.branchPred.RASInCorrect 1021732 # Number of incorrect RAS predictions. 1363system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1364system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1365system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1366system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1367system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1368system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1369system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1370system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 1371system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1372system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1373system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1374system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1375system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1376system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1377system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1378system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1379system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1380system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1381system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1382system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1383system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1384system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1385system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1386system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1387system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1388system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1389system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1390system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1391system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1392system.cpu1.dtb.walker.walks 293746 # Table walker walks requested 1393system.cpu1.dtb.walker.walksLong 293746 # Table walker walks initiated with long descriptors 1394system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 11413 # Level at which table walker walks with long descriptors terminate 1395system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 90757 # Level at which table walker walks with long descriptors terminate 1396system.cpu1.dtb.walker.walkWaitTime::samples 293746 # Table walker wait (enqueue to first request) latency 1397system.cpu1.dtb.walker.walkWaitTime::0 293746 100.00% 100.00% # Table walker wait (enqueue to first request) latency 1398system.cpu1.dtb.walker.walkWaitTime::total 293746 # Table walker wait (enqueue to first request) latency 1399system.cpu1.dtb.walker.walkCompletionTime::samples 102170 # Table walker service (enqueue to completion) latency 1400system.cpu1.dtb.walker.walkCompletionTime::mean 23413.986493 # Table walker service (enqueue to completion) latency 1401system.cpu1.dtb.walker.walkCompletionTime::gmean 21412.179846 # Table walker service (enqueue to completion) latency 1402system.cpu1.dtb.walker.walkCompletionTime::stdev 20342.964000 # Table walker service (enqueue to completion) latency 1403system.cpu1.dtb.walker.walkCompletionTime::0-65535 100862 98.72% 98.72% # Table walker service (enqueue to completion) latency 1404system.cpu1.dtb.walker.walkCompletionTime::65536-131071 167 0.16% 98.88% # Table walker service (enqueue to completion) latency 1405system.cpu1.dtb.walker.walkCompletionTime::131072-196607 952 0.93% 99.82% # Table walker service (enqueue to completion) latency 1406system.cpu1.dtb.walker.walkCompletionTime::196608-262143 45 0.04% 99.86% # Table walker service (enqueue to completion) latency 1407system.cpu1.dtb.walker.walkCompletionTime::262144-327679 52 0.05% 99.91% # Table walker service (enqueue to completion) latency 1408system.cpu1.dtb.walker.walkCompletionTime::327680-393215 35 0.03% 99.94% # Table walker service (enqueue to completion) latency 1409system.cpu1.dtb.walker.walkCompletionTime::393216-458751 35 0.03% 99.98% # Table walker service (enqueue to completion) latency 1410system.cpu1.dtb.walker.walkCompletionTime::458752-524287 12 0.01% 99.99% # Table walker service (enqueue to completion) latency 1411system.cpu1.dtb.walker.walkCompletionTime::524288-589823 6 0.01% 100.00% # Table walker service (enqueue to completion) latency 1412system.cpu1.dtb.walker.walkCompletionTime::589824-655359 3 0.00% 100.00% # Table walker service (enqueue to completion) latency 1413system.cpu1.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 1414system.cpu1.dtb.walker.walkCompletionTime::total 102170 # Table walker service (enqueue to completion) latency 1415system.cpu1.dtb.walker.walksPending::samples 527505760 # Table walker pending requests distribution 1416system.cpu1.dtb.walker.walksPending::0 527505760 100.00% 100.00% # Table walker pending requests distribution 1417system.cpu1.dtb.walker.walksPending::total 527505760 # Table walker pending requests distribution 1418system.cpu1.dtb.walker.walkPageSizes::4K 90757 88.83% 88.83% # Table walker page sizes translated 1419system.cpu1.dtb.walker.walkPageSizes::2M 11413 11.17% 100.00% # Table walker page sizes translated 1420system.cpu1.dtb.walker.walkPageSizes::total 102170 # Table walker page sizes translated 1421system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 293746 # Table walker requests started/completed, data/inst 1422system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1423system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 293746 # Table walker requests started/completed, data/inst 1424system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 102170 # Table walker requests started/completed, data/inst 1425system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1426system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 102170 # Table walker requests started/completed, data/inst 1427system.cpu1.dtb.walker.walkRequestOrigin::total 395916 # Table walker requests started/completed, data/inst 1428system.cpu1.dtb.inst_hits 0 # ITB inst hits 1429system.cpu1.dtb.inst_misses 0 # ITB inst misses 1430system.cpu1.dtb.read_hits 86040245 # DTB read hits 1431system.cpu1.dtb.read_misses 244355 # DTB read misses 1432system.cpu1.dtb.write_hits 75067998 # DTB write hits 1433system.cpu1.dtb.write_misses 49391 # DTB write misses 1434system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed 1435system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1436system.cpu1.dtb.flush_tlb_mva_asid 42784 # Number of times TLB was flushed by MVA & ASID 1437system.cpu1.dtb.flush_tlb_asid 1060 # Number of times TLB was flushed by ASID 1438system.cpu1.dtb.flush_entries 37937 # Number of entries that have been flushed from TLB 1439system.cpu1.dtb.align_faults 1338 # Number of TLB faults due to alignment restrictions 1440system.cpu1.dtb.prefetch_faults 8312 # Number of TLB faults due to prefetch 1441system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 1442system.cpu1.dtb.perms_faults 11189 # Number of TLB faults due to permissions restrictions 1443system.cpu1.dtb.read_accesses 86284600 # DTB read accesses 1444system.cpu1.dtb.write_accesses 75117389 # DTB write accesses 1445system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 1446system.cpu1.dtb.hits 161108243 # DTB hits 1447system.cpu1.dtb.misses 293746 # DTB misses 1448system.cpu1.dtb.accesses 161401989 # DTB accesses 1449system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1450system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1451system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1452system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1453system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1454system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1455system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1456system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 1457system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1458system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1459system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1460system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1461system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1462system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1463system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1464system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1465system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1466system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1467system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1468system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1469system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1470system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1471system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1472system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1473system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1474system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1475system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1476system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1477system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1478system.cpu1.itb.walker.walks 65124 # Table walker walks requested 1479system.cpu1.itb.walker.walksLong 65124 # Table walker walks initiated with long descriptors 1480system.cpu1.itb.walker.walksLongTerminationLevel::Level2 508 # Level at which table walker walks with long descriptors terminate 1481system.cpu1.itb.walker.walksLongTerminationLevel::Level3 55766 # Level at which table walker walks with long descriptors terminate 1482system.cpu1.itb.walker.walkWaitTime::samples 65124 # Table walker wait (enqueue to first request) latency 1483system.cpu1.itb.walker.walkWaitTime::0 65124 100.00% 100.00% # Table walker wait (enqueue to first request) latency 1484system.cpu1.itb.walker.walkWaitTime::total 65124 # Table walker wait (enqueue to first request) latency 1485system.cpu1.itb.walker.walkCompletionTime::samples 56274 # Table walker service (enqueue to completion) latency 1486system.cpu1.itb.walker.walkCompletionTime::mean 26926.564666 # Table walker service (enqueue to completion) latency 1487system.cpu1.itb.walker.walkCompletionTime::gmean 23857.779953 # Table walker service (enqueue to completion) latency 1488system.cpu1.itb.walker.walkCompletionTime::stdev 24945.648372 # Table walker service (enqueue to completion) latency 1489system.cpu1.itb.walker.walkCompletionTime::0-65535 54940 97.63% 97.63% # Table walker service (enqueue to completion) latency 1490system.cpu1.itb.walker.walkCompletionTime::65536-131071 10 0.02% 97.65% # Table walker service (enqueue to completion) latency 1491system.cpu1.itb.walker.walkCompletionTime::131072-196607 1199 2.13% 99.78% # Table walker service (enqueue to completion) latency 1492system.cpu1.itb.walker.walkCompletionTime::196608-262143 37 0.07% 99.84% # Table walker service (enqueue to completion) latency 1493system.cpu1.itb.walker.walkCompletionTime::262144-327679 49 0.09% 99.93% # Table walker service (enqueue to completion) latency 1494system.cpu1.itb.walker.walkCompletionTime::327680-393215 24 0.04% 99.97% # Table walker service (enqueue to completion) latency 1495system.cpu1.itb.walker.walkCompletionTime::393216-458751 8 0.01% 99.99% # Table walker service (enqueue to completion) latency 1496system.cpu1.itb.walker.walkCompletionTime::458752-524287 3 0.01% 99.99% # Table walker service (enqueue to completion) latency 1497system.cpu1.itb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 1498system.cpu1.itb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 1499system.cpu1.itb.walker.walkCompletionTime::total 56274 # Table walker service (enqueue to completion) latency 1500system.cpu1.itb.walker.walksPending::samples 526611260 # Table walker pending requests distribution 1501system.cpu1.itb.walker.walksPending::0 526611260 100.00% 100.00% # Table walker pending requests distribution 1502system.cpu1.itb.walker.walksPending::total 526611260 # Table walker pending requests distribution 1503system.cpu1.itb.walker.walkPageSizes::4K 55766 99.10% 99.10% # Table walker page sizes translated 1504system.cpu1.itb.walker.walkPageSizes::2M 508 0.90% 100.00% # Table walker page sizes translated 1505system.cpu1.itb.walker.walkPageSizes::total 56274 # Table walker page sizes translated 1506system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1507system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 65124 # Table walker requests started/completed, data/inst 1508system.cpu1.itb.walker.walkRequestOrigin_Requested::total 65124 # Table walker requests started/completed, data/inst 1509system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1510system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 56274 # Table walker requests started/completed, data/inst 1511system.cpu1.itb.walker.walkRequestOrigin_Completed::total 56274 # Table walker requests started/completed, data/inst 1512system.cpu1.itb.walker.walkRequestOrigin::total 121398 # Table walker requests started/completed, data/inst 1513system.cpu1.itb.inst_hits 239249458 # ITB inst hits 1514system.cpu1.itb.inst_misses 65124 # ITB inst misses 1515system.cpu1.itb.read_hits 0 # DTB read hits 1516system.cpu1.itb.read_misses 0 # DTB read misses 1517system.cpu1.itb.write_hits 0 # DTB write hits 1518system.cpu1.itb.write_misses 0 # DTB write misses 1519system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed 1520system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1521system.cpu1.itb.flush_tlb_mva_asid 42784 # Number of times TLB was flushed by MVA & ASID 1522system.cpu1.itb.flush_tlb_asid 1060 # Number of times TLB was flushed by ASID 1523system.cpu1.itb.flush_entries 26970 # Number of entries that have been flushed from TLB 1524system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1525system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1526system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1527system.cpu1.itb.perms_faults 220780 # Number of TLB faults due to permissions restrictions 1528system.cpu1.itb.read_accesses 0 # DTB read accesses 1529system.cpu1.itb.write_accesses 0 # DTB write accesses 1530system.cpu1.itb.inst_accesses 239314582 # ITB inst accesses 1531system.cpu1.itb.hits 239249458 # DTB hits 1532system.cpu1.itb.misses 65124 # DTB misses 1533system.cpu1.itb.accesses 239314582 # DTB accesses 1534system.cpu1.numCycles 947127317 # number of cpu cycles simulated 1535system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1536system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 1537system.cpu1.committedInsts 437680583 # Number of instructions committed 1538system.cpu1.committedOps 515109454 # Number of ops (including micro ops) committed 1539system.cpu1.discardedOps 47548266 # Number of ops (including micro ops) which were discarded before commit 1540system.cpu1.numFetchSuspends 4998 # Number of times Execute suspended instruction fetching 1541system.cpu1.quiesceCycles 93977493591 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1542system.cpu1.cpi 2.163969 # CPI: cycles per instruction 1543system.cpu1.ipc 0.462114 # IPC: instructions per cycle 1544system.cpu1.kern.inst.arm 0 # number of arm instructions executed 1545system.cpu1.kern.inst.quiesce 13761 # number of quiesce instructions executed 1546system.cpu1.tickCycles 715510770 # Number of cycles that the object actually ticked 1547system.cpu1.idleCycles 231616547 # Total number of cycles that the object has spent stopped 1548system.cpu1.dcache.tags.replacements 5225400 # number of replacements 1549system.cpu1.dcache.tags.tagsinuse 442.020428 # Cycle average of tags in use 1550system.cpu1.dcache.tags.total_refs 153149767 # Total number of references to valid blocks. 1551system.cpu1.dcache.tags.sampled_refs 5225912 # Sample count of references to valid blocks. 1552system.cpu1.dcache.tags.avg_refs 29.305845 # Average number of references to valid blocks. 1553system.cpu1.dcache.tags.warmup_cycle 8545383120500 # Cycle when the warmup percentage was hit. 1554system.cpu1.dcache.tags.occ_blocks::cpu1.data 442.020428 # Average occupied blocks per requestor 1555system.cpu1.dcache.tags.occ_percent::cpu1.data 0.863321 # Average percentage of cache occupancy 1556system.cpu1.dcache.tags.occ_percent::total 0.863321 # Average percentage of cache occupancy 1557system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1558system.cpu1.dcache.tags.age_task_id_blocks_1024::0 73 # Occupied blocks per task id 1559system.cpu1.dcache.tags.age_task_id_blocks_1024::1 408 # Occupied blocks per task id 1560system.cpu1.dcache.tags.age_task_id_blocks_1024::2 31 # Occupied blocks per task id 1561system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1562system.cpu1.dcache.tags.tag_accesses 324837482 # Number of tag accesses 1563system.cpu1.dcache.tags.data_accesses 324837482 # Number of data accesses 1564system.cpu1.dcache.ReadReq_hits::cpu1.data 78835589 # number of ReadReq hits 1565system.cpu1.dcache.ReadReq_hits::total 78835589 # number of ReadReq hits 1566system.cpu1.dcache.WriteReq_hits::cpu1.data 69932856 # number of WriteReq hits 1567system.cpu1.dcache.WriteReq_hits::total 69932856 # number of WriteReq hits 1568system.cpu1.dcache.SoftPFReq_hits::cpu1.data 235045 # number of SoftPFReq hits 1569system.cpu1.dcache.SoftPFReq_hits::total 235045 # number of SoftPFReq hits 1570system.cpu1.dcache.WriteLineReq_hits::cpu1.data 136840 # number of WriteLineReq hits 1571system.cpu1.dcache.WriteLineReq_hits::total 136840 # number of WriteLineReq hits 1572system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1777859 # number of LoadLockedReq hits 1573system.cpu1.dcache.LoadLockedReq_hits::total 1777859 # number of LoadLockedReq hits 1574system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1734680 # number of StoreCondReq hits 1575system.cpu1.dcache.StoreCondReq_hits::total 1734680 # number of StoreCondReq hits 1576system.cpu1.dcache.demand_hits::cpu1.data 148768445 # number of demand (read+write) hits 1577system.cpu1.dcache.demand_hits::total 148768445 # number of demand (read+write) hits 1578system.cpu1.dcache.overall_hits::cpu1.data 149003490 # number of overall hits 1579system.cpu1.dcache.overall_hits::total 149003490 # number of overall hits 1580system.cpu1.dcache.ReadReq_misses::cpu1.data 3368921 # number of ReadReq misses 1581system.cpu1.dcache.ReadReq_misses::total 3368921 # number of ReadReq misses 1582system.cpu1.dcache.WriteReq_misses::cpu1.data 2278073 # number of WriteReq misses 1583system.cpu1.dcache.WriteReq_misses::total 2278073 # number of WriteReq misses 1584system.cpu1.dcache.SoftPFReq_misses::cpu1.data 647676 # number of SoftPFReq misses 1585system.cpu1.dcache.SoftPFReq_misses::total 647676 # number of SoftPFReq misses 1586system.cpu1.dcache.WriteLineReq_misses::cpu1.data 450910 # number of WriteLineReq misses 1587system.cpu1.dcache.WriteLineReq_misses::total 450910 # number of WriteLineReq misses 1588system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 159516 # number of LoadLockedReq misses 1589system.cpu1.dcache.LoadLockedReq_misses::total 159516 # number of LoadLockedReq misses 1590system.cpu1.dcache.StoreCondReq_misses::cpu1.data 201171 # number of StoreCondReq misses 1591system.cpu1.dcache.StoreCondReq_misses::total 201171 # number of StoreCondReq misses 1592system.cpu1.dcache.demand_misses::cpu1.data 5646994 # number of demand (read+write) misses 1593system.cpu1.dcache.demand_misses::total 5646994 # number of demand (read+write) misses 1594system.cpu1.dcache.overall_misses::cpu1.data 6294670 # number of overall misses 1595system.cpu1.dcache.overall_misses::total 6294670 # number of overall misses 1596system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 55794276000 # number of ReadReq miss cycles 1597system.cpu1.dcache.ReadReq_miss_latency::total 55794276000 # number of ReadReq miss cycles 1598system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 51841670500 # number of WriteReq miss cycles 1599system.cpu1.dcache.WriteReq_miss_latency::total 51841670500 # number of WriteReq miss cycles 1600system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 21264976000 # number of WriteLineReq miss cycles 1601system.cpu1.dcache.WriteLineReq_miss_latency::total 21264976000 # number of WriteLineReq miss cycles 1602system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2730537500 # number of LoadLockedReq miss cycles 1603system.cpu1.dcache.LoadLockedReq_miss_latency::total 2730537500 # number of LoadLockedReq miss cycles 1604system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 5515974000 # number of StoreCondReq miss cycles 1605system.cpu1.dcache.StoreCondReq_miss_latency::total 5515974000 # number of StoreCondReq miss cycles 1606system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 4942500 # number of StoreCondFailReq miss cycles 1607system.cpu1.dcache.StoreCondFailReq_miss_latency::total 4942500 # number of StoreCondFailReq miss cycles 1608system.cpu1.dcache.demand_miss_latency::cpu1.data 107635946500 # number of demand (read+write) miss cycles 1609system.cpu1.dcache.demand_miss_latency::total 107635946500 # number of demand (read+write) miss cycles 1610system.cpu1.dcache.overall_miss_latency::cpu1.data 107635946500 # number of overall miss cycles 1611system.cpu1.dcache.overall_miss_latency::total 107635946500 # number of overall miss cycles 1612system.cpu1.dcache.ReadReq_accesses::cpu1.data 82204510 # number of ReadReq accesses(hits+misses) 1613system.cpu1.dcache.ReadReq_accesses::total 82204510 # number of ReadReq accesses(hits+misses) 1614system.cpu1.dcache.WriteReq_accesses::cpu1.data 72210929 # number of WriteReq accesses(hits+misses) 1615system.cpu1.dcache.WriteReq_accesses::total 72210929 # number of WriteReq accesses(hits+misses) 1616system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 882721 # number of SoftPFReq accesses(hits+misses) 1617system.cpu1.dcache.SoftPFReq_accesses::total 882721 # number of SoftPFReq accesses(hits+misses) 1618system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 587750 # number of WriteLineReq accesses(hits+misses) 1619system.cpu1.dcache.WriteLineReq_accesses::total 587750 # number of WriteLineReq accesses(hits+misses) 1620system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1937375 # number of LoadLockedReq accesses(hits+misses) 1621system.cpu1.dcache.LoadLockedReq_accesses::total 1937375 # number of LoadLockedReq accesses(hits+misses) 1622system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1935851 # number of StoreCondReq accesses(hits+misses) 1623system.cpu1.dcache.StoreCondReq_accesses::total 1935851 # number of StoreCondReq accesses(hits+misses) 1624system.cpu1.dcache.demand_accesses::cpu1.data 154415439 # number of demand (read+write) accesses 1625system.cpu1.dcache.demand_accesses::total 154415439 # number of demand (read+write) accesses 1626system.cpu1.dcache.overall_accesses::cpu1.data 155298160 # number of overall (read+write) accesses 1627system.cpu1.dcache.overall_accesses::total 155298160 # number of overall (read+write) accesses 1628system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.040982 # miss rate for ReadReq accesses 1629system.cpu1.dcache.ReadReq_miss_rate::total 0.040982 # miss rate for ReadReq accesses 1630system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.031547 # miss rate for WriteReq accesses 1631system.cpu1.dcache.WriteReq_miss_rate::total 0.031547 # miss rate for WriteReq accesses 1632system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.733727 # miss rate for SoftPFReq accesses 1633system.cpu1.dcache.SoftPFReq_miss_rate::total 0.733727 # miss rate for SoftPFReq accesses 1634system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.767180 # miss rate for WriteLineReq accesses 1635system.cpu1.dcache.WriteLineReq_miss_rate::total 0.767180 # miss rate for WriteLineReq accesses 1636system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.082336 # miss rate for LoadLockedReq accesses 1637system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.082336 # miss rate for LoadLockedReq accesses 1638system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.103919 # miss rate for StoreCondReq accesses 1639system.cpu1.dcache.StoreCondReq_miss_rate::total 0.103919 # miss rate for StoreCondReq accesses 1640system.cpu1.dcache.demand_miss_rate::cpu1.data 0.036570 # miss rate for demand accesses 1641system.cpu1.dcache.demand_miss_rate::total 0.036570 # miss rate for demand accesses 1642system.cpu1.dcache.overall_miss_rate::cpu1.data 0.040533 # miss rate for overall accesses 1643system.cpu1.dcache.overall_miss_rate::total 0.040533 # miss rate for overall accesses 1644system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16561.467603 # average ReadReq miss latency 1645system.cpu1.dcache.ReadReq_avg_miss_latency::total 16561.467603 # average ReadReq miss latency 1646system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 22756.808276 # average WriteReq miss latency 1647system.cpu1.dcache.WriteReq_avg_miss_latency::total 22756.808276 # average WriteReq miss latency 1648system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 47160.133951 # average WriteLineReq miss latency 1649system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 47160.133951 # average WriteLineReq miss latency 1650system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 17117.640237 # average LoadLockedReq miss latency 1651system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 17117.640237 # average LoadLockedReq miss latency 1652system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 27419.329824 # average StoreCondReq miss latency 1653system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 27419.329824 # average StoreCondReq miss latency 1654system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 1655system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 1656system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19060.750994 # average overall miss latency 1657system.cpu1.dcache.demand_avg_miss_latency::total 19060.750994 # average overall miss latency 1658system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17099.537625 # average overall miss latency 1659system.cpu1.dcache.overall_avg_miss_latency::total 17099.537625 # average overall miss latency 1660system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1661system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1662system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1663system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1664system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1665system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1666system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1667system.cpu1.dcache.cache_copies 0 # number of cache copies performed 1668system.cpu1.dcache.writebacks::writebacks 5225429 # number of writebacks 1669system.cpu1.dcache.writebacks::total 5225429 # number of writebacks 1670system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 382545 # number of ReadReq MSHR hits 1671system.cpu1.dcache.ReadReq_mshr_hits::total 382545 # number of ReadReq MSHR hits 1672system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 937825 # number of WriteReq MSHR hits 1673system.cpu1.dcache.WriteReq_mshr_hits::total 937825 # number of WriteReq MSHR hits 1674system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 58 # number of WriteLineReq MSHR hits 1675system.cpu1.dcache.WriteLineReq_mshr_hits::total 58 # number of WriteLineReq MSHR hits 1676system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 41578 # number of LoadLockedReq MSHR hits 1677system.cpu1.dcache.LoadLockedReq_mshr_hits::total 41578 # number of LoadLockedReq MSHR hits 1678system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data 34 # number of StoreCondReq MSHR hits 1679system.cpu1.dcache.StoreCondReq_mshr_hits::total 34 # number of StoreCondReq MSHR hits 1680system.cpu1.dcache.demand_mshr_hits::cpu1.data 1320370 # number of demand (read+write) MSHR hits 1681system.cpu1.dcache.demand_mshr_hits::total 1320370 # number of demand (read+write) MSHR hits 1682system.cpu1.dcache.overall_mshr_hits::cpu1.data 1320370 # number of overall MSHR hits 1683system.cpu1.dcache.overall_mshr_hits::total 1320370 # number of overall MSHR hits 1684system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2986376 # number of ReadReq MSHR misses 1685system.cpu1.dcache.ReadReq_mshr_misses::total 2986376 # number of ReadReq MSHR misses 1686system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1340248 # number of WriteReq MSHR misses 1687system.cpu1.dcache.WriteReq_mshr_misses::total 1340248 # number of WriteReq MSHR misses 1688system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 647394 # number of SoftPFReq MSHR misses 1689system.cpu1.dcache.SoftPFReq_mshr_misses::total 647394 # number of SoftPFReq MSHR misses 1690system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 450852 # number of WriteLineReq MSHR misses 1691system.cpu1.dcache.WriteLineReq_mshr_misses::total 450852 # number of WriteLineReq MSHR misses 1692system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 117938 # number of LoadLockedReq MSHR misses 1693system.cpu1.dcache.LoadLockedReq_mshr_misses::total 117938 # number of LoadLockedReq MSHR misses 1694system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 201137 # number of StoreCondReq MSHR misses 1695system.cpu1.dcache.StoreCondReq_mshr_misses::total 201137 # number of StoreCondReq MSHR misses 1696system.cpu1.dcache.demand_mshr_misses::cpu1.data 4326624 # number of demand (read+write) MSHR misses 1697system.cpu1.dcache.demand_mshr_misses::total 4326624 # number of demand (read+write) MSHR misses 1698system.cpu1.dcache.overall_mshr_misses::cpu1.data 4974018 # number of overall MSHR misses 1699system.cpu1.dcache.overall_mshr_misses::total 4974018 # number of overall MSHR misses 1700system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 19129 # number of ReadReq MSHR uncacheable 1701system.cpu1.dcache.ReadReq_mshr_uncacheable::total 19129 # number of ReadReq MSHR uncacheable 1702system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 17467 # number of WriteReq MSHR uncacheable 1703system.cpu1.dcache.WriteReq_mshr_uncacheable::total 17467 # number of WriteReq MSHR uncacheable 1704system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 36596 # number of overall MSHR uncacheable misses 1705system.cpu1.dcache.overall_mshr_uncacheable_misses::total 36596 # number of overall MSHR uncacheable misses 1706system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 44483005500 # number of ReadReq MSHR miss cycles 1707system.cpu1.dcache.ReadReq_mshr_miss_latency::total 44483005500 # number of ReadReq MSHR miss cycles 1708system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 30789351000 # number of WriteReq MSHR miss cycles 1709system.cpu1.dcache.WriteReq_mshr_miss_latency::total 30789351000 # number of WriteReq MSHR miss cycles 1710system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 15729879000 # number of SoftPFReq MSHR miss cycles 1711system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 15729879000 # number of SoftPFReq MSHR miss cycles 1712system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 20808027500 # number of WriteLineReq MSHR miss cycles 1713system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 20808027500 # number of WriteLineReq MSHR miss cycles 1714system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1765421000 # number of LoadLockedReq MSHR miss cycles 1715system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1765421000 # number of LoadLockedReq MSHR miss cycles 1716system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 5312775000 # number of StoreCondReq MSHR miss cycles 1717system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 5312775000 # number of StoreCondReq MSHR miss cycles 1718system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 4745500 # number of StoreCondFailReq MSHR miss cycles 1719system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 4745500 # number of StoreCondFailReq MSHR miss cycles 1720system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 75272356500 # number of demand (read+write) MSHR miss cycles 1721system.cpu1.dcache.demand_mshr_miss_latency::total 75272356500 # number of demand (read+write) MSHR miss cycles 1722system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 91002235500 # number of overall MSHR miss cycles 1723system.cpu1.dcache.overall_mshr_miss_latency::total 91002235500 # number of overall MSHR miss cycles 1724system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3151598000 # number of ReadReq MSHR uncacheable cycles 1725system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 3151598000 # number of ReadReq MSHR uncacheable cycles 1726system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2962839500 # number of WriteReq MSHR uncacheable cycles 1727system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 2962839500 # number of WriteReq MSHR uncacheable cycles 1728system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 6114437500 # number of overall MSHR uncacheable cycles 1729system.cpu1.dcache.overall_mshr_uncacheable_latency::total 6114437500 # number of overall MSHR uncacheable cycles 1730system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036329 # mshr miss rate for ReadReq accesses 1731system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036329 # mshr miss rate for ReadReq accesses 1732system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018560 # mshr miss rate for WriteReq accesses 1733system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018560 # mshr miss rate for WriteReq accesses 1734system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.733407 # mshr miss rate for SoftPFReq accesses 1735system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.733407 # mshr miss rate for SoftPFReq accesses 1736system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.767081 # mshr miss rate for WriteLineReq accesses 1737system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.767081 # mshr miss rate for WriteLineReq accesses 1738system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.060875 # mshr miss rate for LoadLockedReq accesses 1739system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.060875 # mshr miss rate for LoadLockedReq accesses 1740system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.103901 # mshr miss rate for StoreCondReq accesses 1741system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.103901 # mshr miss rate for StoreCondReq accesses 1742system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.028019 # mshr miss rate for demand accesses 1743system.cpu1.dcache.demand_mshr_miss_rate::total 0.028019 # mshr miss rate for demand accesses 1744system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.032029 # mshr miss rate for overall accesses 1745system.cpu1.dcache.overall_mshr_miss_rate::total 0.032029 # mshr miss rate for overall accesses 1746system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14895.313082 # average ReadReq mshr miss latency 1747system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14895.313082 # average ReadReq mshr miss latency 1748system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 22972.875916 # average WriteReq mshr miss latency 1749system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 22972.875916 # average WriteReq mshr miss latency 1750system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 24297.227036 # average SoftPFReq mshr miss latency 1751system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 24297.227036 # average SoftPFReq mshr miss latency 1752system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 46152.678706 # average WriteLineReq mshr miss latency 1753system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 46152.678706 # average WriteLineReq mshr miss latency 1754system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14969.060015 # average LoadLockedReq mshr miss latency 1755system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14969.060015 # average LoadLockedReq mshr miss latency 1756system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 26413.713041 # average StoreCondReq mshr miss latency 1757system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 26413.713041 # average StoreCondReq mshr miss latency 1758system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 1759system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 1760system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17397.480461 # average overall mshr miss latency 1761system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17397.480461 # average overall mshr miss latency 1762system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18295.517929 # average overall mshr miss latency 1763system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18295.517929 # average overall mshr miss latency 1764system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 164754.979351 # average ReadReq mshr uncacheable latency 1765system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 164754.979351 # average ReadReq mshr uncacheable latency 1766system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 169624.978531 # average WriteReq mshr uncacheable latency 1767system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 169624.978531 # average WriteReq mshr uncacheable latency 1768system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 167079.393923 # average overall mshr uncacheable latency 1769system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 167079.393923 # average overall mshr uncacheable latency 1770system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1771system.cpu1.icache.tags.replacements 9231311 # number of replacements 1772system.cpu1.icache.tags.tagsinuse 506.694166 # Cycle average of tags in use 1773system.cpu1.icache.tags.total_refs 229790487 # Total number of references to valid blocks. 1774system.cpu1.icache.tags.sampled_refs 9231823 # Sample count of references to valid blocks. 1775system.cpu1.icache.tags.avg_refs 24.891128 # Average number of references to valid blocks. 1776system.cpu1.icache.tags.warmup_cycle 8386495264000 # Cycle when the warmup percentage was hit. 1777system.cpu1.icache.tags.occ_blocks::cpu1.inst 506.694166 # Average occupied blocks per requestor 1778system.cpu1.icache.tags.occ_percent::cpu1.inst 0.989637 # Average percentage of cache occupancy 1779system.cpu1.icache.tags.occ_percent::total 0.989637 # Average percentage of cache occupancy 1780system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1781system.cpu1.icache.tags.age_task_id_blocks_1024::0 100 # Occupied blocks per task id 1782system.cpu1.icache.tags.age_task_id_blocks_1024::1 336 # Occupied blocks per task id 1783system.cpu1.icache.tags.age_task_id_blocks_1024::2 76 # Occupied blocks per task id 1784system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1785system.cpu1.icache.tags.tag_accesses 487276445 # Number of tag accesses 1786system.cpu1.icache.tags.data_accesses 487276445 # Number of data accesses 1787system.cpu1.icache.ReadReq_hits::cpu1.inst 229790487 # number of ReadReq hits 1788system.cpu1.icache.ReadReq_hits::total 229790487 # number of ReadReq hits 1789system.cpu1.icache.demand_hits::cpu1.inst 229790487 # number of demand (read+write) hits 1790system.cpu1.icache.demand_hits::total 229790487 # number of demand (read+write) hits 1791system.cpu1.icache.overall_hits::cpu1.inst 229790487 # number of overall hits 1792system.cpu1.icache.overall_hits::total 229790487 # number of overall hits 1793system.cpu1.icache.ReadReq_misses::cpu1.inst 9231824 # number of ReadReq misses 1794system.cpu1.icache.ReadReq_misses::total 9231824 # number of ReadReq misses 1795system.cpu1.icache.demand_misses::cpu1.inst 9231824 # number of demand (read+write) misses 1796system.cpu1.icache.demand_misses::total 9231824 # number of demand (read+write) misses 1797system.cpu1.icache.overall_misses::cpu1.inst 9231824 # number of overall misses 1798system.cpu1.icache.overall_misses::total 9231824 # number of overall misses 1799system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 94524443000 # number of ReadReq miss cycles 1800system.cpu1.icache.ReadReq_miss_latency::total 94524443000 # number of ReadReq miss cycles 1801system.cpu1.icache.demand_miss_latency::cpu1.inst 94524443000 # number of demand (read+write) miss cycles 1802system.cpu1.icache.demand_miss_latency::total 94524443000 # number of demand (read+write) miss cycles 1803system.cpu1.icache.overall_miss_latency::cpu1.inst 94524443000 # number of overall miss cycles 1804system.cpu1.icache.overall_miss_latency::total 94524443000 # number of overall miss cycles 1805system.cpu1.icache.ReadReq_accesses::cpu1.inst 239022311 # number of ReadReq accesses(hits+misses) 1806system.cpu1.icache.ReadReq_accesses::total 239022311 # number of ReadReq accesses(hits+misses) 1807system.cpu1.icache.demand_accesses::cpu1.inst 239022311 # number of demand (read+write) accesses 1808system.cpu1.icache.demand_accesses::total 239022311 # number of demand (read+write) accesses 1809system.cpu1.icache.overall_accesses::cpu1.inst 239022311 # number of overall (read+write) accesses 1810system.cpu1.icache.overall_accesses::total 239022311 # number of overall (read+write) accesses 1811system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.038623 # miss rate for ReadReq accesses 1812system.cpu1.icache.ReadReq_miss_rate::total 0.038623 # miss rate for ReadReq accesses 1813system.cpu1.icache.demand_miss_rate::cpu1.inst 0.038623 # miss rate for demand accesses 1814system.cpu1.icache.demand_miss_rate::total 0.038623 # miss rate for demand accesses 1815system.cpu1.icache.overall_miss_rate::cpu1.inst 0.038623 # miss rate for overall accesses 1816system.cpu1.icache.overall_miss_rate::total 0.038623 # miss rate for overall accesses 1817system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10238.978018 # average ReadReq miss latency 1818system.cpu1.icache.ReadReq_avg_miss_latency::total 10238.978018 # average ReadReq miss latency 1819system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10238.978018 # average overall miss latency 1820system.cpu1.icache.demand_avg_miss_latency::total 10238.978018 # average overall miss latency 1821system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10238.978018 # average overall miss latency 1822system.cpu1.icache.overall_avg_miss_latency::total 10238.978018 # average overall miss latency 1823system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1824system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1825system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1826system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1827system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1828system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1829system.cpu1.icache.fast_writes 0 # number of fast writes performed 1830system.cpu1.icache.cache_copies 0 # number of cache copies performed 1831system.cpu1.icache.writebacks::writebacks 9231311 # number of writebacks 1832system.cpu1.icache.writebacks::total 9231311 # number of writebacks 1833system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 9231824 # number of ReadReq MSHR misses 1834system.cpu1.icache.ReadReq_mshr_misses::total 9231824 # number of ReadReq MSHR misses 1835system.cpu1.icache.demand_mshr_misses::cpu1.inst 9231824 # number of demand (read+write) MSHR misses 1836system.cpu1.icache.demand_mshr_misses::total 9231824 # number of demand (read+write) MSHR misses 1837system.cpu1.icache.overall_mshr_misses::cpu1.inst 9231824 # number of overall MSHR misses 1838system.cpu1.icache.overall_mshr_misses::total 9231824 # number of overall MSHR misses 1839system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 92 # number of ReadReq MSHR uncacheable 1840system.cpu1.icache.ReadReq_mshr_uncacheable::total 92 # number of ReadReq MSHR uncacheable 1841system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 92 # number of overall MSHR uncacheable misses 1842system.cpu1.icache.overall_mshr_uncacheable_misses::total 92 # number of overall MSHR uncacheable misses 1843system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 89908531500 # number of ReadReq MSHR miss cycles 1844system.cpu1.icache.ReadReq_mshr_miss_latency::total 89908531500 # number of ReadReq MSHR miss cycles 1845system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 89908531500 # number of demand (read+write) MSHR miss cycles 1846system.cpu1.icache.demand_mshr_miss_latency::total 89908531500 # number of demand (read+write) MSHR miss cycles 1847system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 89908531500 # number of overall MSHR miss cycles 1848system.cpu1.icache.overall_mshr_miss_latency::total 89908531500 # number of overall MSHR miss cycles 1849system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 12950500 # number of ReadReq MSHR uncacheable cycles 1850system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 12950500 # number of ReadReq MSHR uncacheable cycles 1851system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 12950500 # number of overall MSHR uncacheable cycles 1852system.cpu1.icache.overall_mshr_uncacheable_latency::total 12950500 # number of overall MSHR uncacheable cycles 1853system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.038623 # mshr miss rate for ReadReq accesses 1854system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.038623 # mshr miss rate for ReadReq accesses 1855system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.038623 # mshr miss rate for demand accesses 1856system.cpu1.icache.demand_mshr_miss_rate::total 0.038623 # mshr miss rate for demand accesses 1857system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.038623 # mshr miss rate for overall accesses 1858system.cpu1.icache.overall_mshr_miss_rate::total 0.038623 # mshr miss rate for overall accesses 1859system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 9738.978072 # average ReadReq mshr miss latency 1860system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 9738.978072 # average ReadReq mshr miss latency 1861system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 9738.978072 # average overall mshr miss latency 1862system.cpu1.icache.demand_avg_mshr_miss_latency::total 9738.978072 # average overall mshr miss latency 1863system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 9738.978072 # average overall mshr miss latency 1864system.cpu1.icache.overall_avg_mshr_miss_latency::total 9738.978072 # average overall mshr miss latency 1865system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 140766.304348 # average ReadReq mshr uncacheable latency 1866system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 140766.304348 # average ReadReq mshr uncacheable latency 1867system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 140766.304348 # average overall mshr uncacheable latency 1868system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 140766.304348 # average overall mshr uncacheable latency 1869system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1870system.cpu1.l2cache.prefetcher.num_hwpf_issued 7101301 # number of hwpf issued 1871system.cpu1.l2cache.prefetcher.pfIdentified 7101636 # number of prefetch candidates identified 1872system.cpu1.l2cache.prefetcher.pfBufferHit 296 # number of redundant prefetches already in prefetch queue 1873system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 1874system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 1875system.cpu1.l2cache.prefetcher.pfSpanPage 867300 # number of prefetches not generated due to page crossing 1876system.cpu1.l2cache.tags.replacements 2326720 # number of replacements 1877system.cpu1.l2cache.tags.tagsinuse 13467.956369 # Cycle average of tags in use 1878system.cpu1.l2cache.tags.total_refs 23154784 # Total number of references to valid blocks. 1879system.cpu1.l2cache.tags.sampled_refs 2342909 # Sample count of references to valid blocks. 1880system.cpu1.l2cache.tags.avg_refs 9.882921 # Average number of references to valid blocks. 1881system.cpu1.l2cache.tags.warmup_cycle 9860254327500 # Cycle when the warmup percentage was hit. 1882system.cpu1.l2cache.tags.occ_blocks::writebacks 12598.584174 # Average occupied blocks per requestor 1883system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 60.491814 # Average occupied blocks per requestor 1884system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 58.201363 # Average occupied blocks per requestor 1885system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 750.679017 # Average occupied blocks per requestor 1886system.cpu1.l2cache.tags.occ_percent::writebacks 0.768957 # Average percentage of cache occupancy 1887system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.003692 # Average percentage of cache occupancy 1888system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.003552 # Average percentage of cache occupancy 1889system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.045818 # Average percentage of cache occupancy 1890system.cpu1.l2cache.tags.occ_percent::total 0.822019 # Average percentage of cache occupancy 1891system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1395 # Occupied blocks per task id 1892system.cpu1.l2cache.tags.occ_task_id_blocks::1023 52 # Occupied blocks per task id 1893system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14742 # Occupied blocks per task id 1894system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 10 # Occupied blocks per task id 1895system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 404 # Occupied blocks per task id 1896system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 859 # Occupied blocks per task id 1897system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 122 # Occupied blocks per task id 1898system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 2 # Occupied blocks per task id 1899system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id 1900system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 31 # Occupied blocks per task id 1901system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 3 # Occupied blocks per task id 1902system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 86 # Occupied blocks per task id 1903system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1149 # Occupied blocks per task id 1904system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5193 # Occupied blocks per task id 1905system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 7319 # Occupied blocks per task id 1906system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 995 # Occupied blocks per task id 1907system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.085144 # Percentage of cache occupancy per task id 1908system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.003174 # Percentage of cache occupancy per task id 1909system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.899780 # Percentage of cache occupancy per task id 1910system.cpu1.l2cache.tags.tag_accesses 488472501 # Number of tag accesses 1911system.cpu1.l2cache.tags.data_accesses 488472501 # Number of data accesses 1912system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 576439 # number of ReadReq hits 1913system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 168221 # number of ReadReq hits 1914system.cpu1.l2cache.ReadReq_hits::total 744660 # number of ReadReq hits 1915system.cpu1.l2cache.WritebackDirty_hits::writebacks 3264846 # number of WritebackDirty hits 1916system.cpu1.l2cache.WritebackDirty_hits::total 3264846 # number of WritebackDirty hits 1917system.cpu1.l2cache.WritebackClean_hits::writebacks 11189694 # number of WritebackClean hits 1918system.cpu1.l2cache.WritebackClean_hits::total 11189694 # number of WritebackClean hits 1919system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 575 # number of UpgradeReq hits 1920system.cpu1.l2cache.UpgradeReq_hits::total 575 # number of UpgradeReq hits 1921system.cpu1.l2cache.ReadExReq_hits::cpu1.data 867363 # number of ReadExReq hits 1922system.cpu1.l2cache.ReadExReq_hits::total 867363 # number of ReadExReq hits 1923system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 8545306 # number of ReadCleanReq hits 1924system.cpu1.l2cache.ReadCleanReq_hits::total 8545306 # number of ReadCleanReq hits 1925system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 2781382 # number of ReadSharedReq hits 1926system.cpu1.l2cache.ReadSharedReq_hits::total 2781382 # number of ReadSharedReq hits 1927system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 181539 # number of InvalidateReq hits 1928system.cpu1.l2cache.InvalidateReq_hits::total 181539 # number of InvalidateReq hits 1929system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 576439 # number of demand (read+write) hits 1930system.cpu1.l2cache.demand_hits::cpu1.itb.walker 168221 # number of demand (read+write) hits 1931system.cpu1.l2cache.demand_hits::cpu1.inst 8545306 # number of demand (read+write) hits 1932system.cpu1.l2cache.demand_hits::cpu1.data 3648745 # number of demand (read+write) hits 1933system.cpu1.l2cache.demand_hits::total 12938711 # number of demand (read+write) hits 1934system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 576439 # number of overall hits 1935system.cpu1.l2cache.overall_hits::cpu1.itb.walker 168221 # number of overall hits 1936system.cpu1.l2cache.overall_hits::cpu1.inst 8545306 # number of overall hits 1937system.cpu1.l2cache.overall_hits::cpu1.data 3648745 # number of overall hits 1938system.cpu1.l2cache.overall_hits::total 12938711 # number of overall hits 1939system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 12346 # number of ReadReq misses 1940system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 8532 # number of ReadReq misses 1941system.cpu1.l2cache.ReadReq_misses::total 20878 # number of ReadReq misses 1942system.cpu1.l2cache.WritebackDirty_misses::writebacks 1 # number of WritebackDirty misses 1943system.cpu1.l2cache.WritebackDirty_misses::total 1 # number of WritebackDirty misses 1944system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 223343 # number of UpgradeReq misses 1945system.cpu1.l2cache.UpgradeReq_misses::total 223343 # number of UpgradeReq misses 1946system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 201132 # number of SCUpgradeReq misses 1947system.cpu1.l2cache.SCUpgradeReq_misses::total 201132 # number of SCUpgradeReq misses 1948system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 5 # number of SCUpgradeFailReq misses 1949system.cpu1.l2cache.SCUpgradeFailReq_misses::total 5 # number of SCUpgradeFailReq misses 1950system.cpu1.l2cache.ReadExReq_misses::cpu1.data 251639 # number of ReadExReq misses 1951system.cpu1.l2cache.ReadExReq_misses::total 251639 # number of ReadExReq misses 1952system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 686518 # number of ReadCleanReq misses 1953system.cpu1.l2cache.ReadCleanReq_misses::total 686518 # number of ReadCleanReq misses 1954system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 970013 # number of ReadSharedReq misses 1955system.cpu1.l2cache.ReadSharedReq_misses::total 970013 # number of ReadSharedReq misses 1956system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 267232 # number of InvalidateReq misses 1957system.cpu1.l2cache.InvalidateReq_misses::total 267232 # number of InvalidateReq misses 1958system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 12346 # number of demand (read+write) misses 1959system.cpu1.l2cache.demand_misses::cpu1.itb.walker 8532 # number of demand (read+write) misses 1960system.cpu1.l2cache.demand_misses::cpu1.inst 686518 # number of demand (read+write) misses 1961system.cpu1.l2cache.demand_misses::cpu1.data 1221652 # number of demand (read+write) misses 1962system.cpu1.l2cache.demand_misses::total 1929048 # number of demand (read+write) misses 1963system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 12346 # number of overall misses 1964system.cpu1.l2cache.overall_misses::cpu1.itb.walker 8532 # number of overall misses 1965system.cpu1.l2cache.overall_misses::cpu1.inst 686518 # number of overall misses 1966system.cpu1.l2cache.overall_misses::cpu1.data 1221652 # number of overall misses 1967system.cpu1.l2cache.overall_misses::total 1929048 # number of overall misses 1968system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 599407500 # number of ReadReq miss cycles 1969system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 460132500 # number of ReadReq miss cycles 1970system.cpu1.l2cache.ReadReq_miss_latency::total 1059540000 # number of ReadReq miss cycles 1971system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 3297082000 # number of UpgradeReq miss cycles 1972system.cpu1.l2cache.UpgradeReq_miss_latency::total 3297082000 # number of UpgradeReq miss cycles 1973system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 1852998500 # number of SCUpgradeReq miss cycles 1974system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 1852998500 # number of SCUpgradeReq miss cycles 1975system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 4653499 # number of SCUpgradeFailReq miss cycles 1976system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 4653499 # number of SCUpgradeFailReq miss cycles 1977system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 14739798000 # number of ReadExReq miss cycles 1978system.cpu1.l2cache.ReadExReq_miss_latency::total 14739798000 # number of ReadExReq miss cycles 1979system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 24441807000 # number of ReadCleanReq miss cycles 1980system.cpu1.l2cache.ReadCleanReq_miss_latency::total 24441807000 # number of ReadCleanReq miss cycles 1981system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 37974197490 # number of ReadSharedReq miss cycles 1982system.cpu1.l2cache.ReadSharedReq_miss_latency::total 37974197490 # number of ReadSharedReq miss cycles 1983system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 18803051000 # number of InvalidateReq miss cycles 1984system.cpu1.l2cache.InvalidateReq_miss_latency::total 18803051000 # number of InvalidateReq miss cycles 1985system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 599407500 # number of demand (read+write) miss cycles 1986system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 460132500 # number of demand (read+write) miss cycles 1987system.cpu1.l2cache.demand_miss_latency::cpu1.inst 24441807000 # number of demand (read+write) miss cycles 1988system.cpu1.l2cache.demand_miss_latency::cpu1.data 52713995490 # number of demand (read+write) miss cycles 1989system.cpu1.l2cache.demand_miss_latency::total 78215342490 # number of demand (read+write) miss cycles 1990system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 599407500 # number of overall miss cycles 1991system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 460132500 # number of overall miss cycles 1992system.cpu1.l2cache.overall_miss_latency::cpu1.inst 24441807000 # number of overall miss cycles 1993system.cpu1.l2cache.overall_miss_latency::cpu1.data 52713995490 # number of overall miss cycles 1994system.cpu1.l2cache.overall_miss_latency::total 78215342490 # number of overall miss cycles 1995system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 588785 # number of ReadReq accesses(hits+misses) 1996system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 176753 # number of ReadReq accesses(hits+misses) 1997system.cpu1.l2cache.ReadReq_accesses::total 765538 # number of ReadReq accesses(hits+misses) 1998system.cpu1.l2cache.WritebackDirty_accesses::writebacks 3264847 # number of WritebackDirty accesses(hits+misses) 1999system.cpu1.l2cache.WritebackDirty_accesses::total 3264847 # number of WritebackDirty accesses(hits+misses) 2000system.cpu1.l2cache.WritebackClean_accesses::writebacks 11189694 # number of WritebackClean accesses(hits+misses) 2001system.cpu1.l2cache.WritebackClean_accesses::total 11189694 # number of WritebackClean accesses(hits+misses) 2002system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 223918 # number of UpgradeReq accesses(hits+misses) 2003system.cpu1.l2cache.UpgradeReq_accesses::total 223918 # number of UpgradeReq accesses(hits+misses) 2004system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 201132 # number of SCUpgradeReq accesses(hits+misses) 2005system.cpu1.l2cache.SCUpgradeReq_accesses::total 201132 # number of SCUpgradeReq accesses(hits+misses) 2006system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 5 # number of SCUpgradeFailReq accesses(hits+misses) 2007system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 5 # number of SCUpgradeFailReq accesses(hits+misses) 2008system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1119002 # number of ReadExReq accesses(hits+misses) 2009system.cpu1.l2cache.ReadExReq_accesses::total 1119002 # number of ReadExReq accesses(hits+misses) 2010system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 9231824 # number of ReadCleanReq accesses(hits+misses) 2011system.cpu1.l2cache.ReadCleanReq_accesses::total 9231824 # number of ReadCleanReq accesses(hits+misses) 2012system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 3751395 # number of ReadSharedReq accesses(hits+misses) 2013system.cpu1.l2cache.ReadSharedReq_accesses::total 3751395 # number of ReadSharedReq accesses(hits+misses) 2014system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 448771 # number of InvalidateReq accesses(hits+misses) 2015system.cpu1.l2cache.InvalidateReq_accesses::total 448771 # number of InvalidateReq accesses(hits+misses) 2016system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 588785 # number of demand (read+write) accesses 2017system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 176753 # number of demand (read+write) accesses 2018system.cpu1.l2cache.demand_accesses::cpu1.inst 9231824 # number of demand (read+write) accesses 2019system.cpu1.l2cache.demand_accesses::cpu1.data 4870397 # number of demand (read+write) accesses 2020system.cpu1.l2cache.demand_accesses::total 14867759 # number of demand (read+write) accesses 2021system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 588785 # number of overall (read+write) accesses 2022system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 176753 # number of overall (read+write) accesses 2023system.cpu1.l2cache.overall_accesses::cpu1.inst 9231824 # number of overall (read+write) accesses 2024system.cpu1.l2cache.overall_accesses::cpu1.data 4870397 # number of overall (read+write) accesses 2025system.cpu1.l2cache.overall_accesses::total 14867759 # number of overall (read+write) accesses 2026system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.020969 # miss rate for ReadReq accesses 2027system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.048271 # miss rate for ReadReq accesses 2028system.cpu1.l2cache.ReadReq_miss_rate::total 0.027272 # miss rate for ReadReq accesses 2029system.cpu1.l2cache.WritebackDirty_miss_rate::writebacks 0.000000 # miss rate for WritebackDirty accesses 2030system.cpu1.l2cache.WritebackDirty_miss_rate::total 0.000000 # miss rate for WritebackDirty accesses 2031system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.997432 # miss rate for UpgradeReq accesses 2032system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.997432 # miss rate for UpgradeReq accesses 2033system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses 2034system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 2035system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses 2036system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 2037system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.224878 # miss rate for ReadExReq accesses 2038system.cpu1.l2cache.ReadExReq_miss_rate::total 0.224878 # miss rate for ReadExReq accesses 2039system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.074364 # miss rate for ReadCleanReq accesses 2040system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.074364 # miss rate for ReadCleanReq accesses 2041system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.258574 # miss rate for ReadSharedReq accesses 2042system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.258574 # miss rate for ReadSharedReq accesses 2043system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.595475 # miss rate for InvalidateReq accesses 2044system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.595475 # miss rate for InvalidateReq accesses 2045system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.020969 # miss rate for demand accesses 2046system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.048271 # miss rate for demand accesses 2047system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.074364 # miss rate for demand accesses 2048system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.250832 # miss rate for demand accesses 2049system.cpu1.l2cache.demand_miss_rate::total 0.129747 # miss rate for demand accesses 2050system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.020969 # miss rate for overall accesses 2051system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.048271 # miss rate for overall accesses 2052system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.074364 # miss rate for overall accesses 2053system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.250832 # miss rate for overall accesses 2054system.cpu1.l2cache.overall_miss_rate::total 0.129747 # miss rate for overall accesses 2055system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 48550.745181 # average ReadReq miss latency 2056system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 53930.203938 # average ReadReq miss latency 2057system.cpu1.l2cache.ReadReq_avg_miss_latency::total 50749.113900 # average ReadReq miss latency 2058system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 14762.414761 # average UpgradeReq miss latency 2059system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 14762.414761 # average UpgradeReq miss latency 2060system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 9212.847782 # average SCUpgradeReq miss latency 2061system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 9212.847782 # average SCUpgradeReq miss latency 2062system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 930699.800000 # average SCUpgradeFailReq miss latency 2063system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 930699.800000 # average SCUpgradeFailReq miss latency 2064system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 58575.173165 # average ReadExReq miss latency 2065system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 58575.173165 # average ReadExReq miss latency 2066system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 35602.572693 # average ReadCleanReq miss latency 2067system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 35602.572693 # average ReadCleanReq miss latency 2068system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 39148.132540 # average ReadSharedReq miss latency 2069system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 39148.132540 # average ReadSharedReq miss latency 2070system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 70362.273231 # average InvalidateReq miss latency 2071system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 70362.273231 # average InvalidateReq miss latency 2072system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 48550.745181 # average overall miss latency 2073system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 53930.203938 # average overall miss latency 2074system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 35602.572693 # average overall miss latency 2075system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 43149.764000 # average overall miss latency 2076system.cpu1.l2cache.demand_avg_miss_latency::total 40546.084125 # average overall miss latency 2077system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 48550.745181 # average overall miss latency 2078system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 53930.203938 # average overall miss latency 2079system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 35602.572693 # average overall miss latency 2080system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 43149.764000 # average overall miss latency 2081system.cpu1.l2cache.overall_avg_miss_latency::total 40546.084125 # average overall miss latency 2082system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2083system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2084system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 2085system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 2086system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2087system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2088system.cpu1.l2cache.fast_writes 0 # number of fast writes performed 2089system.cpu1.l2cache.cache_copies 0 # number of cache copies performed 2090system.cpu1.l2cache.writebacks::writebacks 1166062 # number of writebacks 2091system.cpu1.l2cache.writebacks::total 1166062 # number of writebacks 2092system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 2 # number of ReadReq MSHR hits 2093system.cpu1.l2cache.ReadReq_mshr_hits::total 2 # number of ReadReq MSHR hits 2094system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 8177 # number of ReadExReq MSHR hits 2095system.cpu1.l2cache.ReadExReq_mshr_hits::total 8177 # number of ReadExReq MSHR hits 2096system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst 4 # number of ReadCleanReq MSHR hits 2097system.cpu1.l2cache.ReadCleanReq_mshr_hits::total 4 # number of ReadCleanReq MSHR hits 2098system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 786 # number of ReadSharedReq MSHR hits 2099system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 786 # number of ReadSharedReq MSHR hits 2100system.cpu1.l2cache.InvalidateReq_mshr_hits::cpu1.data 3 # number of InvalidateReq MSHR hits 2101system.cpu1.l2cache.InvalidateReq_mshr_hits::total 3 # number of InvalidateReq MSHR hits 2102system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 2 # number of demand (read+write) MSHR hits 2103system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 4 # number of demand (read+write) MSHR hits 2104system.cpu1.l2cache.demand_mshr_hits::cpu1.data 8963 # number of demand (read+write) MSHR hits 2105system.cpu1.l2cache.demand_mshr_hits::total 8969 # number of demand (read+write) MSHR hits 2106system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 2 # number of overall MSHR hits 2107system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 4 # number of overall MSHR hits 2108system.cpu1.l2cache.overall_mshr_hits::cpu1.data 8963 # number of overall MSHR hits 2109system.cpu1.l2cache.overall_mshr_hits::total 8969 # number of overall MSHR hits 2110system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 12346 # number of ReadReq MSHR misses 2111system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 8530 # number of ReadReq MSHR misses 2112system.cpu1.l2cache.ReadReq_mshr_misses::total 20876 # number of ReadReq MSHR misses 2113system.cpu1.l2cache.WritebackDirty_mshr_misses::writebacks 1 # number of WritebackDirty MSHR misses 2114system.cpu1.l2cache.WritebackDirty_mshr_misses::total 1 # number of WritebackDirty MSHR misses 2115system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 757140 # number of HardPFReq MSHR misses 2116system.cpu1.l2cache.HardPFReq_mshr_misses::total 757140 # number of HardPFReq MSHR misses 2117system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 223343 # number of UpgradeReq MSHR misses 2118system.cpu1.l2cache.UpgradeReq_mshr_misses::total 223343 # number of UpgradeReq MSHR misses 2119system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 201132 # number of SCUpgradeReq MSHR misses 2120system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 201132 # number of SCUpgradeReq MSHR misses 2121system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 5 # number of SCUpgradeFailReq MSHR misses 2122system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 5 # number of SCUpgradeFailReq MSHR misses 2123system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 243462 # number of ReadExReq MSHR misses 2124system.cpu1.l2cache.ReadExReq_mshr_misses::total 243462 # number of ReadExReq MSHR misses 2125system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 686514 # number of ReadCleanReq MSHR misses 2126system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 686514 # number of ReadCleanReq MSHR misses 2127system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 969227 # number of ReadSharedReq MSHR misses 2128system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 969227 # number of ReadSharedReq MSHR misses 2129system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data 267229 # number of InvalidateReq MSHR misses 2130system.cpu1.l2cache.InvalidateReq_mshr_misses::total 267229 # number of InvalidateReq MSHR misses 2131system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 12346 # number of demand (read+write) MSHR misses 2132system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 8530 # number of demand (read+write) MSHR misses 2133system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 686514 # number of demand (read+write) MSHR misses 2134system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1212689 # number of demand (read+write) MSHR misses 2135system.cpu1.l2cache.demand_mshr_misses::total 1920079 # number of demand (read+write) MSHR misses 2136system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 12346 # number of overall MSHR misses 2137system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 8530 # number of overall MSHR misses 2138system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 686514 # number of overall MSHR misses 2139system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1212689 # number of overall MSHR misses 2140system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 757140 # number of overall MSHR misses 2141system.cpu1.l2cache.overall_mshr_misses::total 2677219 # number of overall MSHR misses 2142system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 92 # number of ReadReq MSHR uncacheable 2143system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 19129 # number of ReadReq MSHR uncacheable 2144system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 19221 # number of ReadReq MSHR uncacheable 2145system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 17467 # number of WriteReq MSHR uncacheable 2146system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 17467 # number of WriteReq MSHR uncacheable 2147system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 92 # number of overall MSHR uncacheable misses 2148system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 36596 # number of overall MSHR uncacheable misses 2149system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 36688 # number of overall MSHR uncacheable misses 2150system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 525331500 # number of ReadReq MSHR miss cycles 2151system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 408923500 # number of ReadReq MSHR miss cycles 2152system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 934255000 # number of ReadReq MSHR miss cycles 2153system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 45309762891 # number of HardPFReq MSHR miss cycles 2154system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 45309762891 # number of HardPFReq MSHR miss cycles 2155system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 7082960998 # number of UpgradeReq MSHR miss cycles 2156system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 7082960998 # number of UpgradeReq MSHR miss cycles 2157system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 3799999000 # number of SCUpgradeReq MSHR miss cycles 2158system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 3799999000 # number of SCUpgradeReq MSHR miss cycles 2159system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 4287499 # number of SCUpgradeFailReq MSHR miss cycles 2160system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 4287499 # number of SCUpgradeFailReq MSHR miss cycles 2161system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 11990250000 # number of ReadExReq MSHR miss cycles 2162system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 11990250000 # number of ReadExReq MSHR miss cycles 2163system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 20322650500 # number of ReadCleanReq MSHR miss cycles 2164system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 20322650500 # number of ReadCleanReq MSHR miss cycles 2165system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 32101541990 # number of ReadSharedReq MSHR miss cycles 2166system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 32101541990 # number of ReadSharedReq MSHR miss cycles 2167system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 17199481500 # number of InvalidateReq MSHR miss cycles 2168system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 17199481500 # number of InvalidateReq MSHR miss cycles 2169system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 525331500 # number of demand (read+write) MSHR miss cycles 2170system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 408923500 # number of demand (read+write) MSHR miss cycles 2171system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 20322650500 # number of demand (read+write) MSHR miss cycles 2172system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 44091791990 # number of demand (read+write) MSHR miss cycles 2173system.cpu1.l2cache.demand_mshr_miss_latency::total 65348697490 # number of demand (read+write) MSHR miss cycles 2174system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 525331500 # number of overall MSHR miss cycles 2175system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 408923500 # number of overall MSHR miss cycles 2176system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 20322650500 # number of overall MSHR miss cycles 2177system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 44091791990 # number of overall MSHR miss cycles 2178system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 45309762891 # number of overall MSHR miss cycles 2179system.cpu1.l2cache.overall_mshr_miss_latency::total 110658460381 # number of overall MSHR miss cycles 2180system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 12214500 # number of ReadReq MSHR uncacheable cycles 2181system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 2998478000 # number of ReadReq MSHR uncacheable cycles 2182system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 3010692500 # number of ReadReq MSHR uncacheable cycles 2183system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 2831799500 # number of WriteReq MSHR uncacheable cycles 2184system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 2831799500 # number of WriteReq MSHR uncacheable cycles 2185system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 12214500 # number of overall MSHR uncacheable cycles 2186system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 5830277500 # number of overall MSHR uncacheable cycles 2187system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 5842492000 # number of overall MSHR uncacheable cycles 2188system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.020969 # mshr miss rate for ReadReq accesses 2189system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.048259 # mshr miss rate for ReadReq accesses 2190system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.027270 # mshr miss rate for ReadReq accesses 2191system.cpu1.l2cache.WritebackDirty_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for WritebackDirty accesses 2192system.cpu1.l2cache.WritebackDirty_mshr_miss_rate::total 0.000000 # mshr miss rate for WritebackDirty accesses 2193system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 2194system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 2195system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.997432 # mshr miss rate for UpgradeReq accesses 2196system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.997432 # mshr miss rate for UpgradeReq accesses 2197system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses 2198system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 2199system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses 2200system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 2201system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.217571 # mshr miss rate for ReadExReq accesses 2202system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.217571 # mshr miss rate for ReadExReq accesses 2203system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.074364 # mshr miss rate for ReadCleanReq accesses 2204system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.074364 # mshr miss rate for ReadCleanReq accesses 2205system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.258364 # mshr miss rate for ReadSharedReq accesses 2206system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.258364 # mshr miss rate for ReadSharedReq accesses 2207system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.595469 # mshr miss rate for InvalidateReq accesses 2208system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.595469 # mshr miss rate for InvalidateReq accesses 2209system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.020969 # mshr miss rate for demand accesses 2210system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.048259 # mshr miss rate for demand accesses 2211system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.074364 # mshr miss rate for demand accesses 2212system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.248992 # mshr miss rate for demand accesses 2213system.cpu1.l2cache.demand_mshr_miss_rate::total 0.129144 # mshr miss rate for demand accesses 2214system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.020969 # mshr miss rate for overall accesses 2215system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.048259 # mshr miss rate for overall accesses 2216system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.074364 # mshr miss rate for overall accesses 2217system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.248992 # mshr miss rate for overall accesses 2218system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses 2219system.cpu1.l2cache.overall_mshr_miss_rate::total 0.180069 # mshr miss rate for overall accesses 2220system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 42550.745181 # average ReadReq mshr miss latency 2221system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 47939.449004 # average ReadReq mshr miss latency 2222system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 44752.586702 # average ReadReq mshr miss latency 2223system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 59843.308887 # average HardPFReq mshr miss latency 2224system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 59843.308887 # average HardPFReq mshr miss latency 2225system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 31713.378069 # average UpgradeReq mshr miss latency 2226system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31713.378069 # average UpgradeReq mshr miss latency 2227system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18893.060279 # average SCUpgradeReq mshr miss latency 2228system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18893.060279 # average SCUpgradeReq mshr miss latency 2229system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 857499.800000 # average SCUpgradeFailReq mshr miss latency 2230system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 857499.800000 # average SCUpgradeFailReq mshr miss latency 2231system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 49248.958770 # average ReadExReq mshr miss latency 2232system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 49248.958770 # average ReadExReq mshr miss latency 2233system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 29602.674527 # average ReadCleanReq mshr miss latency 2234system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 29602.674527 # average ReadCleanReq mshr miss latency 2235system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 33120.767364 # average ReadSharedReq mshr miss latency 2236system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 33120.767364 # average ReadSharedReq mshr miss latency 2237system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 64362.331558 # average InvalidateReq mshr miss latency 2238system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 64362.331558 # average InvalidateReq mshr miss latency 2239system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 42550.745181 # average overall mshr miss latency 2240system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 47939.449004 # average overall mshr miss latency 2241system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 29602.674527 # average overall mshr miss latency 2242system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 36358.697069 # average overall mshr miss latency 2243system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 34034.379570 # average overall mshr miss latency 2244system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 42550.745181 # average overall mshr miss latency 2245system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 47939.449004 # average overall mshr miss latency 2246system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 29602.674527 # average overall mshr miss latency 2247system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 36358.697069 # average overall mshr miss latency 2248system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 59843.308887 # average overall mshr miss latency 2249system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 41333.361365 # average overall mshr miss latency 2250system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 132766.304348 # average ReadReq mshr uncacheable latency 2251system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 156750.379006 # average ReadReq mshr uncacheable latency 2252system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 156635.580875 # average ReadReq mshr uncacheable latency 2253system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 162122.831625 # average WriteReq mshr uncacheable latency 2254system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 162122.831625 # average WriteReq mshr uncacheable latency 2255system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 132766.304348 # average overall mshr uncacheable latency 2256system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 159314.610886 # average overall mshr uncacheable latency 2257system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 159248.037505 # average overall mshr uncacheable latency 2258system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 2259system.cpu1.toL2Bus.snoop_filter.tot_requests 29757775 # Total number of requests made to the snoop filter. 2260system.cpu1.toL2Bus.snoop_filter.hit_single_requests 15206900 # Number of requests hitting in the snoop filter with a single holder of the requested data. 2261system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 2197 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 2262system.cpu1.toL2Bus.snoop_filter.tot_snoops 2096240 # Total number of snoops made to the snoop filter. 2263system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 2095918 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 2264system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 322 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 2265system.cpu1.toL2Bus.trans_dist::ReadReq 863744 # Transaction distribution 2266system.cpu1.toL2Bus.trans_dist::ReadResp 13939008 # Transaction distribution 2267system.cpu1.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution 2268system.cpu1.toL2Bus.trans_dist::WriteReq 17467 # Transaction distribution 2269system.cpu1.toL2Bus.trans_dist::WriteResp 17467 # Transaction distribution 2270system.cpu1.toL2Bus.trans_dist::WritebackDirty 4436321 # Transaction distribution 2271system.cpu1.toL2Bus.trans_dist::WritebackClean 11191891 # Transaction distribution 2272system.cpu1.toL2Bus.trans_dist::CleanEvict 2888082 # Transaction distribution 2273system.cpu1.toL2Bus.trans_dist::HardPFReq 986942 # Transaction distribution 2274system.cpu1.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution 2275system.cpu1.toL2Bus.trans_dist::UpgradeReq 436269 # Transaction distribution 2276system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 365311 # Transaction distribution 2277system.cpu1.toL2Bus.trans_dist::UpgradeResp 490098 # Transaction distribution 2278system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 60 # Transaction distribution 2279system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 116 # Transaction distribution 2280system.cpu1.toL2Bus.trans_dist::ReadExReq 1199193 # Transaction distribution 2281system.cpu1.toL2Bus.trans_dist::ReadExResp 1126648 # Transaction distribution 2282system.cpu1.toL2Bus.trans_dist::ReadCleanReq 9231824 # Transaction distribution 2283system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4839539 # Transaction distribution 2284system.cpu1.toL2Bus.trans_dist::InvalidateReq 455831 # Transaction distribution 2285system.cpu1.toL2Bus.trans_dist::InvalidateResp 448771 # Transaction distribution 2286system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 27695142 # Packet count per connected master and slave (bytes) 2287system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16951918 # Packet count per connected master and slave (bytes) 2288system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 371352 # Packet count per connected master and slave (bytes) 2289system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1238709 # Packet count per connected master and slave (bytes) 2290system.cpu1.toL2Bus.pkt_count::total 46257121 # Packet count per connected master and slave (bytes) 2291system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1181646464 # Cumulative packet size per connected master and slave (bytes) 2292system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 652642726 # Cumulative packet size per connected master and slave (bytes) 2293system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1414024 # Cumulative packet size per connected master and slave (bytes) 2294system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4710280 # Cumulative packet size per connected master and slave (bytes) 2295system.cpu1.toL2Bus.pkt_size::total 1840413494 # Cumulative packet size per connected master and slave (bytes) 2296system.cpu1.toL2Bus.snoops 6842316 # Total snoops (count) 2297system.cpu1.toL2Bus.snoop_fanout::samples 22455736 # Request fanout histogram 2298system.cpu1.toL2Bus.snoop_fanout::mean 0.107935 # Request fanout histogram 2299system.cpu1.toL2Bus.snoop_fanout::stdev 0.310344 # Request fanout histogram 2300system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2301system.cpu1.toL2Bus.snoop_fanout::0 20032307 89.21% 89.21% # Request fanout histogram 2302system.cpu1.toL2Bus.snoop_fanout::1 2423107 10.79% 100.00% # Request fanout histogram 2303system.cpu1.toL2Bus.snoop_fanout::2 322 0.00% 100.00% # Request fanout histogram 2304system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2305system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 2306system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 2307system.cpu1.toL2Bus.snoop_fanout::total 22455736 # Request fanout histogram 2308system.cpu1.toL2Bus.reqLayer0.occupancy 29622476486 # Layer occupancy (ticks) 2309system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 2310system.cpu1.toL2Bus.snoopLayer0.occupancy 182393833 # Layer occupancy (ticks) 2311system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 2312system.cpu1.toL2Bus.respLayer0.occupancy 13851399924 # Layer occupancy (ticks) 2313system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 2314system.cpu1.toL2Bus.respLayer1.occupancy 7774596662 # Layer occupancy (ticks) 2315system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 2316system.cpu1.toL2Bus.respLayer2.occupancy 194664868 # Layer occupancy (ticks) 2317system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 2318system.cpu1.toL2Bus.respLayer3.occupancy 650073200 # Layer occupancy (ticks) 2319system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 2320system.iobus.trans_dist::ReadReq 40417 # Transaction distribution 2321system.iobus.trans_dist::ReadResp 40417 # Transaction distribution 2322system.iobus.trans_dist::WriteReq 136988 # Transaction distribution 2323system.iobus.trans_dist::WriteResp 136988 # Transaction distribution 2324system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47856 # Packet count per connected master and slave (bytes) 2325system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 2326system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 2327system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) 2328system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) 2329system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 2330system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 2331system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 2332system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 2333system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) 2334system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 2335system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29808 # Packet count per connected master and slave (bytes) 2336system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) 2337system.iobus.pkt_count_system.bridge.master::total 122998 # Packet count per connected master and slave (bytes) 2338system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231732 # Packet count per connected master and slave (bytes) 2339system.iobus.pkt_count_system.realview.ide.dma::total 231732 # Packet count per connected master and slave (bytes) 2340system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) 2341system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) 2342system.iobus.pkt_count::total 354810 # Packet count per connected master and slave (bytes) 2343system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47876 # Cumulative packet size per connected master and slave (bytes) 2344system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) 2345system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) 2346system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) 2347system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) 2348system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 2349system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2350system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2351system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2352system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) 2353system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2354system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17703 # Cumulative packet size per connected master and slave (bytes) 2355system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) 2356system.iobus.pkt_size_system.bridge.master::total 156013 # Cumulative packet size per connected master and slave (bytes) 2357system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7355280 # Cumulative packet size per connected master and slave (bytes) 2358system.iobus.pkt_size_system.realview.ide.dma::total 7355280 # Cumulative packet size per connected master and slave (bytes) 2359system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 2360system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) 2361system.iobus.pkt_size::total 7513379 # Cumulative packet size per connected master and slave (bytes) 2362system.iobus.reqLayer0.occupancy 47192501 # Layer occupancy (ticks) 2363system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 2364system.iobus.reqLayer1.occupancy 12000 # Layer occupancy (ticks) 2365system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 2366system.iobus.reqLayer2.occupancy 324000 # Layer occupancy (ticks) 2367system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 2368system.iobus.reqLayer3.occupancy 9500 # Layer occupancy (ticks) 2369system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 2370system.iobus.reqLayer4.occupancy 9500 # Layer occupancy (ticks) 2371system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 2372system.iobus.reqLayer10.occupancy 10000 # Layer occupancy (ticks) 2373system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 2374system.iobus.reqLayer13.occupancy 10500 # Layer occupancy (ticks) 2375system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 2376system.iobus.reqLayer14.occupancy 9000 # Layer occupancy (ticks) 2377system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 2378system.iobus.reqLayer15.occupancy 9500 # Layer occupancy (ticks) 2379system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 2380system.iobus.reqLayer16.occupancy 15500 # Layer occupancy (ticks) 2381system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 2382system.iobus.reqLayer17.occupancy 9500 # Layer occupancy (ticks) 2383system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 2384system.iobus.reqLayer23.occupancy 26190001 # Layer occupancy (ticks) 2385system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 2386system.iobus.reqLayer24.occupancy 36429000 # Layer occupancy (ticks) 2387system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 2388system.iobus.reqLayer25.occupancy 568769538 # Layer occupancy (ticks) 2389system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 2390system.iobus.respLayer0.occupancy 92997000 # Layer occupancy (ticks) 2391system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 2392system.iobus.respLayer3.occupancy 148172000 # Layer occupancy (ticks) 2393system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 2394system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) 2395system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) 2396system.iocache.tags.replacements 115847 # number of replacements 2397system.iocache.tags.tagsinuse 11.301670 # Cycle average of tags in use 2398system.iocache.tags.total_refs 3 # Total number of references to valid blocks. 2399system.iocache.tags.sampled_refs 115863 # Sample count of references to valid blocks. 2400system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. 2401system.iocache.tags.warmup_cycle 9145489939000 # Cycle when the warmup percentage was hit. 2402system.iocache.tags.occ_blocks::realview.ethernet 3.832621 # Average occupied blocks per requestor 2403system.iocache.tags.occ_blocks::realview.ide 7.469049 # Average occupied blocks per requestor 2404system.iocache.tags.occ_percent::realview.ethernet 0.239539 # Average percentage of cache occupancy 2405system.iocache.tags.occ_percent::realview.ide 0.466816 # Average percentage of cache occupancy 2406system.iocache.tags.occ_percent::total 0.706354 # Average percentage of cache occupancy 2407system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 2408system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 2409system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 2410system.iocache.tags.tag_accesses 1043151 # Number of tag accesses 2411system.iocache.tags.data_accesses 1043151 # Number of data accesses 2412system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses 2413system.iocache.ReadReq_misses::realview.ide 8882 # number of ReadReq misses 2414system.iocache.ReadReq_misses::total 8919 # number of ReadReq misses 2415system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 2416system.iocache.WriteReq_misses::total 3 # number of WriteReq misses 2417system.iocache.WriteLineReq_misses::realview.ide 106984 # number of WriteLineReq misses 2418system.iocache.WriteLineReq_misses::total 106984 # number of WriteLineReq misses 2419system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses 2420system.iocache.demand_misses::realview.ide 8882 # number of demand (read+write) misses 2421system.iocache.demand_misses::total 8922 # number of demand (read+write) misses 2422system.iocache.overall_misses::realview.ethernet 40 # number of overall misses 2423system.iocache.overall_misses::realview.ide 8882 # number of overall misses 2424system.iocache.overall_misses::total 8922 # number of overall misses 2425system.iocache.ReadReq_miss_latency::realview.ethernet 5198000 # number of ReadReq miss cycles 2426system.iocache.ReadReq_miss_latency::realview.ide 1701700997 # number of ReadReq miss cycles 2427system.iocache.ReadReq_miss_latency::total 1706898997 # number of ReadReq miss cycles 2428system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles 2429system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles 2430system.iocache.WriteLineReq_miss_latency::realview.ide 13567134541 # number of WriteLineReq miss cycles 2431system.iocache.WriteLineReq_miss_latency::total 13567134541 # number of WriteLineReq miss cycles 2432system.iocache.demand_miss_latency::realview.ethernet 5567000 # number of demand (read+write) miss cycles 2433system.iocache.demand_miss_latency::realview.ide 1701700997 # number of demand (read+write) miss cycles 2434system.iocache.demand_miss_latency::total 1707267997 # number of demand (read+write) miss cycles 2435system.iocache.overall_miss_latency::realview.ethernet 5567000 # number of overall miss cycles 2436system.iocache.overall_miss_latency::realview.ide 1701700997 # number of overall miss cycles 2437system.iocache.overall_miss_latency::total 1707267997 # number of overall miss cycles 2438system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) 2439system.iocache.ReadReq_accesses::realview.ide 8882 # number of ReadReq accesses(hits+misses) 2440system.iocache.ReadReq_accesses::total 8919 # number of ReadReq accesses(hits+misses) 2441system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 2442system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 2443system.iocache.WriteLineReq_accesses::realview.ide 106984 # number of WriteLineReq accesses(hits+misses) 2444system.iocache.WriteLineReq_accesses::total 106984 # number of WriteLineReq accesses(hits+misses) 2445system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses 2446system.iocache.demand_accesses::realview.ide 8882 # number of demand (read+write) accesses 2447system.iocache.demand_accesses::total 8922 # number of demand (read+write) accesses 2448system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses 2449system.iocache.overall_accesses::realview.ide 8882 # number of overall (read+write) accesses 2450system.iocache.overall_accesses::total 8922 # number of overall (read+write) accesses 2451system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 2452system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 2453system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 2454system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 2455system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 2456system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 2457system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 2458system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses 2459system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 2460system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 2461system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses 2462system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 2463system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 2464system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140486.486486 # average ReadReq miss latency 2465system.iocache.ReadReq_avg_miss_latency::realview.ide 191589.844292 # average ReadReq miss latency 2466system.iocache.ReadReq_avg_miss_latency::total 191377.844714 # average ReadReq miss latency 2467system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency 2468system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency 2469system.iocache.WriteLineReq_avg_miss_latency::realview.ide 126814.612849 # average WriteLineReq miss latency 2470system.iocache.WriteLineReq_avg_miss_latency::total 126814.612849 # average WriteLineReq miss latency 2471system.iocache.demand_avg_miss_latency::realview.ethernet 139175 # average overall miss latency 2472system.iocache.demand_avg_miss_latency::realview.ide 191589.844292 # average overall miss latency 2473system.iocache.demand_avg_miss_latency::total 191354.852836 # average overall miss latency 2474system.iocache.overall_avg_miss_latency::realview.ethernet 139175 # average overall miss latency 2475system.iocache.overall_avg_miss_latency::realview.ide 191589.844292 # average overall miss latency 2476system.iocache.overall_avg_miss_latency::total 191354.852836 # average overall miss latency 2477system.iocache.blocked_cycles::no_mshrs 34809 # number of cycles access was blocked 2478system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2479system.iocache.blocked::no_mshrs 3501 # number of cycles access was blocked 2480system.iocache.blocked::no_targets 0 # number of cycles access was blocked 2481system.iocache.avg_blocked_cycles::no_mshrs 9.942588 # average number of cycles each access was blocked 2482system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2483system.iocache.fast_writes 0 # number of fast writes performed 2484system.iocache.cache_copies 0 # number of cache copies performed 2485system.iocache.writebacks::writebacks 106950 # number of writebacks 2486system.iocache.writebacks::total 106950 # number of writebacks 2487system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses 2488system.iocache.ReadReq_mshr_misses::realview.ide 8882 # number of ReadReq MSHR misses 2489system.iocache.ReadReq_mshr_misses::total 8919 # number of ReadReq MSHR misses 2490system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses 2491system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses 2492system.iocache.WriteLineReq_mshr_misses::realview.ide 106984 # number of WriteLineReq MSHR misses 2493system.iocache.WriteLineReq_mshr_misses::total 106984 # number of WriteLineReq MSHR misses 2494system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses 2495system.iocache.demand_mshr_misses::realview.ide 8882 # number of demand (read+write) MSHR misses 2496system.iocache.demand_mshr_misses::total 8922 # number of demand (read+write) MSHR misses 2497system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses 2498system.iocache.overall_mshr_misses::realview.ide 8882 # number of overall MSHR misses 2499system.iocache.overall_mshr_misses::total 8922 # number of overall MSHR misses 2500system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3348000 # number of ReadReq MSHR miss cycles 2501system.iocache.ReadReq_mshr_miss_latency::realview.ide 1257600997 # number of ReadReq MSHR miss cycles 2502system.iocache.ReadReq_mshr_miss_latency::total 1260948997 # number of ReadReq MSHR miss cycles 2503system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles 2504system.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles 2505system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8211460570 # number of WriteLineReq MSHR miss cycles 2506system.iocache.WriteLineReq_mshr_miss_latency::total 8211460570 # number of WriteLineReq MSHR miss cycles 2507system.iocache.demand_mshr_miss_latency::realview.ethernet 3567000 # number of demand (read+write) MSHR miss cycles 2508system.iocache.demand_mshr_miss_latency::realview.ide 1257600997 # number of demand (read+write) MSHR miss cycles 2509system.iocache.demand_mshr_miss_latency::total 1261167997 # number of demand (read+write) MSHR miss cycles 2510system.iocache.overall_mshr_miss_latency::realview.ethernet 3567000 # number of overall MSHR miss cycles 2511system.iocache.overall_mshr_miss_latency::realview.ide 1257600997 # number of overall MSHR miss cycles 2512system.iocache.overall_mshr_miss_latency::total 1261167997 # number of overall MSHR miss cycles 2513system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses 2514system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 2515system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 2516system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses 2517system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 2518system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 2519system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 2520system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses 2521system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 2522system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 2523system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses 2524system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 2525system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 2526system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90486.486486 # average ReadReq mshr miss latency 2527system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 141589.844292 # average ReadReq mshr miss latency 2528system.iocache.ReadReq_avg_mshr_miss_latency::total 141377.844714 # average ReadReq mshr miss latency 2529system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency 2530system.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency 2531system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 76754.099398 # average WriteLineReq mshr miss latency 2532system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76754.099398 # average WriteLineReq mshr miss latency 2533system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89175 # average overall mshr miss latency 2534system.iocache.demand_avg_mshr_miss_latency::realview.ide 141589.844292 # average overall mshr miss latency 2535system.iocache.demand_avg_mshr_miss_latency::total 141354.852836 # average overall mshr miss latency 2536system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89175 # average overall mshr miss latency 2537system.iocache.overall_avg_mshr_miss_latency::realview.ide 141589.844292 # average overall mshr miss latency 2538system.iocache.overall_avg_mshr_miss_latency::total 141354.852836 # average overall mshr miss latency 2539system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 2540system.l2c.tags.replacements 1465460 # number of replacements 2541system.l2c.tags.tagsinuse 62985.288046 # Cycle average of tags in use 2542system.l2c.tags.total_refs 6746847 # Total number of references to valid blocks. 2543system.l2c.tags.sampled_refs 1525111 # Sample count of references to valid blocks. 2544system.l2c.tags.avg_refs 4.423840 # Average number of references to valid blocks. 2545system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 2546system.l2c.tags.occ_blocks::writebacks 21606.771340 # Average occupied blocks per requestor 2547system.l2c.tags.occ_blocks::cpu0.dtb.walker 163.937701 # Average occupied blocks per requestor 2548system.l2c.tags.occ_blocks::cpu0.itb.walker 223.248695 # Average occupied blocks per requestor 2549system.l2c.tags.occ_blocks::cpu0.inst 5669.657556 # Average occupied blocks per requestor 2550system.l2c.tags.occ_blocks::cpu0.data 6460.370404 # Average occupied blocks per requestor 2551system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 9729.240754 # Average occupied blocks per requestor 2552system.l2c.tags.occ_blocks::cpu1.dtb.walker 163.294328 # Average occupied blocks per requestor 2553system.l2c.tags.occ_blocks::cpu1.itb.walker 204.500397 # Average occupied blocks per requestor 2554system.l2c.tags.occ_blocks::cpu1.inst 3331.837675 # Average occupied blocks per requestor 2555system.l2c.tags.occ_blocks::cpu1.data 6323.626930 # Average occupied blocks per requestor 2556system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 9108.802265 # Average occupied blocks per requestor 2557system.l2c.tags.occ_percent::writebacks 0.329693 # Average percentage of cache occupancy 2558system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002501 # Average percentage of cache occupancy 2559system.l2c.tags.occ_percent::cpu0.itb.walker 0.003407 # Average percentage of cache occupancy 2560system.l2c.tags.occ_percent::cpu0.inst 0.086512 # Average percentage of cache occupancy 2561system.l2c.tags.occ_percent::cpu0.data 0.098577 # Average percentage of cache occupancy 2562system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.148456 # Average percentage of cache occupancy 2563system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002492 # Average percentage of cache occupancy 2564system.l2c.tags.occ_percent::cpu1.itb.walker 0.003120 # Average percentage of cache occupancy 2565system.l2c.tags.occ_percent::cpu1.inst 0.050840 # Average percentage of cache occupancy 2566system.l2c.tags.occ_percent::cpu1.data 0.096491 # Average percentage of cache occupancy 2567system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.138989 # Average percentage of cache occupancy 2568system.l2c.tags.occ_percent::total 0.961079 # Average percentage of cache occupancy 2569system.l2c.tags.occ_task_id_blocks::1022 9038 # Occupied blocks per task id 2570system.l2c.tags.occ_task_id_blocks::1023 217 # Occupied blocks per task id 2571system.l2c.tags.occ_task_id_blocks::1024 50396 # Occupied blocks per task id 2572system.l2c.tags.age_task_id_blocks_1022::1 130 # Occupied blocks per task id 2573system.l2c.tags.age_task_id_blocks_1022::2 134 # Occupied blocks per task id 2574system.l2c.tags.age_task_id_blocks_1022::3 1705 # Occupied blocks per task id 2575system.l2c.tags.age_task_id_blocks_1022::4 7069 # Occupied blocks per task id 2576system.l2c.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id 2577system.l2c.tags.age_task_id_blocks_1023::2 6 # Occupied blocks per task id 2578system.l2c.tags.age_task_id_blocks_1023::3 23 # Occupied blocks per task id 2579system.l2c.tags.age_task_id_blocks_1023::4 187 # Occupied blocks per task id 2580system.l2c.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id 2581system.l2c.tags.age_task_id_blocks_1024::1 313 # Occupied blocks per task id 2582system.l2c.tags.age_task_id_blocks_1024::2 2486 # Occupied blocks per task id 2583system.l2c.tags.age_task_id_blocks_1024::3 12173 # Occupied blocks per task id 2584system.l2c.tags.age_task_id_blocks_1024::4 35392 # Occupied blocks per task id 2585system.l2c.tags.occ_task_id_percent::1022 0.137909 # Percentage of cache occupancy per task id 2586system.l2c.tags.occ_task_id_percent::1023 0.003311 # Percentage of cache occupancy per task id 2587system.l2c.tags.occ_task_id_percent::1024 0.768982 # Percentage of cache occupancy per task id 2588system.l2c.tags.tag_accesses 82649960 # Number of tag accesses 2589system.l2c.tags.data_accesses 82649960 # Number of data accesses 2590system.l2c.WritebackDirty_hits::writebacks 2868119 # number of WritebackDirty hits 2591system.l2c.WritebackDirty_hits::total 2868119 # number of WritebackDirty hits 2592system.l2c.UpgradeReq_hits::cpu0.data 181384 # number of UpgradeReq hits 2593system.l2c.UpgradeReq_hits::cpu1.data 131978 # number of UpgradeReq hits 2594system.l2c.UpgradeReq_hits::total 313362 # number of UpgradeReq hits 2595system.l2c.SCUpgradeReq_hits::cpu0.data 45809 # number of SCUpgradeReq hits 2596system.l2c.SCUpgradeReq_hits::cpu1.data 40059 # number of SCUpgradeReq hits 2597system.l2c.SCUpgradeReq_hits::total 85868 # number of SCUpgradeReq hits 2598system.l2c.ReadExReq_hits::cpu0.data 200580 # number of ReadExReq hits 2599system.l2c.ReadExReq_hits::cpu1.data 165707 # number of ReadExReq hits 2600system.l2c.ReadExReq_hits::total 366287 # number of ReadExReq hits 2601system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 7480 # number of ReadSharedReq hits 2602system.l2c.ReadSharedReq_hits::cpu0.itb.walker 5183 # number of ReadSharedReq hits 2603system.l2c.ReadSharedReq_hits::cpu0.inst 699361 # number of ReadSharedReq hits 2604system.l2c.ReadSharedReq_hits::cpu0.data 660994 # number of ReadSharedReq hits 2605system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 342500 # number of ReadSharedReq hits 2606system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 6176 # number of ReadSharedReq hits 2607system.l2c.ReadSharedReq_hits::cpu1.itb.walker 4038 # number of ReadSharedReq hits 2608system.l2c.ReadSharedReq_hits::cpu1.inst 639412 # number of ReadSharedReq hits 2609system.l2c.ReadSharedReq_hits::cpu1.data 580820 # number of ReadSharedReq hits 2610system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 295958 # number of ReadSharedReq hits 2611system.l2c.ReadSharedReq_hits::total 3241922 # number of ReadSharedReq hits 2612system.l2c.demand_hits::cpu0.dtb.walker 7480 # number of demand (read+write) hits 2613system.l2c.demand_hits::cpu0.itb.walker 5183 # number of demand (read+write) hits 2614system.l2c.demand_hits::cpu0.inst 699361 # number of demand (read+write) hits 2615system.l2c.demand_hits::cpu0.data 861574 # number of demand (read+write) hits 2616system.l2c.demand_hits::cpu0.l2cache.prefetcher 342500 # number of demand (read+write) hits 2617system.l2c.demand_hits::cpu1.dtb.walker 6176 # number of demand (read+write) hits 2618system.l2c.demand_hits::cpu1.itb.walker 4038 # number of demand (read+write) hits 2619system.l2c.demand_hits::cpu1.inst 639412 # number of demand (read+write) hits 2620system.l2c.demand_hits::cpu1.data 746527 # number of demand (read+write) hits 2621system.l2c.demand_hits::cpu1.l2cache.prefetcher 295958 # number of demand (read+write) hits 2622system.l2c.demand_hits::total 3608209 # number of demand (read+write) hits 2623system.l2c.overall_hits::cpu0.dtb.walker 7480 # number of overall hits 2624system.l2c.overall_hits::cpu0.itb.walker 5183 # number of overall hits 2625system.l2c.overall_hits::cpu0.inst 699361 # number of overall hits 2626system.l2c.overall_hits::cpu0.data 861574 # number of overall hits 2627system.l2c.overall_hits::cpu0.l2cache.prefetcher 342500 # number of overall hits 2628system.l2c.overall_hits::cpu1.dtb.walker 6176 # number of overall hits 2629system.l2c.overall_hits::cpu1.itb.walker 4038 # number of overall hits 2630system.l2c.overall_hits::cpu1.inst 639412 # number of overall hits 2631system.l2c.overall_hits::cpu1.data 746527 # number of overall hits 2632system.l2c.overall_hits::cpu1.l2cache.prefetcher 295958 # number of overall hits 2633system.l2c.overall_hits::total 3608209 # number of overall hits 2634system.l2c.UpgradeReq_misses::cpu0.data 61552 # number of UpgradeReq misses 2635system.l2c.UpgradeReq_misses::cpu1.data 61783 # number of UpgradeReq misses 2636system.l2c.UpgradeReq_misses::total 123335 # number of UpgradeReq misses 2637system.l2c.SCUpgradeReq_misses::cpu0.data 12334 # number of SCUpgradeReq misses 2638system.l2c.SCUpgradeReq_misses::cpu1.data 11273 # number of SCUpgradeReq misses 2639system.l2c.SCUpgradeReq_misses::total 23607 # number of SCUpgradeReq misses 2640system.l2c.ReadExReq_misses::cpu0.data 493827 # number of ReadExReq misses 2641system.l2c.ReadExReq_misses::cpu1.data 156178 # number of ReadExReq misses 2642system.l2c.ReadExReq_misses::total 650005 # number of ReadExReq misses 2643system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 2015 # number of ReadSharedReq misses 2644system.l2c.ReadSharedReq_misses::cpu0.itb.walker 1763 # number of ReadSharedReq misses 2645system.l2c.ReadSharedReq_misses::cpu0.inst 75880 # number of ReadSharedReq misses 2646system.l2c.ReadSharedReq_misses::cpu0.data 147884 # number of ReadSharedReq misses 2647system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 232018 # number of ReadSharedReq misses 2648system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 2405 # number of ReadSharedReq misses 2649system.l2c.ReadSharedReq_misses::cpu1.itb.walker 2064 # number of ReadSharedReq misses 2650system.l2c.ReadSharedReq_misses::cpu1.inst 47101 # number of ReadSharedReq misses 2651system.l2c.ReadSharedReq_misses::cpu1.data 114695 # number of ReadSharedReq misses 2652system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 237376 # number of ReadSharedReq misses 2653system.l2c.ReadSharedReq_misses::total 863201 # number of ReadSharedReq misses 2654system.l2c.demand_misses::cpu0.dtb.walker 2015 # number of demand (read+write) misses 2655system.l2c.demand_misses::cpu0.itb.walker 1763 # number of demand (read+write) misses 2656system.l2c.demand_misses::cpu0.inst 75880 # number of demand (read+write) misses 2657system.l2c.demand_misses::cpu0.data 641711 # number of demand (read+write) misses 2658system.l2c.demand_misses::cpu0.l2cache.prefetcher 232018 # number of demand (read+write) misses 2659system.l2c.demand_misses::cpu1.dtb.walker 2405 # number of demand (read+write) misses 2660system.l2c.demand_misses::cpu1.itb.walker 2064 # number of demand (read+write) misses 2661system.l2c.demand_misses::cpu1.inst 47101 # number of demand (read+write) misses 2662system.l2c.demand_misses::cpu1.data 270873 # number of demand (read+write) misses 2663system.l2c.demand_misses::cpu1.l2cache.prefetcher 237376 # number of demand (read+write) misses 2664system.l2c.demand_misses::total 1513206 # number of demand (read+write) misses 2665system.l2c.overall_misses::cpu0.dtb.walker 2015 # number of overall misses 2666system.l2c.overall_misses::cpu0.itb.walker 1763 # number of overall misses 2667system.l2c.overall_misses::cpu0.inst 75880 # number of overall misses 2668system.l2c.overall_misses::cpu0.data 641711 # number of overall misses 2669system.l2c.overall_misses::cpu0.l2cache.prefetcher 232018 # number of overall misses 2670system.l2c.overall_misses::cpu1.dtb.walker 2405 # number of overall misses 2671system.l2c.overall_misses::cpu1.itb.walker 2064 # number of overall misses 2672system.l2c.overall_misses::cpu1.inst 47101 # number of overall misses 2673system.l2c.overall_misses::cpu1.data 270873 # number of overall misses 2674system.l2c.overall_misses::cpu1.l2cache.prefetcher 237376 # number of overall misses 2675system.l2c.overall_misses::total 1513206 # number of overall misses 2676system.l2c.UpgradeReq_miss_latency::cpu0.data 1080728500 # number of UpgradeReq miss cycles 2677system.l2c.UpgradeReq_miss_latency::cpu1.data 1074141000 # number of UpgradeReq miss cycles 2678system.l2c.UpgradeReq_miss_latency::total 2154869500 # number of UpgradeReq miss cycles 2679system.l2c.SCUpgradeReq_miss_latency::cpu0.data 192695000 # number of SCUpgradeReq miss cycles 2680system.l2c.SCUpgradeReq_miss_latency::cpu1.data 205559500 # number of SCUpgradeReq miss cycles 2681system.l2c.SCUpgradeReq_miss_latency::total 398254500 # number of SCUpgradeReq miss cycles 2682system.l2c.ReadExReq_miss_latency::cpu0.data 68952537500 # number of ReadExReq miss cycles 2683system.l2c.ReadExReq_miss_latency::cpu1.data 21260978999 # number of ReadExReq miss cycles 2684system.l2c.ReadExReq_miss_latency::total 90213516499 # number of ReadExReq miss cycles 2685system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 283038500 # number of ReadSharedReq miss cycles 2686system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 248472000 # number of ReadSharedReq miss cycles 2687system.l2c.ReadSharedReq_miss_latency::cpu0.inst 10197968500 # number of ReadSharedReq miss cycles 2688system.l2c.ReadSharedReq_miss_latency::cpu0.data 20619201500 # number of ReadSharedReq miss cycles 2689system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 38762108448 # number of ReadSharedReq miss cycles 2690system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 338612000 # number of ReadSharedReq miss cycles 2691system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 290311500 # number of ReadSharedReq miss cycles 2692system.l2c.ReadSharedReq_miss_latency::cpu1.inst 6337057500 # number of ReadSharedReq miss cycles 2693system.l2c.ReadSharedReq_miss_latency::cpu1.data 16104459500 # number of ReadSharedReq miss cycles 2694system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 39857778585 # number of ReadSharedReq miss cycles 2695system.l2c.ReadSharedReq_miss_latency::total 133039008033 # number of ReadSharedReq miss cycles 2696system.l2c.demand_miss_latency::cpu0.dtb.walker 283038500 # number of demand (read+write) miss cycles 2697system.l2c.demand_miss_latency::cpu0.itb.walker 248472000 # number of demand (read+write) miss cycles 2698system.l2c.demand_miss_latency::cpu0.inst 10197968500 # number of demand (read+write) miss cycles 2699system.l2c.demand_miss_latency::cpu0.data 89571739000 # number of demand (read+write) miss cycles 2700system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 38762108448 # number of demand (read+write) miss cycles 2701system.l2c.demand_miss_latency::cpu1.dtb.walker 338612000 # number of demand (read+write) miss cycles 2702system.l2c.demand_miss_latency::cpu1.itb.walker 290311500 # number of demand (read+write) miss cycles 2703system.l2c.demand_miss_latency::cpu1.inst 6337057500 # number of demand (read+write) miss cycles 2704system.l2c.demand_miss_latency::cpu1.data 37365438499 # number of demand (read+write) miss cycles 2705system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 39857778585 # number of demand (read+write) miss cycles 2706system.l2c.demand_miss_latency::total 223252524532 # number of demand (read+write) miss cycles 2707system.l2c.overall_miss_latency::cpu0.dtb.walker 283038500 # number of overall miss cycles 2708system.l2c.overall_miss_latency::cpu0.itb.walker 248472000 # number of overall miss cycles 2709system.l2c.overall_miss_latency::cpu0.inst 10197968500 # number of overall miss cycles 2710system.l2c.overall_miss_latency::cpu0.data 89571739000 # number of overall miss cycles 2711system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 38762108448 # number of overall miss cycles 2712system.l2c.overall_miss_latency::cpu1.dtb.walker 338612000 # number of overall miss cycles 2713system.l2c.overall_miss_latency::cpu1.itb.walker 290311500 # number of overall miss cycles 2714system.l2c.overall_miss_latency::cpu1.inst 6337057500 # number of overall miss cycles 2715system.l2c.overall_miss_latency::cpu1.data 37365438499 # number of overall miss cycles 2716system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 39857778585 # number of overall miss cycles 2717system.l2c.overall_miss_latency::total 223252524532 # number of overall miss cycles 2718system.l2c.WritebackDirty_accesses::writebacks 2868119 # number of WritebackDirty accesses(hits+misses) 2719system.l2c.WritebackDirty_accesses::total 2868119 # number of WritebackDirty accesses(hits+misses) 2720system.l2c.UpgradeReq_accesses::cpu0.data 242936 # number of UpgradeReq accesses(hits+misses) 2721system.l2c.UpgradeReq_accesses::cpu1.data 193761 # number of UpgradeReq accesses(hits+misses) 2722system.l2c.UpgradeReq_accesses::total 436697 # number of UpgradeReq accesses(hits+misses) 2723system.l2c.SCUpgradeReq_accesses::cpu0.data 58143 # number of SCUpgradeReq accesses(hits+misses) 2724system.l2c.SCUpgradeReq_accesses::cpu1.data 51332 # number of SCUpgradeReq accesses(hits+misses) 2725system.l2c.SCUpgradeReq_accesses::total 109475 # number of SCUpgradeReq accesses(hits+misses) 2726system.l2c.ReadExReq_accesses::cpu0.data 694407 # number of ReadExReq accesses(hits+misses) 2727system.l2c.ReadExReq_accesses::cpu1.data 321885 # number of ReadExReq accesses(hits+misses) 2728system.l2c.ReadExReq_accesses::total 1016292 # number of ReadExReq accesses(hits+misses) 2729system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 9495 # number of ReadSharedReq accesses(hits+misses) 2730system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 6946 # number of ReadSharedReq accesses(hits+misses) 2731system.l2c.ReadSharedReq_accesses::cpu0.inst 775241 # number of ReadSharedReq accesses(hits+misses) 2732system.l2c.ReadSharedReq_accesses::cpu0.data 808878 # number of ReadSharedReq accesses(hits+misses) 2733system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 574518 # number of ReadSharedReq accesses(hits+misses) 2734system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 8581 # number of ReadSharedReq accesses(hits+misses) 2735system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 6102 # number of ReadSharedReq accesses(hits+misses) 2736system.l2c.ReadSharedReq_accesses::cpu1.inst 686513 # number of ReadSharedReq accesses(hits+misses) 2737system.l2c.ReadSharedReq_accesses::cpu1.data 695515 # number of ReadSharedReq accesses(hits+misses) 2738system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 533334 # number of ReadSharedReq accesses(hits+misses) 2739system.l2c.ReadSharedReq_accesses::total 4105123 # number of ReadSharedReq accesses(hits+misses) 2740system.l2c.demand_accesses::cpu0.dtb.walker 9495 # number of demand (read+write) accesses 2741system.l2c.demand_accesses::cpu0.itb.walker 6946 # number of demand (read+write) accesses 2742system.l2c.demand_accesses::cpu0.inst 775241 # number of demand (read+write) accesses 2743system.l2c.demand_accesses::cpu0.data 1503285 # number of demand (read+write) accesses 2744system.l2c.demand_accesses::cpu0.l2cache.prefetcher 574518 # number of demand (read+write) accesses 2745system.l2c.demand_accesses::cpu1.dtb.walker 8581 # number of demand (read+write) accesses 2746system.l2c.demand_accesses::cpu1.itb.walker 6102 # number of demand (read+write) accesses 2747system.l2c.demand_accesses::cpu1.inst 686513 # number of demand (read+write) accesses 2748system.l2c.demand_accesses::cpu1.data 1017400 # number of demand (read+write) accesses 2749system.l2c.demand_accesses::cpu1.l2cache.prefetcher 533334 # number of demand (read+write) accesses 2750system.l2c.demand_accesses::total 5121415 # number of demand (read+write) accesses 2751system.l2c.overall_accesses::cpu0.dtb.walker 9495 # number of overall (read+write) accesses 2752system.l2c.overall_accesses::cpu0.itb.walker 6946 # number of overall (read+write) accesses 2753system.l2c.overall_accesses::cpu0.inst 775241 # number of overall (read+write) accesses 2754system.l2c.overall_accesses::cpu0.data 1503285 # number of overall (read+write) accesses 2755system.l2c.overall_accesses::cpu0.l2cache.prefetcher 574518 # number of overall (read+write) accesses 2756system.l2c.overall_accesses::cpu1.dtb.walker 8581 # number of overall (read+write) accesses 2757system.l2c.overall_accesses::cpu1.itb.walker 6102 # number of overall (read+write) accesses 2758system.l2c.overall_accesses::cpu1.inst 686513 # number of overall (read+write) accesses 2759system.l2c.overall_accesses::cpu1.data 1017400 # number of overall (read+write) accesses 2760system.l2c.overall_accesses::cpu1.l2cache.prefetcher 533334 # number of overall (read+write) accesses 2761system.l2c.overall_accesses::total 5121415 # number of overall (read+write) accesses 2762system.l2c.UpgradeReq_miss_rate::cpu0.data 0.253367 # miss rate for UpgradeReq accesses 2763system.l2c.UpgradeReq_miss_rate::cpu1.data 0.318862 # miss rate for UpgradeReq accesses 2764system.l2c.UpgradeReq_miss_rate::total 0.282427 # miss rate for UpgradeReq accesses 2765system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.212132 # miss rate for SCUpgradeReq accesses 2766system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.219610 # miss rate for SCUpgradeReq accesses 2767system.l2c.SCUpgradeReq_miss_rate::total 0.215638 # miss rate for SCUpgradeReq accesses 2768system.l2c.ReadExReq_miss_rate::cpu0.data 0.711149 # miss rate for ReadExReq accesses 2769system.l2c.ReadExReq_miss_rate::cpu1.data 0.485198 # miss rate for ReadExReq accesses 2770system.l2c.ReadExReq_miss_rate::total 0.639585 # miss rate for ReadExReq accesses 2771system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.212217 # miss rate for ReadSharedReq accesses 2772system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.253815 # miss rate for ReadSharedReq accesses 2773system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.097879 # miss rate for ReadSharedReq accesses 2774system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.182826 # miss rate for ReadSharedReq accesses 2775system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.403848 # miss rate for ReadSharedReq accesses 2776system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.280270 # miss rate for ReadSharedReq accesses 2777system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.338250 # miss rate for ReadSharedReq accesses 2778system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.068609 # miss rate for ReadSharedReq accesses 2779system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.164907 # miss rate for ReadSharedReq accesses 2780system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.445079 # miss rate for ReadSharedReq accesses 2781system.l2c.ReadSharedReq_miss_rate::total 0.210274 # miss rate for ReadSharedReq accesses 2782system.l2c.demand_miss_rate::cpu0.dtb.walker 0.212217 # miss rate for demand accesses 2783system.l2c.demand_miss_rate::cpu0.itb.walker 0.253815 # miss rate for demand accesses 2784system.l2c.demand_miss_rate::cpu0.inst 0.097879 # miss rate for demand accesses 2785system.l2c.demand_miss_rate::cpu0.data 0.426872 # miss rate for demand accesses 2786system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.403848 # miss rate for demand accesses 2787system.l2c.demand_miss_rate::cpu1.dtb.walker 0.280270 # miss rate for demand accesses 2788system.l2c.demand_miss_rate::cpu1.itb.walker 0.338250 # miss rate for demand accesses 2789system.l2c.demand_miss_rate::cpu1.inst 0.068609 # miss rate for demand accesses 2790system.l2c.demand_miss_rate::cpu1.data 0.266240 # miss rate for demand accesses 2791system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.445079 # miss rate for demand accesses 2792system.l2c.demand_miss_rate::total 0.295466 # miss rate for demand accesses 2793system.l2c.overall_miss_rate::cpu0.dtb.walker 0.212217 # miss rate for overall accesses 2794system.l2c.overall_miss_rate::cpu0.itb.walker 0.253815 # miss rate for overall accesses 2795system.l2c.overall_miss_rate::cpu0.inst 0.097879 # miss rate for overall accesses 2796system.l2c.overall_miss_rate::cpu0.data 0.426872 # miss rate for overall accesses 2797system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.403848 # miss rate for overall accesses 2798system.l2c.overall_miss_rate::cpu1.dtb.walker 0.280270 # miss rate for overall accesses 2799system.l2c.overall_miss_rate::cpu1.itb.walker 0.338250 # miss rate for overall accesses 2800system.l2c.overall_miss_rate::cpu1.inst 0.068609 # miss rate for overall accesses 2801system.l2c.overall_miss_rate::cpu1.data 0.266240 # miss rate for overall accesses 2802system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.445079 # miss rate for overall accesses 2803system.l2c.overall_miss_rate::total 0.295466 # miss rate for overall accesses 2804system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 17557.975370 # average UpgradeReq miss latency 2805system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 17385.704806 # average UpgradeReq miss latency 2806system.l2c.UpgradeReq_avg_miss_latency::total 17471.678761 # average UpgradeReq miss latency 2807system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 15623.074428 # average SCUpgradeReq miss latency 2808system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 18234.675774 # average SCUpgradeReq miss latency 2809system.l2c.SCUpgradeReq_avg_miss_latency::total 16870.186809 # average SCUpgradeReq miss latency 2810system.l2c.ReadExReq_avg_miss_latency::cpu0.data 139628.933817 # average ReadExReq miss latency 2811system.l2c.ReadExReq_avg_miss_latency::cpu1.data 136132.995678 # average ReadExReq miss latency 2812system.l2c.ReadExReq_avg_miss_latency::total 138788.957776 # average ReadExReq miss latency 2813system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 140465.756824 # average ReadSharedReq miss latency 2814system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 140937.039138 # average ReadSharedReq miss latency 2815system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 134396.000264 # average ReadSharedReq miss latency 2816system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 139428.210625 # average ReadSharedReq miss latency 2817system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 167065.091708 # average ReadSharedReq miss latency 2818system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 140795.010395 # average ReadSharedReq miss latency 2819system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 140654.796512 # average ReadSharedReq miss latency 2820system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 134541.888707 # average ReadSharedReq miss latency 2821system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 140411.173111 # average ReadSharedReq miss latency 2822system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 167909.892260 # average ReadSharedReq miss latency 2823system.l2c.ReadSharedReq_avg_miss_latency::total 154122.861342 # average ReadSharedReq miss latency 2824system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 140465.756824 # average overall miss latency 2825system.l2c.demand_avg_miss_latency::cpu0.itb.walker 140937.039138 # average overall miss latency 2826system.l2c.demand_avg_miss_latency::cpu0.inst 134396.000264 # average overall miss latency 2827system.l2c.demand_avg_miss_latency::cpu0.data 139582.676625 # average overall miss latency 2828system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 167065.091708 # average overall miss latency 2829system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 140795.010395 # average overall miss latency 2830system.l2c.demand_avg_miss_latency::cpu1.itb.walker 140654.796512 # average overall miss latency 2831system.l2c.demand_avg_miss_latency::cpu1.inst 134541.888707 # average overall miss latency 2832system.l2c.demand_avg_miss_latency::cpu1.data 137944.492434 # average overall miss latency 2833system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 167909.892260 # average overall miss latency 2834system.l2c.demand_avg_miss_latency::total 147536.108456 # average overall miss latency 2835system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 140465.756824 # average overall miss latency 2836system.l2c.overall_avg_miss_latency::cpu0.itb.walker 140937.039138 # average overall miss latency 2837system.l2c.overall_avg_miss_latency::cpu0.inst 134396.000264 # average overall miss latency 2838system.l2c.overall_avg_miss_latency::cpu0.data 139582.676625 # average overall miss latency 2839system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 167065.091708 # average overall miss latency 2840system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 140795.010395 # average overall miss latency 2841system.l2c.overall_avg_miss_latency::cpu1.itb.walker 140654.796512 # average overall miss latency 2842system.l2c.overall_avg_miss_latency::cpu1.inst 134541.888707 # average overall miss latency 2843system.l2c.overall_avg_miss_latency::cpu1.data 137944.492434 # average overall miss latency 2844system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 167909.892260 # average overall miss latency 2845system.l2c.overall_avg_miss_latency::total 147536.108456 # average overall miss latency 2846system.l2c.blocked_cycles::no_mshrs 2227 # number of cycles access was blocked 2847system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 2848system.l2c.blocked::no_mshrs 45 # number of cycles access was blocked 2849system.l2c.blocked::no_targets 0 # number of cycles access was blocked 2850system.l2c.avg_blocked_cycles::no_mshrs 49.488889 # average number of cycles each access was blocked 2851system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2852system.l2c.fast_writes 0 # number of fast writes performed 2853system.l2c.cache_copies 0 # number of cache copies performed 2854system.l2c.writebacks::writebacks 1132908 # number of writebacks 2855system.l2c.writebacks::total 1132908 # number of writebacks 2856system.l2c.ReadExReq_mshr_hits::cpu1.data 1 # number of ReadExReq MSHR hits 2857system.l2c.ReadExReq_mshr_hits::total 1 # number of ReadExReq MSHR hits 2858system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 168 # number of ReadSharedReq MSHR hits 2859system.l2c.ReadSharedReq_mshr_hits::cpu0.data 25 # number of ReadSharedReq MSHR hits 2860system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 159 # number of ReadSharedReq MSHR hits 2861system.l2c.ReadSharedReq_mshr_hits::cpu1.data 10 # number of ReadSharedReq MSHR hits 2862system.l2c.ReadSharedReq_mshr_hits::cpu1.l2cache.prefetcher 1 # number of ReadSharedReq MSHR hits 2863system.l2c.ReadSharedReq_mshr_hits::total 363 # number of ReadSharedReq MSHR hits 2864system.l2c.demand_mshr_hits::cpu0.inst 168 # number of demand (read+write) MSHR hits 2865system.l2c.demand_mshr_hits::cpu0.data 25 # number of demand (read+write) MSHR hits 2866system.l2c.demand_mshr_hits::cpu1.inst 159 # number of demand (read+write) MSHR hits 2867system.l2c.demand_mshr_hits::cpu1.data 11 # number of demand (read+write) MSHR hits 2868system.l2c.demand_mshr_hits::cpu1.l2cache.prefetcher 1 # number of demand (read+write) MSHR hits 2869system.l2c.demand_mshr_hits::total 364 # number of demand (read+write) MSHR hits 2870system.l2c.overall_mshr_hits::cpu0.inst 168 # number of overall MSHR hits 2871system.l2c.overall_mshr_hits::cpu0.data 25 # number of overall MSHR hits 2872system.l2c.overall_mshr_hits::cpu1.inst 159 # number of overall MSHR hits 2873system.l2c.overall_mshr_hits::cpu1.data 11 # number of overall MSHR hits 2874system.l2c.overall_mshr_hits::cpu1.l2cache.prefetcher 1 # number of overall MSHR hits 2875system.l2c.overall_mshr_hits::total 364 # number of overall MSHR hits 2876system.l2c.CleanEvict_mshr_misses::writebacks 56350 # number of CleanEvict MSHR misses 2877system.l2c.CleanEvict_mshr_misses::total 56350 # number of CleanEvict MSHR misses 2878system.l2c.UpgradeReq_mshr_misses::cpu0.data 61552 # number of UpgradeReq MSHR misses 2879system.l2c.UpgradeReq_mshr_misses::cpu1.data 61783 # number of UpgradeReq MSHR misses 2880system.l2c.UpgradeReq_mshr_misses::total 123335 # number of UpgradeReq MSHR misses 2881system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 12334 # number of SCUpgradeReq MSHR misses 2882system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 11273 # number of SCUpgradeReq MSHR misses 2883system.l2c.SCUpgradeReq_mshr_misses::total 23607 # number of SCUpgradeReq MSHR misses 2884system.l2c.ReadExReq_mshr_misses::cpu0.data 493827 # number of ReadExReq MSHR misses 2885system.l2c.ReadExReq_mshr_misses::cpu1.data 156177 # number of ReadExReq MSHR misses 2886system.l2c.ReadExReq_mshr_misses::total 650004 # number of ReadExReq MSHR misses 2887system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 2015 # number of ReadSharedReq MSHR misses 2888system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 1763 # number of ReadSharedReq MSHR misses 2889system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 75712 # number of ReadSharedReq MSHR misses 2890system.l2c.ReadSharedReq_mshr_misses::cpu0.data 147859 # number of ReadSharedReq MSHR misses 2891system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 232018 # number of ReadSharedReq MSHR misses 2892system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 2405 # number of ReadSharedReq MSHR misses 2893system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker 2064 # number of ReadSharedReq MSHR misses 2894system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 46942 # number of ReadSharedReq MSHR misses 2895system.l2c.ReadSharedReq_mshr_misses::cpu1.data 114685 # number of ReadSharedReq MSHR misses 2896system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 237375 # number of ReadSharedReq MSHR misses 2897system.l2c.ReadSharedReq_mshr_misses::total 862838 # number of ReadSharedReq MSHR misses 2898system.l2c.demand_mshr_misses::cpu0.dtb.walker 2015 # number of demand (read+write) MSHR misses 2899system.l2c.demand_mshr_misses::cpu0.itb.walker 1763 # number of demand (read+write) MSHR misses 2900system.l2c.demand_mshr_misses::cpu0.inst 75712 # number of demand (read+write) MSHR misses 2901system.l2c.demand_mshr_misses::cpu0.data 641686 # number of demand (read+write) MSHR misses 2902system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 232018 # number of demand (read+write) MSHR misses 2903system.l2c.demand_mshr_misses::cpu1.dtb.walker 2405 # number of demand (read+write) MSHR misses 2904system.l2c.demand_mshr_misses::cpu1.itb.walker 2064 # number of demand (read+write) MSHR misses 2905system.l2c.demand_mshr_misses::cpu1.inst 46942 # number of demand (read+write) MSHR misses 2906system.l2c.demand_mshr_misses::cpu1.data 270862 # number of demand (read+write) MSHR misses 2907system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 237375 # number of demand (read+write) MSHR misses 2908system.l2c.demand_mshr_misses::total 1512842 # number of demand (read+write) MSHR misses 2909system.l2c.overall_mshr_misses::cpu0.dtb.walker 2015 # number of overall MSHR misses 2910system.l2c.overall_mshr_misses::cpu0.itb.walker 1763 # number of overall MSHR misses 2911system.l2c.overall_mshr_misses::cpu0.inst 75712 # number of overall MSHR misses 2912system.l2c.overall_mshr_misses::cpu0.data 641686 # number of overall MSHR misses 2913system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 232018 # number of overall MSHR misses 2914system.l2c.overall_mshr_misses::cpu1.dtb.walker 2405 # number of overall MSHR misses 2915system.l2c.overall_mshr_misses::cpu1.itb.walker 2064 # number of overall MSHR misses 2916system.l2c.overall_mshr_misses::cpu1.inst 46942 # number of overall MSHR misses 2917system.l2c.overall_mshr_misses::cpu1.data 270862 # number of overall MSHR misses 2918system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 237375 # number of overall MSHR misses 2919system.l2c.overall_mshr_misses::total 1512842 # number of overall MSHR misses 2920system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 52309 # number of ReadReq MSHR uncacheable 2921system.l2c.ReadReq_mshr_uncacheable::cpu0.data 19530 # number of ReadReq MSHR uncacheable 2922system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 92 # number of ReadReq MSHR uncacheable 2923system.l2c.ReadReq_mshr_uncacheable::cpu1.data 19127 # number of ReadReq MSHR uncacheable 2924system.l2c.ReadReq_mshr_uncacheable::total 91058 # number of ReadReq MSHR uncacheable 2925system.l2c.WriteReq_mshr_uncacheable::cpu0.data 21048 # number of WriteReq MSHR uncacheable 2926system.l2c.WriteReq_mshr_uncacheable::cpu1.data 17467 # number of WriteReq MSHR uncacheable 2927system.l2c.WriteReq_mshr_uncacheable::total 38515 # number of WriteReq MSHR uncacheable 2928system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 52309 # number of overall MSHR uncacheable misses 2929system.l2c.overall_mshr_uncacheable_misses::cpu0.data 40578 # number of overall MSHR uncacheable misses 2930system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 92 # number of overall MSHR uncacheable misses 2931system.l2c.overall_mshr_uncacheable_misses::cpu1.data 36594 # number of overall MSHR uncacheable misses 2932system.l2c.overall_mshr_uncacheable_misses::total 129573 # number of overall MSHR uncacheable misses 2933system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 4349611999 # number of UpgradeReq MSHR miss cycles 2934system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 4356371498 # number of UpgradeReq MSHR miss cycles 2935system.l2c.UpgradeReq_mshr_miss_latency::total 8705983497 # number of UpgradeReq MSHR miss cycles 2936system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 908986500 # number of SCUpgradeReq MSHR miss cycles 2937system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 828559000 # number of SCUpgradeReq MSHR miss cycles 2938system.l2c.SCUpgradeReq_mshr_miss_latency::total 1737545500 # number of SCUpgradeReq MSHR miss cycles 2939system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 64014027660 # number of ReadExReq MSHR miss cycles 2940system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 19698809451 # number of ReadExReq MSHR miss cycles 2941system.l2c.ReadExReq_mshr_miss_latency::total 83712837111 # number of ReadExReq MSHR miss cycles 2942system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 262887003 # number of ReadSharedReq MSHR miss cycles 2943system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 230839505 # number of ReadSharedReq MSHR miss cycles 2944system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 9421666233 # number of ReadSharedReq MSHR miss cycles 2945system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 19137304611 # number of ReadSharedReq MSHR miss cycles 2946system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 36441216300 # number of ReadSharedReq MSHR miss cycles 2947system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 314557509 # number of ReadSharedReq MSHR miss cycles 2948system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 269667010 # number of ReadSharedReq MSHR miss cycles 2949system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 5848765667 # number of ReadSharedReq MSHR miss cycles 2950system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 14956255664 # number of ReadSharedReq MSHR miss cycles 2951system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 37483278358 # number of ReadSharedReq MSHR miss cycles 2952system.l2c.ReadSharedReq_mshr_miss_latency::total 124366437860 # number of ReadSharedReq MSHR miss cycles 2953system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 262887003 # number of demand (read+write) MSHR miss cycles 2954system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 230839505 # number of demand (read+write) MSHR miss cycles 2955system.l2c.demand_mshr_miss_latency::cpu0.inst 9421666233 # number of demand (read+write) MSHR miss cycles 2956system.l2c.demand_mshr_miss_latency::cpu0.data 83151332271 # number of demand (read+write) MSHR miss cycles 2957system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 36441216300 # number of demand (read+write) MSHR miss cycles 2958system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 314557509 # number of demand (read+write) MSHR miss cycles 2959system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 269667010 # number of demand (read+write) MSHR miss cycles 2960system.l2c.demand_mshr_miss_latency::cpu1.inst 5848765667 # number of demand (read+write) MSHR miss cycles 2961system.l2c.demand_mshr_miss_latency::cpu1.data 34655065115 # number of demand (read+write) MSHR miss cycles 2962system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 37483278358 # number of demand (read+write) MSHR miss cycles 2963system.l2c.demand_mshr_miss_latency::total 208079274971 # number of demand (read+write) MSHR miss cycles 2964system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 262887003 # number of overall MSHR miss cycles 2965system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 230839505 # number of overall MSHR miss cycles 2966system.l2c.overall_mshr_miss_latency::cpu0.inst 9421666233 # number of overall MSHR miss cycles 2967system.l2c.overall_mshr_miss_latency::cpu0.data 83151332271 # number of overall MSHR miss cycles 2968system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 36441216300 # number of overall MSHR miss cycles 2969system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 314557509 # number of overall MSHR miss cycles 2970system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 269667010 # number of overall MSHR miss cycles 2971system.l2c.overall_mshr_miss_latency::cpu1.inst 5848765667 # number of overall MSHR miss cycles 2972system.l2c.overall_mshr_miss_latency::cpu1.data 34655065115 # number of overall MSHR miss cycles 2973system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 37483278358 # number of overall MSHR miss cycles 2974system.l2c.overall_mshr_miss_latency::total 208079274971 # number of overall MSHR miss cycles 2975system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 5897666000 # number of ReadReq MSHR uncacheable cycles 2976system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 3292793548 # number of ReadReq MSHR uncacheable cycles 2977system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 10279000 # number of ReadReq MSHR uncacheable cycles 2978system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 2654073009 # number of ReadReq MSHR uncacheable cycles 2979system.l2c.ReadReq_mshr_uncacheable_latency::total 11854811557 # number of ReadReq MSHR uncacheable cycles 2980system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 3455652022 # number of WriteReq MSHR uncacheable cycles 2981system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 2534737541 # number of WriteReq MSHR uncacheable cycles 2982system.l2c.WriteReq_mshr_uncacheable_latency::total 5990389563 # number of WriteReq MSHR uncacheable cycles 2983system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 5897666000 # number of overall MSHR uncacheable cycles 2984system.l2c.overall_mshr_uncacheable_latency::cpu0.data 6748445570 # number of overall MSHR uncacheable cycles 2985system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 10279000 # number of overall MSHR uncacheable cycles 2986system.l2c.overall_mshr_uncacheable_latency::cpu1.data 5188810550 # number of overall MSHR uncacheable cycles 2987system.l2c.overall_mshr_uncacheable_latency::total 17845201120 # number of overall MSHR uncacheable cycles 2988system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 2989system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 2990system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.253367 # mshr miss rate for UpgradeReq accesses 2991system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.318862 # mshr miss rate for UpgradeReq accesses 2992system.l2c.UpgradeReq_mshr_miss_rate::total 0.282427 # mshr miss rate for UpgradeReq accesses 2993system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.212132 # mshr miss rate for SCUpgradeReq accesses 2994system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.219610 # mshr miss rate for SCUpgradeReq accesses 2995system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.215638 # mshr miss rate for SCUpgradeReq accesses 2996system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.711149 # mshr miss rate for ReadExReq accesses 2997system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.485195 # mshr miss rate for ReadExReq accesses 2998system.l2c.ReadExReq_mshr_miss_rate::total 0.639584 # mshr miss rate for ReadExReq accesses 2999system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.212217 # mshr miss rate for ReadSharedReq accesses 3000system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.253815 # mshr miss rate for ReadSharedReq accesses 3001system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.097663 # mshr miss rate for ReadSharedReq accesses 3002system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.182795 # mshr miss rate for ReadSharedReq accesses 3003system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.403848 # mshr miss rate for ReadSharedReq accesses 3004system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.280270 # mshr miss rate for ReadSharedReq accesses 3005system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.338250 # mshr miss rate for ReadSharedReq accesses 3006system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.068377 # mshr miss rate for ReadSharedReq accesses 3007system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.164892 # mshr miss rate for ReadSharedReq accesses 3008system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.445078 # mshr miss rate for ReadSharedReq accesses 3009system.l2c.ReadSharedReq_mshr_miss_rate::total 0.210186 # mshr miss rate for ReadSharedReq accesses 3010system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.212217 # mshr miss rate for demand accesses 3011system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.253815 # mshr miss rate for demand accesses 3012system.l2c.demand_mshr_miss_rate::cpu0.inst 0.097663 # mshr miss rate for demand accesses 3013system.l2c.demand_mshr_miss_rate::cpu0.data 0.426856 # mshr miss rate for demand accesses 3014system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.403848 # mshr miss rate for demand accesses 3015system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.280270 # mshr miss rate for demand accesses 3016system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.338250 # mshr miss rate for demand accesses 3017system.l2c.demand_mshr_miss_rate::cpu1.inst 0.068377 # mshr miss rate for demand accesses 3018system.l2c.demand_mshr_miss_rate::cpu1.data 0.266230 # mshr miss rate for demand accesses 3019system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.445078 # mshr miss rate for demand accesses 3020system.l2c.demand_mshr_miss_rate::total 0.295395 # mshr miss rate for demand accesses 3021system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.212217 # mshr miss rate for overall accesses 3022system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.253815 # mshr miss rate for overall accesses 3023system.l2c.overall_mshr_miss_rate::cpu0.inst 0.097663 # mshr miss rate for overall accesses 3024system.l2c.overall_mshr_miss_rate::cpu0.data 0.426856 # mshr miss rate for overall accesses 3025system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.403848 # mshr miss rate for overall accesses 3026system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.280270 # mshr miss rate for overall accesses 3027system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.338250 # mshr miss rate for overall accesses 3028system.l2c.overall_mshr_miss_rate::cpu1.inst 0.068377 # mshr miss rate for overall accesses 3029system.l2c.overall_mshr_miss_rate::cpu1.data 0.266230 # mshr miss rate for overall accesses 3030system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.445078 # mshr miss rate for overall accesses 3031system.l2c.overall_mshr_miss_rate::total 0.295395 # mshr miss rate for overall accesses 3032system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 70665.648541 # average UpgradeReq mshr miss latency 3033system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 70510.844375 # average UpgradeReq mshr miss latency 3034system.l2c.UpgradeReq_avg_mshr_miss_latency::total 70588.101488 # average UpgradeReq mshr miss latency 3035system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 73697.624453 # average SCUpgradeReq mshr miss latency 3036system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 73499.423401 # average SCUpgradeReq mshr miss latency 3037system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 73602.977930 # average SCUpgradeReq mshr miss latency 3038system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 129628.448141 # average ReadExReq mshr miss latency 3039system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 126131.309034 # average ReadExReq mshr miss latency 3040system.l2c.ReadExReq_avg_mshr_miss_latency::total 128788.187628 # average ReadExReq mshr miss latency 3041system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 130465.013896 # average ReadSharedReq mshr miss latency 3042system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 130935.623936 # average ReadSharedReq mshr miss latency 3043system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 124440.857896 # average ReadSharedReq mshr miss latency 3044system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 129429.419995 # average ReadSharedReq mshr miss latency 3045system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 157062.022343 # average ReadSharedReq mshr miss latency 3046system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 130793.143035 # average ReadSharedReq mshr miss latency 3047system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 130652.621124 # average ReadSharedReq mshr miss latency 3048system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 124595.578948 # average ReadSharedReq mshr miss latency 3049system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 130411.611492 # average ReadSharedReq mshr miss latency 3050system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 157907.439107 # average ReadSharedReq mshr miss latency 3051system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 144136.486641 # average ReadSharedReq mshr miss latency 3052system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 130465.013896 # average overall mshr miss latency 3053system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 130935.623936 # average overall mshr miss latency 3054system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 124440.857896 # average overall mshr miss latency 3055system.l2c.demand_avg_mshr_miss_latency::cpu0.data 129582.587544 # average overall mshr miss latency 3056system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 157062.022343 # average overall mshr miss latency 3057system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 130793.143035 # average overall mshr miss latency 3058system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 130652.621124 # average overall mshr miss latency 3059system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 124595.578948 # average overall mshr miss latency 3060system.l2c.demand_avg_mshr_miss_latency::cpu1.data 127943.621161 # average overall mshr miss latency 3061system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 157907.439107 # average overall mshr miss latency 3062system.l2c.demand_avg_mshr_miss_latency::total 137541.973961 # average overall mshr miss latency 3063system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 130465.013896 # average overall mshr miss latency 3064system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 130935.623936 # average overall mshr miss latency 3065system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 124440.857896 # average overall mshr miss latency 3066system.l2c.overall_avg_mshr_miss_latency::cpu0.data 129582.587544 # average overall mshr miss latency 3067system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 157062.022343 # average overall mshr miss latency 3068system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 130793.143035 # average overall mshr miss latency 3069system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 130652.621124 # average overall mshr miss latency 3070system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 124595.578948 # average overall mshr miss latency 3071system.l2c.overall_avg_mshr_miss_latency::cpu1.data 127943.621161 # average overall mshr miss latency 3072system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 157907.439107 # average overall mshr miss latency 3073system.l2c.overall_avg_mshr_miss_latency::total 137541.973961 # average overall mshr miss latency 3074system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 112746.678392 # average ReadReq mshr uncacheable latency 3075system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 168601.820174 # average ReadReq mshr uncacheable latency 3076system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 111728.260870 # average ReadReq mshr uncacheable latency 3077system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 138760.548387 # average ReadReq mshr uncacheable latency 3078system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 130189.676437 # average ReadReq mshr uncacheable latency 3079system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 164179.590555 # average WriteReq mshr uncacheable latency 3080system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 145115.792122 # average WriteReq mshr uncacheable latency 3081system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 155533.936466 # average WriteReq mshr uncacheable latency 3082system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 112746.678392 # average overall mshr uncacheable latency 3083system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 166307.988812 # average overall mshr uncacheable latency 3084system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 111728.260870 # average overall mshr uncacheable latency 3085system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 141794.024977 # average overall mshr uncacheable latency 3086system.l2c.overall_avg_mshr_uncacheable_latency::total 137723.145408 # average overall mshr uncacheable latency 3087system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 3088system.membus.trans_dist::ReadReq 91058 # Transaction distribution 3089system.membus.trans_dist::ReadResp 962815 # Transaction distribution 3090system.membus.trans_dist::WriteReq 38515 # Transaction distribution 3091system.membus.trans_dist::WriteResp 38515 # Transaction distribution 3092system.membus.trans_dist::WritebackDirty 1239858 # Transaction distribution 3093system.membus.trans_dist::CleanEvict 269903 # Transaction distribution 3094system.membus.trans_dist::UpgradeReq 432314 # Transaction distribution 3095system.membus.trans_dist::SCUpgradeReq 322959 # Transaction distribution 3096system.membus.trans_dist::UpgradeResp 23 # Transaction distribution 3097system.membus.trans_dist::SCUpgradeFailReq 3 # Transaction distribution 3098system.membus.trans_dist::ReadExReq 660243 # Transaction distribution 3099system.membus.trans_dist::ReadExResp 640684 # Transaction distribution 3100system.membus.trans_dist::ReadSharedReq 871757 # Transaction distribution 3101system.membus.trans_dist::InvalidateReq 106984 # Transaction distribution 3102system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122998 # Packet count per connected master and slave (bytes) 3103system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 52 # Packet count per connected master and slave (bytes) 3104system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 26126 # Packet count per connected master and slave (bytes) 3105system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5285035 # Packet count per connected master and slave (bytes) 3106system.membus.pkt_count_system.l2c.mem_side::total 5434211 # Packet count per connected master and slave (bytes) 3107system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 238560 # Packet count per connected master and slave (bytes) 3108system.membus.pkt_count_system.iocache.mem_side::total 238560 # Packet count per connected master and slave (bytes) 3109system.membus.pkt_count::total 5672771 # Packet count per connected master and slave (bytes) 3110system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 156013 # Cumulative packet size per connected master and slave (bytes) 3111system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1324 # Cumulative packet size per connected master and slave (bytes) 3112system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 52252 # Cumulative packet size per connected master and slave (bytes) 3113system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 172058368 # Cumulative packet size per connected master and slave (bytes) 3114system.membus.pkt_size_system.l2c.mem_side::total 172267957 # Cumulative packet size per connected master and slave (bytes) 3115system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7280448 # Cumulative packet size per connected master and slave (bytes) 3116system.membus.pkt_size_system.iocache.mem_side::total 7280448 # Cumulative packet size per connected master and slave (bytes) 3117system.membus.pkt_size::total 179548405 # Cumulative packet size per connected master and slave (bytes) 3118system.membus.snoops 621430 # Total snoops (count) 3119system.membus.snoop_fanout::samples 4033661 # Request fanout histogram 3120system.membus.snoop_fanout::mean 1 # Request fanout histogram 3121system.membus.snoop_fanout::stdev 0 # Request fanout histogram 3122system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 3123system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 3124system.membus.snoop_fanout::1 4033661 100.00% 100.00% # Request fanout histogram 3125system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 3126system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 3127system.membus.snoop_fanout::min_value 1 # Request fanout histogram 3128system.membus.snoop_fanout::max_value 1 # Request fanout histogram 3129system.membus.snoop_fanout::total 4033661 # Request fanout histogram 3130system.membus.reqLayer0.occupancy 110232498 # Layer occupancy (ticks) 3131system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 3132system.membus.reqLayer1.occupancy 33984 # Layer occupancy (ticks) 3133system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 3134system.membus.reqLayer2.occupancy 21930998 # Layer occupancy (ticks) 3135system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 3136system.membus.reqLayer5.occupancy 8790771874 # Layer occupancy (ticks) 3137system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 3138system.membus.respLayer2.occupancy 8289711005 # Layer occupancy (ticks) 3139system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 3140system.membus.respLayer3.occupancy 45511990 # Layer occupancy (ticks) 3141system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 3142system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 3143system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 3144system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 3145system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 3146system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 3147system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks 3148system.realview.ethernet.txBytes 966 # Bytes Transmitted 3149system.realview.ethernet.txPackets 3 # Number of Packets Transmitted 3150system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device 3151system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device 3152system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 3153system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 3154system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 3155system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 3156system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 3157system.realview.ethernet.totBandwidth 163 # Total Bandwidth (bits/s) 3158system.realview.ethernet.totPackets 3 # Total Packets 3159system.realview.ethernet.totBytes 966 # Total Bytes 3160system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) 3161system.realview.ethernet.txBandwidth 163 # Transmit Bandwidth (bits/s) 3162system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) 3163system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 3164system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post 3165system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 3166system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 3167system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post 3168system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 3169system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 3170system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post 3171system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 3172system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 3173system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post 3174system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 3175system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 3176system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post 3177system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 3178system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 3179system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post 3180system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 3181system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 3182system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 3183system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 3184system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 3185system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 3186system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 3187system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 3188system.realview.ethernet.postedInterrupts 13 # number of posts to CPU 3189system.realview.ethernet.droppedPackets 0 # number of packets dropped 3190system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 3191system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 3192system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 3193system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks 3194system.toL2Bus.snoop_filter.tot_requests 12834320 # Total number of requests made to the snoop filter. 3195system.toL2Bus.snoop_filter.hit_single_requests 6946519 # Number of requests hitting in the snoop filter with a single holder of the requested data. 3196system.toL2Bus.snoop_filter.hit_multi_requests 2149909 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 3197system.toL2Bus.snoop_filter.tot_snoops 154845 # Total number of snoops made to the snoop filter. 3198system.toL2Bus.snoop_filter.hit_single_snoops 139190 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 3199system.toL2Bus.snoop_filter.hit_multi_snoops 15655 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 3200system.toL2Bus.trans_dist::ReadReq 91060 # Transaction distribution 3201system.toL2Bus.trans_dist::ReadResp 4987176 # Transaction distribution 3202system.toL2Bus.trans_dist::WriteReq 38515 # Transaction distribution 3203system.toL2Bus.trans_dist::WriteResp 38515 # Transaction distribution 3204system.toL2Bus.trans_dist::WritebackDirty 4108038 # Transaction distribution 3205system.toL2Bus.trans_dist::CleanEvict 3110241 # Transaction distribution 3206system.toL2Bus.trans_dist::UpgradeReq 736356 # Transaction distribution 3207system.toL2Bus.trans_dist::SCUpgradeReq 408827 # Transaction distribution 3208system.toL2Bus.trans_dist::UpgradeResp 1145183 # Transaction distribution 3209system.toL2Bus.trans_dist::SCUpgradeFailReq 116 # Transaction distribution 3210system.toL2Bus.trans_dist::UpgradeFailResp 116 # Transaction distribution 3211system.toL2Bus.trans_dist::ReadExReq 1157626 # Transaction distribution 3212system.toL2Bus.trans_dist::ReadExResp 1157626 # Transaction distribution 3213system.toL2Bus.trans_dist::ReadSharedReq 4903350 # Transaction distribution 3214system.toL2Bus.trans_dist::InvalidateReq 106984 # Transaction distribution 3215system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 10442900 # Packet count per connected master and slave (bytes) 3216system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8319786 # Packet count per connected master and slave (bytes) 3217system.toL2Bus.pkt_count::total 18762686 # Packet count per connected master and slave (bytes) 3218system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 296101599 # Cumulative packet size per connected master and slave (bytes) 3219system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 218919254 # Cumulative packet size per connected master and slave (bytes) 3220system.toL2Bus.pkt_size::total 515020853 # Cumulative packet size per connected master and slave (bytes) 3221system.toL2Bus.snoops 3228731 # Total snoops (count) 3222system.toL2Bus.snoop_fanout::samples 9024232 # Request fanout histogram 3223system.toL2Bus.snoop_fanout::mean 0.357725 # Request fanout histogram 3224system.toL2Bus.snoop_fanout::stdev 0.482936 # Request fanout histogram 3225system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 3226system.toL2Bus.snoop_fanout::0 5811691 64.40% 64.40% # Request fanout histogram 3227system.toL2Bus.snoop_fanout::1 3196886 35.43% 99.83% # Request fanout histogram 3228system.toL2Bus.snoop_fanout::2 15655 0.17% 100.00% # Request fanout histogram 3229system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 3230system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 3231system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 3232system.toL2Bus.snoop_fanout::total 9024232 # Request fanout histogram 3233system.toL2Bus.reqLayer0.occupancy 9776043593 # Layer occupancy (ticks) 3234system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 3235system.toL2Bus.snoopLayer0.occupancy 2607881 # Layer occupancy (ticks) 3236system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 3237system.toL2Bus.respLayer0.occupancy 5412935477 # Layer occupancy (ticks) 3238system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 3239system.toL2Bus.respLayer1.occupancy 4393187885 # Layer occupancy (ticks) 3240system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 3241 3242---------- End Simulation Statistics ---------- 3243