1# Copyright (c) 2012 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license 9# terms below provided that you ensure that this notice is replicated 10# unmodified and in its entirety in all distributions of the software, 11# modified or unmodified, in source code or in binary form. 12# 13# Redistribution and use in source and binary forms, with or without 14# modification, are permitted provided that the following conditions are 15# met: redistributions of source code must retain the above copyright 16# notice, this list of conditions and the following disclaimer; 17# redistributions in binary form must reproduce the above copyright 18# notice, this list of conditions and the following disclaimer in the 19# documentation and/or other materials provided with the distribution; 20# neither the name of the copyright holders nor the names of its 21# contributors may be used to endorse or promote products derived from 22# this software without specific prior written permission. 23# 24# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 25# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 26# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 27# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 28# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 29# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 30# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 31# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 32# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 34# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35# 36# Authors: Andreas Sandberg 37 38from __future__ import print_function 39 40import m5 41import _m5 42from m5.objects import * 43m5.util.addToPath('../configs/') 44from common.Caches import * 45 46class Sequential: 47 """Sequential CPU switcher. 48 49 The sequential CPU switches between all CPUs in a system in 50 order. The CPUs in the system must have been prepared for 51 switching, which in practice means that only one CPU is switched 52 in. base_config.BaseFSSwitcheroo can be used to create such a 53 system. 54 """ 55 def __init__(self, cpus): 56 self.first_cpu = None 57 for (cpuno, cpu) in enumerate(cpus): 58 if not cpu.switched_out: 59 if self.first_cpu != None: 60 fatal("More than one CPU is switched in"); 61 self.first_cpu = cpuno 62 63 if self.first_cpu == None: 64 fatal("The system contains no switched in CPUs") 65 66 self.cur_cpu = self.first_cpu 67 self.cpus = cpus 68 69 def next(self): 70 self.cur_cpu = (self.cur_cpu + 1) % len(self.cpus) 71 return self.cpus[self.cur_cpu] 72 73 def first(self): 74 return self.cpus[self.first_cpu] 75 76def run_test(root, switcher=None, freq=1000, verbose=False): 77 """Test runner for CPU switcheroo tests. 78 79 The switcheroo test runner is used to switch CPUs in a system that 80 has been prepared for CPU switching. Such systems should have 81 multiple CPUs when they are instantiated, but only one should be 82 switched in. Such configurations can be created using the 83 base_config.BaseFSSwitcheroo class. 84 85 A CPU switcher object is used to control switching. The default 86 switcher sequentially switches between all CPUs in a system, 87 starting with the CPU that is currently switched in. 88 89 Unlike most other test runners, this one automatically configures 90 the memory mode of the system based on the first CPU the switcher 91 reports. 92 93 Keyword Arguments: 94 switcher -- CPU switcher implementation. See Sequential for 95 an example implementation. 96 period -- Switching frequency in Hz. 97 verbose -- Enable output at each switch (suppressed by default). 98 """ 99 100 if switcher == None: 101 switcher = Sequential(root.system.cpu) 102 103 current_cpu = switcher.first() 104 system = root.system 105 system.mem_mode = type(current_cpu).memory_mode() 106 107 # Suppress "Entering event queue" messages since we get tons of them. 108 # Worse yet, they include the timestamp, which makes them highly 109 # variable and unsuitable for comparing as test outputs. 110 if not verbose: 111 _m5.core.setLogLevel(_m5.core.LogLevel.WARN) 112 113 # instantiate configuration 114 m5.instantiate() 115 116 # Determine the switching period, this has to be done after 117 # instantiating the system since the time base must be fixed. 118 period = m5.ticks.fromSeconds(1.0 / freq) 119 while True: 120 exit_event = m5.simulate(period) 121 exit_cause = exit_event.getCause() 122 123 if exit_cause == "simulate() limit reached": 124 next_cpu = switcher.next() 125 126 if verbose: 127 print("Switching CPUs...") 128 print("Next CPU: %s" % type(next_cpu)) 129 m5.drain() 130 if current_cpu != next_cpu: 131 m5.switchCpus(system, [ (current_cpu, next_cpu) ], 132 verbose=verbose) 133 else: 134 print("Source CPU and destination CPU are the same," 135 " skipping...") 136 current_cpu = next_cpu 137 elif exit_cause == "target called exit()" or \ 138 exit_cause == "m5_exit instruction encountered": 139 140 sys.exit(0) 141 else: 142 print("Test failed: Unknown exit cause: %s" % exit_cause) 143 sys.exit(1) 144