AbstractController.hh revision 10523
11689SN/A/* 21689SN/A * Copyright (c) 2009 Mark D. Hill and David A. Wood 31689SN/A * All rights reserved. 41689SN/A * 51689SN/A * Redistribution and use in source and binary forms, with or without 61689SN/A * modification, are permitted provided that the following conditions are 71689SN/A * met: redistributions of source code must retain the above copyright 81689SN/A * notice, this list of conditions and the following disclaimer; 91689SN/A * redistributions in binary form must reproduce the above copyright 101689SN/A * notice, this list of conditions and the following disclaimer in the 111689SN/A * documentation and/or other materials provided with the distribution; 121689SN/A * neither the name of the copyright holders nor the names of its 131689SN/A * contributors may be used to endorse or promote products derived from 141689SN/A * this software without specific prior written permission. 151689SN/A * 161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu */ 282665Ssaidi@eecs.umich.edu 291689SN/A#ifndef __MEM_RUBY_SLICC_INTERFACE_ABSTRACTCONTROLLER_HH__ 301689SN/A#define __MEM_RUBY_SLICC_INTERFACE_ABSTRACTCONTROLLER_HH__ 311755SN/A 321755SN/A#include <iostream> 331060SN/A#include <string> 341061SN/A 351684SN/A#include "base/callback.hh" 362165SN/A#include "mem/protocol/AccessPermission.hh" 371060SN/A#include "mem/ruby/common/Address.hh" 381710SN/A#include "mem/ruby/common/Consumer.hh" 391060SN/A#include "mem/ruby/common/DataBlock.hh" 401060SN/A#include "mem/ruby/common/Histogram.hh" 411062SN/A#include "mem/ruby/common/MachineID.hh" 421060SN/A#include "mem/ruby/network/MessageBuffer.hh" 431060SN/A#include "mem/ruby/network/Network.hh" 441060SN/A#include "mem/ruby/system/CacheRecorder.hh" 451060SN/A#include "mem/packet.hh" 461061SN/A#include "params/RubyController.hh" 471061SN/A#include "sim/clocked_object.hh" 481061SN/A 491061SN/Aclass Network; 501461SN/A 511060SN/Aclass AbstractController : public ClockedObject, public Consumer 521060SN/A{ 531060SN/A public: 541060SN/A typedef RubyControllerParams Params; 551061SN/A AbstractController(const Params *p); 561061SN/A void init(); 571061SN/A const Params *params() const { return (const Params *)_params; } 581061SN/A 591461SN/A const NodeID getVersion() const { return m_machineID.getNum(); } 601060SN/A const MachineType getType() const { return m_machineID.getType(); } 611060SN/A 621060SN/A void initNetworkPtr(Network* net_ptr) { m_net_ptr = net_ptr; } 631060SN/A 641061SN/A // return instance name 651061SN/A void blockOnQueue(Address, MessageBuffer*); 661061SN/A void unblock(Address); 671061SN/A 681461SN/A virtual MessageBuffer* getMandatoryQueue() const = 0; 691060SN/A virtual AccessPermission getAccessPermission(const Address& addr) = 0; 701060SN/A 711060SN/A virtual void print(std::ostream & out) const = 0; 721060SN/A virtual void wakeup() = 0; 731061SN/A virtual void resetStats() = 0; 741061SN/A virtual void regStats(); 751061SN/A 761061SN/A virtual void recordCacheTrace(int cntrl, CacheRecorder* tr) = 0; 771461SN/A virtual Sequencer* getSequencer() const = 0; 781062SN/A 791062SN/A //! These functions are used by ruby system to read/write the data blocks 801062SN/A //! that exist with in the controller. 811062SN/A virtual void functionalRead(const Address &addr, PacketPtr) = 0; 821062SN/A //! The return value indicates the number of messages written with the 831062SN/A //! data from the packet. 841062SN/A virtual uint32_t functionalWriteBuffers(PacketPtr&) = 0; 851060SN/A virtual int functionalWrite(const Address &addr, PacketPtr) = 0; 861060SN/A 871060SN/A //! Function for enqueuing a prefetch request 881060SN/A virtual void enqueuePrefetch(const Address&, const RubyRequestType&) 891061SN/A { fatal("Prefetches not implemented!");} 901061SN/A 911061SN/A //! Function for collating statistics from all the controllers of this 921061SN/A //! particular type. This function should only be called from the 931461SN/A //! version 0 of this controller type. 941060SN/A virtual void collateStats() 951060SN/A {fatal("collateStats() should be overridden!");} 961060SN/A 971060SN/A //! Set the message buffer with given name. 981060SN/A virtual void setNetQueue(const std::string& name, MessageBuffer *b) = 0; 991060SN/A 1001060SN/A public: 1011060SN/A MachineID getMachineID() const { return m_machineID; } 1021060SN/A 1031062SN/A Stats::Histogram& getDelayHist() { return m_delayHistogram; } 1041062SN/A Stats::Histogram& getDelayVCHist(uint32_t index) 1051062SN/A { return *(m_delayVCHistogram[index]); } 1061062SN/A 1071061SN/A protected: 1081061SN/A //! Profiles original cache requests including PUTs 1091061SN/A void profileRequest(const std::string &request); 1101060SN/A //! Profiles the delay associated with messages. 1111060SN/A void profileMsgDelay(uint32_t virtualNetwork, Cycles delay); 1121060SN/A 1131060SN/A void stallBuffer(MessageBuffer* buf, Address addr); 1141060SN/A void wakeUpBuffers(Address addr); 1151060SN/A void wakeUpAllBuffers(Address addr); 1161060SN/A void wakeUpAllBuffers(); 1171060SN/A 1181060SN/A protected: 1191060SN/A NodeID m_version; 1201060SN/A MachineID m_machineID; 1211060SN/A NodeID m_clusterID; 1221060SN/A 1231060SN/A Network* m_net_ptr; 1241060SN/A bool m_is_blocking; 1251060SN/A std::map<Address, MessageBuffer*> m_block_map; 1261060SN/A 1271060SN/A typedef std::vector<MessageBuffer*> MsgVecType; 1281060SN/A typedef std::map< Address, MsgVecType* > WaitingBufType; 1291060SN/A WaitingBufType m_waiting_buffers; 1301060SN/A 1311060SN/A unsigned int m_in_ports; 1321060SN/A unsigned int m_cur_in_port; 1331060SN/A int m_number_of_TBEs; 1341060SN/A int m_transitions_per_cycle; 1351060SN/A unsigned int m_buffer_size; 1361060SN/A Cycles m_recycle_latency; 1371060SN/A 1381060SN/A //! Counter for the number of cycles when the transitions carried out 1391060SN/A //! were equal to the maximum allowed 1401060SN/A Stats::Scalar m_fully_busy_cycles; 1411061SN/A 1421061SN/A //! Histogram for profiling delay for the messages this controller 1431061SN/A //! cares for 1441060SN/A Stats::Histogram m_delayHistogram; 1451060SN/A std::vector<Stats::Histogram *> m_delayVCHistogram; 1461060SN/A 1471061SN/A //! Callback class used for collating statistics from all the 1481060SN/A //! controller of this type. 1491060SN/A class StatsCallback : public Callback 1501060SN/A { 1511060SN/A private: 1521061SN/A AbstractController *ctr; 1531684SN/A 1541061SN/A public: 1551061SN/A virtual ~StatsCallback() {} 1561061SN/A StatsCallback(AbstractController *_ctr) : ctr(_ctr) {} 1571061SN/A void process() {ctr->collateStats();} 1581061SN/A }; 1591061SN/A}; 1601060SN/A 1611060SN/A#endif // __MEM_RUBY_SLICC_INTERFACE_ABSTRACTCONTROLLER_HH__ 1621060SN/A