tsunami_io.hh revision 809
11689SN/A/*
21689SN/A * Copyright (c) 2003 The Regents of The University of Michigan
31689SN/A * All rights reserved.
41689SN/A *
51689SN/A * Redistribution and use in source and binary forms, with or without
61689SN/A * modification, are permitted provided that the following conditions are
71689SN/A * met: redistributions of source code must retain the above copyright
81689SN/A * notice, this list of conditions and the following disclaimer;
91689SN/A * redistributions in binary form must reproduce the above copyright
101689SN/A * notice, this list of conditions and the following disclaimer in the
111689SN/A * documentation and/or other materials provided with the distribution;
121689SN/A * neither the name of the copyright holders nor the names of its
131689SN/A * contributors may be used to endorse or promote products derived from
141689SN/A * this software without specific prior written permission.
151689SN/A *
161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
272665Ssaidi@eecs.umich.edu */
282665Ssaidi@eecs.umich.edu
292665Ssaidi@eecs.umich.edu/* @file
301689SN/A * Tsunami Fake I/O Space mapping including RTC/timer interrupts
311689SN/A */
322292SN/A
332292SN/A#ifndef __TSUNAMI_DMA_HH__
341060SN/A#define __TSUNAMI_DMA_HH__
352165SN/A
362669Sktlim@umich.edu#define RTC_RATE 1024
371681SN/A
381858SN/A#include "mem/functional_mem/functional_memory.hh"
391717SN/A#include "dev/tsunami.hh"
401060SN/A
411858SN/A/*
421681SN/A * Tsunami I/O device
431681SN/A */
441681SN/Aclass TsunamiIO : public FunctionalMemory
451063SN/A{
462292SN/A  private:
471060SN/A    Addr addr;
482292SN/A    static const Addr size = 0xff;
492292SN/A
502669Sktlim@umich.edu    struct tm tm;
512669Sktlim@umich.edu
522292SN/A    // In Tsunami RTC only has two i/o ports
531061SN/A    // one  for data and one for address, so you
541060SN/A    // write the address and then read/write the data
551060SN/A    uint8_t RTCAddress;
562107SN/A
572107SN/A  protected:
582107SN/A
592669Sktlim@umich.edu    class ClockEvent : public Event
602107SN/A    {
612159SN/A      protected:
622159SN/A        Tick interval;
632669Sktlim@umich.edu        uint8_t mode;
642669Sktlim@umich.edu        uint8_t status;
652669Sktlim@umich.edu
662669Sktlim@umich.edu      public:
671060SN/A        ClockEvent();
682292SN/A
692292SN/A        virtual void process();
701060SN/A        virtual const char *description();
712292SN/A        void Program(int count);
722292SN/A        void ChangeMode(uint8_t mode);
731060SN/A        uint8_t Status();
742733Sktlim@umich.edu
751060SN/A    };
762292SN/A
772292SN/A    class RTCEvent : public Event
782292SN/A    {
792292SN/A      protected:
801060SN/A        Tsunami* tsunami;
811060SN/A      public:
821060SN/A        RTCEvent(Tsunami* t);
831060SN/A
841060SN/A        virtual void process();
851060SN/A        virtual const char *description();
861060SN/A    };
871060SN/A
882292SN/A    uint8_t uip;
891060SN/A
901060SN/A    uint8_t mask1;
911061SN/A    uint8_t mask2;
921061SN/A    uint8_t mode1;
931060SN/A    uint8_t mode2;
942690Sktlim@umich.edu
951060SN/A    uint8_t picr; //Raw PIC interrput register, before masking
961060SN/A    bool picInterrupting;
971060SN/A
982455SN/A    Tsunami *tsunami;
991060SN/A
1001060SN/A    /*
1011060SN/A     * This timer is initilized, but after I wrote the code
1021060SN/A     * it doesn't seem to be used again, and best I can tell
1031062SN/A     * it too is not connected to any interrupt port
1041061SN/A     */
1052669Sktlim@umich.edu    ClockEvent timer0;
1061060SN/A
1072455SN/A    /*
1082690Sktlim@umich.edu     * This timer is used to control the speaker, which
1092455SN/A     * we normally could care less about, however it is
1102455SN/A     * also used to calculated the clockspeed and hense
1111060SN/A     * bogomips which is kinda important to the scheduler
1121060SN/A     * so we need to implemnt it although after boot I can't
1132292SN/A     * imagine we would be playing with the PC speaker much
1142455SN/A     */
1151060SN/A    ClockEvent timer2;
1161060SN/A
1171060SN/A    RTCEvent rtc;
1181060SN/A
1191062SN/A    uint32_t timerData;
1201061SN/A
1212669Sktlim@umich.edu
1221060SN/A  public:
1232455SN/A    uint32_t  frequency() const { return RTC_RATE; }
1242690Sktlim@umich.edu
1252455SN/A    TsunamiIO(const std::string &name, Tsunami *t, time_t init_time,
1262455SN/A              Addr a, MemoryController *mmu);
1271060SN/A
1281060SN/A    void set_time(time_t t);
1292292SN/A
1302455SN/A    virtual Fault read(MemReqPtr &req, uint8_t *data);
1311060SN/A    virtual Fault write(MemReqPtr &req, const uint8_t *data);
1321060SN/A
1331060SN/A    void postPIC(uint8_t bitvector);
1341060SN/A    void clearPIC(uint8_t bitvector);
1351062SN/A
1361061SN/A    virtual void serialize(std::ostream &os);
1372669Sktlim@umich.edu    virtual void unserialize(Checkpoint *cp, const std::string &section);
1381060SN/A};
1392690Sktlim@umich.edu
1402690Sktlim@umich.edu#endif // __TSUNAMI_IO_HH__
1412455SN/A