tsunami_io.hh revision 809
12SN/A/*
21762SN/A * Copyright (c) 2003 The Regents of The University of Michigan
32SN/A * All rights reserved.
42SN/A *
52SN/A * Redistribution and use in source and binary forms, with or without
62SN/A * modification, are permitted provided that the following conditions are
72SN/A * met: redistributions of source code must retain the above copyright
82SN/A * notice, this list of conditions and the following disclaimer;
92SN/A * redistributions in binary form must reproduce the above copyright
102SN/A * notice, this list of conditions and the following disclaimer in the
112SN/A * documentation and/or other materials provided with the distribution;
122SN/A * neither the name of the copyright holders nor the names of its
132SN/A * contributors may be used to endorse or promote products derived from
142SN/A * this software without specific prior written permission.
152SN/A *
162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
272665Ssaidi@eecs.umich.edu */
282665Ssaidi@eecs.umich.edu
292665Ssaidi@eecs.umich.edu/* @file
302SN/A * Tsunami Fake I/O Space mapping including RTC/timer interrupts
312SN/A */
322SN/A
332SN/A#ifndef __TSUNAMI_DMA_HH__
342SN/A#define __TSUNAMI_DMA_HH__
352SN/A
361354SN/A#define RTC_RATE 1024
371354SN/A
382SN/A#include "mem/functional_mem/functional_memory.hh"
392SN/A#include "dev/tsunami.hh"
405501Snate@binkert.org
415546Snate@binkert.org/*
427004Snate@binkert.org * Tsunami I/O device
432SN/A */
442SN/Aclass TsunamiIO : public FunctionalMemory
4556SN/A{
465769Snate@binkert.org  private:
472361SN/A    Addr addr;
481354SN/A    static const Addr size = 0xff;
496216Snate@binkert.org
5056SN/A    struct tm tm;
512SN/A
525543Ssaidi@eecs.umich.edu    // In Tsunami RTC only has two i/o ports
532SN/A    // one  for data and one for address, so you
541354SN/A    // write the address and then read/write the data
551354SN/A    uint8_t RTCAddress;
562SN/A
572SN/A  protected:
582SN/A
592SN/A    class ClockEvent : public Event
605501Snate@binkert.org    {
615501Snate@binkert.org      protected:
622SN/A        Tick interval;
63395SN/A        uint8_t mode;
642SN/A        uint8_t status;
652SN/A
662SN/A      public:
675769Snate@binkert.org        ClockEvent();
685769Snate@binkert.org
695769Snate@binkert.org        virtual void process();
705769Snate@binkert.org        virtual const char *description();
715769Snate@binkert.org        void Program(int count);
725769Snate@binkert.org        void ChangeMode(uint8_t mode);
735769Snate@binkert.org        uint8_t Status();
745769Snate@binkert.org
755769Snate@binkert.org    };
765769Snate@binkert.org
775769Snate@binkert.org    class RTCEvent : public Event
785769Snate@binkert.org    {
795774Snate@binkert.org      protected:
805774Snate@binkert.org        Tsunami* tsunami;
815774Snate@binkert.org      public:
825769Snate@binkert.org        RTCEvent(Tsunami* t);
832SN/A
845502Snate@binkert.org        virtual void process();
855502Snate@binkert.org        virtual const char *description();
865502Snate@binkert.org    };
875503Snate@binkert.org
885503Snate@binkert.org    uint8_t uip;
895502Snate@binkert.org
905502Snate@binkert.org    uint8_t mask1;
915502Snate@binkert.org    uint8_t mask2;
925502Snate@binkert.org    uint8_t mode1;
935502Snate@binkert.org    uint8_t mode2;
945502Snate@binkert.org
955502Snate@binkert.org    uint8_t picr; //Raw PIC interrput register, before masking
965602Snate@binkert.org    bool picInterrupting;
975602Snate@binkert.org
985501Snate@binkert.org    Tsunami *tsunami;
995543Ssaidi@eecs.umich.edu
1005543Ssaidi@eecs.umich.edu    /*
1015769Snate@binkert.org     * This timer is initilized, but after I wrote the code
1024016Sstever@eecs.umich.edu     * it doesn't seem to be used again, and best I can tell
1034016Sstever@eecs.umich.edu     * it too is not connected to any interrupt port
1044016Sstever@eecs.umich.edu     */
1054016Sstever@eecs.umich.edu    ClockEvent timer0;
1064016Sstever@eecs.umich.edu
1074016Sstever@eecs.umich.edu    /*
1084016Sstever@eecs.umich.edu     * This timer is used to control the speaker, which
1094016Sstever@eecs.umich.edu     * we normally could care less about, however it is
1104016Sstever@eecs.umich.edu     * also used to calculated the clockspeed and hense
1115501Snate@binkert.org     * bogomips which is kinda important to the scheduler
1125605Snate@binkert.org     * so we need to implemnt it although after boot I can't
1135605Snate@binkert.org     * imagine we would be playing with the PC speaker much
1145605Snate@binkert.org     */
1155605Snate@binkert.org    ClockEvent timer2;
1165501Snate@binkert.org
1174016Sstever@eecs.umich.edu    RTCEvent rtc;
1185577SSteve.Reinhardt@amd.com
1195501Snate@binkert.org    uint32_t timerData;
1205501Snate@binkert.org
1215501Snate@binkert.org
1225502Snate@binkert.org  public:
1235502Snate@binkert.org    uint32_t  frequency() const { return RTC_RATE; }
1245605Snate@binkert.org
1255502Snate@binkert.org    TsunamiIO(const std::string &name, Tsunami *t, time_t init_time,
1265502Snate@binkert.org              Addr a, MemoryController *mmu);
1275605Snate@binkert.org
1285605Snate@binkert.org    void set_time(time_t t);
1295605Snate@binkert.org
1305577SSteve.Reinhardt@amd.com    virtual Fault read(MemReqPtr &req, uint8_t *data);
1315502Snate@binkert.org    virtual Fault write(MemReqPtr &req, const uint8_t *data);
1325502Snate@binkert.org
1335502Snate@binkert.org    void postPIC(uint8_t bitvector);
1345502Snate@binkert.org    void clearPIC(uint8_t bitvector);
1352SN/A
1365769Snate@binkert.org    virtual void serialize(std::ostream &os);
1375769Snate@binkert.org    virtual void unserialize(Checkpoint *cp, const std::string &section);
1385769Snate@binkert.org};
1395769Snate@binkert.org
1405769Snate@binkert.org#endif // __TSUNAMI_IO_HH__
1415769Snate@binkert.org