comm.hh revision 2665
17008Snate@binkert.org/* 27008Snate@binkert.org * Copyright (c) 2004-2005 The Regents of The University of Michigan 37008Snate@binkert.org * All rights reserved. 47008Snate@binkert.org * 57008Snate@binkert.org * Redistribution and use in source and binary forms, with or without 67008Snate@binkert.org * modification, are permitted provided that the following conditions are 77008Snate@binkert.org * met: redistributions of source code must retain the above copyright 87008Snate@binkert.org * notice, this list of conditions and the following disclaimer; 97008Snate@binkert.org * redistributions in binary form must reproduce the above copyright 107008Snate@binkert.org * notice, this list of conditions and the following disclaimer in the 117008Snate@binkert.org * documentation and/or other materials provided with the distribution; 127008Snate@binkert.org * neither the name of the copyright holders nor the names of its 137008Snate@binkert.org * contributors may be used to endorse or promote products derived from 147008Snate@binkert.org * this software without specific prior written permission. 157008Snate@binkert.org * 167008Snate@binkert.org * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 177008Snate@binkert.org * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 187008Snate@binkert.org * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 197008Snate@binkert.org * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 207008Snate@binkert.org * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 217008Snate@binkert.org * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 227008Snate@binkert.org * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 237008Snate@binkert.org * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 247008Snate@binkert.org * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 257008Snate@binkert.org * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 267008Snate@binkert.org * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 277008Snate@binkert.org * 286285Snate@binkert.org * Authors: Kevin Lim 297039Snate@binkert.org */ 307039Snate@binkert.org 316285Snate@binkert.org#ifndef __CPU_O3_CPU_COMM_HH__ 327055Snate@binkert.org#define __CPU_O3_CPU_COMM_HH__ 337055Snate@binkert.org 346876Ssteve.reinhardt@amd.com#include <vector> 359745Snilay@cs.wisc.edu 368341Snilay@cs.wisc.edu#include "arch/isa_traits.hh" 376506Spdudnik@gmail.com#include "cpu/inst_seq.hh" 387055Snate@binkert.org#include "sim/host.hh" 398436SBrad.Beckmann@amd.com 409497Snilay@cs.wisc.edu// Find better place to put this typedef. 4110301Snilay@cs.wisc.edu// The impl might be the best place for this. 4210301Snilay@cs.wisc.edutypedef short int PhysRegIndex; 436881SBrad.Beckmann@amd.com 4410301Snilay@cs.wisc.edutemplate<class Impl> 459364Snilay@cs.wisc.edustruct SimpleFetchSimpleDecode { 467055Snate@binkert.org typedef typename Impl::DynInstPtr DynInstPtr; 479465Snilay@cs.wisc.edu 486285Snate@binkert.org int size; 496285Snate@binkert.org 506285Snate@binkert.org DynInstPtr insts[Impl::MaxWidth]; 519465Snilay@cs.wisc.edu}; 527039Snate@binkert.org 537039Snate@binkert.orgtemplate<class Impl> 546876Ssteve.reinhardt@amd.comstruct SimpleDecodeSimpleRename { 558436SBrad.Beckmann@amd.com typedef typename Impl::DynInstPtr DynInstPtr; 569496Snilay@cs.wisc.edu 578257SBrad.Beckmann@amd.com int size; 589745Snilay@cs.wisc.edu 5910078Snilay@cs.wisc.edu DynInstPtr insts[Impl::MaxWidth]; 6010078Snilay@cs.wisc.edu}; 6110078Snilay@cs.wisc.edu 629819Snilay@cs.wisc.edutemplate<class Impl> 639819Snilay@cs.wisc.edustruct SimpleRenameSimpleIEW { 649819Snilay@cs.wisc.edu typedef typename Impl::DynInstPtr DynInstPtr; 659819Snilay@cs.wisc.edu 669819Snilay@cs.wisc.edu int size; 679819Snilay@cs.wisc.edu 687039Snate@binkert.org DynInstPtr insts[Impl::MaxWidth]; 698531Snilay@cs.wisc.edu}; 706285Snate@binkert.org 717055Snate@binkert.orgtemplate<class Impl> 727039Snate@binkert.orgstruct SimpleIEWSimpleCommit { 7310012Snilay@cs.wisc.edu typedef typename Impl::DynInstPtr DynInstPtr; 7410012Snilay@cs.wisc.edu 759745Snilay@cs.wisc.edu int size; 768683Snilay@cs.wisc.edu 778683Snilay@cs.wisc.edu DynInstPtr insts[Impl::MaxWidth]; 789302Snilay@cs.wisc.edu 7910523Snilay@cs.wisc.edu bool squash; 8010523Snilay@cs.wisc.edu bool branchMispredict; 8110522Snilay@cs.wisc.edu bool branchTaken; 829302Snilay@cs.wisc.edu uint64_t mispredPC; 839302Snilay@cs.wisc.edu uint64_t nextPC; 849302Snilay@cs.wisc.edu InstSeqNum squashedSeqNum; 8510522Snilay@cs.wisc.edu}; 869363Snilay@cs.wisc.edu 879363Snilay@cs.wisc.edutemplate<class Impl> 889363Snilay@cs.wisc.edustruct IssueStruct { 899363Snilay@cs.wisc.edu typedef typename Impl::DynInstPtr DynInstPtr; 909364Snilay@cs.wisc.edu 919745Snilay@cs.wisc.edu int size; 929745Snilay@cs.wisc.edu 939745Snilay@cs.wisc.edu DynInstPtr insts[Impl::MaxWidth]; 949745Snilay@cs.wisc.edu}; 959745Snilay@cs.wisc.edu 969745Snilay@cs.wisc.edustruct TimeBufStruct { 9710311Snilay@cs.wisc.edu struct decodeComm { 9810311Snilay@cs.wisc.edu bool squash; 9910311Snilay@cs.wisc.edu bool stall; 1009496Snilay@cs.wisc.edu bool predIncorrect; 1019496Snilay@cs.wisc.edu uint64_t branchAddr; 1029496Snilay@cs.wisc.edu 10310012Snilay@cs.wisc.edu InstSeqNum doneSeqNum; 10410012Snilay@cs.wisc.edu 10510012Snilay@cs.wisc.edu // Might want to package this kind of branch stuff into a single 1069497Snilay@cs.wisc.edu // struct as it is used pretty frequently. 1079496Snilay@cs.wisc.edu bool branchMispredict; 1089496Snilay@cs.wisc.edu bool branchTaken; 1099496Snilay@cs.wisc.edu uint64_t mispredPC; 1109497Snilay@cs.wisc.edu uint64_t nextPC; 1119507Snilay@cs.wisc.edu }; 1129496Snilay@cs.wisc.edu 1139596Snilay@cs.wisc.edu decodeComm decodeInfo; 1149596Snilay@cs.wisc.edu 1159596Snilay@cs.wisc.edu // Rename can't actually tell anything to squash or send a new PC back 1169596Snilay@cs.wisc.edu // because it doesn't do anything along those lines. But maybe leave 1179596Snilay@cs.wisc.edu // these fields in here to keep the stages mostly orthagonal. 1189364Snilay@cs.wisc.edu struct renameComm { 1199364Snilay@cs.wisc.edu bool squash; 12010005Snilay@cs.wisc.edu bool stall; 12110005Snilay@cs.wisc.edu 12210005Snilay@cs.wisc.edu uint64_t nextPC; 1239364Snilay@cs.wisc.edu }; 1249364Snilay@cs.wisc.edu 1259364Snilay@cs.wisc.edu renameComm renameInfo; 12610087Snilay@cs.wisc.edu 1279364Snilay@cs.wisc.edu struct iewComm { 1289364Snilay@cs.wisc.edu bool stall; 1299364Snilay@cs.wisc.edu 13010087Snilay@cs.wisc.edu // Also eventually include skid buffer space. 1319996Snilay@cs.wisc.edu unsigned freeIQEntries; 1329996Snilay@cs.wisc.edu }; 1339364Snilay@cs.wisc.edu 13410005Snilay@cs.wisc.edu iewComm iewInfo; 13510096Snilay@cs.wisc.edu 13610005Snilay@cs.wisc.edu struct commitComm { 1379496Snilay@cs.wisc.edu bool squash; 1389496Snilay@cs.wisc.edu bool stall; 1399496Snilay@cs.wisc.edu unsigned freeROBEntries; 14010012Snilay@cs.wisc.edu 1419497Snilay@cs.wisc.edu bool branchMispredict; 1429497Snilay@cs.wisc.edu bool branchTaken; 1439497Snilay@cs.wisc.edu uint64_t mispredPC; 14410012Snilay@cs.wisc.edu uint64_t nextPC; 14510012Snilay@cs.wisc.edu 1469745Snilay@cs.wisc.edu bool robSquashing; 1479745Snilay@cs.wisc.edu 1489745Snilay@cs.wisc.edu // Represents the instruction that has either been retired or 1499745Snilay@cs.wisc.edu // squashed. Similar to having a single bus that broadcasts the 1509745Snilay@cs.wisc.edu // retired or squashed sequence number. 1519745Snilay@cs.wisc.edu InstSeqNum doneSeqNum; 1529745Snilay@cs.wisc.edu 1539745Snilay@cs.wisc.edu // Extra bit of information so that the LDSTQ only updates when it 1549745Snilay@cs.wisc.edu // needs to. 1559745Snilay@cs.wisc.edu bool commitIsLoad; 15610012Snilay@cs.wisc.edu 1579745Snilay@cs.wisc.edu // Communication specifically to the IQ to tell the IQ that it can 1589745Snilay@cs.wisc.edu // schedule a non-speculative instruction. 1596285Snate@binkert.org InstSeqNum nonSpecSeqNum; 1606285Snate@binkert.org }; 1617039Snate@binkert.org 162 commitComm commitInfo; 163}; 164 165#endif //__CPU_O3_CPU_COMM_HH__ 166