comm.hh revision 2665
1/* 2 * Copyright (c) 2004-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Kevin Lim 29 */ 30 31#ifndef __CPU_O3_CPU_COMM_HH__ 32#define __CPU_O3_CPU_COMM_HH__ 33 34#include <vector> 35 36#include "arch/isa_traits.hh" 37#include "cpu/inst_seq.hh" 38#include "sim/host.hh" 39 40// Find better place to put this typedef. 41// The impl might be the best place for this. 42typedef short int PhysRegIndex; 43 44template<class Impl> 45struct SimpleFetchSimpleDecode { 46 typedef typename Impl::DynInstPtr DynInstPtr; 47 48 int size; 49 50 DynInstPtr insts[Impl::MaxWidth]; 51}; 52 53template<class Impl> 54struct SimpleDecodeSimpleRename { 55 typedef typename Impl::DynInstPtr DynInstPtr; 56 57 int size; 58 59 DynInstPtr insts[Impl::MaxWidth]; 60}; 61 62template<class Impl> 63struct SimpleRenameSimpleIEW { 64 typedef typename Impl::DynInstPtr DynInstPtr; 65 66 int size; 67 68 DynInstPtr insts[Impl::MaxWidth]; 69}; 70 71template<class Impl> 72struct SimpleIEWSimpleCommit { 73 typedef typename Impl::DynInstPtr DynInstPtr; 74 75 int size; 76 77 DynInstPtr insts[Impl::MaxWidth]; 78 79 bool squash; 80 bool branchMispredict; 81 bool branchTaken; 82 uint64_t mispredPC; 83 uint64_t nextPC; 84 InstSeqNum squashedSeqNum; 85}; 86 87template<class Impl> 88struct IssueStruct { 89 typedef typename Impl::DynInstPtr DynInstPtr; 90 91 int size; 92 93 DynInstPtr insts[Impl::MaxWidth]; 94}; 95 96struct TimeBufStruct { 97 struct decodeComm { 98 bool squash; 99 bool stall; 100 bool predIncorrect; 101 uint64_t branchAddr; 102 103 InstSeqNum doneSeqNum; 104 105 // Might want to package this kind of branch stuff into a single 106 // struct as it is used pretty frequently. 107 bool branchMispredict; 108 bool branchTaken; 109 uint64_t mispredPC; 110 uint64_t nextPC; 111 }; 112 113 decodeComm decodeInfo; 114 115 // Rename can't actually tell anything to squash or send a new PC back 116 // because it doesn't do anything along those lines. But maybe leave 117 // these fields in here to keep the stages mostly orthagonal. 118 struct renameComm { 119 bool squash; 120 bool stall; 121 122 uint64_t nextPC; 123 }; 124 125 renameComm renameInfo; 126 127 struct iewComm { 128 bool stall; 129 130 // Also eventually include skid buffer space. 131 unsigned freeIQEntries; 132 }; 133 134 iewComm iewInfo; 135 136 struct commitComm { 137 bool squash; 138 bool stall; 139 unsigned freeROBEntries; 140 141 bool branchMispredict; 142 bool branchTaken; 143 uint64_t mispredPC; 144 uint64_t nextPC; 145 146 bool robSquashing; 147 148 // Represents the instruction that has either been retired or 149 // squashed. Similar to having a single bus that broadcasts the 150 // retired or squashed sequence number. 151 InstSeqNum doneSeqNum; 152 153 // Extra bit of information so that the LDSTQ only updates when it 154 // needs to. 155 bool commitIsLoad; 156 157 // Communication specifically to the IQ to tell the IQ that it can 158 // schedule a non-speculative instruction. 159 InstSeqNum nonSpecSeqNum; 160 }; 161 162 commitComm commitInfo; 163}; 164 165#endif //__CPU_O3_CPU_COMM_HH__ 166