comm.hh revision 1461
12810SN/A#ifndef __CPU_BETA_CPU_COMM_HH__ 212724Snikos.nikoleris@arm.com#define __CPU_BETA_CPU_COMM_HH__ 38856Sandreas.hansson@arm.com 48856Sandreas.hansson@arm.com#include <stdint.h> 58856Sandreas.hansson@arm.com#include <vector> 68856Sandreas.hansson@arm.com#include "arch/alpha/isa_traits.hh" 78856Sandreas.hansson@arm.com#include "cpu/inst_seq.hh" 88856Sandreas.hansson@arm.com 98856Sandreas.hansson@arm.com// Find better place to put this typedef. 108856Sandreas.hansson@arm.com// The impl might be the best place for this. 118856Sandreas.hansson@arm.comtypedef short int PhysRegIndex; 128856Sandreas.hansson@arm.com 138856Sandreas.hansson@arm.comtemplate<class Impl> 142810SN/Astruct SimpleFetchSimpleDecode { 152810SN/A typedef typename Impl::DynInstPtr DynInstPtr; 162810SN/A 172810SN/A int size; 182810SN/A 192810SN/A DynInstPtr insts[Impl::MaxWidth]; 202810SN/A}; 212810SN/A 222810SN/Atemplate<class Impl> 232810SN/Astruct SimpleDecodeSimpleRename { 242810SN/A typedef typename Impl::DynInstPtr DynInstPtr; 252810SN/A 262810SN/A int size; 272810SN/A 282810SN/A DynInstPtr insts[Impl::MaxWidth]; 292810SN/A}; 302810SN/A 312810SN/Atemplate<class Impl> 322810SN/Astruct SimpleRenameSimpleIEW { 332810SN/A typedef typename Impl::DynInstPtr DynInstPtr; 342810SN/A 352810SN/A int size; 362810SN/A 372810SN/A DynInstPtr insts[Impl::MaxWidth]; 382810SN/A}; 392810SN/A 402810SN/Atemplate<class Impl> 414458SN/Astruct SimpleIEWSimpleCommit { 424458SN/A typedef typename Impl::DynInstPtr DynInstPtr; 4312724Snikos.nikoleris@arm.com 4412724Snikos.nikoleris@arm.com int size; 452810SN/A 462810SN/A DynInstPtr insts[Impl::MaxWidth]; 472810SN/A 482810SN/A bool squash; 492810SN/A bool branchMispredict; 502810SN/A bool branchTaken; 512810SN/A uint64_t mispredPC; 5211051Sandreas.hansson@arm.com uint64_t nextPC; 5311051Sandreas.hansson@arm.com unsigned globalHist; 542810SN/A InstSeqNum squashedSeqNum; 5512724Snikos.nikoleris@arm.com}; 5612724Snikos.nikoleris@arm.com 577676Snate@binkert.orgtemplate<class Impl> 582810SN/Astruct IssueStruct { 5912724Snikos.nikoleris@arm.com typedef typename Impl::DynInstPtr DynInstPtr; 602810SN/A 612810SN/A int size; 626215Snate@binkert.org 638232Snate@binkert.org DynInstPtr insts[Impl::MaxWidth]; 648232Snate@binkert.org}; 6512724Snikos.nikoleris@arm.com 6612724Snikos.nikoleris@arm.comstruct TimeBufStruct { 675338Sstever@gmail.com struct decodeComm { 6812724Snikos.nikoleris@arm.com bool squash; 6911375Sandreas.hansson@arm.com bool stall; 7012724Snikos.nikoleris@arm.com bool predIncorrect; 712810SN/A uint64_t branchAddr; 722810SN/A 7312724Snikos.nikoleris@arm.com InstSeqNum doneSeqNum; 748914Sandreas.hansson@arm.com 758229Snate@binkert.org // Might want to package this kind of branch stuff into a single 762811SN/A // struct as it is used pretty frequently. 7712724Snikos.nikoleris@arm.com bool branchMispredict; 784626SN/A bool branchTaken; 798833Sdam.sunwoo@arm.com uint64_t mispredPC; 802810SN/A uint64_t nextPC; 8112724Snikos.nikoleris@arm.com unsigned globalHist; 8212724Snikos.nikoleris@arm.com }; 8312724Snikos.nikoleris@arm.com 8412724Snikos.nikoleris@arm.com decodeComm decodeInfo; 8512724Snikos.nikoleris@arm.com 8612724Snikos.nikoleris@arm.com // Rename can't actually tell anything to squash or send a new PC back 8712724Snikos.nikoleris@arm.com // because it doesn't do anything along those lines. But maybe leave 8812724Snikos.nikoleris@arm.com // these fields in here to keep the stages mostly orthagonal. 892810SN/A struct renameComm { 902810SN/A bool squash; 912810SN/A bool stall; 922810SN/A 932810SN/A uint64_t nextPC; 9411375Sandreas.hansson@arm.com }; 954628SN/A 964628SN/A renameComm renameInfo; 974628SN/A 984628SN/A struct iewComm { 994628SN/A bool stall; 1004628SN/A 1014628SN/A // Also eventually include skid buffer space. 1024628SN/A unsigned freeIQEntries; 1038737Skoansin.tan@gmail.com }; 1044628SN/A 1054628SN/A iewComm iewInfo; 1064628SN/A 1074628SN/A struct commitComm { 1084628SN/A bool squash; 1094628SN/A bool stall; 1104628SN/A unsigned freeROBEntries; 1114628SN/A 1124628SN/A bool branchMispredict; 1134628SN/A bool branchTaken; 1148737Skoansin.tan@gmail.com uint64_t mispredPC; 1154628SN/A uint64_t nextPC; 1168856Sandreas.hansson@arm.com unsigned globalHist; 1178856Sandreas.hansson@arm.com 1188856Sandreas.hansson@arm.com // Think of better names here. 1198856Sandreas.hansson@arm.com // Will need to be a variety of sizes... 1208856Sandreas.hansson@arm.com // Maybe make it a vector, that way only need one object. 12110942Sandreas.hansson@arm.com std::vector<PhysRegIndex> freeRegs; 1228856Sandreas.hansson@arm.com 1238856Sandreas.hansson@arm.com bool robSquashing; 1248856Sandreas.hansson@arm.com 1258922Swilliam.wang@arm.com // Represents the instruction that has either been retired or 1262810SN/A // squashed. Similar to having a single bus that broadcasts the 1278856Sandreas.hansson@arm.com // retired or squashed sequence number. 1282844SN/A InstSeqNum doneSeqNum; 1298856Sandreas.hansson@arm.com 1308856Sandreas.hansson@arm.com // Extra bits of information so that the LDSTQ only updates when it 1318856Sandreas.hansson@arm.com // needs to. 13210713Sandreas.hansson@arm.com bool commitIsStore; 1338856Sandreas.hansson@arm.com bool commitIsLoad; 13410942Sandreas.hansson@arm.com 1358856Sandreas.hansson@arm.com // Communication specifically to the IQ to tell the IQ that it can 13610942Sandreas.hansson@arm.com // schedule a non-speculative instruction. 13710713Sandreas.hansson@arm.com InstSeqNum nonSpecSeqNum; 1388856Sandreas.hansson@arm.com }; 1398856Sandreas.hansson@arm.com 1403738SN/A commitComm commitInfo; 1414458SN/A}; 1428856Sandreas.hansson@arm.com 14310713Sandreas.hansson@arm.com#endif //__CPU_BETA_CPU_COMM_HH__ 14410713Sandreas.hansson@arm.com