comm.hh revision 1461 
1#ifndef __CPU_BETA_CPU_COMM_HH__
2#define __CPU_BETA_CPU_COMM_HH__
3
4#include <stdint.h>
5#include <vector>
6#include "arch/alpha/isa_traits.hh"
7#include "cpu/inst_seq.hh"
8
9// Find better place to put this typedef.
10// The impl might be the best place for this.
11typedef short int PhysRegIndex;
12
13template<class Impl>
14struct SimpleFetchSimpleDecode {
15    typedef typename Impl::DynInstPtr DynInstPtr;
16
17    int size;
18
19    DynInstPtr insts[Impl::MaxWidth];
20};
21
22template<class Impl>
23struct SimpleDecodeSimpleRename {
24    typedef typename Impl::DynInstPtr DynInstPtr;
25
26    int size;
27
28    DynInstPtr insts[Impl::MaxWidth];
29};
30
31template<class Impl>
32struct SimpleRenameSimpleIEW {
33    typedef typename Impl::DynInstPtr DynInstPtr;
34
35    int size;
36
37    DynInstPtr insts[Impl::MaxWidth];
38};
39
40template<class Impl>
41struct SimpleIEWSimpleCommit {
42    typedef typename Impl::DynInstPtr DynInstPtr;
43
44    int size;
45
46    DynInstPtr insts[Impl::MaxWidth];
47
48    bool squash;
49    bool branchMispredict;
50    bool branchTaken;
51    uint64_t mispredPC;
52    uint64_t nextPC;
53    unsigned globalHist;
54    InstSeqNum squashedSeqNum;
55};
56
57template<class Impl>
58struct IssueStruct {
59    typedef typename Impl::DynInstPtr DynInstPtr;
60
61    int size;
62
63    DynInstPtr insts[Impl::MaxWidth];
64};
65
66struct TimeBufStruct {
67    struct decodeComm {
68        bool squash;
69        bool stall;
70        bool predIncorrect;
71        uint64_t branchAddr;
72
73        InstSeqNum doneSeqNum;
74
75        // Might want to package this kind of branch stuff into a single
76        // struct as it is used pretty frequently.
77        bool branchMispredict;
78        bool branchTaken;
79        uint64_t mispredPC;
80        uint64_t nextPC;
81        unsigned globalHist;
82    };
83
84    decodeComm decodeInfo;
85
86    // Rename can't actually tell anything to squash or send a new PC back
87    // because it doesn't do anything along those lines.  But maybe leave
88    // these fields in here to keep the stages mostly orthagonal.
89    struct renameComm {
90        bool squash;
91        bool stall;
92
93        uint64_t nextPC;
94    };
95
96    renameComm renameInfo;
97
98    struct iewComm {
99        bool stall;
100
101        // Also eventually include skid buffer space.
102        unsigned freeIQEntries;
103    };
104
105    iewComm iewInfo;
106
107    struct commitComm {
108        bool squash;
109        bool stall;
110        unsigned freeROBEntries;
111
112        bool branchMispredict;
113        bool branchTaken;
114        uint64_t mispredPC;
115        uint64_t nextPC;
116        unsigned globalHist;
117
118        // Think of better names here.
119        // Will need to be a variety of sizes...
120        // Maybe make it a vector, that way only need one object.
121        std::vector<PhysRegIndex> freeRegs;
122
123        bool robSquashing;
124
125        // Represents the instruction that has either been retired or
126        // squashed.  Similar to having a single bus that broadcasts the
127        // retired or squashed sequence number.
128        InstSeqNum doneSeqNum;
129
130        // Extra bits of information so that the LDSTQ only updates when it
131        // needs to.
132        bool commitIsStore;
133        bool commitIsLoad;
134
135        // Communication specifically to the IQ to tell the IQ that it can
136        // schedule a non-speculative instruction.
137        InstSeqNum nonSpecSeqNum;
138    };
139
140    commitComm commitInfo;
141};
142
143#endif //__CPU_BETA_CPU_COMM_HH__
144