base_dyn_inst.hh revision 8545
11060SN/A/* 27944SGiacomo.Gabrielli@arm.com * Copyright (c) 2011 ARM Limited 37944SGiacomo.Gabrielli@arm.com * All rights reserved. 47944SGiacomo.Gabrielli@arm.com * 57944SGiacomo.Gabrielli@arm.com * The license below extends only to copyright in the software and shall 67944SGiacomo.Gabrielli@arm.com * not be construed as granting a license to any other intellectual 77944SGiacomo.Gabrielli@arm.com * property including but not limited to intellectual property relating 87944SGiacomo.Gabrielli@arm.com * to a hardware implementation of the functionality of the software 97944SGiacomo.Gabrielli@arm.com * licensed hereunder. You may use the software subject to the license 107944SGiacomo.Gabrielli@arm.com * terms below provided that you ensure that this notice is replicated 117944SGiacomo.Gabrielli@arm.com * unmodified and in its entirety in all distributions of the software, 127944SGiacomo.Gabrielli@arm.com * modified or unmodified, in source code or in binary form. 137944SGiacomo.Gabrielli@arm.com * 142702Sktlim@umich.edu * Copyright (c) 2004-2006 The Regents of The University of Michigan 156973Stjones1@inf.ed.ac.uk * Copyright (c) 2009 The University of Edinburgh 161060SN/A * All rights reserved. 171060SN/A * 181060SN/A * Redistribution and use in source and binary forms, with or without 191060SN/A * modification, are permitted provided that the following conditions are 201060SN/A * met: redistributions of source code must retain the above copyright 211060SN/A * notice, this list of conditions and the following disclaimer; 221060SN/A * redistributions in binary form must reproduce the above copyright 231060SN/A * notice, this list of conditions and the following disclaimer in the 241060SN/A * documentation and/or other materials provided with the distribution; 251060SN/A * neither the name of the copyright holders nor the names of its 261060SN/A * contributors may be used to endorse or promote products derived from 271060SN/A * this software without specific prior written permission. 281060SN/A * 291060SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 301060SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 311060SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 321060SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 331060SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 341060SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 351060SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 361060SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 371060SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 381060SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 391060SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402665Ssaidi@eecs.umich.edu * 412665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 426973Stjones1@inf.ed.ac.uk * Timothy M. Jones 431060SN/A */ 441060SN/A 451464SN/A#ifndef __CPU_BASE_DYN_INST_HH__ 461464SN/A#define __CPU_BASE_DYN_INST_HH__ 471060SN/A 482731Sktlim@umich.edu#include <bitset> 492292SN/A#include <list> 501464SN/A#include <string> 511060SN/A 522669Sktlim@umich.edu#include "arch/faults.hh" 537720Sgblack@eecs.umich.edu#include "arch/utility.hh" 541060SN/A#include "base/fast_alloc.hh" 551060SN/A#include "base/trace.hh" 561858SN/A#include "config/full_system.hh" 576658Snate@binkert.org#include "config/the_isa.hh" 583770Sgblack@eecs.umich.edu#include "cpu/o3/comm.hh" 591464SN/A#include "cpu/exetrace.hh" 601464SN/A#include "cpu/inst_seq.hh" 612669Sktlim@umich.edu#include "cpu/op_class.hh" 621060SN/A#include "cpu/static_inst.hh" 636973Stjones1@inf.ed.ac.uk#include "cpu/translation.hh" 642669Sktlim@umich.edu#include "mem/packet.hh" 657678Sgblack@eecs.umich.edu#include "sim/byteswap.hh" 662292SN/A#include "sim/system.hh" 676023Snate@binkert.org#include "sim/tlb.hh" 681060SN/A 691060SN/A/** 701060SN/A * @file 711060SN/A * Defines a dynamic instruction context. 721060SN/A */ 731060SN/A 741060SN/Atemplate <class Impl> 751061SN/Aclass BaseDynInst : public FastAlloc, public RefCounted 761060SN/A{ 771060SN/A public: 781060SN/A // Typedef for the CPU. 792733Sktlim@umich.edu typedef typename Impl::CPUType ImplCPU; 802733Sktlim@umich.edu typedef typename ImplCPU::ImplState ImplState; 811060SN/A 822292SN/A // Logical register index type. 832107SN/A typedef TheISA::RegIndex RegIndex; 842690Sktlim@umich.edu // Integer register type. 852107SN/A typedef TheISA::IntReg IntReg; 862690Sktlim@umich.edu // Floating point register type. 872690Sktlim@umich.edu typedef TheISA::FloatReg FloatReg; 881060SN/A 892292SN/A // The DynInstPtr type. 902292SN/A typedef typename Impl::DynInstPtr DynInstPtr; 918486Sgblack@eecs.umich.edu typedef RefCountingPtr<BaseDynInst<Impl> > BaseDynInstPtr; 922292SN/A 932292SN/A // The list of instructions iterator type. 942292SN/A typedef typename std::list<DynInstPtr>::iterator ListIt; 952292SN/A 961060SN/A enum { 975543Ssaidi@eecs.umich.edu MaxInstSrcRegs = TheISA::MaxInstSrcRegs, /// Max source regs 985543Ssaidi@eecs.umich.edu MaxInstDestRegs = TheISA::MaxInstDestRegs, /// Max dest regs 991060SN/A }; 1001060SN/A 1012292SN/A /** The StaticInst used by this BaseDynInst. */ 1022107SN/A StaticInstPtr staticInst; 1038502Sgblack@eecs.umich.edu StaticInstPtr macroop; 1041060SN/A 1051060SN/A //////////////////////////////////////////// 1061060SN/A // 1071060SN/A // INSTRUCTION EXECUTION 1081060SN/A // 1091060SN/A //////////////////////////////////////////// 1102292SN/A /** InstRecord that tracks this instructions. */ 1111060SN/A Trace::InstRecord *traceData; 1121060SN/A 1135358Sgblack@eecs.umich.edu void demapPage(Addr vaddr, uint64_t asn) 1145358Sgblack@eecs.umich.edu { 1155358Sgblack@eecs.umich.edu cpu->demapPage(vaddr, asn); 1165358Sgblack@eecs.umich.edu } 1175358Sgblack@eecs.umich.edu void demapInstPage(Addr vaddr, uint64_t asn) 1185358Sgblack@eecs.umich.edu { 1195358Sgblack@eecs.umich.edu cpu->demapPage(vaddr, asn); 1205358Sgblack@eecs.umich.edu } 1215358Sgblack@eecs.umich.edu void demapDataPage(Addr vaddr, uint64_t asn) 1225358Sgblack@eecs.umich.edu { 1235358Sgblack@eecs.umich.edu cpu->demapPage(vaddr, asn); 1245358Sgblack@eecs.umich.edu } 1255358Sgblack@eecs.umich.edu 1268444Sgblack@eecs.umich.edu Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags); 1277520Sgblack@eecs.umich.edu 1288444Sgblack@eecs.umich.edu Fault writeMem(uint8_t *data, unsigned size, 1298444Sgblack@eecs.umich.edu Addr addr, unsigned flags, uint64_t *res); 1307520Sgblack@eecs.umich.edu 1316974Stjones1@inf.ed.ac.uk /** Splits a request in two if it crosses a dcache block. */ 1326974Stjones1@inf.ed.ac.uk void splitRequest(RequestPtr req, RequestPtr &sreqLow, 1336974Stjones1@inf.ed.ac.uk RequestPtr &sreqHigh); 1346974Stjones1@inf.ed.ac.uk 1356973Stjones1@inf.ed.ac.uk /** Initiate a DTB address translation. */ 1366974Stjones1@inf.ed.ac.uk void initiateTranslation(RequestPtr req, RequestPtr sreqLow, 1376974Stjones1@inf.ed.ac.uk RequestPtr sreqHigh, uint64_t *res, 1386973Stjones1@inf.ed.ac.uk BaseTLB::Mode mode); 1396973Stjones1@inf.ed.ac.uk 1406973Stjones1@inf.ed.ac.uk /** Finish a DTB address translation. */ 1416973Stjones1@inf.ed.ac.uk void finishTranslation(WholeTranslationState *state); 1421060SN/A 1437944SGiacomo.Gabrielli@arm.com /** True if the DTB address translation has started. */ 1447944SGiacomo.Gabrielli@arm.com bool translationStarted; 1457944SGiacomo.Gabrielli@arm.com 1467944SGiacomo.Gabrielli@arm.com /** True if the DTB address translation has completed. */ 1477944SGiacomo.Gabrielli@arm.com bool translationCompleted; 1487944SGiacomo.Gabrielli@arm.com 1498545Ssaidi@eecs.umich.edu /** True if this address was found to match a previous load and they issued 1508545Ssaidi@eecs.umich.edu * out of order. If that happend, then it's only a problem if an incoming 1518545Ssaidi@eecs.umich.edu * snoop invalidate modifies the line, in which case we need to squash. 1528545Ssaidi@eecs.umich.edu * If nothing modified the line the order doesn't matter. 1538545Ssaidi@eecs.umich.edu */ 1548545Ssaidi@eecs.umich.edu bool possibleLoadViolation; 1558545Ssaidi@eecs.umich.edu 1568545Ssaidi@eecs.umich.edu /** True if the address hit a external snoop while sitting in the LSQ. 1578545Ssaidi@eecs.umich.edu * If this is true and a older instruction sees it, this instruction must 1588545Ssaidi@eecs.umich.edu * reexecute 1598545Ssaidi@eecs.umich.edu */ 1608545Ssaidi@eecs.umich.edu bool hitExternalSnoop; 1618545Ssaidi@eecs.umich.edu 1627944SGiacomo.Gabrielli@arm.com /** 1637944SGiacomo.Gabrielli@arm.com * Returns true if the DTB address translation is being delayed due to a hw 1647944SGiacomo.Gabrielli@arm.com * page table walk. 1657944SGiacomo.Gabrielli@arm.com */ 1667944SGiacomo.Gabrielli@arm.com bool isTranslationDelayed() const 1677944SGiacomo.Gabrielli@arm.com { 1687944SGiacomo.Gabrielli@arm.com return (translationStarted && !translationCompleted); 1697944SGiacomo.Gabrielli@arm.com } 1707944SGiacomo.Gabrielli@arm.com 1717944SGiacomo.Gabrielli@arm.com /** 1727944SGiacomo.Gabrielli@arm.com * Saved memory requests (needed when the DTB address translation is 1737944SGiacomo.Gabrielli@arm.com * delayed due to a hw page table walk). 1747944SGiacomo.Gabrielli@arm.com */ 1757944SGiacomo.Gabrielli@arm.com RequestPtr savedReq; 1767944SGiacomo.Gabrielli@arm.com RequestPtr savedSreqLow; 1777944SGiacomo.Gabrielli@arm.com RequestPtr savedSreqHigh; 1787944SGiacomo.Gabrielli@arm.com 1791684SN/A /** @todo: Consider making this private. */ 1801060SN/A public: 1811060SN/A /** The sequence number of the instruction. */ 1821060SN/A InstSeqNum seqNum; 1831060SN/A 1842731Sktlim@umich.edu enum Status { 1852731Sktlim@umich.edu IqEntry, /// Instruction is in the IQ 1862731Sktlim@umich.edu RobEntry, /// Instruction is in the ROB 1872731Sktlim@umich.edu LsqEntry, /// Instruction is in the LSQ 1882731Sktlim@umich.edu Completed, /// Instruction has completed 1892731Sktlim@umich.edu ResultReady, /// Instruction has its result 1902731Sktlim@umich.edu CanIssue, /// Instruction can issue and execute 1912731Sktlim@umich.edu Issued, /// Instruction has issued 1922731Sktlim@umich.edu Executed, /// Instruction has executed 1932731Sktlim@umich.edu CanCommit, /// Instruction can commit 1942731Sktlim@umich.edu AtCommit, /// Instruction has reached commit 1952731Sktlim@umich.edu Committed, /// Instruction has committed 1962731Sktlim@umich.edu Squashed, /// Instruction is squashed 1972731Sktlim@umich.edu SquashedInIQ, /// Instruction is squashed in the IQ 1982731Sktlim@umich.edu SquashedInLSQ, /// Instruction is squashed in the LSQ 1992731Sktlim@umich.edu SquashedInROB, /// Instruction is squashed in the ROB 2002731Sktlim@umich.edu RecoverInst, /// Is a recover instruction 2012731Sktlim@umich.edu BlockingInst, /// Is a blocking instruction 2022731Sktlim@umich.edu ThreadsyncWait, /// Is a thread synchronization instruction 2032731Sktlim@umich.edu SerializeBefore, /// Needs to serialize on 2042731Sktlim@umich.edu /// instructions ahead of it 2052731Sktlim@umich.edu SerializeAfter, /// Needs to serialize instructions behind it 2062731Sktlim@umich.edu SerializeHandled, /// Serialization has been handled 2072731Sktlim@umich.edu NumStatus 2082731Sktlim@umich.edu }; 2092292SN/A 2102731Sktlim@umich.edu /** The status of this BaseDynInst. Several bits can be set. */ 2112731Sktlim@umich.edu std::bitset<NumStatus> status; 2121060SN/A 2131060SN/A /** The thread this instruction is from. */ 2146221Snate@binkert.org ThreadID threadNumber; 2151060SN/A 2161060SN/A /** data address space ID, for loads & stores. */ 2171060SN/A short asid; 2181060SN/A 2192292SN/A /** How many source registers are ready. */ 2202292SN/A unsigned readyRegs; 2212292SN/A 2222733Sktlim@umich.edu /** Pointer to the Impl's CPU object. */ 2232733Sktlim@umich.edu ImplCPU *cpu; 2241060SN/A 2252680Sktlim@umich.edu /** Pointer to the thread state. */ 2262292SN/A ImplState *thread; 2271060SN/A 2281060SN/A /** The kind of fault this instruction has generated. */ 2292132SN/A Fault fault; 2301060SN/A 2312702Sktlim@umich.edu /** Pointer to the data for the memory access. */ 2322669Sktlim@umich.edu uint8_t *memData; 2332292SN/A 2341060SN/A /** The effective virtual address (lds & stores only). */ 2351060SN/A Addr effAddr; 2361060SN/A 2378199SAli.Saidi@ARM.com /** The size of the request */ 2388199SAli.Saidi@ARM.com Addr effSize; 2398199SAli.Saidi@ARM.com 2404032Sktlim@umich.edu /** Is the effective virtual address valid. */ 2414032Sktlim@umich.edu bool effAddrValid; 2424032Sktlim@umich.edu 2431060SN/A /** The effective physical address. */ 2441060SN/A Addr physEffAddr; 2451060SN/A 2461060SN/A /** The memory request flags (from translation). */ 2471060SN/A unsigned memReqFlags; 2481060SN/A 2491464SN/A union Result { 2501464SN/A uint64_t integer; 2512356SN/A// float fp; 2521464SN/A double dbl; 2531464SN/A }; 2541060SN/A 2551464SN/A /** The result of the instruction; assumes for now that there's only one 2561464SN/A * destination register. 2571464SN/A */ 2581464SN/A Result instResult; 2591060SN/A 2603326Sktlim@umich.edu /** Records changes to result? */ 2613326Sktlim@umich.edu bool recordResult; 2623326Sktlim@umich.edu 2637597Sminkyu.jeong@arm.com /** Did this instruction execute, or is it predicated false */ 2647597Sminkyu.jeong@arm.com bool predicate; 2657597Sminkyu.jeong@arm.com 2663965Sgblack@eecs.umich.edu protected: 2677720Sgblack@eecs.umich.edu /** PC state for this instruction. */ 2687720Sgblack@eecs.umich.edu TheISA::PCState pc; 2691060SN/A 2707720Sgblack@eecs.umich.edu /** Predicted PC state after this instruction. */ 2717720Sgblack@eecs.umich.edu TheISA::PCState predPC; 2724636Sgblack@eecs.umich.edu 2733794Sgblack@eecs.umich.edu /** If this is a branch that was predicted taken */ 2743794Sgblack@eecs.umich.edu bool predTaken; 2753794Sgblack@eecs.umich.edu 2763965Sgblack@eecs.umich.edu public: 2773965Sgblack@eecs.umich.edu 2782292SN/A#ifdef DEBUG 2792292SN/A void dumpSNList(); 2802292SN/A#endif 2812292SN/A 2822292SN/A /** Whether or not the source register is ready. 2832292SN/A * @todo: Not sure this should be here vs the derived class. 2841060SN/A */ 2851060SN/A bool _readySrcRegIdx[MaxInstSrcRegs]; 2861060SN/A 2873770Sgblack@eecs.umich.edu protected: 2883770Sgblack@eecs.umich.edu /** Flattened register index of the destination registers of this 2893770Sgblack@eecs.umich.edu * instruction. 2903770Sgblack@eecs.umich.edu */ 2913770Sgblack@eecs.umich.edu TheISA::RegIndex _flatDestRegIdx[TheISA::MaxInstDestRegs]; 2923770Sgblack@eecs.umich.edu 2933770Sgblack@eecs.umich.edu /** Flattened register index of the source registers of this 2943770Sgblack@eecs.umich.edu * instruction. 2953770Sgblack@eecs.umich.edu */ 2963770Sgblack@eecs.umich.edu TheISA::RegIndex _flatSrcRegIdx[TheISA::MaxInstSrcRegs]; 2973770Sgblack@eecs.umich.edu 2983770Sgblack@eecs.umich.edu /** Physical register index of the destination registers of this 2993770Sgblack@eecs.umich.edu * instruction. 3003770Sgblack@eecs.umich.edu */ 3013770Sgblack@eecs.umich.edu PhysRegIndex _destRegIdx[TheISA::MaxInstDestRegs]; 3023770Sgblack@eecs.umich.edu 3033770Sgblack@eecs.umich.edu /** Physical register index of the source registers of this 3043770Sgblack@eecs.umich.edu * instruction. 3053770Sgblack@eecs.umich.edu */ 3063770Sgblack@eecs.umich.edu PhysRegIndex _srcRegIdx[TheISA::MaxInstSrcRegs]; 3073770Sgblack@eecs.umich.edu 3083770Sgblack@eecs.umich.edu /** Physical register index of the previous producers of the 3093770Sgblack@eecs.umich.edu * architected destinations. 3103770Sgblack@eecs.umich.edu */ 3113770Sgblack@eecs.umich.edu PhysRegIndex _prevDestRegIdx[TheISA::MaxInstDestRegs]; 3123770Sgblack@eecs.umich.edu 3131060SN/A public: 3143770Sgblack@eecs.umich.edu 3153770Sgblack@eecs.umich.edu /** Returns the physical register index of the i'th destination 3163770Sgblack@eecs.umich.edu * register. 3173770Sgblack@eecs.umich.edu */ 3183770Sgblack@eecs.umich.edu PhysRegIndex renamedDestRegIdx(int idx) const 3193770Sgblack@eecs.umich.edu { 3203770Sgblack@eecs.umich.edu return _destRegIdx[idx]; 3213770Sgblack@eecs.umich.edu } 3223770Sgblack@eecs.umich.edu 3233770Sgblack@eecs.umich.edu /** Returns the physical register index of the i'th source register. */ 3243770Sgblack@eecs.umich.edu PhysRegIndex renamedSrcRegIdx(int idx) const 3253770Sgblack@eecs.umich.edu { 3263770Sgblack@eecs.umich.edu return _srcRegIdx[idx]; 3273770Sgblack@eecs.umich.edu } 3283770Sgblack@eecs.umich.edu 3293770Sgblack@eecs.umich.edu /** Returns the flattened register index of the i'th destination 3303770Sgblack@eecs.umich.edu * register. 3313770Sgblack@eecs.umich.edu */ 3323770Sgblack@eecs.umich.edu TheISA::RegIndex flattenedDestRegIdx(int idx) const 3333770Sgblack@eecs.umich.edu { 3343770Sgblack@eecs.umich.edu return _flatDestRegIdx[idx]; 3353770Sgblack@eecs.umich.edu } 3363770Sgblack@eecs.umich.edu 3373770Sgblack@eecs.umich.edu /** Returns the flattened register index of the i'th source register */ 3383770Sgblack@eecs.umich.edu TheISA::RegIndex flattenedSrcRegIdx(int idx) const 3393770Sgblack@eecs.umich.edu { 3403770Sgblack@eecs.umich.edu return _flatSrcRegIdx[idx]; 3413770Sgblack@eecs.umich.edu } 3423770Sgblack@eecs.umich.edu 3433770Sgblack@eecs.umich.edu /** Returns the physical register index of the previous physical register 3443770Sgblack@eecs.umich.edu * that remapped to the same logical register index. 3453770Sgblack@eecs.umich.edu */ 3463770Sgblack@eecs.umich.edu PhysRegIndex prevDestRegIdx(int idx) const 3473770Sgblack@eecs.umich.edu { 3483770Sgblack@eecs.umich.edu return _prevDestRegIdx[idx]; 3493770Sgblack@eecs.umich.edu } 3503770Sgblack@eecs.umich.edu 3513770Sgblack@eecs.umich.edu /** Renames a destination register to a physical register. Also records 3523770Sgblack@eecs.umich.edu * the previous physical register that the logical register mapped to. 3533770Sgblack@eecs.umich.edu */ 3543770Sgblack@eecs.umich.edu void renameDestReg(int idx, 3553770Sgblack@eecs.umich.edu PhysRegIndex renamed_dest, 3563770Sgblack@eecs.umich.edu PhysRegIndex previous_rename) 3573770Sgblack@eecs.umich.edu { 3583770Sgblack@eecs.umich.edu _destRegIdx[idx] = renamed_dest; 3593770Sgblack@eecs.umich.edu _prevDestRegIdx[idx] = previous_rename; 3603770Sgblack@eecs.umich.edu } 3613770Sgblack@eecs.umich.edu 3623770Sgblack@eecs.umich.edu /** Renames a source logical register to the physical register which 3633770Sgblack@eecs.umich.edu * has/will produce that logical register's result. 3643770Sgblack@eecs.umich.edu * @todo: add in whether or not the source register is ready. 3653770Sgblack@eecs.umich.edu */ 3663770Sgblack@eecs.umich.edu void renameSrcReg(int idx, PhysRegIndex renamed_src) 3673770Sgblack@eecs.umich.edu { 3683770Sgblack@eecs.umich.edu _srcRegIdx[idx] = renamed_src; 3693770Sgblack@eecs.umich.edu } 3703770Sgblack@eecs.umich.edu 3713770Sgblack@eecs.umich.edu /** Flattens a source architectural register index into a logical index. 3723770Sgblack@eecs.umich.edu */ 3733770Sgblack@eecs.umich.edu void flattenSrcReg(int idx, TheISA::RegIndex flattened_src) 3743770Sgblack@eecs.umich.edu { 3753770Sgblack@eecs.umich.edu _flatSrcRegIdx[idx] = flattened_src; 3763770Sgblack@eecs.umich.edu } 3773770Sgblack@eecs.umich.edu 3783770Sgblack@eecs.umich.edu /** Flattens a destination architectural register index into a logical 3793770Sgblack@eecs.umich.edu * index. 3803770Sgblack@eecs.umich.edu */ 3813770Sgblack@eecs.umich.edu void flattenDestReg(int idx, TheISA::RegIndex flattened_dest) 3823770Sgblack@eecs.umich.edu { 3833770Sgblack@eecs.umich.edu _flatDestRegIdx[idx] = flattened_dest; 3843770Sgblack@eecs.umich.edu } 3854636Sgblack@eecs.umich.edu /** BaseDynInst constructor given a binary instruction. 3864636Sgblack@eecs.umich.edu * @param staticInst A StaticInstPtr to the underlying instruction. 3877720Sgblack@eecs.umich.edu * @param pc The PC state for the instruction. 3887720Sgblack@eecs.umich.edu * @param predPC The predicted next PC state for the instruction. 3894636Sgblack@eecs.umich.edu * @param seq_num The sequence number of the instruction. 3904636Sgblack@eecs.umich.edu * @param cpu Pointer to the instruction's CPU. 3914636Sgblack@eecs.umich.edu */ 3928502Sgblack@eecs.umich.edu BaseDynInst(StaticInstPtr staticInst, StaticInstPtr macroop, 3938502Sgblack@eecs.umich.edu TheISA::PCState pc, TheISA::PCState predPC, 3948502Sgblack@eecs.umich.edu InstSeqNum seq_num, ImplCPU *cpu); 3953770Sgblack@eecs.umich.edu 3962292SN/A /** BaseDynInst constructor given a StaticInst pointer. 3972292SN/A * @param _staticInst The StaticInst for this BaseDynInst. 3982292SN/A */ 3998502Sgblack@eecs.umich.edu BaseDynInst(StaticInstPtr staticInst, StaticInstPtr macroop); 4001060SN/A 4011060SN/A /** BaseDynInst destructor. */ 4021060SN/A ~BaseDynInst(); 4031060SN/A 4041464SN/A private: 4051684SN/A /** Function to initialize variables in the constructors. */ 4061464SN/A void initVars(); 4071060SN/A 4081464SN/A public: 4091060SN/A /** Dumps out contents of this BaseDynInst. */ 4101060SN/A void dump(); 4111060SN/A 4121060SN/A /** Dumps out contents of this BaseDynInst into given string. */ 4131060SN/A void dump(std::string &outstring); 4141060SN/A 4153326Sktlim@umich.edu /** Read this CPU's ID. */ 4165712Shsul@eecs.umich.edu int cpuId() { return cpu->cpuId(); } 4173326Sktlim@umich.edu 4185714Shsul@eecs.umich.edu /** Read this context's system-wide ID **/ 4195714Shsul@eecs.umich.edu int contextId() { return thread->contextId(); } 4205714Shsul@eecs.umich.edu 4211060SN/A /** Returns the fault type. */ 4222132SN/A Fault getFault() { return fault; } 4231060SN/A 4241060SN/A /** Checks whether or not this instruction has had its branch target 4251060SN/A * calculated yet. For now it is not utilized and is hacked to be 4261060SN/A * always false. 4272292SN/A * @todo: Actually use this instruction. 4281060SN/A */ 4291060SN/A bool doneTargCalc() { return false; } 4301060SN/A 4317720Sgblack@eecs.umich.edu /** Set the predicted target of this current instruction. */ 4327720Sgblack@eecs.umich.edu void setPredTarg(const TheISA::PCState &_predPC) 4333965Sgblack@eecs.umich.edu { 4347720Sgblack@eecs.umich.edu predPC = _predPC; 4353965Sgblack@eecs.umich.edu } 4362935Sksewell@umich.edu 4377720Sgblack@eecs.umich.edu const TheISA::PCState &readPredTarg() { return predPC; } 4381060SN/A 4393794Sgblack@eecs.umich.edu /** Returns the predicted PC immediately after the branch. */ 4407720Sgblack@eecs.umich.edu Addr predInstAddr() { return predPC.instAddr(); } 4413794Sgblack@eecs.umich.edu 4423794Sgblack@eecs.umich.edu /** Returns the predicted PC two instructions after the branch */ 4437720Sgblack@eecs.umich.edu Addr predNextInstAddr() { return predPC.nextInstAddr(); } 4441060SN/A 4454636Sgblack@eecs.umich.edu /** Returns the predicted micro PC after the branch */ 4467720Sgblack@eecs.umich.edu Addr predMicroPC() { return predPC.microPC(); } 4474636Sgblack@eecs.umich.edu 4481060SN/A /** Returns whether the instruction was predicted taken or not. */ 4493794Sgblack@eecs.umich.edu bool readPredTaken() 4503794Sgblack@eecs.umich.edu { 4513794Sgblack@eecs.umich.edu return predTaken; 4523794Sgblack@eecs.umich.edu } 4533794Sgblack@eecs.umich.edu 4543794Sgblack@eecs.umich.edu void setPredTaken(bool predicted_taken) 4553794Sgblack@eecs.umich.edu { 4563794Sgblack@eecs.umich.edu predTaken = predicted_taken; 4573794Sgblack@eecs.umich.edu } 4581060SN/A 4591060SN/A /** Returns whether the instruction mispredicted. */ 4602935Sksewell@umich.edu bool mispredicted() 4613794Sgblack@eecs.umich.edu { 4627720Sgblack@eecs.umich.edu TheISA::PCState tempPC = pc; 4637720Sgblack@eecs.umich.edu TheISA::advancePC(tempPC, staticInst); 4647720Sgblack@eecs.umich.edu return !(tempPC == predPC); 4653794Sgblack@eecs.umich.edu } 4663794Sgblack@eecs.umich.edu 4671060SN/A // 4681060SN/A // Instruction types. Forward checks to StaticInst object. 4691060SN/A // 4705543Ssaidi@eecs.umich.edu bool isNop() const { return staticInst->isNop(); } 4715543Ssaidi@eecs.umich.edu bool isMemRef() const { return staticInst->isMemRef(); } 4725543Ssaidi@eecs.umich.edu bool isLoad() const { return staticInst->isLoad(); } 4735543Ssaidi@eecs.umich.edu bool isStore() const { return staticInst->isStore(); } 4742336SN/A bool isStoreConditional() const 4752336SN/A { return staticInst->isStoreConditional(); } 4761060SN/A bool isInstPrefetch() const { return staticInst->isInstPrefetch(); } 4771060SN/A bool isDataPrefetch() const { return staticInst->isDataPrefetch(); } 4785543Ssaidi@eecs.umich.edu bool isInteger() const { return staticInst->isInteger(); } 4795543Ssaidi@eecs.umich.edu bool isFloating() const { return staticInst->isFloating(); } 4805543Ssaidi@eecs.umich.edu bool isControl() const { return staticInst->isControl(); } 4815543Ssaidi@eecs.umich.edu bool isCall() const { return staticInst->isCall(); } 4825543Ssaidi@eecs.umich.edu bool isReturn() const { return staticInst->isReturn(); } 4835543Ssaidi@eecs.umich.edu bool isDirectCtrl() const { return staticInst->isDirectCtrl(); } 4841060SN/A bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); } 4855543Ssaidi@eecs.umich.edu bool isCondCtrl() const { return staticInst->isCondCtrl(); } 4865543Ssaidi@eecs.umich.edu bool isUncondCtrl() const { return staticInst->isUncondCtrl(); } 4872935Sksewell@umich.edu bool isCondDelaySlot() const { return staticInst->isCondDelaySlot(); } 4881060SN/A bool isThreadSync() const { return staticInst->isThreadSync(); } 4891060SN/A bool isSerializing() const { return staticInst->isSerializing(); } 4902292SN/A bool isSerializeBefore() const 4912731Sktlim@umich.edu { return staticInst->isSerializeBefore() || status[SerializeBefore]; } 4922292SN/A bool isSerializeAfter() const 4932731Sktlim@umich.edu { return staticInst->isSerializeAfter() || status[SerializeAfter]; } 4947784SAli.Saidi@ARM.com bool isSquashAfter() const { return staticInst->isSquashAfter(); } 4951060SN/A bool isMemBarrier() const { return staticInst->isMemBarrier(); } 4961060SN/A bool isWriteBarrier() const { return staticInst->isWriteBarrier(); } 4971060SN/A bool isNonSpeculative() const { return staticInst->isNonSpeculative(); } 4982292SN/A bool isQuiesce() const { return staticInst->isQuiesce(); } 4992336SN/A bool isIprAccess() const { return staticInst->isIprAccess(); } 5002308SN/A bool isUnverifiable() const { return staticInst->isUnverifiable(); } 5014828Sgblack@eecs.umich.edu bool isSyscall() const { return staticInst->isSyscall(); } 5024654Sgblack@eecs.umich.edu bool isMacroop() const { return staticInst->isMacroop(); } 5034654Sgblack@eecs.umich.edu bool isMicroop() const { return staticInst->isMicroop(); } 5044636Sgblack@eecs.umich.edu bool isDelayedCommit() const { return staticInst->isDelayedCommit(); } 5054654Sgblack@eecs.umich.edu bool isLastMicroop() const { return staticInst->isLastMicroop(); } 5064654Sgblack@eecs.umich.edu bool isFirstMicroop() const { return staticInst->isFirstMicroop(); } 5074636Sgblack@eecs.umich.edu bool isMicroBranch() const { return staticInst->isMicroBranch(); } 5082292SN/A 5092292SN/A /** Temporarily sets this instruction as a serialize before instruction. */ 5102731Sktlim@umich.edu void setSerializeBefore() { status.set(SerializeBefore); } 5112292SN/A 5122292SN/A /** Clears the serializeBefore part of this instruction. */ 5132731Sktlim@umich.edu void clearSerializeBefore() { status.reset(SerializeBefore); } 5142292SN/A 5152292SN/A /** Checks if this serializeBefore is only temporarily set. */ 5162731Sktlim@umich.edu bool isTempSerializeBefore() { return status[SerializeBefore]; } 5172292SN/A 5182292SN/A /** Temporarily sets this instruction as a serialize after instruction. */ 5192731Sktlim@umich.edu void setSerializeAfter() { status.set(SerializeAfter); } 5202292SN/A 5212292SN/A /** Clears the serializeAfter part of this instruction.*/ 5222731Sktlim@umich.edu void clearSerializeAfter() { status.reset(SerializeAfter); } 5232292SN/A 5242292SN/A /** Checks if this serializeAfter is only temporarily set. */ 5252731Sktlim@umich.edu bool isTempSerializeAfter() { return status[SerializeAfter]; } 5262292SN/A 5272731Sktlim@umich.edu /** Sets the serialization part of this instruction as handled. */ 5282731Sktlim@umich.edu void setSerializeHandled() { status.set(SerializeHandled); } 5292292SN/A 5302292SN/A /** Checks if the serialization part of this instruction has been 5312292SN/A * handled. This does not apply to the temporary serializing 5322292SN/A * state; it only applies to this instruction's own permanent 5332292SN/A * serializing state. 5342292SN/A */ 5352731Sktlim@umich.edu bool isSerializeHandled() { return status[SerializeHandled]; } 5361060SN/A 5371464SN/A /** Returns the opclass of this instruction. */ 5381464SN/A OpClass opClass() const { return staticInst->opClass(); } 5391464SN/A 5401464SN/A /** Returns the branch target address. */ 5417720Sgblack@eecs.umich.edu TheISA::PCState branchTarget() const 5427720Sgblack@eecs.umich.edu { return staticInst->branchTarget(pc); } 5431464SN/A 5442292SN/A /** Returns the number of source registers. */ 5455543Ssaidi@eecs.umich.edu int8_t numSrcRegs() const { return staticInst->numSrcRegs(); } 5461684SN/A 5472292SN/A /** Returns the number of destination registers. */ 5481060SN/A int8_t numDestRegs() const { return staticInst->numDestRegs(); } 5491060SN/A 5501060SN/A // the following are used to track physical register usage 5511060SN/A // for machines with separate int & FP reg files 5521060SN/A int8_t numFPDestRegs() const { return staticInst->numFPDestRegs(); } 5531060SN/A int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); } 5541060SN/A 5551060SN/A /** Returns the logical register index of the i'th destination register. */ 5562292SN/A RegIndex destRegIdx(int i) const { return staticInst->destRegIdx(i); } 5571060SN/A 5581060SN/A /** Returns the logical register index of the i'th source register. */ 5592292SN/A RegIndex srcRegIdx(int i) const { return staticInst->srcRegIdx(i); } 5601060SN/A 5611684SN/A /** Returns the result of an integer instruction. */ 5621464SN/A uint64_t readIntResult() { return instResult.integer; } 5631684SN/A 5641684SN/A /** Returns the result of a floating point instruction. */ 5652356SN/A float readFloatResult() { return (float)instResult.dbl; } 5661684SN/A 5671684SN/A /** Returns the result of a floating point (double) instruction. */ 5681464SN/A double readDoubleResult() { return instResult.dbl; } 5691060SN/A 5702702Sktlim@umich.edu /** Records an integer register being set to a value. */ 5713735Sstever@eecs.umich.edu void setIntRegOperand(const StaticInst *si, int idx, uint64_t val) 5721060SN/A { 5733326Sktlim@umich.edu if (recordResult) 5743326Sktlim@umich.edu instResult.integer = val; 5751060SN/A } 5761060SN/A 5772702Sktlim@umich.edu /** Records an fp register being set to a value. */ 5783735Sstever@eecs.umich.edu void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val, 5793735Sstever@eecs.umich.edu int width) 5802690Sktlim@umich.edu { 5813326Sktlim@umich.edu if (recordResult) { 5823326Sktlim@umich.edu if (width == 32) 5833326Sktlim@umich.edu instResult.dbl = (double)val; 5843326Sktlim@umich.edu else if (width == 64) 5853326Sktlim@umich.edu instResult.dbl = val; 5863326Sktlim@umich.edu else 5873326Sktlim@umich.edu panic("Unsupported width!"); 5883326Sktlim@umich.edu } 5892690Sktlim@umich.edu } 5902690Sktlim@umich.edu 5912702Sktlim@umich.edu /** Records an fp register being set to a value. */ 5923735Sstever@eecs.umich.edu void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val) 5931060SN/A { 5943326Sktlim@umich.edu if (recordResult) 5953326Sktlim@umich.edu instResult.dbl = (double)val; 5962308SN/A } 5971060SN/A 5982702Sktlim@umich.edu /** Records an fp register being set to an integer value. */ 5993735Sstever@eecs.umich.edu void setFloatRegOperandBits(const StaticInst *si, int idx, uint64_t val, 6003735Sstever@eecs.umich.edu int width) 6012308SN/A { 6023326Sktlim@umich.edu if (recordResult) 6033326Sktlim@umich.edu instResult.integer = val; 6042308SN/A } 6051060SN/A 6062702Sktlim@umich.edu /** Records an fp register being set to an integer value. */ 6073735Sstever@eecs.umich.edu void setFloatRegOperandBits(const StaticInst *si, int idx, uint64_t val) 6082308SN/A { 6093326Sktlim@umich.edu if (recordResult) 6103326Sktlim@umich.edu instResult.integer = val; 6111060SN/A } 6121060SN/A 6132190SN/A /** Records that one of the source registers is ready. */ 6142292SN/A void markSrcRegReady(); 6152190SN/A 6162331SN/A /** Marks a specific register as ready. */ 6172292SN/A void markSrcRegReady(RegIndex src_idx); 6182190SN/A 6191684SN/A /** Returns if a source register is ready. */ 6201464SN/A bool isReadySrcRegIdx(int idx) const 6211464SN/A { 6221464SN/A return this->_readySrcRegIdx[idx]; 6231464SN/A } 6241464SN/A 6251684SN/A /** Sets this instruction as completed. */ 6262731Sktlim@umich.edu void setCompleted() { status.set(Completed); } 6271464SN/A 6282292SN/A /** Returns whether or not this instruction is completed. */ 6292731Sktlim@umich.edu bool isCompleted() const { return status[Completed]; } 6301464SN/A 6312731Sktlim@umich.edu /** Marks the result as ready. */ 6322731Sktlim@umich.edu void setResultReady() { status.set(ResultReady); } 6332308SN/A 6342731Sktlim@umich.edu /** Returns whether or not the result is ready. */ 6352731Sktlim@umich.edu bool isResultReady() const { return status[ResultReady]; } 6362308SN/A 6371060SN/A /** Sets this instruction as ready to issue. */ 6382731Sktlim@umich.edu void setCanIssue() { status.set(CanIssue); } 6391060SN/A 6401060SN/A /** Returns whether or not this instruction is ready to issue. */ 6412731Sktlim@umich.edu bool readyToIssue() const { return status[CanIssue]; } 6421060SN/A 6434032Sktlim@umich.edu /** Clears this instruction being able to issue. */ 6444032Sktlim@umich.edu void clearCanIssue() { status.reset(CanIssue); } 6454032Sktlim@umich.edu 6461060SN/A /** Sets this instruction as issued from the IQ. */ 6472731Sktlim@umich.edu void setIssued() { status.set(Issued); } 6481060SN/A 6491060SN/A /** Returns whether or not this instruction has issued. */ 6502731Sktlim@umich.edu bool isIssued() const { return status[Issued]; } 6511060SN/A 6524032Sktlim@umich.edu /** Clears this instruction as being issued. */ 6534032Sktlim@umich.edu void clearIssued() { status.reset(Issued); } 6544032Sktlim@umich.edu 6551060SN/A /** Sets this instruction as executed. */ 6562731Sktlim@umich.edu void setExecuted() { status.set(Executed); } 6571060SN/A 6581060SN/A /** Returns whether or not this instruction has executed. */ 6592731Sktlim@umich.edu bool isExecuted() const { return status[Executed]; } 6601060SN/A 6611060SN/A /** Sets this instruction as ready to commit. */ 6622731Sktlim@umich.edu void setCanCommit() { status.set(CanCommit); } 6631060SN/A 6641061SN/A /** Clears this instruction as being ready to commit. */ 6652731Sktlim@umich.edu void clearCanCommit() { status.reset(CanCommit); } 6661061SN/A 6671060SN/A /** Returns whether or not this instruction is ready to commit. */ 6682731Sktlim@umich.edu bool readyToCommit() const { return status[CanCommit]; } 6692731Sktlim@umich.edu 6702731Sktlim@umich.edu void setAtCommit() { status.set(AtCommit); } 6712731Sktlim@umich.edu 6722731Sktlim@umich.edu bool isAtCommit() { return status[AtCommit]; } 6731060SN/A 6742292SN/A /** Sets this instruction as committed. */ 6752731Sktlim@umich.edu void setCommitted() { status.set(Committed); } 6762292SN/A 6772292SN/A /** Returns whether or not this instruction is committed. */ 6782731Sktlim@umich.edu bool isCommitted() const { return status[Committed]; } 6792292SN/A 6801060SN/A /** Sets this instruction as squashed. */ 6812731Sktlim@umich.edu void setSquashed() { status.set(Squashed); } 6821060SN/A 6831060SN/A /** Returns whether or not this instruction is squashed. */ 6842731Sktlim@umich.edu bool isSquashed() const { return status[Squashed]; } 6851060SN/A 6862292SN/A //Instruction Queue Entry 6872292SN/A //----------------------- 6882292SN/A /** Sets this instruction as a entry the IQ. */ 6892731Sktlim@umich.edu void setInIQ() { status.set(IqEntry); } 6902292SN/A 6912292SN/A /** Sets this instruction as a entry the IQ. */ 6922731Sktlim@umich.edu void clearInIQ() { status.reset(IqEntry); } 6932731Sktlim@umich.edu 6942731Sktlim@umich.edu /** Returns whether or not this instruction has issued. */ 6952731Sktlim@umich.edu bool isInIQ() const { return status[IqEntry]; } 6962292SN/A 6971060SN/A /** Sets this instruction as squashed in the IQ. */ 6982731Sktlim@umich.edu void setSquashedInIQ() { status.set(SquashedInIQ); status.set(Squashed);} 6991060SN/A 7001060SN/A /** Returns whether or not this instruction is squashed in the IQ. */ 7012731Sktlim@umich.edu bool isSquashedInIQ() const { return status[SquashedInIQ]; } 7022292SN/A 7032292SN/A 7042292SN/A //Load / Store Queue Functions 7052292SN/A //----------------------- 7062292SN/A /** Sets this instruction as a entry the LSQ. */ 7072731Sktlim@umich.edu void setInLSQ() { status.set(LsqEntry); } 7082292SN/A 7092292SN/A /** Sets this instruction as a entry the LSQ. */ 7102731Sktlim@umich.edu void removeInLSQ() { status.reset(LsqEntry); } 7112731Sktlim@umich.edu 7122731Sktlim@umich.edu /** Returns whether or not this instruction is in the LSQ. */ 7132731Sktlim@umich.edu bool isInLSQ() const { return status[LsqEntry]; } 7142292SN/A 7152292SN/A /** Sets this instruction as squashed in the LSQ. */ 7162731Sktlim@umich.edu void setSquashedInLSQ() { status.set(SquashedInLSQ);} 7172292SN/A 7182292SN/A /** Returns whether or not this instruction is squashed in the LSQ. */ 7192731Sktlim@umich.edu bool isSquashedInLSQ() const { return status[SquashedInLSQ]; } 7202292SN/A 7212292SN/A 7222292SN/A //Reorder Buffer Functions 7232292SN/A //----------------------- 7242292SN/A /** Sets this instruction as a entry the ROB. */ 7252731Sktlim@umich.edu void setInROB() { status.set(RobEntry); } 7262292SN/A 7272292SN/A /** Sets this instruction as a entry the ROB. */ 7282731Sktlim@umich.edu void clearInROB() { status.reset(RobEntry); } 7292731Sktlim@umich.edu 7302731Sktlim@umich.edu /** Returns whether or not this instruction is in the ROB. */ 7312731Sktlim@umich.edu bool isInROB() const { return status[RobEntry]; } 7322292SN/A 7332292SN/A /** Sets this instruction as squashed in the ROB. */ 7342731Sktlim@umich.edu void setSquashedInROB() { status.set(SquashedInROB); } 7352292SN/A 7362292SN/A /** Returns whether or not this instruction is squashed in the ROB. */ 7372731Sktlim@umich.edu bool isSquashedInROB() const { return status[SquashedInROB]; } 7382292SN/A 7397720Sgblack@eecs.umich.edu /** Read the PC state of this instruction. */ 7407720Sgblack@eecs.umich.edu const TheISA::PCState pcState() const { return pc; } 7417720Sgblack@eecs.umich.edu 7427720Sgblack@eecs.umich.edu /** Set the PC state of this instruction. */ 7437720Sgblack@eecs.umich.edu const void pcState(const TheISA::PCState &val) { pc = val; } 7447720Sgblack@eecs.umich.edu 7451060SN/A /** Read the PC of this instruction. */ 7467720Sgblack@eecs.umich.edu const Addr instAddr() const { return pc.instAddr(); } 7477720Sgblack@eecs.umich.edu 7487720Sgblack@eecs.umich.edu /** Read the PC of the next instruction. */ 7497720Sgblack@eecs.umich.edu const Addr nextInstAddr() const { return pc.nextInstAddr(); } 7501060SN/A 7514636Sgblack@eecs.umich.edu /**Read the micro PC of this instruction. */ 7527720Sgblack@eecs.umich.edu const Addr microPC() const { return pc.microPC(); } 7534636Sgblack@eecs.umich.edu 7547597Sminkyu.jeong@arm.com bool readPredicate() 7557597Sminkyu.jeong@arm.com { 7567597Sminkyu.jeong@arm.com return predicate; 7577597Sminkyu.jeong@arm.com } 7587597Sminkyu.jeong@arm.com 7597597Sminkyu.jeong@arm.com void setPredicate(bool val) 7607597Sminkyu.jeong@arm.com { 7617597Sminkyu.jeong@arm.com predicate = val; 7627600Sminkyu.jeong@arm.com 7637600Sminkyu.jeong@arm.com if (traceData) { 7647600Sminkyu.jeong@arm.com traceData->setPredicate(val); 7657600Sminkyu.jeong@arm.com } 7667597Sminkyu.jeong@arm.com } 7677597Sminkyu.jeong@arm.com 7682702Sktlim@umich.edu /** Sets the ASID. */ 7692292SN/A void setASID(short addr_space_id) { asid = addr_space_id; } 7702292SN/A 7712702Sktlim@umich.edu /** Sets the thread id. */ 7726221Snate@binkert.org void setTid(ThreadID tid) { threadNumber = tid; } 7732292SN/A 7742731Sktlim@umich.edu /** Sets the pointer to the thread state. */ 7752702Sktlim@umich.edu void setThreadState(ImplState *state) { thread = state; } 7761060SN/A 7772731Sktlim@umich.edu /** Returns the thread context. */ 7782680Sktlim@umich.edu ThreadContext *tcBase() { return thread->getTC(); } 7791464SN/A 7801464SN/A private: 7811684SN/A /** Instruction effective address. 7821684SN/A * @todo: Consider if this is necessary or not. 7831684SN/A */ 7841464SN/A Addr instEffAddr; 7852292SN/A 7861684SN/A /** Whether or not the effective address calculation is completed. 7871684SN/A * @todo: Consider if this is necessary or not. 7881684SN/A */ 7891464SN/A bool eaCalcDone; 7901464SN/A 7914032Sktlim@umich.edu /** Is this instruction's memory access uncacheable. */ 7924032Sktlim@umich.edu bool isUncacheable; 7934032Sktlim@umich.edu 7944032Sktlim@umich.edu /** Has this instruction generated a memory request. */ 7954032Sktlim@umich.edu bool reqMade; 7964032Sktlim@umich.edu 7971464SN/A public: 7981684SN/A /** Sets the effective address. */ 7991464SN/A void setEA(Addr &ea) { instEffAddr = ea; eaCalcDone = true; } 8001684SN/A 8011684SN/A /** Returns the effective address. */ 8021464SN/A const Addr &getEA() const { return instEffAddr; } 8031684SN/A 8041684SN/A /** Returns whether or not the eff. addr. calculation has been completed. */ 8051464SN/A bool doneEACalc() { return eaCalcDone; } 8061684SN/A 8071684SN/A /** Returns whether or not the eff. addr. source registers are ready. */ 8081464SN/A bool eaSrcsReady(); 8091681SN/A 8102292SN/A /** Whether or not the memory operation is done. */ 8112292SN/A bool memOpDone; 8122292SN/A 8134032Sktlim@umich.edu /** Is this instruction's memory access uncacheable. */ 8144032Sktlim@umich.edu bool uncacheable() { return isUncacheable; } 8154032Sktlim@umich.edu 8164032Sktlim@umich.edu /** Has this instruction generated a memory request. */ 8174032Sktlim@umich.edu bool hasRequest() { return reqMade; } 8184032Sktlim@umich.edu 8191681SN/A public: 8201684SN/A /** Load queue index. */ 8211681SN/A int16_t lqIdx; 8221684SN/A 8231684SN/A /** Store queue index. */ 8241681SN/A int16_t sqIdx; 8252292SN/A 8262292SN/A /** Iterator pointing to this BaseDynInst in the list of all insts. */ 8272292SN/A ListIt instListIt; 8282292SN/A 8292292SN/A /** Returns iterator to this instruction in the list of all insts. */ 8302292SN/A ListIt &getInstListIt() { return instListIt; } 8312292SN/A 8322292SN/A /** Sets iterator for this instruction in the list of all insts. */ 8332292SN/A void setInstListIt(ListIt _instListIt) { instListIt = _instListIt; } 8343326Sktlim@umich.edu 8353326Sktlim@umich.edu public: 8363326Sktlim@umich.edu /** Returns the number of consecutive store conditional failures. */ 8373326Sktlim@umich.edu unsigned readStCondFailures() 8383326Sktlim@umich.edu { return thread->storeCondFailures; } 8393326Sktlim@umich.edu 8403326Sktlim@umich.edu /** Sets the number of consecutive store conditional failures. */ 8413326Sktlim@umich.edu void setStCondFailures(unsigned sc_failures) 8423326Sktlim@umich.edu { thread->storeCondFailures = sc_failures; } 8431060SN/A}; 8441060SN/A 8451060SN/Atemplate<class Impl> 8467520Sgblack@eecs.umich.eduFault 8478444Sgblack@eecs.umich.eduBaseDynInst<Impl>::readMem(Addr addr, uint8_t *data, 8488444Sgblack@eecs.umich.edu unsigned size, unsigned flags) 8491060SN/A{ 8504032Sktlim@umich.edu reqMade = true; 8517944SGiacomo.Gabrielli@arm.com Request *req = NULL; 8526974Stjones1@inf.ed.ac.uk Request *sreqLow = NULL; 8536974Stjones1@inf.ed.ac.uk Request *sreqHigh = NULL; 8546974Stjones1@inf.ed.ac.uk 8557944SGiacomo.Gabrielli@arm.com if (reqMade && translationStarted) { 8567944SGiacomo.Gabrielli@arm.com req = savedReq; 8577944SGiacomo.Gabrielli@arm.com sreqLow = savedSreqLow; 8587944SGiacomo.Gabrielli@arm.com sreqHigh = savedSreqHigh; 8597944SGiacomo.Gabrielli@arm.com } else { 8607944SGiacomo.Gabrielli@arm.com req = new Request(asid, addr, size, flags, this->pc.instAddr(), 8617944SGiacomo.Gabrielli@arm.com thread->contextId(), threadNumber); 8624032Sktlim@umich.edu 8637944SGiacomo.Gabrielli@arm.com // Only split the request if the ISA supports unaligned accesses. 8647944SGiacomo.Gabrielli@arm.com if (TheISA::HasUnalignedMemAcc) { 8657944SGiacomo.Gabrielli@arm.com splitRequest(req, sreqLow, sreqHigh); 8667944SGiacomo.Gabrielli@arm.com } 8677944SGiacomo.Gabrielli@arm.com initiateTranslation(req, sreqLow, sreqHigh, NULL, BaseTLB::Read); 8681060SN/A } 8691060SN/A 8707944SGiacomo.Gabrielli@arm.com if (translationCompleted) { 8717944SGiacomo.Gabrielli@arm.com if (fault == NoFault) { 8727944SGiacomo.Gabrielli@arm.com effAddr = req->getVaddr(); 8738199SAli.Saidi@ARM.com effSize = size; 8747944SGiacomo.Gabrielli@arm.com effAddrValid = true; 8757944SGiacomo.Gabrielli@arm.com fault = cpu->read(req, sreqLow, sreqHigh, data, lqIdx); 8767944SGiacomo.Gabrielli@arm.com } else { 8777944SGiacomo.Gabrielli@arm.com // Commit will have to clean up whatever happened. Set this 8787944SGiacomo.Gabrielli@arm.com // instruction as executed. 8797944SGiacomo.Gabrielli@arm.com this->setExecuted(); 8807944SGiacomo.Gabrielli@arm.com } 8817944SGiacomo.Gabrielli@arm.com 8827944SGiacomo.Gabrielli@arm.com if (fault != NoFault) { 8837944SGiacomo.Gabrielli@arm.com // Return a fixed value to keep simulation deterministic even 8847944SGiacomo.Gabrielli@arm.com // along misspeculated paths. 8857944SGiacomo.Gabrielli@arm.com if (data) 8867944SGiacomo.Gabrielli@arm.com bzero(data, size); 8877944SGiacomo.Gabrielli@arm.com } 8887577SAli.Saidi@ARM.com } 8897577SAli.Saidi@ARM.com 8901060SN/A if (traceData) { 8911060SN/A traceData->setAddr(addr); 8921060SN/A } 8931060SN/A 8941060SN/A return fault; 8951060SN/A} 8961060SN/A 8971060SN/Atemplate<class Impl> 8987520Sgblack@eecs.umich.eduFault 8998444Sgblack@eecs.umich.eduBaseDynInst<Impl>::writeMem(uint8_t *data, unsigned size, 9008444Sgblack@eecs.umich.edu Addr addr, unsigned flags, uint64_t *res) 9011060SN/A{ 9021060SN/A if (traceData) { 9031060SN/A traceData->setAddr(addr); 9041060SN/A } 9051060SN/A 9064032Sktlim@umich.edu reqMade = true; 9077944SGiacomo.Gabrielli@arm.com Request *req = NULL; 9086974Stjones1@inf.ed.ac.uk Request *sreqLow = NULL; 9096974Stjones1@inf.ed.ac.uk Request *sreqHigh = NULL; 9106974Stjones1@inf.ed.ac.uk 9117944SGiacomo.Gabrielli@arm.com if (reqMade && translationStarted) { 9127944SGiacomo.Gabrielli@arm.com req = savedReq; 9137944SGiacomo.Gabrielli@arm.com sreqLow = savedSreqLow; 9147944SGiacomo.Gabrielli@arm.com sreqHigh = savedSreqHigh; 9157944SGiacomo.Gabrielli@arm.com } else { 9167944SGiacomo.Gabrielli@arm.com req = new Request(asid, addr, size, flags, this->pc.instAddr(), 9177944SGiacomo.Gabrielli@arm.com thread->contextId(), threadNumber); 9187944SGiacomo.Gabrielli@arm.com 9197944SGiacomo.Gabrielli@arm.com // Only split the request if the ISA supports unaligned accesses. 9207944SGiacomo.Gabrielli@arm.com if (TheISA::HasUnalignedMemAcc) { 9217944SGiacomo.Gabrielli@arm.com splitRequest(req, sreqLow, sreqHigh); 9227944SGiacomo.Gabrielli@arm.com } 9237944SGiacomo.Gabrielli@arm.com initiateTranslation(req, sreqLow, sreqHigh, res, BaseTLB::Write); 9246974Stjones1@inf.ed.ac.uk } 9254032Sktlim@umich.edu 9267944SGiacomo.Gabrielli@arm.com if (fault == NoFault && translationCompleted) { 9272678Sktlim@umich.edu effAddr = req->getVaddr(); 9288199SAli.Saidi@ARM.com effSize = size; 9294032Sktlim@umich.edu effAddrValid = true; 9306975Stjones1@inf.ed.ac.uk fault = cpu->write(req, sreqLow, sreqHigh, data, sqIdx); 9311060SN/A } 9321060SN/A 9331060SN/A return fault; 9341060SN/A} 9351060SN/A 9366973Stjones1@inf.ed.ac.uktemplate<class Impl> 9376973Stjones1@inf.ed.ac.ukinline void 9386974Stjones1@inf.ed.ac.ukBaseDynInst<Impl>::splitRequest(RequestPtr req, RequestPtr &sreqLow, 9396974Stjones1@inf.ed.ac.uk RequestPtr &sreqHigh) 9406974Stjones1@inf.ed.ac.uk{ 9416974Stjones1@inf.ed.ac.uk // Check to see if the request crosses the next level block boundary. 9426974Stjones1@inf.ed.ac.uk unsigned block_size = cpu->getDcachePort()->peerBlockSize(); 9436974Stjones1@inf.ed.ac.uk Addr addr = req->getVaddr(); 9446974Stjones1@inf.ed.ac.uk Addr split_addr = roundDown(addr + req->getSize() - 1, block_size); 9456974Stjones1@inf.ed.ac.uk assert(split_addr <= addr || split_addr - addr < block_size); 9466974Stjones1@inf.ed.ac.uk 9476974Stjones1@inf.ed.ac.uk // Spans two blocks. 9486974Stjones1@inf.ed.ac.uk if (split_addr > addr) { 9496974Stjones1@inf.ed.ac.uk req->splitOnVaddr(split_addr, sreqLow, sreqHigh); 9506974Stjones1@inf.ed.ac.uk } 9516974Stjones1@inf.ed.ac.uk} 9526974Stjones1@inf.ed.ac.uk 9536974Stjones1@inf.ed.ac.uktemplate<class Impl> 9546974Stjones1@inf.ed.ac.ukinline void 9556974Stjones1@inf.ed.ac.ukBaseDynInst<Impl>::initiateTranslation(RequestPtr req, RequestPtr sreqLow, 9566974Stjones1@inf.ed.ac.uk RequestPtr sreqHigh, uint64_t *res, 9576973Stjones1@inf.ed.ac.uk BaseTLB::Mode mode) 9586973Stjones1@inf.ed.ac.uk{ 9597944SGiacomo.Gabrielli@arm.com translationStarted = true; 9607944SGiacomo.Gabrielli@arm.com 9616974Stjones1@inf.ed.ac.uk if (!TheISA::HasUnalignedMemAcc || sreqLow == NULL) { 9626974Stjones1@inf.ed.ac.uk WholeTranslationState *state = 9636974Stjones1@inf.ed.ac.uk new WholeTranslationState(req, NULL, res, mode); 9646974Stjones1@inf.ed.ac.uk 9656974Stjones1@inf.ed.ac.uk // One translation if the request isn't split. 9668486Sgblack@eecs.umich.edu DataTranslation<BaseDynInstPtr> *trans = 9678486Sgblack@eecs.umich.edu new DataTranslation<BaseDynInstPtr>(this, state); 9686974Stjones1@inf.ed.ac.uk cpu->dtb->translateTiming(req, thread->getTC(), trans, mode); 9697944SGiacomo.Gabrielli@arm.com if (!translationCompleted) { 9707944SGiacomo.Gabrielli@arm.com // Save memory requests. 9717944SGiacomo.Gabrielli@arm.com savedReq = state->mainReq; 9727944SGiacomo.Gabrielli@arm.com savedSreqLow = state->sreqLow; 9737944SGiacomo.Gabrielli@arm.com savedSreqHigh = state->sreqHigh; 9747944SGiacomo.Gabrielli@arm.com } 9756974Stjones1@inf.ed.ac.uk } else { 9766974Stjones1@inf.ed.ac.uk WholeTranslationState *state = 9776974Stjones1@inf.ed.ac.uk new WholeTranslationState(req, sreqLow, sreqHigh, NULL, res, mode); 9786974Stjones1@inf.ed.ac.uk 9796974Stjones1@inf.ed.ac.uk // Two translations when the request is split. 9808486Sgblack@eecs.umich.edu DataTranslation<BaseDynInstPtr> *stransLow = 9818486Sgblack@eecs.umich.edu new DataTranslation<BaseDynInstPtr>(this, state, 0); 9828486Sgblack@eecs.umich.edu DataTranslation<BaseDynInstPtr> *stransHigh = 9838486Sgblack@eecs.umich.edu new DataTranslation<BaseDynInstPtr>(this, state, 1); 9846974Stjones1@inf.ed.ac.uk 9856974Stjones1@inf.ed.ac.uk cpu->dtb->translateTiming(sreqLow, thread->getTC(), stransLow, mode); 9866974Stjones1@inf.ed.ac.uk cpu->dtb->translateTiming(sreqHigh, thread->getTC(), stransHigh, mode); 9877944SGiacomo.Gabrielli@arm.com if (!translationCompleted) { 9887944SGiacomo.Gabrielli@arm.com // Save memory requests. 9897944SGiacomo.Gabrielli@arm.com savedReq = state->mainReq; 9907944SGiacomo.Gabrielli@arm.com savedSreqLow = state->sreqLow; 9917944SGiacomo.Gabrielli@arm.com savedSreqHigh = state->sreqHigh; 9927944SGiacomo.Gabrielli@arm.com } 9936974Stjones1@inf.ed.ac.uk } 9946973Stjones1@inf.ed.ac.uk} 9956973Stjones1@inf.ed.ac.uk 9966973Stjones1@inf.ed.ac.uktemplate<class Impl> 9976973Stjones1@inf.ed.ac.ukinline void 9986973Stjones1@inf.ed.ac.ukBaseDynInst<Impl>::finishTranslation(WholeTranslationState *state) 9996973Stjones1@inf.ed.ac.uk{ 10006973Stjones1@inf.ed.ac.uk fault = state->getFault(); 10016973Stjones1@inf.ed.ac.uk 10026973Stjones1@inf.ed.ac.uk if (state->isUncacheable()) 10036973Stjones1@inf.ed.ac.uk isUncacheable = true; 10046973Stjones1@inf.ed.ac.uk 10056973Stjones1@inf.ed.ac.uk if (fault == NoFault) { 10066973Stjones1@inf.ed.ac.uk physEffAddr = state->getPaddr(); 10076973Stjones1@inf.ed.ac.uk memReqFlags = state->getFlags(); 10086973Stjones1@inf.ed.ac.uk 10096973Stjones1@inf.ed.ac.uk if (state->mainReq->isCondSwap()) { 10106973Stjones1@inf.ed.ac.uk assert(state->res); 10116973Stjones1@inf.ed.ac.uk state->mainReq->setExtraData(*state->res); 10126973Stjones1@inf.ed.ac.uk } 10136973Stjones1@inf.ed.ac.uk 10146973Stjones1@inf.ed.ac.uk } else { 10156973Stjones1@inf.ed.ac.uk state->deleteReqs(); 10166973Stjones1@inf.ed.ac.uk } 10176973Stjones1@inf.ed.ac.uk delete state; 10187944SGiacomo.Gabrielli@arm.com 10197944SGiacomo.Gabrielli@arm.com translationCompleted = true; 10206973Stjones1@inf.ed.ac.uk} 10216973Stjones1@inf.ed.ac.uk 10221464SN/A#endif // __CPU_BASE_DYN_INST_HH__ 1023