base_dyn_inst.hh revision 12109
11060SN/A/* 212107SRekai.GonzalezAlberquilla@arm.com * Copyright (c) 2011,2013,2016 ARM Limited 39920Syasuko.eckert@amd.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 47944SGiacomo.Gabrielli@arm.com * All rights reserved. 57944SGiacomo.Gabrielli@arm.com * 67944SGiacomo.Gabrielli@arm.com * The license below extends only to copyright in the software and shall 77944SGiacomo.Gabrielli@arm.com * not be construed as granting a license to any other intellectual 87944SGiacomo.Gabrielli@arm.com * property including but not limited to intellectual property relating 97944SGiacomo.Gabrielli@arm.com * to a hardware implementation of the functionality of the software 107944SGiacomo.Gabrielli@arm.com * licensed hereunder. You may use the software subject to the license 117944SGiacomo.Gabrielli@arm.com * terms below provided that you ensure that this notice is replicated 127944SGiacomo.Gabrielli@arm.com * unmodified and in its entirety in all distributions of the software, 137944SGiacomo.Gabrielli@arm.com * modified or unmodified, in source code or in binary form. 147944SGiacomo.Gabrielli@arm.com * 152702Sktlim@umich.edu * Copyright (c) 2004-2006 The Regents of The University of Michigan 166973Stjones1@inf.ed.ac.uk * Copyright (c) 2009 The University of Edinburgh 171060SN/A * All rights reserved. 181060SN/A * 191060SN/A * Redistribution and use in source and binary forms, with or without 201060SN/A * modification, are permitted provided that the following conditions are 211060SN/A * met: redistributions of source code must retain the above copyright 221060SN/A * notice, this list of conditions and the following disclaimer; 231060SN/A * redistributions in binary form must reproduce the above copyright 241060SN/A * notice, this list of conditions and the following disclaimer in the 251060SN/A * documentation and/or other materials provided with the distribution; 261060SN/A * neither the name of the copyright holders nor the names of its 271060SN/A * contributors may be used to endorse or promote products derived from 281060SN/A * this software without specific prior written permission. 291060SN/A * 301060SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 311060SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 321060SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 331060SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 341060SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 351060SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 361060SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 371060SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 381060SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 391060SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 401060SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 412665Ssaidi@eecs.umich.edu * 422665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 436973Stjones1@inf.ed.ac.uk * Timothy M. Jones 441060SN/A */ 451060SN/A 461464SN/A#ifndef __CPU_BASE_DYN_INST_HH__ 471464SN/A#define __CPU_BASE_DYN_INST_HH__ 481060SN/A 4910835Sandreas.hansson@arm.com#include <array> 502731Sktlim@umich.edu#include <bitset> 5112109SRekai.GonzalezAlberquilla@arm.com#include <deque> 522292SN/A#include <list> 531464SN/A#include <string> 541060SN/A 5510687SAndreas.Sandberg@ARM.com#include "arch/generic/tlb.hh" 567720Sgblack@eecs.umich.edu#include "arch/utility.hh" 571060SN/A#include "base/trace.hh" 586658Snate@binkert.org#include "config/the_isa.hh" 598887Sgeoffrey.blake@arm.com#include "cpu/checker/cpu.hh" 6010319SAndreas.Sandberg@ARM.com#include "cpu/exec_context.hh" 611464SN/A#include "cpu/exetrace.hh" 6212107SRekai.GonzalezAlberquilla@arm.com#include "cpu/inst_res.hh" 631464SN/A#include "cpu/inst_seq.hh" 6412107SRekai.GonzalezAlberquilla@arm.com#include "cpu/o3/comm.hh" 652669Sktlim@umich.edu#include "cpu/op_class.hh" 661060SN/A#include "cpu/static_inst.hh" 676973Stjones1@inf.ed.ac.uk#include "cpu/translation.hh" 682669Sktlim@umich.edu#include "mem/packet.hh" 6911608Snikos.nikoleris@arm.com#include "mem/request.hh" 707678Sgblack@eecs.umich.edu#include "sim/byteswap.hh" 712292SN/A#include "sim/system.hh" 721060SN/A 731060SN/A/** 741060SN/A * @file 751060SN/A * Defines a dynamic instruction context. 761060SN/A */ 771060SN/A 781060SN/Atemplate <class Impl> 7910319SAndreas.Sandberg@ARM.comclass BaseDynInst : public ExecContext, public RefCounted 801060SN/A{ 811060SN/A public: 821060SN/A // Typedef for the CPU. 832733Sktlim@umich.edu typedef typename Impl::CPUType ImplCPU; 842733Sktlim@umich.edu typedef typename ImplCPU::ImplState ImplState; 8512109SRekai.GonzalezAlberquilla@arm.com using VecRegContainer = TheISA::VecRegContainer; 861060SN/A 872292SN/A // The DynInstPtr type. 882292SN/A typedef typename Impl::DynInstPtr DynInstPtr; 898486Sgblack@eecs.umich.edu typedef RefCountingPtr<BaseDynInst<Impl> > BaseDynInstPtr; 902292SN/A 912292SN/A // The list of instructions iterator type. 922292SN/A typedef typename std::list<DynInstPtr>::iterator ListIt; 932292SN/A 941060SN/A enum { 955543Ssaidi@eecs.umich.edu MaxInstSrcRegs = TheISA::MaxInstSrcRegs, /// Max source regs 968902Sandreas.hansson@arm.com MaxInstDestRegs = TheISA::MaxInstDestRegs /// Max dest regs 971060SN/A }; 981060SN/A 999046SAli.Saidi@ARM.com protected: 1009046SAli.Saidi@ARM.com enum Status { 1019046SAli.Saidi@ARM.com IqEntry, /// Instruction is in the IQ 1029046SAli.Saidi@ARM.com RobEntry, /// Instruction is in the ROB 1039046SAli.Saidi@ARM.com LsqEntry, /// Instruction is in the LSQ 1049046SAli.Saidi@ARM.com Completed, /// Instruction has completed 1059046SAli.Saidi@ARM.com ResultReady, /// Instruction has its result 1069046SAli.Saidi@ARM.com CanIssue, /// Instruction can issue and execute 1079046SAli.Saidi@ARM.com Issued, /// Instruction has issued 1089046SAli.Saidi@ARM.com Executed, /// Instruction has executed 1099046SAli.Saidi@ARM.com CanCommit, /// Instruction can commit 1109046SAli.Saidi@ARM.com AtCommit, /// Instruction has reached commit 1119046SAli.Saidi@ARM.com Committed, /// Instruction has committed 1129046SAli.Saidi@ARM.com Squashed, /// Instruction is squashed 1139046SAli.Saidi@ARM.com SquashedInIQ, /// Instruction is squashed in the IQ 1149046SAli.Saidi@ARM.com SquashedInLSQ, /// Instruction is squashed in the LSQ 1159046SAli.Saidi@ARM.com SquashedInROB, /// Instruction is squashed in the ROB 1169046SAli.Saidi@ARM.com RecoverInst, /// Is a recover instruction 1179046SAli.Saidi@ARM.com BlockingInst, /// Is a blocking instruction 1189046SAli.Saidi@ARM.com ThreadsyncWait, /// Is a thread synchronization instruction 1199046SAli.Saidi@ARM.com SerializeBefore, /// Needs to serialize on 1209046SAli.Saidi@ARM.com /// instructions ahead of it 1219046SAli.Saidi@ARM.com SerializeAfter, /// Needs to serialize instructions behind it 1229046SAli.Saidi@ARM.com SerializeHandled, /// Serialization has been handled 1239046SAli.Saidi@ARM.com NumStatus 1249046SAli.Saidi@ARM.com }; 1259046SAli.Saidi@ARM.com 1269046SAli.Saidi@ARM.com enum Flags { 1279046SAli.Saidi@ARM.com TranslationStarted, 1289046SAli.Saidi@ARM.com TranslationCompleted, 1299046SAli.Saidi@ARM.com PossibleLoadViolation, 1309046SAli.Saidi@ARM.com HitExternalSnoop, 1319046SAli.Saidi@ARM.com EffAddrValid, 1329046SAli.Saidi@ARM.com RecordResult, 1339046SAli.Saidi@ARM.com Predicate, 1349046SAli.Saidi@ARM.com PredTaken, 1359046SAli.Saidi@ARM.com /** Whether or not the effective address calculation is completed. 1369046SAli.Saidi@ARM.com * @todo: Consider if this is necessary or not. 1379046SAli.Saidi@ARM.com */ 1389046SAli.Saidi@ARM.com EACalcDone, 13910824SAndreas.Sandberg@ARM.com IsStrictlyOrdered, 1409046SAli.Saidi@ARM.com ReqMade, 1419046SAli.Saidi@ARM.com MemOpDone, 1429046SAli.Saidi@ARM.com MaxFlags 1439046SAli.Saidi@ARM.com }; 1449046SAli.Saidi@ARM.com 1459046SAli.Saidi@ARM.com public: 1469046SAli.Saidi@ARM.com /** The sequence number of the instruction. */ 1479046SAli.Saidi@ARM.com InstSeqNum seqNum; 1489046SAli.Saidi@ARM.com 1492292SN/A /** The StaticInst used by this BaseDynInst. */ 15010417Sandreas.hansson@arm.com const StaticInstPtr staticInst; 1519046SAli.Saidi@ARM.com 1529046SAli.Saidi@ARM.com /** Pointer to the Impl's CPU object. */ 1539046SAli.Saidi@ARM.com ImplCPU *cpu; 1549046SAli.Saidi@ARM.com 15510030SAli.Saidi@ARM.com BaseCPU *getCpuPtr() { return cpu; } 15610030SAli.Saidi@ARM.com 1579046SAli.Saidi@ARM.com /** Pointer to the thread state. */ 1589046SAli.Saidi@ARM.com ImplState *thread; 1599046SAli.Saidi@ARM.com 1609046SAli.Saidi@ARM.com /** The kind of fault this instruction has generated. */ 1619046SAli.Saidi@ARM.com Fault fault; 1629046SAli.Saidi@ARM.com 1639046SAli.Saidi@ARM.com /** InstRecord that tracks this instructions. */ 1649046SAli.Saidi@ARM.com Trace::InstRecord *traceData; 1659046SAli.Saidi@ARM.com 1669046SAli.Saidi@ARM.com protected: 1679046SAli.Saidi@ARM.com /** The result of the instruction; assumes an instruction can have many 1689046SAli.Saidi@ARM.com * destination registers. 1699046SAli.Saidi@ARM.com */ 17012107SRekai.GonzalezAlberquilla@arm.com std::queue<InstResult> instResult; 1719046SAli.Saidi@ARM.com 1729046SAli.Saidi@ARM.com /** PC state for this instruction. */ 1739046SAli.Saidi@ARM.com TheISA::PCState pc; 1749046SAli.Saidi@ARM.com 1759046SAli.Saidi@ARM.com /* An amalgamation of a lot of boolean values into one */ 1769046SAli.Saidi@ARM.com std::bitset<MaxFlags> instFlags; 1779046SAli.Saidi@ARM.com 1789046SAli.Saidi@ARM.com /** The status of this BaseDynInst. Several bits can be set. */ 1799046SAli.Saidi@ARM.com std::bitset<NumStatus> status; 1809046SAli.Saidi@ARM.com 1819046SAli.Saidi@ARM.com /** Whether or not the source register is ready. 1829046SAli.Saidi@ARM.com * @todo: Not sure this should be here vs the derived class. 1839046SAli.Saidi@ARM.com */ 1849046SAli.Saidi@ARM.com std::bitset<MaxInstSrcRegs> _readySrcRegIdx; 1859046SAli.Saidi@ARM.com 1869046SAli.Saidi@ARM.com public: 1879046SAli.Saidi@ARM.com /** The thread this instruction is from. */ 1889046SAli.Saidi@ARM.com ThreadID threadNumber; 1899046SAli.Saidi@ARM.com 1909046SAli.Saidi@ARM.com /** Iterator pointing to this BaseDynInst in the list of all insts. */ 1919046SAli.Saidi@ARM.com ListIt instListIt; 1929046SAli.Saidi@ARM.com 1939046SAli.Saidi@ARM.com ////////////////////// Branch Data /////////////// 1949046SAli.Saidi@ARM.com /** Predicted PC state after this instruction. */ 1959046SAli.Saidi@ARM.com TheISA::PCState predPC; 1969046SAli.Saidi@ARM.com 1979046SAli.Saidi@ARM.com /** The Macroop if one exists */ 19810417Sandreas.hansson@arm.com const StaticInstPtr macroop; 1991060SN/A 2009046SAli.Saidi@ARM.com /** How many source registers are ready. */ 2019046SAli.Saidi@ARM.com uint8_t readyRegs; 2029046SAli.Saidi@ARM.com 2039046SAli.Saidi@ARM.com public: 2049046SAli.Saidi@ARM.com /////////////////////// Load Store Data ////////////////////// 2059046SAli.Saidi@ARM.com /** The effective virtual address (lds & stores only). */ 2069046SAli.Saidi@ARM.com Addr effAddr; 2079046SAli.Saidi@ARM.com 2089046SAli.Saidi@ARM.com /** The effective physical address. */ 20911097Songal@cs.wisc.edu Addr physEffAddrLow; 21011097Songal@cs.wisc.edu 21111097Songal@cs.wisc.edu /** The effective physical address 21211097Songal@cs.wisc.edu * of the second request for a split request 21311097Songal@cs.wisc.edu */ 21411097Songal@cs.wisc.edu Addr physEffAddrHigh; 2159046SAli.Saidi@ARM.com 2169046SAli.Saidi@ARM.com /** The memory request flags (from translation). */ 2179046SAli.Saidi@ARM.com unsigned memReqFlags; 2189046SAli.Saidi@ARM.com 2199046SAli.Saidi@ARM.com /** data address space ID, for loads & stores. */ 2209046SAli.Saidi@ARM.com short asid; 2219046SAli.Saidi@ARM.com 2229046SAli.Saidi@ARM.com /** The size of the request */ 2239046SAli.Saidi@ARM.com uint8_t effSize; 2249046SAli.Saidi@ARM.com 2259046SAli.Saidi@ARM.com /** Pointer to the data for the memory access. */ 2269046SAli.Saidi@ARM.com uint8_t *memData; 2279046SAli.Saidi@ARM.com 2289046SAli.Saidi@ARM.com /** Load queue index. */ 2299046SAli.Saidi@ARM.com int16_t lqIdx; 2309046SAli.Saidi@ARM.com 2319046SAli.Saidi@ARM.com /** Store queue index. */ 2329046SAli.Saidi@ARM.com int16_t sqIdx; 2339046SAli.Saidi@ARM.com 2349046SAli.Saidi@ARM.com 2359046SAli.Saidi@ARM.com /////////////////////// TLB Miss ////////////////////// 2369046SAli.Saidi@ARM.com /** 2379046SAli.Saidi@ARM.com * Saved memory requests (needed when the DTB address translation is 2389046SAli.Saidi@ARM.com * delayed due to a hw page table walk). 2399046SAli.Saidi@ARM.com */ 2409046SAli.Saidi@ARM.com RequestPtr savedReq; 2419046SAli.Saidi@ARM.com RequestPtr savedSreqLow; 2429046SAli.Saidi@ARM.com RequestPtr savedSreqHigh; 2439046SAli.Saidi@ARM.com 2449046SAli.Saidi@ARM.com /////////////////////// Checker ////////////////////// 2459046SAli.Saidi@ARM.com // Need a copy of main request pointer to verify on writes. 2469046SAli.Saidi@ARM.com RequestPtr reqToVerify; 2479046SAli.Saidi@ARM.com 2489046SAli.Saidi@ARM.com private: 2499046SAli.Saidi@ARM.com /** Instruction effective address. 2509046SAli.Saidi@ARM.com * @todo: Consider if this is necessary or not. 2519046SAli.Saidi@ARM.com */ 2529046SAli.Saidi@ARM.com Addr instEffAddr; 2539046SAli.Saidi@ARM.com 2549046SAli.Saidi@ARM.com protected: 2559046SAli.Saidi@ARM.com /** Flattened register index of the destination registers of this 2569046SAli.Saidi@ARM.com * instruction. 2579046SAli.Saidi@ARM.com */ 25812104Snathanael.premillieu@arm.com std::array<RegId, TheISA::MaxInstDestRegs> _flatDestRegIdx; 2599046SAli.Saidi@ARM.com 2609046SAli.Saidi@ARM.com /** Physical register index of the destination registers of this 2619046SAli.Saidi@ARM.com * instruction. 2629046SAli.Saidi@ARM.com */ 26312105Snathanael.premillieu@arm.com std::array<PhysRegIdPtr, TheISA::MaxInstDestRegs> _destRegIdx; 2649046SAli.Saidi@ARM.com 2659046SAli.Saidi@ARM.com /** Physical register index of the source registers of this 2669046SAli.Saidi@ARM.com * instruction. 2679046SAli.Saidi@ARM.com */ 26812105Snathanael.premillieu@arm.com std::array<PhysRegIdPtr, TheISA::MaxInstSrcRegs> _srcRegIdx; 2699046SAli.Saidi@ARM.com 2709046SAli.Saidi@ARM.com /** Physical register index of the previous producers of the 2719046SAli.Saidi@ARM.com * architected destinations. 2729046SAli.Saidi@ARM.com */ 27312105Snathanael.premillieu@arm.com std::array<PhysRegIdPtr, TheISA::MaxInstDestRegs> _prevDestRegIdx; 2749046SAli.Saidi@ARM.com 2759046SAli.Saidi@ARM.com 2769046SAli.Saidi@ARM.com public: 2779046SAli.Saidi@ARM.com /** Records changes to result? */ 2789046SAli.Saidi@ARM.com void recordResult(bool f) { instFlags[RecordResult] = f; } 2799046SAli.Saidi@ARM.com 2809046SAli.Saidi@ARM.com /** Is the effective virtual address valid. */ 2819046SAli.Saidi@ARM.com bool effAddrValid() const { return instFlags[EffAddrValid]; } 2829046SAli.Saidi@ARM.com 2839046SAli.Saidi@ARM.com /** Whether or not the memory operation is done. */ 2849046SAli.Saidi@ARM.com bool memOpDone() const { return instFlags[MemOpDone]; } 2859046SAli.Saidi@ARM.com void memOpDone(bool f) { instFlags[MemOpDone] = f; } 2869046SAli.Saidi@ARM.com 2879046SAli.Saidi@ARM.com 2881060SN/A //////////////////////////////////////////// 2891060SN/A // 2901060SN/A // INSTRUCTION EXECUTION 2911060SN/A // 2921060SN/A //////////////////////////////////////////// 2931060SN/A 2945358Sgblack@eecs.umich.edu void demapPage(Addr vaddr, uint64_t asn) 2955358Sgblack@eecs.umich.edu { 2965358Sgblack@eecs.umich.edu cpu->demapPage(vaddr, asn); 2975358Sgblack@eecs.umich.edu } 2985358Sgblack@eecs.umich.edu void demapInstPage(Addr vaddr, uint64_t asn) 2995358Sgblack@eecs.umich.edu { 3005358Sgblack@eecs.umich.edu cpu->demapPage(vaddr, asn); 3015358Sgblack@eecs.umich.edu } 3025358Sgblack@eecs.umich.edu void demapDataPage(Addr vaddr, uint64_t asn) 3035358Sgblack@eecs.umich.edu { 3045358Sgblack@eecs.umich.edu cpu->demapPage(vaddr, asn); 3055358Sgblack@eecs.umich.edu } 3065358Sgblack@eecs.umich.edu 30711608Snikos.nikoleris@arm.com Fault initiateMemRead(Addr addr, unsigned size, Request::Flags flags); 3087520Sgblack@eecs.umich.edu 30911608Snikos.nikoleris@arm.com Fault writeMem(uint8_t *data, unsigned size, Addr addr, 31011608Snikos.nikoleris@arm.com Request::Flags flags, uint64_t *res); 3117520Sgblack@eecs.umich.edu 3126974Stjones1@inf.ed.ac.uk /** Splits a request in two if it crosses a dcache block. */ 3136974Stjones1@inf.ed.ac.uk void splitRequest(RequestPtr req, RequestPtr &sreqLow, 3146974Stjones1@inf.ed.ac.uk RequestPtr &sreqHigh); 3156974Stjones1@inf.ed.ac.uk 3166973Stjones1@inf.ed.ac.uk /** Initiate a DTB address translation. */ 3176974Stjones1@inf.ed.ac.uk void initiateTranslation(RequestPtr req, RequestPtr sreqLow, 3186974Stjones1@inf.ed.ac.uk RequestPtr sreqHigh, uint64_t *res, 3196973Stjones1@inf.ed.ac.uk BaseTLB::Mode mode); 3206973Stjones1@inf.ed.ac.uk 3216973Stjones1@inf.ed.ac.uk /** Finish a DTB address translation. */ 3226973Stjones1@inf.ed.ac.uk void finishTranslation(WholeTranslationState *state); 3231060SN/A 3247944SGiacomo.Gabrielli@arm.com /** True if the DTB address translation has started. */ 3259046SAli.Saidi@ARM.com bool translationStarted() const { return instFlags[TranslationStarted]; } 3269046SAli.Saidi@ARM.com void translationStarted(bool f) { instFlags[TranslationStarted] = f; } 3277944SGiacomo.Gabrielli@arm.com 3287944SGiacomo.Gabrielli@arm.com /** True if the DTB address translation has completed. */ 3299046SAli.Saidi@ARM.com bool translationCompleted() const { return instFlags[TranslationCompleted]; } 3309046SAli.Saidi@ARM.com void translationCompleted(bool f) { instFlags[TranslationCompleted] = f; } 3317944SGiacomo.Gabrielli@arm.com 3328545Ssaidi@eecs.umich.edu /** True if this address was found to match a previous load and they issued 3338545Ssaidi@eecs.umich.edu * out of order. If that happend, then it's only a problem if an incoming 3348545Ssaidi@eecs.umich.edu * snoop invalidate modifies the line, in which case we need to squash. 3358545Ssaidi@eecs.umich.edu * If nothing modified the line the order doesn't matter. 3368545Ssaidi@eecs.umich.edu */ 3379046SAli.Saidi@ARM.com bool possibleLoadViolation() const { return instFlags[PossibleLoadViolation]; } 3389046SAli.Saidi@ARM.com void possibleLoadViolation(bool f) { instFlags[PossibleLoadViolation] = f; } 3398545Ssaidi@eecs.umich.edu 3408545Ssaidi@eecs.umich.edu /** True if the address hit a external snoop while sitting in the LSQ. 3418545Ssaidi@eecs.umich.edu * If this is true and a older instruction sees it, this instruction must 3428545Ssaidi@eecs.umich.edu * reexecute 3438545Ssaidi@eecs.umich.edu */ 3449046SAli.Saidi@ARM.com bool hitExternalSnoop() const { return instFlags[HitExternalSnoop]; } 3459046SAli.Saidi@ARM.com void hitExternalSnoop(bool f) { instFlags[HitExternalSnoop] = f; } 3468545Ssaidi@eecs.umich.edu 3477944SGiacomo.Gabrielli@arm.com /** 3487944SGiacomo.Gabrielli@arm.com * Returns true if the DTB address translation is being delayed due to a hw 3497944SGiacomo.Gabrielli@arm.com * page table walk. 3507944SGiacomo.Gabrielli@arm.com */ 3517944SGiacomo.Gabrielli@arm.com bool isTranslationDelayed() const 3527944SGiacomo.Gabrielli@arm.com { 3539046SAli.Saidi@ARM.com return (translationStarted() && !translationCompleted()); 3547944SGiacomo.Gabrielli@arm.com } 3557944SGiacomo.Gabrielli@arm.com 3561060SN/A public: 3572292SN/A#ifdef DEBUG 3582292SN/A void dumpSNList(); 3592292SN/A#endif 3602292SN/A 3613770Sgblack@eecs.umich.edu /** Returns the physical register index of the i'th destination 3623770Sgblack@eecs.umich.edu * register. 3633770Sgblack@eecs.umich.edu */ 36412105Snathanael.premillieu@arm.com PhysRegIdPtr renamedDestRegIdx(int idx) const 3653770Sgblack@eecs.umich.edu { 3663770Sgblack@eecs.umich.edu return _destRegIdx[idx]; 3673770Sgblack@eecs.umich.edu } 3683770Sgblack@eecs.umich.edu 3693770Sgblack@eecs.umich.edu /** Returns the physical register index of the i'th source register. */ 37012105Snathanael.premillieu@arm.com PhysRegIdPtr renamedSrcRegIdx(int idx) const 3713770Sgblack@eecs.umich.edu { 3729046SAli.Saidi@ARM.com assert(TheISA::MaxInstSrcRegs > idx); 3733770Sgblack@eecs.umich.edu return _srcRegIdx[idx]; 3743770Sgblack@eecs.umich.edu } 3753770Sgblack@eecs.umich.edu 3763770Sgblack@eecs.umich.edu /** Returns the flattened register index of the i'th destination 3773770Sgblack@eecs.umich.edu * register. 3783770Sgblack@eecs.umich.edu */ 37912106SRekai.GonzalezAlberquilla@arm.com const RegId& flattenedDestRegIdx(int idx) const 3803770Sgblack@eecs.umich.edu { 3813770Sgblack@eecs.umich.edu return _flatDestRegIdx[idx]; 3823770Sgblack@eecs.umich.edu } 3833770Sgblack@eecs.umich.edu 3843770Sgblack@eecs.umich.edu /** Returns the physical register index of the previous physical register 3853770Sgblack@eecs.umich.edu * that remapped to the same logical register index. 3863770Sgblack@eecs.umich.edu */ 38712105Snathanael.premillieu@arm.com PhysRegIdPtr prevDestRegIdx(int idx) const 3883770Sgblack@eecs.umich.edu { 3893770Sgblack@eecs.umich.edu return _prevDestRegIdx[idx]; 3903770Sgblack@eecs.umich.edu } 3913770Sgblack@eecs.umich.edu 3923770Sgblack@eecs.umich.edu /** Renames a destination register to a physical register. Also records 3933770Sgblack@eecs.umich.edu * the previous physical register that the logical register mapped to. 3943770Sgblack@eecs.umich.edu */ 3953770Sgblack@eecs.umich.edu void renameDestReg(int idx, 39612105Snathanael.premillieu@arm.com PhysRegIdPtr renamed_dest, 39712105Snathanael.premillieu@arm.com PhysRegIdPtr previous_rename) 3983770Sgblack@eecs.umich.edu { 3993770Sgblack@eecs.umich.edu _destRegIdx[idx] = renamed_dest; 4003770Sgblack@eecs.umich.edu _prevDestRegIdx[idx] = previous_rename; 4013770Sgblack@eecs.umich.edu } 4023770Sgblack@eecs.umich.edu 4033770Sgblack@eecs.umich.edu /** Renames a source logical register to the physical register which 4043770Sgblack@eecs.umich.edu * has/will produce that logical register's result. 4053770Sgblack@eecs.umich.edu * @todo: add in whether or not the source register is ready. 4063770Sgblack@eecs.umich.edu */ 40712105Snathanael.premillieu@arm.com void renameSrcReg(int idx, PhysRegIdPtr renamed_src) 4083770Sgblack@eecs.umich.edu { 4093770Sgblack@eecs.umich.edu _srcRegIdx[idx] = renamed_src; 4103770Sgblack@eecs.umich.edu } 4113770Sgblack@eecs.umich.edu 4123770Sgblack@eecs.umich.edu /** Flattens a destination architectural register index into a logical 4133770Sgblack@eecs.umich.edu * index. 4143770Sgblack@eecs.umich.edu */ 41512106SRekai.GonzalezAlberquilla@arm.com void flattenDestReg(int idx, const RegId& flattened_dest) 4163770Sgblack@eecs.umich.edu { 4173770Sgblack@eecs.umich.edu _flatDestRegIdx[idx] = flattened_dest; 4183770Sgblack@eecs.umich.edu } 4194636Sgblack@eecs.umich.edu /** BaseDynInst constructor given a binary instruction. 4204636Sgblack@eecs.umich.edu * @param staticInst A StaticInstPtr to the underlying instruction. 4217720Sgblack@eecs.umich.edu * @param pc The PC state for the instruction. 4227720Sgblack@eecs.umich.edu * @param predPC The predicted next PC state for the instruction. 4234636Sgblack@eecs.umich.edu * @param seq_num The sequence number of the instruction. 4244636Sgblack@eecs.umich.edu * @param cpu Pointer to the instruction's CPU. 4254636Sgblack@eecs.umich.edu */ 42610417Sandreas.hansson@arm.com BaseDynInst(const StaticInstPtr &staticInst, const StaticInstPtr ¯oop, 4278502Sgblack@eecs.umich.edu TheISA::PCState pc, TheISA::PCState predPC, 4288502Sgblack@eecs.umich.edu InstSeqNum seq_num, ImplCPU *cpu); 4293770Sgblack@eecs.umich.edu 4302292SN/A /** BaseDynInst constructor given a StaticInst pointer. 4312292SN/A * @param _staticInst The StaticInst for this BaseDynInst. 4322292SN/A */ 43310417Sandreas.hansson@arm.com BaseDynInst(const StaticInstPtr &staticInst, const StaticInstPtr ¯oop); 4341060SN/A 4351060SN/A /** BaseDynInst destructor. */ 4361060SN/A ~BaseDynInst(); 4371060SN/A 4381464SN/A private: 4391684SN/A /** Function to initialize variables in the constructors. */ 4401464SN/A void initVars(); 4411060SN/A 4421464SN/A public: 4431060SN/A /** Dumps out contents of this BaseDynInst. */ 4441060SN/A void dump(); 4451060SN/A 4461060SN/A /** Dumps out contents of this BaseDynInst into given string. */ 4471060SN/A void dump(std::string &outstring); 4481060SN/A 4493326Sktlim@umich.edu /** Read this CPU's ID. */ 45010110Sandreas.hansson@arm.com int cpuId() const { return cpu->cpuId(); } 4513326Sktlim@umich.edu 45210190Sakash.bagdia@arm.com /** Read this CPU's Socket ID. */ 45310190Sakash.bagdia@arm.com uint32_t socketId() const { return cpu->socketId(); } 45410190Sakash.bagdia@arm.com 4558832SAli.Saidi@ARM.com /** Read this CPU's data requestor ID */ 45610110Sandreas.hansson@arm.com MasterID masterId() const { return cpu->dataMasterId(); } 4578832SAli.Saidi@ARM.com 4585714Shsul@eecs.umich.edu /** Read this context's system-wide ID **/ 45911005Sandreas.sandberg@arm.com ContextID contextId() const { return thread->contextId(); } 4605714Shsul@eecs.umich.edu 4611060SN/A /** Returns the fault type. */ 46210110Sandreas.hansson@arm.com Fault getFault() const { return fault; } 4631060SN/A 4641060SN/A /** Checks whether or not this instruction has had its branch target 4651060SN/A * calculated yet. For now it is not utilized and is hacked to be 4661060SN/A * always false. 4672292SN/A * @todo: Actually use this instruction. 4681060SN/A */ 4691060SN/A bool doneTargCalc() { return false; } 4701060SN/A 4717720Sgblack@eecs.umich.edu /** Set the predicted target of this current instruction. */ 4727720Sgblack@eecs.umich.edu void setPredTarg(const TheISA::PCState &_predPC) 4733965Sgblack@eecs.umich.edu { 4747720Sgblack@eecs.umich.edu predPC = _predPC; 4753965Sgblack@eecs.umich.edu } 4762935Sksewell@umich.edu 4777720Sgblack@eecs.umich.edu const TheISA::PCState &readPredTarg() { return predPC; } 4781060SN/A 4793794Sgblack@eecs.umich.edu /** Returns the predicted PC immediately after the branch. */ 4807720Sgblack@eecs.umich.edu Addr predInstAddr() { return predPC.instAddr(); } 4813794Sgblack@eecs.umich.edu 4823794Sgblack@eecs.umich.edu /** Returns the predicted PC two instructions after the branch */ 4837720Sgblack@eecs.umich.edu Addr predNextInstAddr() { return predPC.nextInstAddr(); } 4841060SN/A 4854636Sgblack@eecs.umich.edu /** Returns the predicted micro PC after the branch */ 4867720Sgblack@eecs.umich.edu Addr predMicroPC() { return predPC.microPC(); } 4874636Sgblack@eecs.umich.edu 4881060SN/A /** Returns whether the instruction was predicted taken or not. */ 4893794Sgblack@eecs.umich.edu bool readPredTaken() 4903794Sgblack@eecs.umich.edu { 4919046SAli.Saidi@ARM.com return instFlags[PredTaken]; 4923794Sgblack@eecs.umich.edu } 4933794Sgblack@eecs.umich.edu 4943794Sgblack@eecs.umich.edu void setPredTaken(bool predicted_taken) 4953794Sgblack@eecs.umich.edu { 4969046SAli.Saidi@ARM.com instFlags[PredTaken] = predicted_taken; 4973794Sgblack@eecs.umich.edu } 4981060SN/A 4991060SN/A /** Returns whether the instruction mispredicted. */ 5002935Sksewell@umich.edu bool mispredicted() 5013794Sgblack@eecs.umich.edu { 5027720Sgblack@eecs.umich.edu TheISA::PCState tempPC = pc; 5037720Sgblack@eecs.umich.edu TheISA::advancePC(tempPC, staticInst); 5047720Sgblack@eecs.umich.edu return !(tempPC == predPC); 5053794Sgblack@eecs.umich.edu } 5063794Sgblack@eecs.umich.edu 5071060SN/A // 5081060SN/A // Instruction types. Forward checks to StaticInst object. 5091060SN/A // 5105543Ssaidi@eecs.umich.edu bool isNop() const { return staticInst->isNop(); } 5115543Ssaidi@eecs.umich.edu bool isMemRef() const { return staticInst->isMemRef(); } 5125543Ssaidi@eecs.umich.edu bool isLoad() const { return staticInst->isLoad(); } 5135543Ssaidi@eecs.umich.edu bool isStore() const { return staticInst->isStore(); } 5142336SN/A bool isStoreConditional() const 5152336SN/A { return staticInst->isStoreConditional(); } 5161060SN/A bool isInstPrefetch() const { return staticInst->isInstPrefetch(); } 5171060SN/A bool isDataPrefetch() const { return staticInst->isDataPrefetch(); } 5185543Ssaidi@eecs.umich.edu bool isInteger() const { return staticInst->isInteger(); } 5195543Ssaidi@eecs.umich.edu bool isFloating() const { return staticInst->isFloating(); } 5205543Ssaidi@eecs.umich.edu bool isControl() const { return staticInst->isControl(); } 5215543Ssaidi@eecs.umich.edu bool isCall() const { return staticInst->isCall(); } 5225543Ssaidi@eecs.umich.edu bool isReturn() const { return staticInst->isReturn(); } 5235543Ssaidi@eecs.umich.edu bool isDirectCtrl() const { return staticInst->isDirectCtrl(); } 5241060SN/A bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); } 5255543Ssaidi@eecs.umich.edu bool isCondCtrl() const { return staticInst->isCondCtrl(); } 5265543Ssaidi@eecs.umich.edu bool isUncondCtrl() const { return staticInst->isUncondCtrl(); } 5272935Sksewell@umich.edu bool isCondDelaySlot() const { return staticInst->isCondDelaySlot(); } 5281060SN/A bool isThreadSync() const { return staticInst->isThreadSync(); } 5291060SN/A bool isSerializing() const { return staticInst->isSerializing(); } 5302292SN/A bool isSerializeBefore() const 5312731Sktlim@umich.edu { return staticInst->isSerializeBefore() || status[SerializeBefore]; } 5322292SN/A bool isSerializeAfter() const 5332731Sktlim@umich.edu { return staticInst->isSerializeAfter() || status[SerializeAfter]; } 5347784SAli.Saidi@ARM.com bool isSquashAfter() const { return staticInst->isSquashAfter(); } 5351060SN/A bool isMemBarrier() const { return staticInst->isMemBarrier(); } 5361060SN/A bool isWriteBarrier() const { return staticInst->isWriteBarrier(); } 5371060SN/A bool isNonSpeculative() const { return staticInst->isNonSpeculative(); } 5382292SN/A bool isQuiesce() const { return staticInst->isQuiesce(); } 5392336SN/A bool isIprAccess() const { return staticInst->isIprAccess(); } 5402308SN/A bool isUnverifiable() const { return staticInst->isUnverifiable(); } 5414828Sgblack@eecs.umich.edu bool isSyscall() const { return staticInst->isSyscall(); } 5424654Sgblack@eecs.umich.edu bool isMacroop() const { return staticInst->isMacroop(); } 5434654Sgblack@eecs.umich.edu bool isMicroop() const { return staticInst->isMicroop(); } 5444636Sgblack@eecs.umich.edu bool isDelayedCommit() const { return staticInst->isDelayedCommit(); } 5454654Sgblack@eecs.umich.edu bool isLastMicroop() const { return staticInst->isLastMicroop(); } 5464654Sgblack@eecs.umich.edu bool isFirstMicroop() const { return staticInst->isFirstMicroop(); } 5474636Sgblack@eecs.umich.edu bool isMicroBranch() const { return staticInst->isMicroBranch(); } 5482292SN/A 5492292SN/A /** Temporarily sets this instruction as a serialize before instruction. */ 5502731Sktlim@umich.edu void setSerializeBefore() { status.set(SerializeBefore); } 5512292SN/A 5522292SN/A /** Clears the serializeBefore part of this instruction. */ 5532731Sktlim@umich.edu void clearSerializeBefore() { status.reset(SerializeBefore); } 5542292SN/A 5552292SN/A /** Checks if this serializeBefore is only temporarily set. */ 5562731Sktlim@umich.edu bool isTempSerializeBefore() { return status[SerializeBefore]; } 5572292SN/A 5582292SN/A /** Temporarily sets this instruction as a serialize after instruction. */ 5592731Sktlim@umich.edu void setSerializeAfter() { status.set(SerializeAfter); } 5602292SN/A 5612292SN/A /** Clears the serializeAfter part of this instruction.*/ 5622731Sktlim@umich.edu void clearSerializeAfter() { status.reset(SerializeAfter); } 5632292SN/A 5642292SN/A /** Checks if this serializeAfter is only temporarily set. */ 5652731Sktlim@umich.edu bool isTempSerializeAfter() { return status[SerializeAfter]; } 5662292SN/A 5672731Sktlim@umich.edu /** Sets the serialization part of this instruction as handled. */ 5682731Sktlim@umich.edu void setSerializeHandled() { status.set(SerializeHandled); } 5692292SN/A 5702292SN/A /** Checks if the serialization part of this instruction has been 5712292SN/A * handled. This does not apply to the temporary serializing 5722292SN/A * state; it only applies to this instruction's own permanent 5732292SN/A * serializing state. 5742292SN/A */ 5752731Sktlim@umich.edu bool isSerializeHandled() { return status[SerializeHandled]; } 5761060SN/A 5771464SN/A /** Returns the opclass of this instruction. */ 5781464SN/A OpClass opClass() const { return staticInst->opClass(); } 5791464SN/A 5801464SN/A /** Returns the branch target address. */ 5817720Sgblack@eecs.umich.edu TheISA::PCState branchTarget() const 5827720Sgblack@eecs.umich.edu { return staticInst->branchTarget(pc); } 5831464SN/A 5842292SN/A /** Returns the number of source registers. */ 5855543Ssaidi@eecs.umich.edu int8_t numSrcRegs() const { return staticInst->numSrcRegs(); } 5861684SN/A 5872292SN/A /** Returns the number of destination registers. */ 5881060SN/A int8_t numDestRegs() const { return staticInst->numDestRegs(); } 5891060SN/A 5901060SN/A // the following are used to track physical register usage 5911060SN/A // for machines with separate int & FP reg files 5921060SN/A int8_t numFPDestRegs() const { return staticInst->numFPDestRegs(); } 5931060SN/A int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); } 59410715SRekai.GonzalezAlberquilla@arm.com int8_t numCCDestRegs() const { return staticInst->numCCDestRegs(); } 59512109SRekai.GonzalezAlberquilla@arm.com int8_t numVecDestRegs() const { return staticInst->numVecDestRegs(); } 59612109SRekai.GonzalezAlberquilla@arm.com int8_t numVecElemDestRegs() const { 59712109SRekai.GonzalezAlberquilla@arm.com return staticInst->numVecElemDestRegs(); 59812109SRekai.GonzalezAlberquilla@arm.com } 5991060SN/A 6001060SN/A /** Returns the logical register index of the i'th destination register. */ 60112106SRekai.GonzalezAlberquilla@arm.com const RegId& destRegIdx(int i) const { return staticInst->destRegIdx(i); } 6021060SN/A 6031060SN/A /** Returns the logical register index of the i'th source register. */ 60412106SRekai.GonzalezAlberquilla@arm.com const RegId& srcRegIdx(int i) const { return staticInst->srcRegIdx(i); } 6051060SN/A 60612107SRekai.GonzalezAlberquilla@arm.com /** Return the size of the instResult queue. */ 60712107SRekai.GonzalezAlberquilla@arm.com uint8_t resultSize() { return instResult.size(); } 60812107SRekai.GonzalezAlberquilla@arm.com 60912107SRekai.GonzalezAlberquilla@arm.com /** Pops a result off the instResult queue. 61012107SRekai.GonzalezAlberquilla@arm.com * If the result stack is empty, return the default value. 61112107SRekai.GonzalezAlberquilla@arm.com * */ 61212107SRekai.GonzalezAlberquilla@arm.com InstResult popResult(InstResult dflt = InstResult()) 6138733Sgeoffrey.blake@arm.com { 6148733Sgeoffrey.blake@arm.com if (!instResult.empty()) { 61512107SRekai.GonzalezAlberquilla@arm.com InstResult t = instResult.front(); 6168733Sgeoffrey.blake@arm.com instResult.pop(); 61712107SRekai.GonzalezAlberquilla@arm.com return t; 6188733Sgeoffrey.blake@arm.com } 61912107SRekai.GonzalezAlberquilla@arm.com return dflt; 6208733Sgeoffrey.blake@arm.com } 6211684SN/A 62212107SRekai.GonzalezAlberquilla@arm.com /** Pushes a result onto the instResult queue. */ 62312109SRekai.GonzalezAlberquilla@arm.com /** @{ */ 62412109SRekai.GonzalezAlberquilla@arm.com /** Scalar result. */ 62512107SRekai.GonzalezAlberquilla@arm.com template<typename T> 62612107SRekai.GonzalezAlberquilla@arm.com void setScalarResult(T&& t) 6278733Sgeoffrey.blake@arm.com { 6289046SAli.Saidi@ARM.com if (instFlags[RecordResult]) { 62912107SRekai.GonzalezAlberquilla@arm.com instResult.push(InstResult(std::forward<T>(t), 63012107SRekai.GonzalezAlberquilla@arm.com InstResult::ResultType::Scalar)); 6318733Sgeoffrey.blake@arm.com } 6328733Sgeoffrey.blake@arm.com } 6331060SN/A 63412109SRekai.GonzalezAlberquilla@arm.com /** Full vector result. */ 63512109SRekai.GonzalezAlberquilla@arm.com template<typename T> 63612109SRekai.GonzalezAlberquilla@arm.com void setVecResult(T&& t) 63712109SRekai.GonzalezAlberquilla@arm.com { 63812109SRekai.GonzalezAlberquilla@arm.com if (instFlags[RecordResult]) { 63912109SRekai.GonzalezAlberquilla@arm.com instResult.push(InstResult(std::forward<T>(t), 64012109SRekai.GonzalezAlberquilla@arm.com InstResult::ResultType::VecReg)); 64112109SRekai.GonzalezAlberquilla@arm.com } 64212109SRekai.GonzalezAlberquilla@arm.com } 64312109SRekai.GonzalezAlberquilla@arm.com 64412109SRekai.GonzalezAlberquilla@arm.com /** Vector element result. */ 64512109SRekai.GonzalezAlberquilla@arm.com template<typename T> 64612109SRekai.GonzalezAlberquilla@arm.com void setVecElemResult(T&& t) 64712109SRekai.GonzalezAlberquilla@arm.com { 64812109SRekai.GonzalezAlberquilla@arm.com if (instFlags[RecordResult]) { 64912109SRekai.GonzalezAlberquilla@arm.com instResult.push(InstResult(std::forward<T>(t), 65012109SRekai.GonzalezAlberquilla@arm.com InstResult::ResultType::VecElem)); 65112109SRekai.GonzalezAlberquilla@arm.com } 65212109SRekai.GonzalezAlberquilla@arm.com } 65312109SRekai.GonzalezAlberquilla@arm.com /** @} */ 65412109SRekai.GonzalezAlberquilla@arm.com 6552702Sktlim@umich.edu /** Records an integer register being set to a value. */ 65610319SAndreas.Sandberg@ARM.com void setIntRegOperand(const StaticInst *si, int idx, IntReg val) 6571060SN/A { 65812107SRekai.GonzalezAlberquilla@arm.com setScalarResult(val); 6591060SN/A } 6601060SN/A 6619920Syasuko.eckert@amd.com /** Records a CC register being set to a value. */ 66210319SAndreas.Sandberg@ARM.com void setCCRegOperand(const StaticInst *si, int idx, CCReg val) 6639920Syasuko.eckert@amd.com { 66412107SRekai.GonzalezAlberquilla@arm.com setScalarResult(val); 6659920Syasuko.eckert@amd.com } 6669920Syasuko.eckert@amd.com 6672702Sktlim@umich.edu /** Records an fp register being set to a value. */ 6683735Sstever@eecs.umich.edu void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val) 6691060SN/A { 67012107SRekai.GonzalezAlberquilla@arm.com setScalarResult(val); 6712308SN/A } 6721060SN/A 67312109SRekai.GonzalezAlberquilla@arm.com /** Record a vector register being set to a value */ 67412109SRekai.GonzalezAlberquilla@arm.com void setVecRegOperand(const StaticInst *si, int idx, 67512109SRekai.GonzalezAlberquilla@arm.com const VecRegContainer& val) 67612109SRekai.GonzalezAlberquilla@arm.com { 67712109SRekai.GonzalezAlberquilla@arm.com setVecResult(val); 67812109SRekai.GonzalezAlberquilla@arm.com } 67912109SRekai.GonzalezAlberquilla@arm.com 6802702Sktlim@umich.edu /** Records an fp register being set to an integer value. */ 68112107SRekai.GonzalezAlberquilla@arm.com void 68212107SRekai.GonzalezAlberquilla@arm.com setFloatRegOperandBits(const StaticInst *si, int idx, FloatRegBits val) 6832308SN/A { 68412107SRekai.GonzalezAlberquilla@arm.com setScalarResult(val); 6851060SN/A } 6861060SN/A 68712109SRekai.GonzalezAlberquilla@arm.com /** Record a vector register being set to a value */ 68812109SRekai.GonzalezAlberquilla@arm.com void setVecElemOperand(const StaticInst *si, int idx, const VecElem val) 68912109SRekai.GonzalezAlberquilla@arm.com { 69012109SRekai.GonzalezAlberquilla@arm.com setVecElemResult(val); 69112109SRekai.GonzalezAlberquilla@arm.com } 69212109SRekai.GonzalezAlberquilla@arm.com 6932190SN/A /** Records that one of the source registers is ready. */ 6942292SN/A void markSrcRegReady(); 6952190SN/A 6962331SN/A /** Marks a specific register as ready. */ 6972292SN/A void markSrcRegReady(RegIndex src_idx); 6982190SN/A 6991684SN/A /** Returns if a source register is ready. */ 7001464SN/A bool isReadySrcRegIdx(int idx) const 7011464SN/A { 7021464SN/A return this->_readySrcRegIdx[idx]; 7031464SN/A } 7041464SN/A 7051684SN/A /** Sets this instruction as completed. */ 7062731Sktlim@umich.edu void setCompleted() { status.set(Completed); } 7071464SN/A 7082292SN/A /** Returns whether or not this instruction is completed. */ 7092731Sktlim@umich.edu bool isCompleted() const { return status[Completed]; } 7101464SN/A 7112731Sktlim@umich.edu /** Marks the result as ready. */ 7122731Sktlim@umich.edu void setResultReady() { status.set(ResultReady); } 7132308SN/A 7142731Sktlim@umich.edu /** Returns whether or not the result is ready. */ 7152731Sktlim@umich.edu bool isResultReady() const { return status[ResultReady]; } 7162308SN/A 7171060SN/A /** Sets this instruction as ready to issue. */ 7182731Sktlim@umich.edu void setCanIssue() { status.set(CanIssue); } 7191060SN/A 7201060SN/A /** Returns whether or not this instruction is ready to issue. */ 7212731Sktlim@umich.edu bool readyToIssue() const { return status[CanIssue]; } 7221060SN/A 7234032Sktlim@umich.edu /** Clears this instruction being able to issue. */ 7244032Sktlim@umich.edu void clearCanIssue() { status.reset(CanIssue); } 7254032Sktlim@umich.edu 7261060SN/A /** Sets this instruction as issued from the IQ. */ 7272731Sktlim@umich.edu void setIssued() { status.set(Issued); } 7281060SN/A 7291060SN/A /** Returns whether or not this instruction has issued. */ 7302731Sktlim@umich.edu bool isIssued() const { return status[Issued]; } 7311060SN/A 7324032Sktlim@umich.edu /** Clears this instruction as being issued. */ 7334032Sktlim@umich.edu void clearIssued() { status.reset(Issued); } 7344032Sktlim@umich.edu 7351060SN/A /** Sets this instruction as executed. */ 7362731Sktlim@umich.edu void setExecuted() { status.set(Executed); } 7371060SN/A 7381060SN/A /** Returns whether or not this instruction has executed. */ 7392731Sktlim@umich.edu bool isExecuted() const { return status[Executed]; } 7401060SN/A 7411060SN/A /** Sets this instruction as ready to commit. */ 7422731Sktlim@umich.edu void setCanCommit() { status.set(CanCommit); } 7431060SN/A 7441061SN/A /** Clears this instruction as being ready to commit. */ 7452731Sktlim@umich.edu void clearCanCommit() { status.reset(CanCommit); } 7461061SN/A 7471060SN/A /** Returns whether or not this instruction is ready to commit. */ 7482731Sktlim@umich.edu bool readyToCommit() const { return status[CanCommit]; } 7492731Sktlim@umich.edu 7502731Sktlim@umich.edu void setAtCommit() { status.set(AtCommit); } 7512731Sktlim@umich.edu 7522731Sktlim@umich.edu bool isAtCommit() { return status[AtCommit]; } 7531060SN/A 7542292SN/A /** Sets this instruction as committed. */ 7552731Sktlim@umich.edu void setCommitted() { status.set(Committed); } 7562292SN/A 7572292SN/A /** Returns whether or not this instruction is committed. */ 7582731Sktlim@umich.edu bool isCommitted() const { return status[Committed]; } 7592292SN/A 7601060SN/A /** Sets this instruction as squashed. */ 7612731Sktlim@umich.edu void setSquashed() { status.set(Squashed); } 7621060SN/A 7631060SN/A /** Returns whether or not this instruction is squashed. */ 7642731Sktlim@umich.edu bool isSquashed() const { return status[Squashed]; } 7651060SN/A 7662292SN/A //Instruction Queue Entry 7672292SN/A //----------------------- 7682292SN/A /** Sets this instruction as a entry the IQ. */ 7692731Sktlim@umich.edu void setInIQ() { status.set(IqEntry); } 7702292SN/A 7712292SN/A /** Sets this instruction as a entry the IQ. */ 7722731Sktlim@umich.edu void clearInIQ() { status.reset(IqEntry); } 7732731Sktlim@umich.edu 7742731Sktlim@umich.edu /** Returns whether or not this instruction has issued. */ 7752731Sktlim@umich.edu bool isInIQ() const { return status[IqEntry]; } 7762292SN/A 7771060SN/A /** Sets this instruction as squashed in the IQ. */ 7782731Sktlim@umich.edu void setSquashedInIQ() { status.set(SquashedInIQ); status.set(Squashed);} 7791060SN/A 7801060SN/A /** Returns whether or not this instruction is squashed in the IQ. */ 7812731Sktlim@umich.edu bool isSquashedInIQ() const { return status[SquashedInIQ]; } 7822292SN/A 7832292SN/A 7842292SN/A //Load / Store Queue Functions 7852292SN/A //----------------------- 7862292SN/A /** Sets this instruction as a entry the LSQ. */ 7872731Sktlim@umich.edu void setInLSQ() { status.set(LsqEntry); } 7882292SN/A 7892292SN/A /** Sets this instruction as a entry the LSQ. */ 7902731Sktlim@umich.edu void removeInLSQ() { status.reset(LsqEntry); } 7912731Sktlim@umich.edu 7922731Sktlim@umich.edu /** Returns whether or not this instruction is in the LSQ. */ 7932731Sktlim@umich.edu bool isInLSQ() const { return status[LsqEntry]; } 7942292SN/A 7952292SN/A /** Sets this instruction as squashed in the LSQ. */ 7962731Sktlim@umich.edu void setSquashedInLSQ() { status.set(SquashedInLSQ);} 7972292SN/A 7982292SN/A /** Returns whether or not this instruction is squashed in the LSQ. */ 7992731Sktlim@umich.edu bool isSquashedInLSQ() const { return status[SquashedInLSQ]; } 8002292SN/A 8012292SN/A 8022292SN/A //Reorder Buffer Functions 8032292SN/A //----------------------- 8042292SN/A /** Sets this instruction as a entry the ROB. */ 8052731Sktlim@umich.edu void setInROB() { status.set(RobEntry); } 8062292SN/A 8072292SN/A /** Sets this instruction as a entry the ROB. */ 8082731Sktlim@umich.edu void clearInROB() { status.reset(RobEntry); } 8092731Sktlim@umich.edu 8102731Sktlim@umich.edu /** Returns whether or not this instruction is in the ROB. */ 8112731Sktlim@umich.edu bool isInROB() const { return status[RobEntry]; } 8122292SN/A 8132292SN/A /** Sets this instruction as squashed in the ROB. */ 8142731Sktlim@umich.edu void setSquashedInROB() { status.set(SquashedInROB); } 8152292SN/A 8162292SN/A /** Returns whether or not this instruction is squashed in the ROB. */ 8172731Sktlim@umich.edu bool isSquashedInROB() const { return status[SquashedInROB]; } 8182292SN/A 8197720Sgblack@eecs.umich.edu /** Read the PC state of this instruction. */ 82010319SAndreas.Sandberg@ARM.com TheISA::PCState pcState() const { return pc; } 8217720Sgblack@eecs.umich.edu 8227720Sgblack@eecs.umich.edu /** Set the PC state of this instruction. */ 82310319SAndreas.Sandberg@ARM.com void pcState(const TheISA::PCState &val) { pc = val; } 8247720Sgblack@eecs.umich.edu 8251060SN/A /** Read the PC of this instruction. */ 82611294Sandreas.hansson@arm.com Addr instAddr() const { return pc.instAddr(); } 8277720Sgblack@eecs.umich.edu 8287720Sgblack@eecs.umich.edu /** Read the PC of the next instruction. */ 82911294Sandreas.hansson@arm.com Addr nextInstAddr() const { return pc.nextInstAddr(); } 8301060SN/A 8314636Sgblack@eecs.umich.edu /**Read the micro PC of this instruction. */ 83211294Sandreas.hansson@arm.com Addr microPC() const { return pc.microPC(); } 8334636Sgblack@eecs.umich.edu 8347597Sminkyu.jeong@arm.com bool readPredicate() 8357597Sminkyu.jeong@arm.com { 8369046SAli.Saidi@ARM.com return instFlags[Predicate]; 8377597Sminkyu.jeong@arm.com } 8387597Sminkyu.jeong@arm.com 8397597Sminkyu.jeong@arm.com void setPredicate(bool val) 8407597Sminkyu.jeong@arm.com { 8419046SAli.Saidi@ARM.com instFlags[Predicate] = val; 8427600Sminkyu.jeong@arm.com 8437600Sminkyu.jeong@arm.com if (traceData) { 8447600Sminkyu.jeong@arm.com traceData->setPredicate(val); 8457600Sminkyu.jeong@arm.com } 8467597Sminkyu.jeong@arm.com } 8477597Sminkyu.jeong@arm.com 8482702Sktlim@umich.edu /** Sets the ASID. */ 8492292SN/A void setASID(short addr_space_id) { asid = addr_space_id; } 8502292SN/A 8512702Sktlim@umich.edu /** Sets the thread id. */ 8526221Snate@binkert.org void setTid(ThreadID tid) { threadNumber = tid; } 8532292SN/A 8542731Sktlim@umich.edu /** Sets the pointer to the thread state. */ 8552702Sktlim@umich.edu void setThreadState(ImplState *state) { thread = state; } 8561060SN/A 8572731Sktlim@umich.edu /** Returns the thread context. */ 8582680Sktlim@umich.edu ThreadContext *tcBase() { return thread->getTC(); } 8591464SN/A 8601464SN/A public: 8611684SN/A /** Sets the effective address. */ 86210319SAndreas.Sandberg@ARM.com void setEA(Addr ea) { instEffAddr = ea; instFlags[EACalcDone] = true; } 8631684SN/A 8641684SN/A /** Returns the effective address. */ 86510319SAndreas.Sandberg@ARM.com Addr getEA() const { return instEffAddr; } 8661684SN/A 8671684SN/A /** Returns whether or not the eff. addr. calculation has been completed. */ 8689046SAli.Saidi@ARM.com bool doneEACalc() { return instFlags[EACalcDone]; } 8691684SN/A 8701684SN/A /** Returns whether or not the eff. addr. source registers are ready. */ 8711464SN/A bool eaSrcsReady(); 8721681SN/A 87310824SAndreas.Sandberg@ARM.com /** Is this instruction's memory access strictly ordered? */ 87410824SAndreas.Sandberg@ARM.com bool strictlyOrdered() const { return instFlags[IsStrictlyOrdered]; } 8754032Sktlim@umich.edu 8764032Sktlim@umich.edu /** Has this instruction generated a memory request. */ 8779046SAli.Saidi@ARM.com bool hasRequest() { return instFlags[ReqMade]; } 8782292SN/A 8792292SN/A /** Returns iterator to this instruction in the list of all insts. */ 8802292SN/A ListIt &getInstListIt() { return instListIt; } 8812292SN/A 8822292SN/A /** Sets iterator for this instruction in the list of all insts. */ 8832292SN/A void setInstListIt(ListIt _instListIt) { instListIt = _instListIt; } 8843326Sktlim@umich.edu 8853326Sktlim@umich.edu public: 8863326Sktlim@umich.edu /** Returns the number of consecutive store conditional failures. */ 88710319SAndreas.Sandberg@ARM.com unsigned int readStCondFailures() const 8883326Sktlim@umich.edu { return thread->storeCondFailures; } 8893326Sktlim@umich.edu 8903326Sktlim@umich.edu /** Sets the number of consecutive store conditional failures. */ 89110319SAndreas.Sandberg@ARM.com void setStCondFailures(unsigned int sc_failures) 8923326Sktlim@umich.edu { thread->storeCondFailures = sc_failures; } 89310529Smorr@cs.wisc.edu 89410529Smorr@cs.wisc.edu public: 89510529Smorr@cs.wisc.edu // monitor/mwait funtions 89611148Smitch.hayenga@arm.com void armMonitor(Addr address) { cpu->armMonitor(threadNumber, address); } 89711148Smitch.hayenga@arm.com bool mwait(PacketPtr pkt) { return cpu->mwait(threadNumber, pkt); } 89810529Smorr@cs.wisc.edu void mwaitAtomic(ThreadContext *tc) 89911148Smitch.hayenga@arm.com { return cpu->mwaitAtomic(threadNumber, tc, cpu->dtb); } 90011148Smitch.hayenga@arm.com AddressMonitor *getAddrMonitor() 90111148Smitch.hayenga@arm.com { return cpu->getCpuAddrMonitor(threadNumber); } 9021060SN/A}; 9031060SN/A 9041060SN/Atemplate<class Impl> 9057520Sgblack@eecs.umich.eduFault 90611608Snikos.nikoleris@arm.comBaseDynInst<Impl>::initiateMemRead(Addr addr, unsigned size, 90711608Snikos.nikoleris@arm.com Request::Flags flags) 9081060SN/A{ 9099046SAli.Saidi@ARM.com instFlags[ReqMade] = true; 9107944SGiacomo.Gabrielli@arm.com Request *req = NULL; 9116974Stjones1@inf.ed.ac.uk Request *sreqLow = NULL; 9126974Stjones1@inf.ed.ac.uk Request *sreqHigh = NULL; 9136974Stjones1@inf.ed.ac.uk 9149046SAli.Saidi@ARM.com if (instFlags[ReqMade] && translationStarted()) { 9157944SGiacomo.Gabrielli@arm.com req = savedReq; 9167944SGiacomo.Gabrielli@arm.com sreqLow = savedSreqLow; 9177944SGiacomo.Gabrielli@arm.com sreqHigh = savedSreqHigh; 9187944SGiacomo.Gabrielli@arm.com } else { 9198832SAli.Saidi@ARM.com req = new Request(asid, addr, size, flags, masterId(), this->pc.instAddr(), 92011435Smitch.hayenga@arm.com thread->contextId()); 9214032Sktlim@umich.edu 92210024Sdam.sunwoo@arm.com req->taskId(cpu->taskId()); 92310024Sdam.sunwoo@arm.com 9247944SGiacomo.Gabrielli@arm.com // Only split the request if the ISA supports unaligned accesses. 9257944SGiacomo.Gabrielli@arm.com if (TheISA::HasUnalignedMemAcc) { 9267944SGiacomo.Gabrielli@arm.com splitRequest(req, sreqLow, sreqHigh); 9277944SGiacomo.Gabrielli@arm.com } 9287944SGiacomo.Gabrielli@arm.com initiateTranslation(req, sreqLow, sreqHigh, NULL, BaseTLB::Read); 9291060SN/A } 9301060SN/A 9319046SAli.Saidi@ARM.com if (translationCompleted()) { 9327944SGiacomo.Gabrielli@arm.com if (fault == NoFault) { 9337944SGiacomo.Gabrielli@arm.com effAddr = req->getVaddr(); 9348199SAli.Saidi@ARM.com effSize = size; 9359046SAli.Saidi@ARM.com instFlags[EffAddrValid] = true; 9368887Sgeoffrey.blake@arm.com 9378887Sgeoffrey.blake@arm.com if (cpu->checker) { 9388887Sgeoffrey.blake@arm.com if (reqToVerify != NULL) { 9398887Sgeoffrey.blake@arm.com delete reqToVerify; 9408887Sgeoffrey.blake@arm.com } 9418887Sgeoffrey.blake@arm.com reqToVerify = new Request(*req); 9428733Sgeoffrey.blake@arm.com } 94311302Ssteve.reinhardt@amd.com fault = cpu->read(req, sreqLow, sreqHigh, lqIdx); 9447944SGiacomo.Gabrielli@arm.com } else { 9457944SGiacomo.Gabrielli@arm.com // Commit will have to clean up whatever happened. Set this 9467944SGiacomo.Gabrielli@arm.com // instruction as executed. 9477944SGiacomo.Gabrielli@arm.com this->setExecuted(); 9487944SGiacomo.Gabrielli@arm.com } 9497577SAli.Saidi@ARM.com } 9507577SAli.Saidi@ARM.com 95110665SAli.Saidi@ARM.com if (traceData) 95210665SAli.Saidi@ARM.com traceData->setMem(addr, size, flags); 9531060SN/A 9541060SN/A return fault; 9551060SN/A} 9561060SN/A 9571060SN/Atemplate<class Impl> 9587520Sgblack@eecs.umich.eduFault 95911608Snikos.nikoleris@arm.comBaseDynInst<Impl>::writeMem(uint8_t *data, unsigned size, Addr addr, 96011608Snikos.nikoleris@arm.com Request::Flags flags, uint64_t *res) 9611060SN/A{ 96210665SAli.Saidi@ARM.com if (traceData) 96310665SAli.Saidi@ARM.com traceData->setMem(addr, size, flags); 9641060SN/A 9659046SAli.Saidi@ARM.com instFlags[ReqMade] = true; 9667944SGiacomo.Gabrielli@arm.com Request *req = NULL; 9676974Stjones1@inf.ed.ac.uk Request *sreqLow = NULL; 9686974Stjones1@inf.ed.ac.uk Request *sreqHigh = NULL; 9696974Stjones1@inf.ed.ac.uk 9709046SAli.Saidi@ARM.com if (instFlags[ReqMade] && translationStarted()) { 9717944SGiacomo.Gabrielli@arm.com req = savedReq; 9727944SGiacomo.Gabrielli@arm.com sreqLow = savedSreqLow; 9737944SGiacomo.Gabrielli@arm.com sreqHigh = savedSreqHigh; 9747944SGiacomo.Gabrielli@arm.com } else { 9758832SAli.Saidi@ARM.com req = new Request(asid, addr, size, flags, masterId(), this->pc.instAddr(), 97611435Smitch.hayenga@arm.com thread->contextId()); 9777944SGiacomo.Gabrielli@arm.com 97810024Sdam.sunwoo@arm.com req->taskId(cpu->taskId()); 97910024Sdam.sunwoo@arm.com 9807944SGiacomo.Gabrielli@arm.com // Only split the request if the ISA supports unaligned accesses. 9817944SGiacomo.Gabrielli@arm.com if (TheISA::HasUnalignedMemAcc) { 9827944SGiacomo.Gabrielli@arm.com splitRequest(req, sreqLow, sreqHigh); 9837944SGiacomo.Gabrielli@arm.com } 9847944SGiacomo.Gabrielli@arm.com initiateTranslation(req, sreqLow, sreqHigh, res, BaseTLB::Write); 9856974Stjones1@inf.ed.ac.uk } 9864032Sktlim@umich.edu 9879046SAli.Saidi@ARM.com if (fault == NoFault && translationCompleted()) { 9882678Sktlim@umich.edu effAddr = req->getVaddr(); 9898199SAli.Saidi@ARM.com effSize = size; 9909046SAli.Saidi@ARM.com instFlags[EffAddrValid] = true; 9918887Sgeoffrey.blake@arm.com 9928887Sgeoffrey.blake@arm.com if (cpu->checker) { 9938887Sgeoffrey.blake@arm.com if (reqToVerify != NULL) { 9948887Sgeoffrey.blake@arm.com delete reqToVerify; 9958887Sgeoffrey.blake@arm.com } 9968887Sgeoffrey.blake@arm.com reqToVerify = new Request(*req); 9978733Sgeoffrey.blake@arm.com } 9986975Stjones1@inf.ed.ac.uk fault = cpu->write(req, sreqLow, sreqHigh, data, sqIdx); 9991060SN/A } 10001060SN/A 10011060SN/A return fault; 10021060SN/A} 10031060SN/A 10046973Stjones1@inf.ed.ac.uktemplate<class Impl> 10056973Stjones1@inf.ed.ac.ukinline void 10066974Stjones1@inf.ed.ac.ukBaseDynInst<Impl>::splitRequest(RequestPtr req, RequestPtr &sreqLow, 10076974Stjones1@inf.ed.ac.uk RequestPtr &sreqHigh) 10086974Stjones1@inf.ed.ac.uk{ 10096974Stjones1@inf.ed.ac.uk // Check to see if the request crosses the next level block boundary. 10109814Sandreas.hansson@arm.com unsigned block_size = cpu->cacheLineSize(); 10116974Stjones1@inf.ed.ac.uk Addr addr = req->getVaddr(); 10126974Stjones1@inf.ed.ac.uk Addr split_addr = roundDown(addr + req->getSize() - 1, block_size); 10136974Stjones1@inf.ed.ac.uk assert(split_addr <= addr || split_addr - addr < block_size); 10146974Stjones1@inf.ed.ac.uk 10156974Stjones1@inf.ed.ac.uk // Spans two blocks. 10166974Stjones1@inf.ed.ac.uk if (split_addr > addr) { 10176974Stjones1@inf.ed.ac.uk req->splitOnVaddr(split_addr, sreqLow, sreqHigh); 10186974Stjones1@inf.ed.ac.uk } 10196974Stjones1@inf.ed.ac.uk} 10206974Stjones1@inf.ed.ac.uk 10216974Stjones1@inf.ed.ac.uktemplate<class Impl> 10226974Stjones1@inf.ed.ac.ukinline void 10236974Stjones1@inf.ed.ac.ukBaseDynInst<Impl>::initiateTranslation(RequestPtr req, RequestPtr sreqLow, 10246974Stjones1@inf.ed.ac.uk RequestPtr sreqHigh, uint64_t *res, 10256973Stjones1@inf.ed.ac.uk BaseTLB::Mode mode) 10266973Stjones1@inf.ed.ac.uk{ 10279046SAli.Saidi@ARM.com translationStarted(true); 10287944SGiacomo.Gabrielli@arm.com 10296974Stjones1@inf.ed.ac.uk if (!TheISA::HasUnalignedMemAcc || sreqLow == NULL) { 10306974Stjones1@inf.ed.ac.uk WholeTranslationState *state = 10316974Stjones1@inf.ed.ac.uk new WholeTranslationState(req, NULL, res, mode); 10326974Stjones1@inf.ed.ac.uk 10336974Stjones1@inf.ed.ac.uk // One translation if the request isn't split. 10348486Sgblack@eecs.umich.edu DataTranslation<BaseDynInstPtr> *trans = 10358486Sgblack@eecs.umich.edu new DataTranslation<BaseDynInstPtr>(this, state); 10369932SAli.Saidi@ARM.com 10376974Stjones1@inf.ed.ac.uk cpu->dtb->translateTiming(req, thread->getTC(), trans, mode); 10389932SAli.Saidi@ARM.com 10399046SAli.Saidi@ARM.com if (!translationCompleted()) { 10409932SAli.Saidi@ARM.com // The translation isn't yet complete, so we can't possibly have a 10419932SAli.Saidi@ARM.com // fault. Overwrite any existing fault we might have from a previous 10429932SAli.Saidi@ARM.com // execution of this instruction (e.g. an uncachable load that 10439932SAli.Saidi@ARM.com // couldn't execute because it wasn't at the head of the ROB). 10449932SAli.Saidi@ARM.com fault = NoFault; 10459932SAli.Saidi@ARM.com 10467944SGiacomo.Gabrielli@arm.com // Save memory requests. 10477944SGiacomo.Gabrielli@arm.com savedReq = state->mainReq; 10487944SGiacomo.Gabrielli@arm.com savedSreqLow = state->sreqLow; 10497944SGiacomo.Gabrielli@arm.com savedSreqHigh = state->sreqHigh; 10507944SGiacomo.Gabrielli@arm.com } 10516974Stjones1@inf.ed.ac.uk } else { 10526974Stjones1@inf.ed.ac.uk WholeTranslationState *state = 10536974Stjones1@inf.ed.ac.uk new WholeTranslationState(req, sreqLow, sreqHigh, NULL, res, mode); 10546974Stjones1@inf.ed.ac.uk 10556974Stjones1@inf.ed.ac.uk // Two translations when the request is split. 10568486Sgblack@eecs.umich.edu DataTranslation<BaseDynInstPtr> *stransLow = 10578486Sgblack@eecs.umich.edu new DataTranslation<BaseDynInstPtr>(this, state, 0); 10588486Sgblack@eecs.umich.edu DataTranslation<BaseDynInstPtr> *stransHigh = 10598486Sgblack@eecs.umich.edu new DataTranslation<BaseDynInstPtr>(this, state, 1); 10606974Stjones1@inf.ed.ac.uk 10616974Stjones1@inf.ed.ac.uk cpu->dtb->translateTiming(sreqLow, thread->getTC(), stransLow, mode); 10626974Stjones1@inf.ed.ac.uk cpu->dtb->translateTiming(sreqHigh, thread->getTC(), stransHigh, mode); 10639932SAli.Saidi@ARM.com 10649046SAli.Saidi@ARM.com if (!translationCompleted()) { 10659932SAli.Saidi@ARM.com // The translation isn't yet complete, so we can't possibly have a 10669932SAli.Saidi@ARM.com // fault. Overwrite any existing fault we might have from a previous 10679932SAli.Saidi@ARM.com // execution of this instruction (e.g. an uncachable load that 10689932SAli.Saidi@ARM.com // couldn't execute because it wasn't at the head of the ROB). 10699932SAli.Saidi@ARM.com fault = NoFault; 10709932SAli.Saidi@ARM.com 10717944SGiacomo.Gabrielli@arm.com // Save memory requests. 10727944SGiacomo.Gabrielli@arm.com savedReq = state->mainReq; 10737944SGiacomo.Gabrielli@arm.com savedSreqLow = state->sreqLow; 10747944SGiacomo.Gabrielli@arm.com savedSreqHigh = state->sreqHigh; 10757944SGiacomo.Gabrielli@arm.com } 10766974Stjones1@inf.ed.ac.uk } 10776973Stjones1@inf.ed.ac.uk} 10786973Stjones1@inf.ed.ac.uk 10796973Stjones1@inf.ed.ac.uktemplate<class Impl> 10806973Stjones1@inf.ed.ac.ukinline void 10816973Stjones1@inf.ed.ac.ukBaseDynInst<Impl>::finishTranslation(WholeTranslationState *state) 10826973Stjones1@inf.ed.ac.uk{ 10836973Stjones1@inf.ed.ac.uk fault = state->getFault(); 10846973Stjones1@inf.ed.ac.uk 108510824SAndreas.Sandberg@ARM.com instFlags[IsStrictlyOrdered] = state->isStrictlyOrdered(); 10866973Stjones1@inf.ed.ac.uk 10876973Stjones1@inf.ed.ac.uk if (fault == NoFault) { 108811097Songal@cs.wisc.edu // save Paddr for a single req 108911097Songal@cs.wisc.edu physEffAddrLow = state->getPaddr(); 109011097Songal@cs.wisc.edu 109111097Songal@cs.wisc.edu // case for the request that has been split 109211097Songal@cs.wisc.edu if (state->isSplit) { 109311097Songal@cs.wisc.edu physEffAddrLow = state->sreqLow->getPaddr(); 109411097Songal@cs.wisc.edu physEffAddrHigh = state->sreqHigh->getPaddr(); 109511097Songal@cs.wisc.edu } 109611097Songal@cs.wisc.edu 10976973Stjones1@inf.ed.ac.uk memReqFlags = state->getFlags(); 10986973Stjones1@inf.ed.ac.uk 10996973Stjones1@inf.ed.ac.uk if (state->mainReq->isCondSwap()) { 11006973Stjones1@inf.ed.ac.uk assert(state->res); 11016973Stjones1@inf.ed.ac.uk state->mainReq->setExtraData(*state->res); 11026973Stjones1@inf.ed.ac.uk } 11036973Stjones1@inf.ed.ac.uk 11046973Stjones1@inf.ed.ac.uk } else { 11056973Stjones1@inf.ed.ac.uk state->deleteReqs(); 11066973Stjones1@inf.ed.ac.uk } 11076973Stjones1@inf.ed.ac.uk delete state; 11087944SGiacomo.Gabrielli@arm.com 11099046SAli.Saidi@ARM.com translationCompleted(true); 11106973Stjones1@inf.ed.ac.uk} 11116973Stjones1@inf.ed.ac.uk 11121464SN/A#endif // __CPU_BASE_DYN_INST_HH__ 1113