base_dyn_inst.hh revision 12109
11689SN/A/* 22325SN/A * Copyright (c) 2011,2013,2016 ARM Limited 31689SN/A * Copyright (c) 2013 Advanced Micro Devices, Inc. 41689SN/A * All rights reserved. 51689SN/A * 61689SN/A * The license below extends only to copyright in the software and shall 71689SN/A * not be construed as granting a license to any other intellectual 81689SN/A * property including but not limited to intellectual property relating 91689SN/A * to a hardware implementation of the functionality of the software 101689SN/A * licensed hereunder. You may use the software subject to the license 111689SN/A * terms below provided that you ensure that this notice is replicated 121689SN/A * unmodified and in its entirety in all distributions of the software, 131689SN/A * modified or unmodified, in source code or in binary form. 141689SN/A * 151689SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 161689SN/A * Copyright (c) 2009 The University of Edinburgh 171689SN/A * All rights reserved. 181689SN/A * 191689SN/A * Redistribution and use in source and binary forms, with or without 201689SN/A * modification, are permitted provided that the following conditions are 211689SN/A * met: redistributions of source code must retain the above copyright 221689SN/A * notice, this list of conditions and the following disclaimer; 231689SN/A * redistributions in binary form must reproduce the above copyright 241689SN/A * notice, this list of conditions and the following disclaimer in the 251689SN/A * documentation and/or other materials provided with the distribution; 261689SN/A * neither the name of the copyright holders nor the names of its 272665Ssaidi@eecs.umich.edu * contributors may be used to endorse or promote products derived from 282665Ssaidi@eecs.umich.edu * this software without specific prior written permission. 292756Sksewell@umich.edu * 301689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 311689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 321858SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 332733Sktlim@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 341858SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 351858SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 362356SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 371060SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 381060SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 391060SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 401060SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 411060SN/A * 422325SN/A * Authors: Kevin Lim 432683Sktlim@umich.edu * Timothy M. Jones 442680Sktlim@umich.edu */ 452817Sksewell@umich.edu 461717SN/A#ifndef __CPU_BASE_DYN_INST_HH__ 471060SN/A#define __CPU_BASE_DYN_INST_HH__ 484167Sbinkertn@umich.edu 492292SN/A#include <array> 502292SN/A#include <bitset> 512794Sktlim@umich.edu#include <deque> 522794Sktlim@umich.edu#include <list> 532794Sktlim@umich.edu#include <string> 542794Sktlim@umich.edu 551060SN/A#include "arch/generic/tlb.hh" 562669Sktlim@umich.edu#include "arch/utility.hh" 571060SN/A#include "base/trace.hh" 582733Sktlim@umich.edu#include "config/the_isa.hh" 592292SN/A#include "cpu/checker/cpu.hh" 601060SN/A#include "cpu/exec_context.hh" 611060SN/A#include "cpu/exetrace.hh" 621060SN/A#include "cpu/inst_res.hh" 632292SN/A#include "cpu/inst_seq.hh" 642733Sktlim@umich.edu#include "cpu/o3/comm.hh" 652292SN/A#include "cpu/op_class.hh" 662292SN/A#include "cpu/static_inst.hh" 672292SN/A#include "cpu/translation.hh" 682292SN/A#include "mem/packet.hh" 691060SN/A#include "mem/request.hh" 701755SN/A#include "sim/byteswap.hh" 711060SN/A#include "sim/system.hh" 721060SN/A 731060SN/A/** 741060SN/A * @file 751060SN/A * Defines a dynamic instruction context. 761060SN/A */ 771755SN/A 781060SN/Atemplate <class Impl> 791060SN/Aclass BaseDynInst : public ExecContext, public RefCounted 801060SN/A{ 811060SN/A public: 821060SN/A // Typedef for the CPU. 831060SN/A typedef typename Impl::CPUType ImplCPU; 841755SN/A typedef typename ImplCPU::ImplState ImplState; 851060SN/A using VecRegContainer = TheISA::VecRegContainer; 864873Sstever@eecs.umich.edu 871060SN/A // The DynInstPtr type. 881060SN/A typedef typename Impl::DynInstPtr DynInstPtr; 891060SN/A typedef RefCountingPtr<BaseDynInst<Impl> > BaseDynInstPtr; 902829Sksewell@umich.edu 913221Sktlim@umich.edu // The list of instructions iterator type. 922829Sksewell@umich.edu typedef typename std::list<DynInstPtr>::iterator ListIt; 932829Sksewell@umich.edu 942829Sksewell@umich.edu enum { 952829Sksewell@umich.edu MaxInstSrcRegs = TheISA::MaxInstSrcRegs, /// Max source regs 962829Sksewell@umich.edu MaxInstDestRegs = TheISA::MaxInstDestRegs /// Max dest regs 972829Sksewell@umich.edu }; 982829Sksewell@umich.edu 992829Sksewell@umich.edu protected: 1002829Sksewell@umich.edu enum Status { 1012829Sksewell@umich.edu IqEntry, /// Instruction is in the IQ 1022829Sksewell@umich.edu RobEntry, /// Instruction is in the ROB 1032829Sksewell@umich.edu LsqEntry, /// Instruction is in the LSQ 1042829Sksewell@umich.edu Completed, /// Instruction has completed 1052829Sksewell@umich.edu ResultReady, /// Instruction has its result 1062829Sksewell@umich.edu CanIssue, /// Instruction can issue and execute 1072829Sksewell@umich.edu Issued, /// Instruction has issued 1082829Sksewell@umich.edu Executed, /// Instruction has executed 1092829Sksewell@umich.edu CanCommit, /// Instruction can commit 1102829Sksewell@umich.edu AtCommit, /// Instruction has reached commit 1112829Sksewell@umich.edu Committed, /// Instruction has committed 1122829Sksewell@umich.edu Squashed, /// Instruction is squashed 1132829Sksewell@umich.edu SquashedInIQ, /// Instruction is squashed in the IQ 1142829Sksewell@umich.edu SquashedInLSQ, /// Instruction is squashed in the LSQ 1154873Sstever@eecs.umich.edu SquashedInROB, /// Instruction is squashed in the ROB 1162829Sksewell@umich.edu RecoverInst, /// Is a recover instruction 1172829Sksewell@umich.edu BlockingInst, /// Is a blocking instruction 1182829Sksewell@umich.edu ThreadsyncWait, /// Is a thread synchronization instruction 1192875Sksewell@umich.edu SerializeBefore, /// Needs to serialize on 1203859Sbinkertn@umich.edu /// instructions ahead of it 1212875Sksewell@umich.edu SerializeAfter, /// Needs to serialize instructions behind it 1222875Sksewell@umich.edu SerializeHandled, /// Serialization has been handled 1232875Sksewell@umich.edu NumStatus 1242875Sksewell@umich.edu }; 1252875Sksewell@umich.edu 1262875Sksewell@umich.edu enum Flags { 1273859Sbinkertn@umich.edu TranslationStarted, 1282875Sksewell@umich.edu TranslationCompleted, 1292875Sksewell@umich.edu PossibleLoadViolation, 1302875Sksewell@umich.edu HitExternalSnoop, 1313859Sbinkertn@umich.edu EffAddrValid, 1322875Sksewell@umich.edu RecordResult, 1332875Sksewell@umich.edu Predicate, 1342875Sksewell@umich.edu PredTaken, 1352875Sksewell@umich.edu /** Whether or not the effective address calculation is completed. 1362875Sksewell@umich.edu * @todo: Consider if this is necessary or not. 1372875Sksewell@umich.edu */ 1382875Sksewell@umich.edu EACalcDone, 1393221Sktlim@umich.edu IsStrictlyOrdered, 1403221Sktlim@umich.edu ReqMade, 1412875Sksewell@umich.edu MemOpDone, 1422875Sksewell@umich.edu MaxFlags 1432875Sksewell@umich.edu }; 1442875Sksewell@umich.edu 1452875Sksewell@umich.edu public: 1462875Sksewell@umich.edu /** The sequence number of the instruction. */ 1474873Sstever@eecs.umich.edu InstSeqNum seqNum; 1482875Sksewell@umich.edu 1492875Sksewell@umich.edu /** The StaticInst used by this BaseDynInst. */ 1502875Sksewell@umich.edu const StaticInstPtr staticInst; 1514329Sktlim@umich.edu 1522733Sktlim@umich.edu /** Pointer to the Impl's CPU object. */ 1533781Sgblack@eecs.umich.edu ImplCPU *cpu; 1543781Sgblack@eecs.umich.edu 1553781Sgblack@eecs.umich.edu BaseCPU *getCpuPtr() { return cpu; } 1563781Sgblack@eecs.umich.edu 1571060SN/A /** Pointer to the thread state. */ 1582292SN/A ImplState *thread; 1594329Sktlim@umich.edu 1604329Sktlim@umich.edu /** The kind of fault this instruction has generated. */ 1614329Sktlim@umich.edu Fault fault; 1624329Sktlim@umich.edu 1634329Sktlim@umich.edu /** InstRecord that tracks this instructions. */ 1641060SN/A Trace::InstRecord *traceData; 1654329Sktlim@umich.edu 1664329Sktlim@umich.edu protected: 1671060SN/A /** The result of the instruction; assumes an instruction can have many 1682831Sksewell@umich.edu * destination registers. 1692292SN/A */ 1702292SN/A std::queue<InstResult> instResult; 1711060SN/A 1724329Sktlim@umich.edu /** PC state for this instruction. */ 1734329Sktlim@umich.edu TheISA::PCState pc; 1742292SN/A 1752292SN/A /* An amalgamation of a lot of boolean values into one */ 1761060SN/A std::bitset<MaxFlags> instFlags; 1772831Sksewell@umich.edu 1782292SN/A /** The status of this BaseDynInst. Several bits can be set. */ 1792292SN/A std::bitset<NumStatus> status; 1802292SN/A 1812292SN/A /** Whether or not the source register is ready. 1821060SN/A * @todo: Not sure this should be here vs the derived class. 1832873Sktlim@umich.edu */ 1842873Sktlim@umich.edu std::bitset<MaxInstSrcRegs> _readySrcRegIdx; 1852873Sktlim@umich.edu 1862873Sktlim@umich.edu public: 1872873Sktlim@umich.edu /** The thread this instruction is from. */ 1882873Sktlim@umich.edu ThreadID threadNumber; 1892873Sktlim@umich.edu 1902873Sktlim@umich.edu /** Iterator pointing to this BaseDynInst in the list of all insts. */ 1911060SN/A ListIt instListIt; 1921060SN/A 1931858SN/A ////////////////////// Branch Data /////////////// 1942292SN/A /** Predicted PC state after this instruction. */ 1951060SN/A TheISA::PCState predPC; 1961060SN/A 1972843Sktlim@umich.edu /** The Macroop if one exists */ 1982316SN/A const StaticInstPtr macroop; 1992316SN/A 2001060SN/A /** How many source registers are ready. */ 2013221Sktlim@umich.edu uint8_t readyRegs; 2023221Sktlim@umich.edu 2033221Sktlim@umich.edu public: 2043221Sktlim@umich.edu /////////////////////// Load Store Data ////////////////////// 2053221Sktlim@umich.edu /** The effective virtual address (lds & stores only). */ 2061681SN/A Addr effAddr; 2074598Sbinkertn@umich.edu 2082794Sktlim@umich.edu /** The effective physical address. */ 2092316SN/A Addr physEffAddrLow; 2102316SN/A 2112316SN/A /** The effective physical address 2122316SN/A * of the second request for a split request 2132316SN/A */ 2144598Sbinkertn@umich.edu Addr physEffAddrHigh; 2154598Sbinkertn@umich.edu 2164598Sbinkertn@umich.edu /** The memory request flags (from translation). */ 2172794Sktlim@umich.edu unsigned memReqFlags; 2182316SN/A 2191858SN/A /** data address space ID, for loads & stores. */ 2202292SN/A short asid; 2212292SN/A 2221681SN/A /** The size of the request */ 2231681SN/A uint8_t effSize; 2242325SN/A 2252325SN/A /** Pointer to the data for the memory access. */ 2262325SN/A uint8_t *memData; 2271060SN/A 2282292SN/A /** Load queue index. */ 2292292SN/A int16_t lqIdx; 2302292SN/A 2312292SN/A /** Store queue index. */ 2322292SN/A int16_t sqIdx; 2332292SN/A 2341060SN/A 2351060SN/A /////////////////////// TLB Miss ////////////////////// 2361060SN/A /** 2371060SN/A * Saved memory requests (needed when the DTB address translation is 2381060SN/A * delayed due to a hw page table walk). 2391060SN/A */ 2401060SN/A RequestPtr savedReq; 2411060SN/A RequestPtr savedSreqLow; 2421060SN/A RequestPtr savedSreqHigh; 2431060SN/A 2441060SN/A /////////////////////// Checker ////////////////////// 2452292SN/A // Need a copy of main request pointer to verify on writes. 2461060SN/A RequestPtr reqToVerify; 2471060SN/A 2481060SN/A private: 2491060SN/A /** Instruction effective address. 2501060SN/A * @todo: Consider if this is necessary or not. 2511060SN/A */ 2521060SN/A Addr instEffAddr; 2531060SN/A 2542292SN/A protected: 2552292SN/A /** Flattened register index of the destination registers of this 2562292SN/A * instruction. 2572292SN/A */ 2582292SN/A std::array<RegId, TheISA::MaxInstDestRegs> _flatDestRegIdx; 2592307SN/A 2602831Sksewell@umich.edu /** Physical register index of the destination registers of this 2612831Sksewell@umich.edu * instruction. 2622831Sksewell@umich.edu */ 2632831Sksewell@umich.edu std::array<PhysRegIdPtr, TheISA::MaxInstDestRegs> _destRegIdx; 2642831Sksewell@umich.edu 2652831Sksewell@umich.edu /** Physical register index of the source registers of this 2662292SN/A * instruction. 2672307SN/A */ 2682292SN/A std::array<PhysRegIdPtr, TheISA::MaxInstSrcRegs> _srcRegIdx; 2692292SN/A 2702316SN/A /** Physical register index of the previous producers of the 2712292SN/A * architected destinations. 2722292SN/A */ 2732292SN/A std::array<PhysRegIdPtr, TheISA::MaxInstDestRegs> _prevDestRegIdx; 2742292SN/A 2752292SN/A 2762292SN/A public: 2771060SN/A /** Records changes to result? */ 2782292SN/A void recordResult(bool f) { instFlags[RecordResult] = f; } 2792292SN/A 2801060SN/A /** Is the effective virtual address valid. */ 2812292SN/A bool effAddrValid() const { return instFlags[EffAddrValid]; } 2822307SN/A 2832292SN/A /** Whether or not the memory operation is done. */ 2842292SN/A bool memOpDone() const { return instFlags[MemOpDone]; } 2852292SN/A void memOpDone(bool f) { instFlags[MemOpDone] = f; } 2862325SN/A 2872292SN/A 2882292SN/A //////////////////////////////////////////// 2892292SN/A // 2902325SN/A // INSTRUCTION EXECUTION 2912292SN/A // 2922292SN/A //////////////////////////////////////////// 2932292SN/A 2942292SN/A void demapPage(Addr vaddr, uint64_t asn) 2952292SN/A { 2962292SN/A cpu->demapPage(vaddr, asn); 2972292SN/A } 2982292SN/A void demapInstPage(Addr vaddr, uint64_t asn) 2992292SN/A { 3002292SN/A cpu->demapPage(vaddr, asn); 3012292SN/A } 3022325SN/A void demapDataPage(Addr vaddr, uint64_t asn) 3032292SN/A { 3042292SN/A cpu->demapPage(vaddr, asn); 3052292SN/A } 3062325SN/A 3072292SN/A Fault initiateMemRead(Addr addr, unsigned size, Request::Flags flags); 3082292SN/A 3092292SN/A Fault writeMem(uint8_t *data, unsigned size, Addr addr, 3102292SN/A Request::Flags flags, uint64_t *res); 3112292SN/A 3122292SN/A /** Splits a request in two if it crosses a dcache block. */ 3132292SN/A void splitRequest(RequestPtr req, RequestPtr &sreqLow, 3142292SN/A RequestPtr &sreqHigh); 3153221Sktlim@umich.edu 3163221Sktlim@umich.edu /** Initiate a DTB address translation. */ 3173221Sktlim@umich.edu void initiateTranslation(RequestPtr req, RequestPtr sreqLow, 3182292SN/A RequestPtr sreqHigh, uint64_t *res, 3192292SN/A BaseTLB::Mode mode); 3202292SN/A 3212292SN/A /** Finish a DTB address translation. */ 3222292SN/A void finishTranslation(WholeTranslationState *state); 3232292SN/A 3242292SN/A /** True if the DTB address translation has started. */ 3252292SN/A bool translationStarted() const { return instFlags[TranslationStarted]; } 3262292SN/A void translationStarted(bool f) { instFlags[TranslationStarted] = f; } 3271060SN/A 3282292SN/A /** True if the DTB address translation has completed. */ 3291060SN/A bool translationCompleted() const { return instFlags[TranslationCompleted]; } 3301060SN/A void translationCompleted(bool f) { instFlags[TranslationCompleted] = f; } 3312292SN/A 3322292SN/A /** True if this address was found to match a previous load and they issued 3332292SN/A * out of order. If that happend, then it's only a problem if an incoming 3342829Sksewell@umich.edu * snoop invalidate modifies the line, in which case we need to squash. 3352829Sksewell@umich.edu * If nothing modified the line the order doesn't matter. 3363093Sksewell@umich.edu */ 3373093Sksewell@umich.edu bool possibleLoadViolation() const { return instFlags[PossibleLoadViolation]; } 3383093Sksewell@umich.edu void possibleLoadViolation(bool f) { instFlags[PossibleLoadViolation] = f; } 3393093Sksewell@umich.edu 3403093Sksewell@umich.edu /** True if the address hit a external snoop while sitting in the LSQ. 3412292SN/A * If this is true and a older instruction sees it, this instruction must 3421060SN/A * reexecute 3431060SN/A */ 3441060SN/A bool hitExternalSnoop() const { return instFlags[HitExternalSnoop]; } 3451755SN/A void hitExternalSnoop(bool f) { instFlags[HitExternalSnoop] = f; } 3461060SN/A 3471060SN/A /** 3481060SN/A * Returns true if the DTB address translation is being delayed due to a hw 3491060SN/A * page table walk. 3501060SN/A */ 3511755SN/A bool isTranslationDelayed() const 3521062SN/A { 3532733Sktlim@umich.edu return (translationStarted() && !translationCompleted()); 3542292SN/A } 3552733Sktlim@umich.edu 3562292SN/A public: 3572292SN/A#ifdef DEBUG 3582292SN/A void dumpSNList(); 3592292SN/A#endif 3602292SN/A 3612292SN/A /** Returns the physical register index of the i'th destination 3622292SN/A * register. 3632292SN/A */ 3642292SN/A PhysRegIdPtr renamedDestRegIdx(int idx) const 3652292SN/A { 3662292SN/A return _destRegIdx[idx]; 3672292SN/A } 3682292SN/A 3692292SN/A /** Returns the physical register index of the i'th source register. */ 3702292SN/A PhysRegIdPtr renamedSrcRegIdx(int idx) const 3712292SN/A { 3722292SN/A assert(TheISA::MaxInstSrcRegs > idx); 3732292SN/A return _srcRegIdx[idx]; 3742292SN/A } 3752292SN/A 3762292SN/A /** Returns the flattened register index of the i'th destination 3772292SN/A * register. 3782292SN/A */ 3792292SN/A const RegId& flattenedDestRegIdx(int idx) const 3802292SN/A { 3812292SN/A return _flatDestRegIdx[idx]; 3822292SN/A } 3832292SN/A 3842292SN/A /** Returns the physical register index of the previous physical register 3854392Sktlim@umich.edu * that remapped to the same logical register index. 3862292SN/A */ 3872292SN/A PhysRegIdPtr prevDestRegIdx(int idx) const 3882292SN/A { 3892292SN/A return _prevDestRegIdx[idx]; 3902292SN/A } 3914392Sktlim@umich.edu 3922292SN/A /** Renames a destination register to a physical register. Also records 3932292SN/A * the previous physical register that the logical register mapped to. 3942292SN/A */ 3952292SN/A void renameDestReg(int idx, 3962292SN/A PhysRegIdPtr renamed_dest, 3974392Sktlim@umich.edu PhysRegIdPtr previous_rename) 3982292SN/A { 3992292SN/A _destRegIdx[idx] = renamed_dest; 4002292SN/A _prevDestRegIdx[idx] = previous_rename; 4012292SN/A } 4022292SN/A 4034392Sktlim@umich.edu /** Renames a source logical register to the physical register which 4042292SN/A * has/will produce that logical register's result. 4051062SN/A * @todo: add in whether or not the source register is ready. 4061062SN/A */ 4071062SN/A void renameSrcReg(int idx, PhysRegIdPtr renamed_src) 4082871Sktlim@umich.edu { 4092871Sktlim@umich.edu _srcRegIdx[idx] = renamed_src; 4102871Sktlim@umich.edu } 4112871Sktlim@umich.edu 4122871Sktlim@umich.edu /** Flattens a destination architectural register index into a logical 4132871Sktlim@umich.edu * index. 4142871Sktlim@umich.edu */ 4152871Sktlim@umich.edu void flattenDestReg(int idx, const RegId& flattened_dest) 4162871Sktlim@umich.edu { 4172871Sktlim@umich.edu _flatDestRegIdx[idx] = flattened_dest; 4182871Sktlim@umich.edu } 4192871Sktlim@umich.edu /** BaseDynInst constructor given a binary instruction. 4201062SN/A * @param staticInst A StaticInstPtr to the underlying instruction. 4211755SN/A * @param pc The PC state for the instruction. 4221060SN/A * @param predPC The predicted next PC state for the instruction. 4232733Sktlim@umich.edu * @param seq_num The sequence number of the instruction. 4241060SN/A * @param cpu Pointer to the instruction's CPU. 4252292SN/A */ 4262292SN/A BaseDynInst(const StaticInstPtr &staticInst, const StaticInstPtr ¯oop, 4272325SN/A TheISA::PCState pc, TheISA::PCState predPC, 4282292SN/A InstSeqNum seq_num, ImplCPU *cpu); 4292292SN/A 4301060SN/A /** BaseDynInst constructor given a StaticInst pointer. 4311060SN/A * @param _staticInst The StaticInst for this BaseDynInst. 4321060SN/A */ 4331060SN/A BaseDynInst(const StaticInstPtr &staticInst, const StaticInstPtr ¯oop); 4341060SN/A 4351060SN/A /** BaseDynInst destructor. */ 4361060SN/A ~BaseDynInst(); 4371060SN/A 4381060SN/A private: 4391060SN/A /** Function to initialize variables in the constructors. */ 4402292SN/A void initVars(); 4412292SN/A 4422292SN/A public: 4432292SN/A /** Dumps out contents of this BaseDynInst. */ 4442292SN/A void dump(); 4451060SN/A 4461060SN/A /** Dumps out contents of this BaseDynInst into given string. */ 4471060SN/A void dump(std::string &outstring); 4481060SN/A 4491060SN/A /** Read this CPU's ID. */ 4501060SN/A int cpuId() const { return cpu->cpuId(); } 4511060SN/A 4522325SN/A /** Read this CPU's Socket ID. */ 4532292SN/A uint32_t socketId() const { return cpu->socketId(); } 4542292SN/A 4552292SN/A /** Read this CPU's data requestor ID */ 4562292SN/A MasterID masterId() const { return cpu->dataMasterId(); } 4572292SN/A 4582325SN/A /** Read this context's system-wide ID **/ 4592867Sktlim@umich.edu ContextID contextId() const { return thread->contextId(); } 4602905Sktlim@umich.edu 4613226Sktlim@umich.edu /** Returns the fault type. */ 4622325SN/A Fault getFault() const { return fault; } 4632325SN/A 4643221Sktlim@umich.edu /** Checks whether or not this instruction has had its branch target 4653226Sktlim@umich.edu * calculated yet. For now it is not utilized and is hacked to be 4662325SN/A * always false. 4672325SN/A * @todo: Actually use this instruction. 4682325SN/A */ 4694030Sktlim@umich.edu bool doneTargCalc() { return false; } 4703226Sktlim@umich.edu 4712325SN/A /** Set the predicted target of this current instruction. */ 4722292SN/A void setPredTarg(const TheISA::PCState &_predPC) 4732292SN/A { 4742292SN/A predPC = _predPC; 4752292SN/A } 4762292SN/A 4772292SN/A const TheISA::PCState &readPredTarg() { return predPC; } 4781060SN/A 4791060SN/A /** Returns the predicted PC immediately after the branch. */ 4801060SN/A Addr predInstAddr() { return predPC.instAddr(); } 4811060SN/A 4821755SN/A /** Returns the predicted PC two instructions after the branch */ 4831060SN/A Addr predNextInstAddr() { return predPC.nextInstAddr(); } 4842307SN/A 4852680Sktlim@umich.edu /** Returns the predicted micro PC after the branch */ 4862292SN/A Addr predMicroPC() { return predPC.microPC(); } 4871060SN/A 4882292SN/A /** Returns whether the instruction was predicted taken or not. */ 4892292SN/A bool readPredTaken() 4902292SN/A { 4912292SN/A return instFlags[PredTaken]; 4922292SN/A } 4932292SN/A 4941858SN/A void setPredTaken(bool predicted_taken) 4952680Sktlim@umich.edu { 4961681SN/A instFlags[PredTaken] = predicted_taken; 4972680Sktlim@umich.edu } 4981681SN/A 4992292SN/A /** Returns whether the instruction mispredicted. */ 5002680Sktlim@umich.edu bool mispredicted() 5012292SN/A { 5021060SN/A TheISA::PCState tempPC = pc; 5031060SN/A TheISA::advancePC(tempPC, staticInst); 5042292SN/A return !(tempPC == predPC); 5052680Sktlim@umich.edu } 5062292SN/A 5072292SN/A // 5082292SN/A // Instruction types. Forward checks to StaticInst object. 5092292SN/A // 5102292SN/A bool isNop() const { return staticInst->isNop(); } 5112292SN/A bool isMemRef() const { return staticInst->isMemRef(); } 5122292SN/A bool isLoad() const { return staticInst->isLoad(); } 5132316SN/A bool isStore() const { return staticInst->isStore(); } 5142292SN/A bool isStoreConditional() const 5152292SN/A { return staticInst->isStoreConditional(); } 5162292SN/A bool isInstPrefetch() const { return staticInst->isInstPrefetch(); } 5172292SN/A bool isDataPrefetch() const { return staticInst->isDataPrefetch(); } 5182292SN/A bool isInteger() const { return staticInst->isInteger(); } 5192292SN/A bool isFloating() const { return staticInst->isFloating(); } 5202292SN/A bool isControl() const { return staticInst->isControl(); } 5212292SN/A bool isCall() const { return staticInst->isCall(); } 5222292SN/A bool isReturn() const { return staticInst->isReturn(); } 5232292SN/A bool isDirectCtrl() const { return staticInst->isDirectCtrl(); } 5242875Sksewell@umich.edu bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); } 5252875Sksewell@umich.edu bool isCondCtrl() const { return staticInst->isCondCtrl(); } 5262875Sksewell@umich.edu bool isUncondCtrl() const { return staticInst->isUncondCtrl(); } 5272875Sksewell@umich.edu bool isCondDelaySlot() const { return staticInst->isCondDelaySlot(); } 5282875Sksewell@umich.edu bool isThreadSync() const { return staticInst->isThreadSync(); } 5293226Sktlim@umich.edu bool isSerializing() const { return staticInst->isSerializing(); } 5303226Sktlim@umich.edu bool isSerializeBefore() const 5312875Sksewell@umich.edu { return staticInst->isSerializeBefore() || status[SerializeBefore]; } 5322875Sksewell@umich.edu bool isSerializeAfter() const 5332875Sksewell@umich.edu { return staticInst->isSerializeAfter() || status[SerializeAfter]; } 5342875Sksewell@umich.edu bool isSquashAfter() const { return staticInst->isSquashAfter(); } 5352875Sksewell@umich.edu bool isMemBarrier() const { return staticInst->isMemBarrier(); } 5362875Sksewell@umich.edu bool isWriteBarrier() const { return staticInst->isWriteBarrier(); } 5372875Sksewell@umich.edu bool isNonSpeculative() const { return staticInst->isNonSpeculative(); } 5382875Sksewell@umich.edu bool isQuiesce() const { return staticInst->isQuiesce(); } 5392875Sksewell@umich.edu bool isIprAccess() const { return staticInst->isIprAccess(); } 5402875Sksewell@umich.edu bool isUnverifiable() const { return staticInst->isUnverifiable(); } 5412875Sksewell@umich.edu bool isSyscall() const { return staticInst->isSyscall(); } 5422875Sksewell@umich.edu bool isMacroop() const { return staticInst->isMacroop(); } 5432875Sksewell@umich.edu bool isMicroop() const { return staticInst->isMicroop(); } 5442875Sksewell@umich.edu bool isDelayedCommit() const { return staticInst->isDelayedCommit(); } 5452875Sksewell@umich.edu bool isLastMicroop() const { return staticInst->isLastMicroop(); } 5462875Sksewell@umich.edu bool isFirstMicroop() const { return staticInst->isFirstMicroop(); } 5473226Sktlim@umich.edu bool isMicroBranch() const { return staticInst->isMicroBranch(); } 5483226Sktlim@umich.edu 5492875Sksewell@umich.edu /** Temporarily sets this instruction as a serialize before instruction. */ 5502875Sksewell@umich.edu void setSerializeBefore() { status.set(SerializeBefore); } 5512875Sksewell@umich.edu 5522875Sksewell@umich.edu /** Clears the serializeBefore part of this instruction. */ 5532875Sksewell@umich.edu void clearSerializeBefore() { status.reset(SerializeBefore); } 5542875Sksewell@umich.edu 5552875Sksewell@umich.edu /** Checks if this serializeBefore is only temporarily set. */ 5562875Sksewell@umich.edu bool isTempSerializeBefore() { return status[SerializeBefore]; } 5572875Sksewell@umich.edu 5582875Sksewell@umich.edu /** Temporarily sets this instruction as a serialize after instruction. */ 5592875Sksewell@umich.edu void setSerializeAfter() { status.set(SerializeAfter); } 5602875Sksewell@umich.edu 5612875Sksewell@umich.edu /** Clears the serializeAfter part of this instruction.*/ 5622875Sksewell@umich.edu void clearSerializeAfter() { status.reset(SerializeAfter); } 5632875Sksewell@umich.edu 5642875Sksewell@umich.edu /** Checks if this serializeAfter is only temporarily set. */ 5652875Sksewell@umich.edu bool isTempSerializeAfter() { return status[SerializeAfter]; } 5662875Sksewell@umich.edu 5672875Sksewell@umich.edu /** Sets the serialization part of this instruction as handled. */ 5682875Sksewell@umich.edu void setSerializeHandled() { status.set(SerializeHandled); } 5693221Sktlim@umich.edu 5702875Sksewell@umich.edu /** Checks if the serialization part of this instruction has been 5712875Sksewell@umich.edu * handled. This does not apply to the temporary serializing 5722875Sksewell@umich.edu * state; it only applies to this instruction's own permanent 5732875Sksewell@umich.edu * serializing state. 5742875Sksewell@umich.edu */ 5752875Sksewell@umich.edu bool isSerializeHandled() { return status[SerializeHandled]; } 5762875Sksewell@umich.edu 5772875Sksewell@umich.edu /** Returns the opclass of this instruction. */ 5782875Sksewell@umich.edu OpClass opClass() const { return staticInst->opClass(); } 5792875Sksewell@umich.edu 5802875Sksewell@umich.edu /** Returns the branch target address. */ 5812875Sksewell@umich.edu TheISA::PCState branchTarget() const 5822875Sksewell@umich.edu { return staticInst->branchTarget(pc); } 5832875Sksewell@umich.edu 5843221Sktlim@umich.edu /** Returns the number of source registers. */ 5853221Sktlim@umich.edu int8_t numSrcRegs() const { return staticInst->numSrcRegs(); } 5862875Sksewell@umich.edu 5872875Sksewell@umich.edu /** Returns the number of destination registers. */ 5882875Sksewell@umich.edu int8_t numDestRegs() const { return staticInst->numDestRegs(); } 5892875Sksewell@umich.edu 5902875Sksewell@umich.edu // the following are used to track physical register usage 5913221Sktlim@umich.edu // for machines with separate int & FP reg files 5923221Sktlim@umich.edu int8_t numFPDestRegs() const { return staticInst->numFPDestRegs(); } 5932875Sksewell@umich.edu int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); } 5942875Sksewell@umich.edu int8_t numCCDestRegs() const { return staticInst->numCCDestRegs(); } 5953221Sktlim@umich.edu int8_t numVecDestRegs() const { return staticInst->numVecDestRegs(); } 5963221Sktlim@umich.edu int8_t numVecElemDestRegs() const { 5973221Sktlim@umich.edu return staticInst->numVecElemDestRegs(); 5982875Sksewell@umich.edu } 5992875Sksewell@umich.edu 6002875Sksewell@umich.edu /** Returns the logical register index of the i'th destination register. */ 6012875Sksewell@umich.edu const RegId& destRegIdx(int i) const { return staticInst->destRegIdx(i); } 6022875Sksewell@umich.edu 6032875Sksewell@umich.edu /** Returns the logical register index of the i'th source register. */ 6042875Sksewell@umich.edu const RegId& srcRegIdx(int i) const { return staticInst->srcRegIdx(i); } 6052875Sksewell@umich.edu 6063221Sktlim@umich.edu /** Return the size of the instResult queue. */ 6073221Sktlim@umich.edu uint8_t resultSize() { return instResult.size(); } 6083859Sbinkertn@umich.edu 6093859Sbinkertn@umich.edu /** Pops a result off the instResult queue. 6102910Sksewell@umich.edu * If the result stack is empty, return the default value. 6112875Sksewell@umich.edu * */ 6122875Sksewell@umich.edu InstResult popResult(InstResult dflt = InstResult()) 6132875Sksewell@umich.edu { 6142875Sksewell@umich.edu if (!instResult.empty()) { 6152875Sksewell@umich.edu InstResult t = instResult.front(); 6162875Sksewell@umich.edu instResult.pop(); 6172875Sksewell@umich.edu return t; 6182910Sksewell@umich.edu } 6192910Sksewell@umich.edu return dflt; 6203221Sktlim@umich.edu } 6212875Sksewell@umich.edu 6222875Sksewell@umich.edu /** Pushes a result onto the instResult queue. */ 6232875Sksewell@umich.edu /** @{ */ 6242875Sksewell@umich.edu /** Scalar result. */ 6252292SN/A template<typename T> 6262292SN/A void setScalarResult(T&& t) 6272847Sksewell@umich.edu { 6282292SN/A if (instFlags[RecordResult]) { 6292683Sktlim@umich.edu instResult.push(InstResult(std::forward<T>(t), 6302292SN/A InstResult::ResultType::Scalar)); 6312680Sktlim@umich.edu } 6322292SN/A } 6332847Sksewell@umich.edu 6342292SN/A /** Full vector result. */ 6352292SN/A template<typename T> 6362292SN/A void setVecResult(T&& t) 6372292SN/A { 6382292SN/A if (instFlags[RecordResult]) { 6392292SN/A instResult.push(InstResult(std::forward<T>(t), 6402292SN/A InstResult::ResultType::VecReg)); 6412292SN/A } 6422292SN/A } 6432292SN/A 6442292SN/A /** Vector element result. */ 6452292SN/A template<typename T> 6462292SN/A void setVecElemResult(T&& t) 6472292SN/A { 6482292SN/A if (instFlags[RecordResult]) { 6492292SN/A instResult.push(InstResult(std::forward<T>(t), 6502292SN/A InstResult::ResultType::VecElem)); 6512292SN/A } 6522292SN/A } 6532847Sksewell@umich.edu /** @} */ 6542292SN/A 6552847Sksewell@umich.edu /** Records an integer register being set to a value. */ 6562847Sksewell@umich.edu void setIntRegOperand(const StaticInst *si, int idx, IntReg val) 6572847Sksewell@umich.edu { 6582847Sksewell@umich.edu setScalarResult(val); 6592292SN/A } 6602680Sktlim@umich.edu 6612292SN/A /** Records a CC register being set to a value. */ 6622292SN/A void setCCRegOperand(const StaticInst *si, int idx, CCReg val) 6632292SN/A { 6642292SN/A setScalarResult(val); 6652292SN/A } 6662292SN/A 6672292SN/A /** Records an fp register being set to a value. */ 6682292SN/A void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val) 6692292SN/A { 6702292SN/A setScalarResult(val); 6712292SN/A } 6722292SN/A 6732877Sksewell@umich.edu /** Record a vector register being set to a value */ 6742847Sksewell@umich.edu void setVecRegOperand(const StaticInst *si, int idx, 6752847Sksewell@umich.edu const VecRegContainer& val) 6762847Sksewell@umich.edu { 6772847Sksewell@umich.edu setVecResult(val); 6782847Sksewell@umich.edu } 6792847Sksewell@umich.edu 6802292SN/A /** Records an fp register being set to an integer value. */ 6812292SN/A void 6822292SN/A setFloatRegOperandBits(const StaticInst *si, int idx, FloatRegBits val) 6832292SN/A { 6842292SN/A setScalarResult(val); 6852292SN/A } 6862292SN/A 6872847Sksewell@umich.edu /** Record a vector register being set to a value */ 6882292SN/A void setVecElemOperand(const StaticInst *si, int idx, const VecElem val) 6892292SN/A { 6902292SN/A setVecElemResult(val); 6912292SN/A } 6922292SN/A 6932292SN/A /** Records that one of the source registers is ready. */ 6942292SN/A void markSrcRegReady(); 6952847Sksewell@umich.edu 6962935Sksewell@umich.edu /** Marks a specific register as ready. */ 6974636Sgblack@eecs.umich.edu void markSrcRegReady(RegIndex src_idx); 6982292SN/A 6992935Sksewell@umich.edu /** Returns if a source register is ready. */ 7002875Sksewell@umich.edu bool isReadySrcRegIdx(int idx) const 7012935Sksewell@umich.edu { 7022292SN/A return this->_readySrcRegIdx[idx]; 7032292SN/A } 7042292SN/A 7052847Sksewell@umich.edu /** Sets this instruction as completed. */ 7063229Sktlim@umich.edu void setCompleted() { status.set(Completed); } 7073229Sktlim@umich.edu 7083229Sktlim@umich.edu /** Returns whether or not this instruction is completed. */ 7093229Sktlim@umich.edu bool isCompleted() const { return status[Completed]; } 7103229Sktlim@umich.edu 7113229Sktlim@umich.edu /** Marks the result as ready. */ 7122292SN/A void setResultReady() { status.set(ResultReady); } 7132292SN/A 7142292SN/A /** Returns whether or not the result is ready. */ 7152292SN/A bool isResultReady() const { return status[ResultReady]; } 7163229Sktlim@umich.edu 7172292SN/A /** Sets this instruction as ready to issue. */ 7182292SN/A void setCanIssue() { status.set(CanIssue); } 7192292SN/A 7202292SN/A /** Returns whether or not this instruction is ready to issue. */ 7212292SN/A bool readyToIssue() const { return status[CanIssue]; } 7222292SN/A 7232292SN/A /** Clears this instruction being able to issue. */ 7242733Sktlim@umich.edu void clearCanIssue() { status.reset(CanIssue); } 7252292SN/A 7262292SN/A /** Sets this instruction as issued from the IQ. */ 7272292SN/A void setIssued() { status.set(Issued); } 7282292SN/A 7292292SN/A /** Returns whether or not this instruction has issued. */ 7302292SN/A bool isIssued() const { return status[Issued]; } 7312733Sktlim@umich.edu 7322292SN/A /** Clears this instruction as being issued. */ 7332292SN/A void clearIssued() { status.reset(Issued); } 7342292SN/A 7352292SN/A /** Sets this instruction as executed. */ 7362733Sktlim@umich.edu void setExecuted() { status.set(Executed); } 7372292SN/A 7382292SN/A /** Returns whether or not this instruction has executed. */ 7392292SN/A bool isExecuted() const { return status[Executed]; } 7402292SN/A 7412292SN/A /** Sets this instruction as ready to commit. */ 7422733Sktlim@umich.edu void setCanCommit() { status.set(CanCommit); } 7432292SN/A 7442292SN/A /** Clears this instruction as being ready to commit. */ 7452292SN/A void clearCanCommit() { status.reset(CanCommit); } 7462292SN/A 7472292SN/A /** Returns whether or not this instruction is ready to commit. */ 7482733Sktlim@umich.edu bool readyToCommit() const { return status[CanCommit]; } 7492292SN/A 7502292SN/A void setAtCommit() { status.set(AtCommit); } 7512292SN/A 7522292SN/A bool isAtCommit() { return status[AtCommit]; } 7532292SN/A 7542733Sktlim@umich.edu /** Sets this instruction as committed. */ 7552292SN/A void setCommitted() { status.set(Committed); } 7562292SN/A 7572292SN/A /** Returns whether or not this instruction is committed. */ 7582292SN/A bool isCommitted() const { return status[Committed]; } 7592292SN/A 7602292SN/A /** Sets this instruction as squashed. */ 7612292SN/A void setSquashed() { status.set(Squashed); } 7622292SN/A 7632292SN/A /** Returns whether or not this instruction is squashed. */ 7642292SN/A bool isSquashed() const { return status[Squashed]; } 7652292SN/A 7662292SN/A //Instruction Queue Entry 7672292SN/A //----------------------- 7682292SN/A /** Sets this instruction as a entry the IQ. */ 7692292SN/A void setInIQ() { status.set(IqEntry); } 7702292SN/A 7712292SN/A /** Sets this instruction as a entry the IQ. */ 7722875Sksewell@umich.edu void clearInIQ() { status.reset(IqEntry); } 7732292SN/A 7742292SN/A /** Returns whether or not this instruction has issued. */ 7751060SN/A bool isInIQ() const { return status[IqEntry]; } 7761060SN/A 7771060SN/A /** Sets this instruction as squashed in the IQ. */ 7784192Sktlim@umich.edu void setSquashedInIQ() { status.set(SquashedInIQ); status.set(Squashed);} 7794192Sktlim@umich.edu 7804192Sktlim@umich.edu /** Returns whether or not this instruction is squashed in the IQ. */ 7814192Sktlim@umich.edu bool isSquashedInIQ() const { return status[SquashedInIQ]; } 7824192Sktlim@umich.edu 7834192Sktlim@umich.edu 7844192Sktlim@umich.edu //Load / Store Queue Functions 7854192Sktlim@umich.edu //----------------------- 7864192Sktlim@umich.edu /** Sets this instruction as a entry the LSQ. */ 7874192Sktlim@umich.edu void setInLSQ() { status.set(LsqEntry); } 7884192Sktlim@umich.edu 7894192Sktlim@umich.edu /** Sets this instruction as a entry the LSQ. */ 7901060SN/A void removeInLSQ() { status.reset(LsqEntry); } 7912852Sktlim@umich.edu 7922864Sktlim@umich.edu /** Returns whether or not this instruction is in the LSQ. */ 7932864Sktlim@umich.edu bool isInLSQ() const { return status[LsqEntry]; } 7942918Sktlim@umich.edu 7952918Sktlim@umich.edu /** Sets this instruction as squashed in the LSQ. */ 7962864Sktlim@umich.edu void setSquashedInLSQ() { status.set(SquashedInLSQ);} 7972864Sktlim@umich.edu 7982864Sktlim@umich.edu /** Returns whether or not this instruction is squashed in the LSQ. */ 7992864Sktlim@umich.edu bool isSquashedInLSQ() const { return status[SquashedInLSQ]; } 8002864Sktlim@umich.edu 8012864Sktlim@umich.edu 8022864Sktlim@umich.edu //Reorder Buffer Functions 8032864Sktlim@umich.edu //----------------------- 8042864Sktlim@umich.edu /** Sets this instruction as a entry the ROB. */ 8052864Sktlim@umich.edu void setInROB() { status.set(RobEntry); } 8062864Sktlim@umich.edu 8072864Sktlim@umich.edu /** Sets this instruction as a entry the ROB. */ 8082864Sktlim@umich.edu void clearInROB() { status.reset(RobEntry); } 8092864Sktlim@umich.edu 8102864Sktlim@umich.edu /** Returns whether or not this instruction is in the ROB. */ 8112864Sktlim@umich.edu bool isInROB() const { return status[RobEntry]; } 8122864Sktlim@umich.edu 8132864Sktlim@umich.edu /** Sets this instruction as squashed in the ROB. */ 8142864Sktlim@umich.edu void setSquashedInROB() { status.set(SquashedInROB); } 8152864Sktlim@umich.edu 8162918Sktlim@umich.edu /** Returns whether or not this instruction is squashed in the ROB. */ 8172918Sktlim@umich.edu bool isSquashedInROB() const { return status[SquashedInROB]; } 8182864Sktlim@umich.edu 8192864Sktlim@umich.edu /** Read the PC state of this instruction. */ 8202864Sktlim@umich.edu TheISA::PCState pcState() const { return pc; } 8212864Sktlim@umich.edu 8222864Sktlim@umich.edu /** Set the PC state of this instruction. */ 8232864Sktlim@umich.edu void pcState(const TheISA::PCState &val) { pc = val; } 8242864Sktlim@umich.edu 8252864Sktlim@umich.edu /** Read the PC of this instruction. */ 8262864Sktlim@umich.edu Addr instAddr() const { return pc.instAddr(); } 8272864Sktlim@umich.edu 8282864Sktlim@umich.edu /** Read the PC of the next instruction. */ 8292864Sktlim@umich.edu Addr nextInstAddr() const { return pc.nextInstAddr(); } 8302864Sktlim@umich.edu 8312864Sktlim@umich.edu /**Read the micro PC of this instruction. */ 8322864Sktlim@umich.edu Addr microPC() const { return pc.microPC(); } 8332864Sktlim@umich.edu 8342905Sktlim@umich.edu bool readPredicate() 8352843Sktlim@umich.edu { 8361060SN/A return instFlags[Predicate]; 8373125Sktlim@umich.edu } 8383512Sktlim@umich.edu 8393512Sktlim@umich.edu void setPredicate(bool val) 8403512Sktlim@umich.edu { 8413512Sktlim@umich.edu instFlags[Predicate] = val; 8423512Sktlim@umich.edu 8433512Sktlim@umich.edu if (traceData) { 8442843Sktlim@umich.edu traceData->setPredicate(val); 8452843Sktlim@umich.edu } 8462843Sktlim@umich.edu } 8472843Sktlim@umich.edu 8482843Sktlim@umich.edu /** Sets the ASID. */ 8492843Sktlim@umich.edu void setASID(short addr_space_id) { asid = addr_space_id; } 8502325SN/A 8512325SN/A /** Sets the thread id. */ 8522863Sktlim@umich.edu void setTid(ThreadID tid) { threadNumber = tid; } 8532905Sktlim@umich.edu 8542864Sktlim@umich.edu /** Sets the pointer to the thread state. */ 8552864Sktlim@umich.edu void setThreadState(ImplState *state) { thread = state; } 8562864Sktlim@umich.edu 8572864Sktlim@umich.edu /** Returns the thread context. */ 8582864Sktlim@umich.edu ThreadContext *tcBase() { return thread->getTC(); } 8592843Sktlim@umich.edu 8602863Sktlim@umich.edu public: 8612863Sktlim@umich.edu /** Sets the effective address. */ 8622852Sktlim@umich.edu void setEA(Addr ea) { instEffAddr = ea; instFlags[EACalcDone] = true; } 8632905Sktlim@umich.edu 8642863Sktlim@umich.edu /** Returns the effective address. */ 8652905Sktlim@umich.edu Addr getEA() const { return instEffAddr; } 8662863Sktlim@umich.edu 8672316SN/A /** Returns whether or not the eff. addr. calculation has been completed. */ 8682310SN/A bool doneEACalc() { return instFlags[EACalcDone]; } 8692316SN/A 8702316SN/A /** Returns whether or not the eff. addr. source registers are ready. */ 8712843Sktlim@umich.edu bool eaSrcsReady(); 8722316SN/A 8732843Sktlim@umich.edu /** Is this instruction's memory access strictly ordered? */ 8742843Sktlim@umich.edu bool strictlyOrdered() const { return instFlags[IsStrictlyOrdered]; } 8752843Sktlim@umich.edu 8762843Sktlim@umich.edu /** Has this instruction generated a memory request. */ 8772843Sktlim@umich.edu bool hasRequest() { return instFlags[ReqMade]; } 8782316SN/A 8792905Sktlim@umich.edu /** Returns iterator to this instruction in the list of all insts. */ 8802905Sktlim@umich.edu ListIt &getInstListIt() { return instListIt; } 8812864Sktlim@umich.edu 8822864Sktlim@umich.edu /** Sets iterator for this instruction in the list of all insts. */ 8832864Sktlim@umich.edu void setInstListIt(ListIt _instListIt) { instListIt = _instListIt; } 8843319Shsul@eecs.umich.edu 8853319Shsul@eecs.umich.edu public: 8863319Shsul@eecs.umich.edu /** Returns the number of consecutive store conditional failures. */ 8873319Shsul@eecs.umich.edu unsigned int readStCondFailures() const 8882843Sktlim@umich.edu { return thread->storeCondFailures; } 8894030Sktlim@umich.edu 8902843Sktlim@umich.edu /** Sets the number of consecutive store conditional failures. */ 8912843Sktlim@umich.edu void setStCondFailures(unsigned int sc_failures) 8922316SN/A { thread->storeCondFailures = sc_failures; } 8932843Sktlim@umich.edu 8942843Sktlim@umich.edu public: 8952843Sktlim@umich.edu // monitor/mwait funtions 8962843Sktlim@umich.edu void armMonitor(Addr address) { cpu->armMonitor(threadNumber, address); } 8972843Sktlim@umich.edu bool mwait(PacketPtr pkt) { return cpu->mwait(threadNumber, pkt); } 8982316SN/A void mwaitAtomic(ThreadContext *tc) 8992316SN/A { return cpu->mwaitAtomic(threadNumber, tc, cpu->dtb); } 9002863Sktlim@umich.edu AddressMonitor *getAddrMonitor() 9012905Sktlim@umich.edu { return cpu->getCpuAddrMonitor(threadNumber); } 9022863Sktlim@umich.edu}; 9033126Sktlim@umich.edu 9043126Sktlim@umich.edutemplate<class Impl> 9052863Sktlim@umich.eduFault 9062863Sktlim@umich.eduBaseDynInst<Impl>::initiateMemRead(Addr addr, unsigned size, 9072863Sktlim@umich.edu Request::Flags flags) 9082863Sktlim@umich.edu{ 9092310SN/A instFlags[ReqMade] = true; 9102843Sktlim@umich.edu Request *req = NULL; 9112843Sktlim@umich.edu Request *sreqLow = NULL; 9122843Sktlim@umich.edu Request *sreqHigh = NULL; 9132843Sktlim@umich.edu 9142843Sktlim@umich.edu if (instFlags[ReqMade] && translationStarted()) { 9152843Sktlim@umich.edu req = savedReq; 9162843Sktlim@umich.edu sreqLow = savedSreqLow; 9172843Sktlim@umich.edu sreqHigh = savedSreqHigh; 9182843Sktlim@umich.edu } else { 9192325SN/A req = new Request(asid, addr, size, flags, masterId(), this->pc.instAddr(), 9202843Sktlim@umich.edu thread->contextId()); 9212843Sktlim@umich.edu 9222843Sktlim@umich.edu req->taskId(cpu->taskId()); 9232843Sktlim@umich.edu 9242843Sktlim@umich.edu // Only split the request if the ISA supports unaligned accesses. 9252843Sktlim@umich.edu if (TheISA::HasUnalignedMemAcc) { 9262843Sktlim@umich.edu splitRequest(req, sreqLow, sreqHigh); 9272843Sktlim@umich.edu } 9282843Sktlim@umich.edu initiateTranslation(req, sreqLow, sreqHigh, NULL, BaseTLB::Read); 9292843Sktlim@umich.edu } 9302843Sktlim@umich.edu 9313126Sktlim@umich.edu if (translationCompleted()) { 9323126Sktlim@umich.edu if (fault == NoFault) { 9331060SN/A effAddr = req->getVaddr(); 9341060SN/A effSize = size; 9351060SN/A instFlags[EffAddrValid] = true; 9361060SN/A 9371755SN/A if (cpu->checker) { 9381060SN/A if (reqToVerify != NULL) { 9392325SN/A delete reqToVerify; 9402873Sktlim@umich.edu } 9412307SN/A reqToVerify = new Request(*req); 9422307SN/A } 9432307SN/A fault = cpu->read(req, sreqLow, sreqHigh, lqIdx); 9442307SN/A } else { 9452307SN/A // Commit will have to clean up whatever happened. Set this 9462307SN/A // instruction as executed. 9472307SN/A this->setExecuted(); 9482325SN/A } 9492307SN/A } 9504192Sktlim@umich.edu 9511060SN/A if (traceData) 9522307SN/A traceData->setMem(addr, size, flags); 9532307SN/A 9542307SN/A return fault; 9552307SN/A} 9562307SN/A 9572307SN/Atemplate<class Impl> 9581060SN/AFault 9591060SN/ABaseDynInst<Impl>::writeMem(uint8_t *data, unsigned size, Addr addr, 9602325SN/A Request::Flags flags, uint64_t *res) 9612325SN/A{ 9622307SN/A if (traceData) 9632307SN/A traceData->setMem(addr, size, flags); 9642307SN/A 9652307SN/A instFlags[ReqMade] = true; 9662307SN/A Request *req = NULL; 9672307SN/A Request *sreqLow = NULL; 9682325SN/A Request *sreqHigh = NULL; 9692325SN/A 9702733Sktlim@umich.edu if (instFlags[ReqMade] && translationStarted()) { 9712307SN/A req = savedReq; 9722307SN/A sreqLow = savedSreqLow; 9732307SN/A sreqHigh = savedSreqHigh; 9742307SN/A } else { 9752307SN/A req = new Request(asid, addr, size, flags, masterId(), this->pc.instAddr(), 9762325SN/A thread->contextId()); 9772307SN/A 9782680Sktlim@umich.edu req->taskId(cpu->taskId()); 9792680Sktlim@umich.edu 9802680Sktlim@umich.edu // Only split the request if the ISA supports unaligned accesses. 9811681SN/A if (TheISA::HasUnalignedMemAcc) { 9824030Sktlim@umich.edu splitRequest(req, sreqLow, sreqHigh); 9831681SN/A } 9841060SN/A initiateTranslation(req, sreqLow, sreqHigh, res, BaseTLB::Write); 9852307SN/A } 9864030Sktlim@umich.edu 9871060SN/A if (fault == NoFault && translationCompleted()) { 9881060SN/A effAddr = req->getVaddr(); 9891060SN/A effSize = size; 9901060SN/A instFlags[EffAddrValid] = true; 9911755SN/A 9921060SN/A if (cpu->checker) { 9931060SN/A if (reqToVerify != NULL) { 9941060SN/A delete reqToVerify; 9951060SN/A } 9961060SN/A reqToVerify = new Request(*req); 9972455SN/A } 9982455SN/A fault = cpu->write(req, sreqLow, sreqHigh, data, sqIdx); 9991060SN/A } 10002455SN/A 10011060SN/A return fault; 10021060SN/A} 10031060SN/A 10042455SN/Atemplate<class Impl> 10052455SN/Ainline void 10061060SN/ABaseDynInst<Impl>::splitRequest(RequestPtr req, RequestPtr &sreqLow, 10072455SN/A RequestPtr &sreqHigh) 10081060SN/A{ 10091060SN/A // Check to see if the request crosses the next level block boundary. 10101060SN/A unsigned block_size = cpu->cacheLineSize(); 10112455SN/A Addr addr = req->getVaddr(); 10122455SN/A Addr split_addr = roundDown(addr + req->getSize() - 1, block_size); 10131060SN/A assert(split_addr <= addr || split_addr - addr < block_size); 10142455SN/A 10152455SN/A // Spans two blocks. 10162455SN/A if (split_addr > addr) { 10172455SN/A req->splitOnVaddr(split_addr, sreqLow, sreqHigh); 10182455SN/A } 10192455SN/A} 10202455SN/A 10212455SN/Atemplate<class Impl> 10221060SN/Ainline void 10231060SN/ABaseDynInst<Impl>::initiateTranslation(RequestPtr req, RequestPtr sreqLow, 10241060SN/A RequestPtr sreqHigh, uint64_t *res, 10251060SN/A BaseTLB::Mode mode) 10261755SN/A{ 10271060SN/A translationStarted(true); 10281060SN/A 10291060SN/A if (!TheISA::HasUnalignedMemAcc || sreqLow == NULL) { 10301060SN/A WholeTranslationState *state = 10311060SN/A new WholeTranslationState(req, NULL, res, mode); 10321060SN/A 10332455SN/A // One translation if the request isn't split. 10341060SN/A DataTranslation<BaseDynInstPtr> *trans = 10352455SN/A new DataTranslation<BaseDynInstPtr>(this, state); 10361060SN/A 10371060SN/A cpu->dtb->translateTiming(req, thread->getTC(), trans, mode); 10381060SN/A 10391060SN/A if (!translationCompleted()) { 10402455SN/A // The translation isn't yet complete, so we can't possibly have a 10411060SN/A // fault. Overwrite any existing fault we might have from a previous 10422455SN/A // execution of this instruction (e.g. an uncachable load that 10431060SN/A // couldn't execute because it wasn't at the head of the ROB). 10441060SN/A fault = NoFault; 10451060SN/A 10461060SN/A // Save memory requests. 10472455SN/A savedReq = state->mainReq; 10481060SN/A savedSreqLow = state->sreqLow; 10492455SN/A savedSreqHigh = state->sreqHigh; 10502455SN/A } 10512455SN/A } else { 10522455SN/A WholeTranslationState *state = 10532455SN/A new WholeTranslationState(req, sreqLow, sreqHigh, NULL, res, mode); 10542455SN/A 10552455SN/A // Two translations when the request is split. 10562455SN/A DataTranslation<BaseDynInstPtr> *stransLow = 10571060SN/A new DataTranslation<BaseDynInstPtr>(this, state, 0); 10581060SN/A DataTranslation<BaseDynInstPtr> *stransHigh = 10591060SN/A new DataTranslation<BaseDynInstPtr>(this, state, 1); 10601060SN/A 10612292SN/A cpu->dtb->translateTiming(sreqLow, thread->getTC(), stransLow, mode); 10621060SN/A cpu->dtb->translateTiming(sreqHigh, thread->getTC(), stransHigh, mode); 10632292SN/A 10642292SN/A if (!translationCompleted()) { 10652292SN/A // The translation isn't yet complete, so we can't possibly have a 10662292SN/A // fault. Overwrite any existing fault we might have from a previous 10672292SN/A // execution of this instruction (e.g. an uncachable load that 10682292SN/A // couldn't execute because it wasn't at the head of the ROB). 10692292SN/A fault = NoFault; 10702292SN/A 10712292SN/A // Save memory requests. 10722307SN/A savedReq = state->mainReq; 10732307SN/A savedSreqLow = state->sreqLow; 10742292SN/A savedSreqHigh = state->sreqHigh; 10752669Sktlim@umich.edu } 10762292SN/A } 10772292SN/A} 10782292SN/A 10792292SN/Atemplate<class Impl> 10802292SN/Ainline void 10812292SN/ABaseDynInst<Impl>::finishTranslation(WholeTranslationState *state) 10822307SN/A{ 10832307SN/A fault = state->getFault(); 10842292SN/A 10852669Sktlim@umich.edu instFlags[IsStrictlyOrdered] = state->isStrictlyOrdered(); 10862292SN/A 10872292SN/A if (fault == NoFault) { 10882292SN/A // save Paddr for a single req 10892292SN/A physEffAddrLow = state->getPaddr(); 10902292SN/A 10912292SN/A // case for the request that has been split 10922307SN/A if (state->isSplit) { 10932307SN/A physEffAddrLow = state->sreqLow->getPaddr(); 10942292SN/A physEffAddrHigh = state->sreqHigh->getPaddr(); 10952669Sktlim@umich.edu } 10961060SN/A 10971060SN/A memReqFlags = state->getFlags(); 10981060SN/A 10991060SN/A if (state->mainReq->isCondSwap()) { 11002292SN/A assert(state->res); 11011060SN/A state->mainReq->setExtraData(*state->res); 11022292SN/A } 11032292SN/A 11042292SN/A } else { 11051060SN/A state->deleteReqs(); 11061060SN/A } 11071060SN/A delete state; 11081060SN/A 11092292SN/A translationCompleted(true); 11101060SN/A} 11112918Sktlim@umich.edu 11122918Sktlim@umich.edu#endif // __CPU_BASE_DYN_INST_HH__ 11132292SN/A