registers.hh revision 12104
12914Ssaidi@eecs.umich.edu/*
28856Sandreas.hansson@arm.com * Copyright (c) 2007 The Hewlett-Packard Development Company
38856Sandreas.hansson@arm.com * Copyright (c) 2013 Advanced Micro Devices, Inc.
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372914Ssaidi@eecs.umich.edu *
382914Ssaidi@eecs.umich.edu * Authors: Gabe Black
392914Ssaidi@eecs.umich.edu */
402914Ssaidi@eecs.umich.edu
418856Sandreas.hansson@arm.com#ifndef __ARCH_X86_REGISTERS_HH__
422914Ssaidi@eecs.umich.edu#define __ARCH_X86_REGISTERS_HH__
432914Ssaidi@eecs.umich.edu
443091Sstever@eecs.umich.edu#include "arch/x86/generated/max_inst_regs.hh"
453091Sstever@eecs.umich.edu#include "arch/x86/regs/int.hh"
463091Sstever@eecs.umich.edu#include "arch/x86/regs/ccr.hh"
472914Ssaidi@eecs.umich.edu#include "arch/x86/regs/misc.hh"
482914Ssaidi@eecs.umich.edu#include "arch/x86/x86_traits.hh"
493091Sstever@eecs.umich.edu
503091Sstever@eecs.umich.edunamespace X86ISA
512914Ssaidi@eecs.umich.edu{
522914Ssaidi@eecs.umich.eduusing X86ISAInst::MaxInstSrcRegs;
538229Snate@binkert.orgusing X86ISAInst::MaxInstDestRegs;
548229Snate@binkert.orgusing X86ISAInst::MaxMiscDestRegs;
558229Snate@binkert.orgconst int NumMiscRegs = NUM_MISCREGS;
562914Ssaidi@eecs.umich.edu
572914Ssaidi@eecs.umich.educonst int NumIntArchRegs = NUM_INTREGS;
582914Ssaidi@eecs.umich.educonst int NumIntRegs = NumIntArchRegs + NumMicroIntRegs + NumImplicitIntRegs;
593091Sstever@eecs.umich.educonst int NumCCRegs = NUM_CCREGS;
603091Sstever@eecs.umich.edu
613091Sstever@eecs.umich.edu#define ISA_HAS_CC_REGS
623091Sstever@eecs.umich.edu
633091Sstever@eecs.umich.edu// Each 128 bit xmm register is broken into two effective 64 bit registers.
643091Sstever@eecs.umich.edu// Add 8 for the indices that are mapped over the fp stack
653091Sstever@eecs.umich.educonst int NumFloatRegs =
663091Sstever@eecs.umich.edu    NumMMXRegs + 2 * NumXMMRegs + NumMicroFpRegs + 8;
673091Sstever@eecs.umich.edu
683091Sstever@eecs.umich.edu// These enumerate all the registers for dependence tracking.
693091Sstever@eecs.umich.eduenum DependenceTags {
703091Sstever@eecs.umich.edu    // FP_Reg_Base must be large enough to be bigger than any integer
713091Sstever@eecs.umich.edu    // register index which has the IntFoldBit (1 << 6) set.  To be safe
722914Ssaidi@eecs.umich.edu    // we just start at (1 << 7) == 128.
732914Ssaidi@eecs.umich.edu    FP_Reg_Base = 128,
742914Ssaidi@eecs.umich.edu    CC_Reg_Base = FP_Reg_Base + NumFloatRegs,
754490Sstever@eecs.umich.edu    Misc_Reg_Base = CC_Reg_Base + NumCCRegs,
764490Sstever@eecs.umich.edu    Max_Reg_Index = Misc_Reg_Base + NumMiscRegs
774490Sstever@eecs.umich.edu};
784490Sstever@eecs.umich.edu
794490Sstever@eecs.umich.edu// semantically meaningful register indices
804490Sstever@eecs.umich.edu//There is no such register in X86
814490Sstever@eecs.umich.educonst int ZeroReg = NUM_INTREGS;
824490Sstever@eecs.umich.educonst int StackPointerReg = INTREG_RSP;
834490Sstever@eecs.umich.edu//X86 doesn't seem to have a link register
844490Sstever@eecs.umich.educonst int ReturnAddressReg = 0;
854490Sstever@eecs.umich.educonst int ReturnValueReg = INTREG_RAX;
864490Sstever@eecs.umich.educonst int FramePointerReg = INTREG_RBP;
874490Sstever@eecs.umich.edu
883090Sstever@eecs.umich.edu// Some OS syscalls use a second register (rdx) to return a second
893090Sstever@eecs.umich.edu// value
904490Sstever@eecs.umich.educonst int SyscallPseudoReturnReg = INTREG_RDX;
914490Sstever@eecs.umich.edu
928856Sandreas.hansson@arm.comtypedef uint64_t IntReg;
938856Sandreas.hansson@arm.comtypedef uint64_t CCReg;
948856Sandreas.hansson@arm.comtypedef uint64_t MiscReg;
954490Sstever@eecs.umich.edu
964490Sstever@eecs.umich.edu//These floating point types are correct for mmx, but not
974490Sstever@eecs.umich.edu//technically for x87 (80 bits) or at all for xmm (128 bits)
983091Sstever@eecs.umich.edutypedef double FloatReg;
992914Ssaidi@eecs.umich.edutypedef uint64_t FloatRegBits;
1003090Sstever@eecs.umich.edutypedef union
1013403Ssaidi@eecs.umich.edu{
1023403Ssaidi@eecs.umich.edu    IntReg intReg;
1033403Ssaidi@eecs.umich.edu    FloatReg fpReg;
1043403Ssaidi@eecs.umich.edu    CCReg ccReg;
1058856Sandreas.hansson@arm.com    MiscReg ctrlReg;
1068856Sandreas.hansson@arm.com} AnyReg;
1072914Ssaidi@eecs.umich.edu
1082914Ssaidi@eecs.umich.edu} // namespace X86ISA
1092914Ssaidi@eecs.umich.edu
1102914Ssaidi@eecs.umich.edu#endif // __ARCH_X86_REGFILE_HH__
1112914Ssaidi@eecs.umich.edu