registers.hh revision 12104
12914Ssaidi@eecs.umich.edu/* 28856Sandreas.hansson@arm.com * Copyright (c) 2007 The Hewlett-Packard Development Company 38856Sandreas.hansson@arm.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 48856Sandreas.hansson@arm.com * All rights reserved. 58856Sandreas.hansson@arm.com * 68856Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 78856Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 88856Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 98856Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 108856Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 118856Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 128856Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 138856Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 142914Ssaidi@eecs.umich.edu * 152914Ssaidi@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 162914Ssaidi@eecs.umich.edu * modification, are permitted provided that the following conditions are 172914Ssaidi@eecs.umich.edu * met: redistributions of source code must retain the above copyright 182914Ssaidi@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 192914Ssaidi@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 202914Ssaidi@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 212914Ssaidi@eecs.umich.edu * documentation and/or other materials provided with the distribution; 222914Ssaidi@eecs.umich.edu * neither the name of the copyright holders nor the names of its 232914Ssaidi@eecs.umich.edu * contributors may be used to endorse or promote products derived from 242914Ssaidi@eecs.umich.edu * this software without specific prior written permission. 252914Ssaidi@eecs.umich.edu * 262914Ssaidi@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 272914Ssaidi@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 282914Ssaidi@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 292914Ssaidi@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 302914Ssaidi@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 312914Ssaidi@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 322914Ssaidi@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 332914Ssaidi@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 342914Ssaidi@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 352914Ssaidi@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 362914Ssaidi@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 372914Ssaidi@eecs.umich.edu * 382914Ssaidi@eecs.umich.edu * Authors: Gabe Black 392914Ssaidi@eecs.umich.edu */ 402914Ssaidi@eecs.umich.edu 418856Sandreas.hansson@arm.com#ifndef __ARCH_X86_REGISTERS_HH__ 422914Ssaidi@eecs.umich.edu#define __ARCH_X86_REGISTERS_HH__ 432914Ssaidi@eecs.umich.edu 443091Sstever@eecs.umich.edu#include "arch/x86/generated/max_inst_regs.hh" 453091Sstever@eecs.umich.edu#include "arch/x86/regs/int.hh" 463091Sstever@eecs.umich.edu#include "arch/x86/regs/ccr.hh" 472914Ssaidi@eecs.umich.edu#include "arch/x86/regs/misc.hh" 482914Ssaidi@eecs.umich.edu#include "arch/x86/x86_traits.hh" 493091Sstever@eecs.umich.edu 503091Sstever@eecs.umich.edunamespace X86ISA 512914Ssaidi@eecs.umich.edu{ 522914Ssaidi@eecs.umich.eduusing X86ISAInst::MaxInstSrcRegs; 538229Snate@binkert.orgusing X86ISAInst::MaxInstDestRegs; 548229Snate@binkert.orgusing X86ISAInst::MaxMiscDestRegs; 558229Snate@binkert.orgconst int NumMiscRegs = NUM_MISCREGS; 562914Ssaidi@eecs.umich.edu 572914Ssaidi@eecs.umich.educonst int NumIntArchRegs = NUM_INTREGS; 582914Ssaidi@eecs.umich.educonst int NumIntRegs = NumIntArchRegs + NumMicroIntRegs + NumImplicitIntRegs; 593091Sstever@eecs.umich.educonst int NumCCRegs = NUM_CCREGS; 603091Sstever@eecs.umich.edu 613091Sstever@eecs.umich.edu#define ISA_HAS_CC_REGS 623091Sstever@eecs.umich.edu 633091Sstever@eecs.umich.edu// Each 128 bit xmm register is broken into two effective 64 bit registers. 643091Sstever@eecs.umich.edu// Add 8 for the indices that are mapped over the fp stack 653091Sstever@eecs.umich.educonst int NumFloatRegs = 663091Sstever@eecs.umich.edu NumMMXRegs + 2 * NumXMMRegs + NumMicroFpRegs + 8; 673091Sstever@eecs.umich.edu 683091Sstever@eecs.umich.edu// These enumerate all the registers for dependence tracking. 693091Sstever@eecs.umich.eduenum DependenceTags { 703091Sstever@eecs.umich.edu // FP_Reg_Base must be large enough to be bigger than any integer 713091Sstever@eecs.umich.edu // register index which has the IntFoldBit (1 << 6) set. To be safe 722914Ssaidi@eecs.umich.edu // we just start at (1 << 7) == 128. 732914Ssaidi@eecs.umich.edu FP_Reg_Base = 128, 742914Ssaidi@eecs.umich.edu CC_Reg_Base = FP_Reg_Base + NumFloatRegs, 754490Sstever@eecs.umich.edu Misc_Reg_Base = CC_Reg_Base + NumCCRegs, 764490Sstever@eecs.umich.edu Max_Reg_Index = Misc_Reg_Base + NumMiscRegs 774490Sstever@eecs.umich.edu}; 784490Sstever@eecs.umich.edu 794490Sstever@eecs.umich.edu// semantically meaningful register indices 804490Sstever@eecs.umich.edu//There is no such register in X86 814490Sstever@eecs.umich.educonst int ZeroReg = NUM_INTREGS; 824490Sstever@eecs.umich.educonst int StackPointerReg = INTREG_RSP; 834490Sstever@eecs.umich.edu//X86 doesn't seem to have a link register 844490Sstever@eecs.umich.educonst int ReturnAddressReg = 0; 854490Sstever@eecs.umich.educonst int ReturnValueReg = INTREG_RAX; 864490Sstever@eecs.umich.educonst int FramePointerReg = INTREG_RBP; 874490Sstever@eecs.umich.edu 883090Sstever@eecs.umich.edu// Some OS syscalls use a second register (rdx) to return a second 893090Sstever@eecs.umich.edu// value 904490Sstever@eecs.umich.educonst int SyscallPseudoReturnReg = INTREG_RDX; 914490Sstever@eecs.umich.edu 928856Sandreas.hansson@arm.comtypedef uint64_t IntReg; 938856Sandreas.hansson@arm.comtypedef uint64_t CCReg; 948856Sandreas.hansson@arm.comtypedef uint64_t MiscReg; 954490Sstever@eecs.umich.edu 964490Sstever@eecs.umich.edu//These floating point types are correct for mmx, but not 974490Sstever@eecs.umich.edu//technically for x87 (80 bits) or at all for xmm (128 bits) 983091Sstever@eecs.umich.edutypedef double FloatReg; 992914Ssaidi@eecs.umich.edutypedef uint64_t FloatRegBits; 1003090Sstever@eecs.umich.edutypedef union 1013403Ssaidi@eecs.umich.edu{ 1023403Ssaidi@eecs.umich.edu IntReg intReg; 1033403Ssaidi@eecs.umich.edu FloatReg fpReg; 1043403Ssaidi@eecs.umich.edu CCReg ccReg; 1058856Sandreas.hansson@arm.com MiscReg ctrlReg; 1068856Sandreas.hansson@arm.com} AnyReg; 1072914Ssaidi@eecs.umich.edu 1082914Ssaidi@eecs.umich.edu} // namespace X86ISA 1092914Ssaidi@eecs.umich.edu 1102914Ssaidi@eecs.umich.edu#endif // __ARCH_X86_REGFILE_HH__ 1112914Ssaidi@eecs.umich.edu