registers.hh revision 12109
14120SN/A/*
24120SN/A * Copyright (c) 2007 The Hewlett-Packard Development Company
39917Ssteve.reinhardt@amd.com * Copyright (c) 2013 Advanced Micro Devices, Inc.
44120SN/A * All rights reserved.
54120SN/A *
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144120SN/A *
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374120SN/A *
384120SN/A * Authors: Gabe Black
394120SN/A */
404120SN/A
416329Sgblack@eecs.umich.edu#ifndef __ARCH_X86_REGISTERS_HH__
426329Sgblack@eecs.umich.edu#define __ARCH_X86_REGISTERS_HH__
436216SN/A
4412109SRekai.GonzalezAlberquilla@arm.com#include "arch/generic/vec_reg.hh"
458961Sgblack@eecs.umich.edu#include "arch/x86/generated/max_inst_regs.hh"
467629Sgblack@eecs.umich.edu#include "arch/x86/regs/int.hh"
479921Syasuko.eckert@amd.com#include "arch/x86/regs/ccr.hh"
487629Sgblack@eecs.umich.edu#include "arch/x86/regs/misc.hh"
496315SN/A#include "arch/x86/x86_traits.hh"
504137SN/A
514120SN/Anamespace X86ISA
524120SN/A{
536329Sgblack@eecs.umich.eduusing X86ISAInst::MaxInstSrcRegs;
546329Sgblack@eecs.umich.eduusing X86ISAInst::MaxInstDestRegs;
559046SAli.Saidi@ARM.comusing X86ISAInst::MaxMiscDestRegs;
566329Sgblack@eecs.umich.educonst int NumMiscRegs = NUM_MISCREGS;
576313SN/A
586329Sgblack@eecs.umich.educonst int NumIntArchRegs = NUM_INTREGS;
599921Syasuko.eckert@amd.comconst int NumIntRegs = NumIntArchRegs + NumMicroIntRegs + NumImplicitIntRegs;
609921Syasuko.eckert@amd.comconst int NumCCRegs = NUM_CCREGS;
619921Syasuko.eckert@amd.com
629921Syasuko.eckert@amd.com#define ISA_HAS_CC_REGS
636319SN/A
649917Ssteve.reinhardt@amd.com// Each 128 bit xmm register is broken into two effective 64 bit registers.
659917Ssteve.reinhardt@amd.com// Add 8 for the indices that are mapped over the fp stack
666329Sgblack@eecs.umich.educonst int NumFloatRegs =
679917Ssteve.reinhardt@amd.com    NumMMXRegs + 2 * NumXMMRegs + NumMicroFpRegs + 8;
686315SN/A
696329Sgblack@eecs.umich.edu// These enumerate all the registers for dependence tracking.
706329Sgblack@eecs.umich.eduenum DependenceTags {
719918Ssteve.reinhardt@amd.com    // FP_Reg_Base must be large enough to be bigger than any integer
729917Ssteve.reinhardt@amd.com    // register index which has the IntFoldBit (1 << 6) set.  To be safe
739917Ssteve.reinhardt@amd.com    // we just start at (1 << 7) == 128.
749918Ssteve.reinhardt@amd.com    FP_Reg_Base = 128,
759920Syasuko.eckert@amd.com    CC_Reg_Base = FP_Reg_Base + NumFloatRegs,
7610935Snilay@cs.wisc.edu    Misc_Reg_Base = CC_Reg_Base + NumCCRegs,
779918Ssteve.reinhardt@amd.com    Max_Reg_Index = Misc_Reg_Base + NumMiscRegs
786329Sgblack@eecs.umich.edu};
794137SN/A
806329Sgblack@eecs.umich.edu// semantically meaningful register indices
816329Sgblack@eecs.umich.edu//There is no such register in X86
826329Sgblack@eecs.umich.educonst int ZeroReg = NUM_INTREGS;
836329Sgblack@eecs.umich.educonst int StackPointerReg = INTREG_RSP;
846329Sgblack@eecs.umich.edu//X86 doesn't seem to have a link register
856329Sgblack@eecs.umich.educonst int ReturnAddressReg = 0;
866329Sgblack@eecs.umich.educonst int ReturnValueReg = INTREG_RAX;
876329Sgblack@eecs.umich.educonst int FramePointerReg = INTREG_RBP;
884137SN/A
896329Sgblack@eecs.umich.edu// Some OS syscalls use a second register (rdx) to return a second
906329Sgblack@eecs.umich.edu// value
916329Sgblack@eecs.umich.educonst int SyscallPseudoReturnReg = INTREG_RDX;
926329Sgblack@eecs.umich.edu
936329Sgblack@eecs.umich.edutypedef uint64_t IntReg;
949920Syasuko.eckert@amd.comtypedef uint64_t CCReg;
956329Sgblack@eecs.umich.edutypedef uint64_t MiscReg;
966329Sgblack@eecs.umich.edu
9712109SRekai.GonzalezAlberquilla@arm.com// dummy typedefs since we don't have vector regs
9812109SRekai.GonzalezAlberquilla@arm.comconstexpr unsigned NumVecElemPerVecReg = 2;
9912109SRekai.GonzalezAlberquilla@arm.comusing VecElem = uint32_t;
10012109SRekai.GonzalezAlberquilla@arm.comusing VecReg = ::VecRegT<VecElem, NumVecElemPerVecReg, false>;
10112109SRekai.GonzalezAlberquilla@arm.comusing ConstVecReg = ::VecRegT<VecElem, NumVecElemPerVecReg, true>;
10212109SRekai.GonzalezAlberquilla@arm.comusing VecRegContainer = VecReg::Container;
10312109SRekai.GonzalezAlberquilla@arm.com// This has to be one to prevent warnings that are treated as errors
10412109SRekai.GonzalezAlberquilla@arm.comconstexpr unsigned NumVecRegs = 1;
10512109SRekai.GonzalezAlberquilla@arm.com
1066329Sgblack@eecs.umich.edu//These floating point types are correct for mmx, but not
1076329Sgblack@eecs.umich.edu//technically for x87 (80 bits) or at all for xmm (128 bits)
1086329Sgblack@eecs.umich.edutypedef double FloatReg;
1096329Sgblack@eecs.umich.edutypedef uint64_t FloatRegBits;
1106329Sgblack@eecs.umich.edutypedef union
1116329Sgblack@eecs.umich.edu{
1126329Sgblack@eecs.umich.edu    IntReg intReg;
1136329Sgblack@eecs.umich.edu    FloatReg fpReg;
1149921Syasuko.eckert@amd.com    CCReg ccReg;
1156329Sgblack@eecs.umich.edu    MiscReg ctrlReg;
1166329Sgblack@eecs.umich.edu} AnyReg;
1176329Sgblack@eecs.umich.edu
1187811Ssteve.reinhardt@amd.com} // namespace X86ISA
1194120SN/A
1204120SN/A#endif // __ARCH_X86_REGFILE_HH__
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