mmapped_ipr.hh revision 8229:78bf55f23338 
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279384SAndreas.Sandberg@arm.com *
289384SAndreas.Sandberg@arm.com * Authors: Ali Saidi
299384SAndreas.Sandberg@arm.com */
309384SAndreas.Sandberg@arm.com
319384SAndreas.Sandberg@arm.com#ifndef __ARCH_SPARC_MMAPPED_IPR_HH__
329384SAndreas.Sandberg@arm.com#define __ARCH_SPARC_MMAPPED_IPR_HH__
339384SAndreas.Sandberg@arm.com
349384SAndreas.Sandberg@arm.com/**
359384SAndreas.Sandberg@arm.com * @file
369384SAndreas.Sandberg@arm.com *
379384SAndreas.Sandberg@arm.com * ISA-specific helper functions for memory mapped IPR accesses.
389384SAndreas.Sandberg@arm.com */
399384SAndreas.Sandberg@arm.com
409384SAndreas.Sandberg@arm.com#include "arch/sparc/tlb.hh"
419384SAndreas.Sandberg@arm.com#include "config/full_system.hh"
429384SAndreas.Sandberg@arm.com#include "cpu/thread_context.hh"
439384SAndreas.Sandberg@arm.com#include "mem/packet.hh"
449384SAndreas.Sandberg@arm.com
459384SAndreas.Sandberg@arm.comnamespace SparcISA
469384SAndreas.Sandberg@arm.com{
479384SAndreas.Sandberg@arm.com
489384SAndreas.Sandberg@arm.cominline Tick
499384SAndreas.Sandberg@arm.comhandleIprRead(ThreadContext *xc, Packet *pkt)
509384SAndreas.Sandberg@arm.com{
519384SAndreas.Sandberg@arm.com#if FULL_SYSTEM
529384SAndreas.Sandberg@arm.com    return xc->getDTBPtr()->doMmuRegRead(xc, pkt);
539384SAndreas.Sandberg@arm.com#else
549384SAndreas.Sandberg@arm.com    panic("Shouldn't have a memory mapped register in SE\n");
559384SAndreas.Sandberg@arm.com#endif
569384SAndreas.Sandberg@arm.com}
579384SAndreas.Sandberg@arm.com
589384SAndreas.Sandberg@arm.cominline Tick
599384SAndreas.Sandberg@arm.comhandleIprWrite(ThreadContext *xc, Packet *pkt)
609384SAndreas.Sandberg@arm.com{
619384SAndreas.Sandberg@arm.com#if FULL_SYSTEM
629384SAndreas.Sandberg@arm.com    return xc->getDTBPtr()->doMmuRegWrite(xc, pkt);
639384SAndreas.Sandberg@arm.com#else
649384SAndreas.Sandberg@arm.com    panic("Shouldn't have a memory mapped register in SE\n");
659384SAndreas.Sandberg@arm.com#endif
66}
67
68
69} // namespace SparcISA
70
71#endif
72