mmapped_ipr.hh revision 8105
16145Snate@binkert.org/*
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276145Snate@binkert.org *
286145Snate@binkert.org * Authors: Ali Saidi
297832Snate@binkert.org */
307547SBrad.Beckmann@amd.com
317547SBrad.Beckmann@amd.com#ifndef __ARCH_SPARC_MMAPPED_IPR_HH__
328645Snilay@cs.wisc.edu#define __ARCH_SPARC_MMAPPED_IPR_HH__
337454Snate@binkert.org
347054Snate@binkert.org/**
3510301Snilay@cs.wisc.edu * @file
368258SBrad.Beckmann@amd.com *
376154Snate@binkert.org * ISA-specific helper functions for memory mapped IPR accesses.
387054Snate@binkert.org */
397547SBrad.Beckmann@amd.com
406154Snate@binkert.org#include "config/full_system.hh"
416154Snate@binkert.org#include "cpu/thread_context.hh"
426145Snate@binkert.org#include "mem/packet.hh"
437055Snate@binkert.org#include "arch/sparc/tlb.hh"
447454Snate@binkert.org
457055Snate@binkert.org
466876Ssteve.reinhardt@amd.comnamespace SparcISA
476876Ssteve.reinhardt@amd.com{
486285Snate@binkert.org
498259SBrad.Beckmann@amd.cominline Tick
508259SBrad.Beckmann@amd.comhandleIprRead(ThreadContext *xc, Packet *pkt)
518259SBrad.Beckmann@amd.com{
528259SBrad.Beckmann@amd.com#if FULL_SYSTEM
537054Snate@binkert.org    return xc->getDTBPtr()->doMmuRegRead(xc, pkt);
547054Snate@binkert.org#else
557054Snate@binkert.org    panic("Shouldn't have a memory mapped register in SE\n");
567454Snate@binkert.org#endif
576285Snate@binkert.org}
589274Snilay@cs.wisc.edu
599593Snilay@cs.wisc.eduinline Tick
609593Snilay@cs.wisc.eduhandleIprWrite(ThreadContext *xc, Packet *pkt)
619274Snilay@cs.wisc.edu{
629858Snilay@cs.wisc.edu#if FULL_SYSTEM
639274Snilay@cs.wisc.edu    return xc->getDTBPtr()->doMmuRegWrite(xc, pkt);
649274Snilay@cs.wisc.edu#else
656881SBrad.Beckmann@amd.com    panic("Shouldn't have a memory mapped register in SE\n");
666285Snate@binkert.org#endif
677054Snate@binkert.org}
687054Snate@binkert.org
696881SBrad.Beckmann@amd.com
707054Snate@binkert.org} // namespace SparcISA
716881SBrad.Beckmann@amd.com
727054Snate@binkert.org#endif
737054Snate@binkert.org