isa_traits.hh revision 5222
12023SN/A/* 25222Sksewell@umich.edu * Copyright N) 2007 MIPS Technologies, Inc. All Rights Reserved 32023SN/A * 45222Sksewell@umich.edu * This software is part of the M5 simulator. 52023SN/A * 65222Sksewell@umich.edu * THIS IS A LEGAL AGREEMENT. BY DOWNLOADING, USING, COPYING, CREATING 75222Sksewell@umich.edu * DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING 85222Sksewell@umich.edu * TO THESE TERMS AND CONDITIONS. 92665Ssaidi@eecs.umich.edu * 105222Sksewell@umich.edu * Permission is granted to use, copy, create derivative works and 115222Sksewell@umich.edu * distribute this software and such derivative works for any purpose, 125222Sksewell@umich.edu * so long as (1) the copyright notice above, this grant of permission, 135222Sksewell@umich.edu * and the disclaimer below appear in all copies and derivative works 145222Sksewell@umich.edu * made, (2) the copyright notice above is augmented as appropriate to 155222Sksewell@umich.edu * reflect the addition of any new copyrightable work in a derivative 165222Sksewell@umich.edu * work (e.g., Copyright N) <Publication Year> Copyright Owner), and (3) 175222Sksewell@umich.edu * the name of MIPS Technologies, Inc. ($(B!H(BMIPS$(B!I(B) is not used in any 185222Sksewell@umich.edu * advertising or publicity pertaining to the use or distribution of 195222Sksewell@umich.edu * this software without specific, written prior authorization. 205222Sksewell@umich.edu * 215222Sksewell@umich.edu * THIS SOFTWARE IS PROVIDED $(B!H(BAS IS.$(B!I(B MIPS MAKES NO WARRANTIES AND 225222Sksewell@umich.edu * DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR 235222Sksewell@umich.edu * OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 245222Sksewell@umich.edu * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND 255222Sksewell@umich.edu * NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE. 265222Sksewell@umich.edu * IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT, 275222Sksewell@umich.edu * INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF 285222Sksewell@umich.edu * ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT, 295222Sksewell@umich.edu * THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY 305222Sksewell@umich.edu * IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR 315222Sksewell@umich.edu * STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE 325222Sksewell@umich.edu * POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE. 335222Sksewell@umich.edu * 345222Sksewell@umich.edu * Authors: Gabe M. Black 355222Sksewell@umich.edu * Korey L. Sewell 365222Sksewell@umich.edu * Jaidev Patwardhan 372023SN/A */ 382023SN/A 392028SN/A#ifndef __ARCH_MIPS_ISA_TRAITS_HH__ 402028SN/A#define __ARCH_MIPS_ISA_TRAITS_HH__ 412023SN/A 422597SN/A#include "arch/mips/types.hh" 435222Sksewell@umich.edu#include "config/full_system.hh" 442023SN/A#include "sim/host.hh" 452023SN/A 462239SN/Anamespace LittleEndianGuest {}; 472239SN/A 482028SN/A#define TARGET_MIPS 492023SN/A 502131SN/Aclass StaticInstPtr; 512023SN/A 522131SN/Anamespace MipsISA 532023SN/A{ 542525SN/A using namespace LittleEndianGuest; 552525SN/A 562447SN/A StaticInstPtr decodeInst(ExtMachInst); 572023SN/A 585222Sksewell@umich.edu // MIPS DOES have a delay slot 593093Sksewell@umich.edu #define ISA_HAS_DELAY_SLOT 1 603093Sksewell@umich.edu 612972Sgblack@eecs.umich.edu const Addr PageShift = 13; 622972Sgblack@eecs.umich.edu const Addr PageBytes = ULL(1) << PageShift; 635222Sksewell@umich.edu const Addr Page_Mask = ~(PageBytes - 1); 642972Sgblack@eecs.umich.edu const Addr PageOffset = PageBytes - 1; 652239SN/A 665222Sksewell@umich.edu 675222Sksewell@umich.edu //////////////////////////////////////////////////////////////////////// 685222Sksewell@umich.edu // 695222Sksewell@umich.edu // Translation stuff 705222Sksewell@umich.edu // 715222Sksewell@umich.edu 725222Sksewell@umich.edu const Addr PteShift = 3; 735222Sksewell@umich.edu const Addr NPtePageShift = PageShift - PteShift; 745222Sksewell@umich.edu const Addr NPtePage = ULL(1) << NPtePageShift; 755222Sksewell@umich.edu const Addr PteMask = NPtePage - 1; 765222Sksewell@umich.edu 775222Sksewell@umich.edu //// All 'Mapped' segments go through the TLB 785222Sksewell@umich.edu //// All other segments are translated by dropping the MSB, to give 795222Sksewell@umich.edu //// the corresponding physical address 805222Sksewell@umich.edu // User Segment - Mapped 815222Sksewell@umich.edu const Addr USegBase = ULL(0x0); 825222Sksewell@umich.edu const Addr USegEnd = ULL(0x7FFFFFFF); 835222Sksewell@umich.edu 845222Sksewell@umich.edu // Kernel Segment 0 - Unmapped 855222Sksewell@umich.edu const Addr KSeg0End = ULL(0x9FFFFFFF); 865222Sksewell@umich.edu const Addr KSeg0Base = ULL(0x80000000); 875222Sksewell@umich.edu const Addr KSeg0Mask = ULL(0x1FFFFFFF); 885222Sksewell@umich.edu 895222Sksewell@umich.edu // Kernel Segment 1 - Unmapped, Uncached 905222Sksewell@umich.edu const Addr KSeg1End = ULL(0xBFFFFFFF); 915222Sksewell@umich.edu const Addr KSeg1Base = ULL(0xA0000000); 925222Sksewell@umich.edu const Addr KSeg1Mask = ULL(0x1FFFFFFF); 935222Sksewell@umich.edu 945222Sksewell@umich.edu // Kernel/Supervisor Segment - Mapped 955222Sksewell@umich.edu const Addr KSSegEnd = ULL(0xDFFFFFFF); 965222Sksewell@umich.edu const Addr KSSegBase = ULL(0xC0000000); 975222Sksewell@umich.edu 985222Sksewell@umich.edu // Kernel Segment 3 - Mapped 995222Sksewell@umich.edu const Addr KSeg3End = ULL(0xFFFFFFFF); 1005222Sksewell@umich.edu const Addr KSeg3Base = ULL(0xE0000000); 1015222Sksewell@umich.edu 1025222Sksewell@umich.edu 1035222Sksewell@umich.edu // For loading... XXX This maybe could be USegEnd?? --ali 1045222Sksewell@umich.edu const Addr LoadAddrMask = ULL(0xffffffffff); 1055222Sksewell@umich.edu 1065222Sksewell@umich.edu inline Addr Phys2K0Seg(Addr addr) 1075222Sksewell@umich.edu { 1085222Sksewell@umich.edu // if (addr & PAddrUncachedBit43) { 1095222Sksewell@umich.edu// addr &= PAddrUncachedMask; 1105222Sksewell@umich.edu// addr |= PAddrUncachedBit40; 1115222Sksewell@umich.edu// } 1125222Sksewell@umich.edu return addr | KSeg0Base; 1135222Sksewell@umich.edu } 1145222Sksewell@umich.edu 1155222Sksewell@umich.edu //////////////////////////////////////////////////////////////////////// 1165222Sksewell@umich.edu // 1175222Sksewell@umich.edu // Interrupt levels 1185222Sksewell@umich.edu // 1195222Sksewell@umich.edu enum InterruptLevels 1205222Sksewell@umich.edu { 1215222Sksewell@umich.edu INTLEVEL_SOFTWARE_MIN = 4, 1225222Sksewell@umich.edu INTLEVEL_SOFTWARE_MAX = 19, 1235222Sksewell@umich.edu 1245222Sksewell@umich.edu INTLEVEL_EXTERNAL_MIN = 20, 1255222Sksewell@umich.edu INTLEVEL_EXTERNAL_MAX = 34, 1265222Sksewell@umich.edu 1275222Sksewell@umich.edu INTLEVEL_IRQ0 = 20, 1285222Sksewell@umich.edu INTLEVEL_IRQ1 = 21, 1295222Sksewell@umich.edu INTINDEX_ETHERNET = 0, 1305222Sksewell@umich.edu INTINDEX_SCSI = 1, 1315222Sksewell@umich.edu INTLEVEL_IRQ2 = 22, 1325222Sksewell@umich.edu INTLEVEL_IRQ3 = 23, 1335222Sksewell@umich.edu 1345222Sksewell@umich.edu INTLEVEL_SERIAL = 33, 1355222Sksewell@umich.edu 1365222Sksewell@umich.edu NumInterruptLevels = INTLEVEL_EXTERNAL_MAX 1375222Sksewell@umich.edu }; 1385222Sksewell@umich.edu 1395222Sksewell@umich.edu 1405222Sksewell@umich.edu // MIPS modes 1415222Sksewell@umich.edu enum mode_type 1425222Sksewell@umich.edu { 1435222Sksewell@umich.edu mode_kernel = 0, // kernel 1445222Sksewell@umich.edu mode_supervisor = 1, // supervisor 1455222Sksewell@umich.edu mode_user = 2, // user mode 1465222Sksewell@umich.edu mode_debug = 3, // debug mode 1475222Sksewell@umich.edu mode_number // number of modes 1485222Sksewell@umich.edu }; 1495222Sksewell@umich.edu 1505222Sksewell@umich.edu inline mode_type getOperatingMode(MiscReg Stat) 1515222Sksewell@umich.edu { 1525222Sksewell@umich.edu if((Stat & 0x10000006) != 0 || (Stat & 0x18) ==0) 1535222Sksewell@umich.edu return mode_kernel; 1545222Sksewell@umich.edu else{ 1555222Sksewell@umich.edu if((Stat & 0x18) == 0x8) 1565222Sksewell@umich.edu return mode_supervisor; 1575222Sksewell@umich.edu else if((Stat & 0x18) == 0x10) 1585222Sksewell@umich.edu return mode_user; 1595222Sksewell@umich.edu else return mode_number; 1605222Sksewell@umich.edu } 1615222Sksewell@umich.edu } 1625222Sksewell@umich.edu 1635222Sksewell@umich.edu 1642972Sgblack@eecs.umich.edu // return a no-op instruction... used for instruction fetch faults 1652972Sgblack@eecs.umich.edu const ExtMachInst NoopMachInst = 0x00000000; 1662131SN/A 1672972Sgblack@eecs.umich.edu // Constants Related to the number of registers 1682972Sgblack@eecs.umich.edu const int NumIntArchRegs = 32; 1694661Sksewell@umich.edu const int NumIntSpecialRegs = 9; 1702972Sgblack@eecs.umich.edu const int NumFloatArchRegs = 32; 1712972Sgblack@eecs.umich.edu const int NumFloatSpecialRegs = 5; 1722597SN/A 1735222Sksewell@umich.edu const int NumShadowRegSets = 16; // Maximum number of shadow register sets 1745222Sksewell@umich.edu const int NumIntRegs = NumIntArchRegs*NumShadowRegSets + NumIntSpecialRegs; //HI & LO Regs 1755222Sksewell@umich.edu const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs;// 1765222Sksewell@umich.edu 1772972Sgblack@eecs.umich.edu // Static instruction parameters 1785222Sksewell@umich.edu const int MaxInstSrcRegs = 10; 1795222Sksewell@umich.edu const int MaxInstDestRegs = 8; 1802597SN/A 1812972Sgblack@eecs.umich.edu // semantically meaningful register indices 1822972Sgblack@eecs.umich.edu const int ZeroReg = 0; 1832972Sgblack@eecs.umich.edu const int AssemblerReg = 1; 1842972Sgblack@eecs.umich.edu const int ReturnValueReg = 2; 1852972Sgblack@eecs.umich.edu const int ReturnValueReg1 = 2; 1862972Sgblack@eecs.umich.edu const int ReturnValueReg2 = 3; 1875222Sksewell@umich.edu const int ArgumentReg0 = 4; 1885222Sksewell@umich.edu const int ArgumentReg1 = 5; 1895222Sksewell@umich.edu const int ArgumentReg2 = 6; 1905222Sksewell@umich.edu const int ArgumentReg3 = 7; 1912972Sgblack@eecs.umich.edu const int KernelReg0 = 26; 1922972Sgblack@eecs.umich.edu const int KernelReg1 = 27; 1932972Sgblack@eecs.umich.edu const int GlobalPointerReg = 28; 1942972Sgblack@eecs.umich.edu const int StackPointerReg = 29; 1952972Sgblack@eecs.umich.edu const int FramePointerReg = 30; 1962972Sgblack@eecs.umich.edu const int ReturnAddressReg = 31; 1972597SN/A 1985222Sksewell@umich.edu const int ArgumentReg[] = {4, 5, 6, 7}; 1995222Sksewell@umich.edu const int NumArgumentRegs = sizeof(ArgumentReg) / sizeof(const int); 2005222Sksewell@umich.edu 2012972Sgblack@eecs.umich.edu const int SyscallNumReg = ReturnValueReg1; 2024661Sksewell@umich.edu const int SyscallPseudoReturnReg = ReturnValueReg2; 2035222Sksewell@umich.edu const int SyscallSuccessReg = ArgumentReg3; 2042131SN/A 2052972Sgblack@eecs.umich.edu const int LogVMPageSize = 13; // 8K bytes 2062972Sgblack@eecs.umich.edu const int VMPageSize = (1 << LogVMPageSize); 2072131SN/A 2082972Sgblack@eecs.umich.edu const int BranchPredAddrShiftAmt = 2; // instructions are 4-byte aligned 2092131SN/A 2102972Sgblack@eecs.umich.edu const int MachineBytes = 4; 2112972Sgblack@eecs.umich.edu const int WordBytes = 4; 2122972Sgblack@eecs.umich.edu const int HalfwordBytes = 2; 2132972Sgblack@eecs.umich.edu const int ByteBytes = 1; 2142131SN/A 2152972Sgblack@eecs.umich.edu const int ANNOTE_NONE = 0; 2162972Sgblack@eecs.umich.edu const uint32_t ITOUCH_ANNOTE = 0xffffffff; 2172131SN/A 2185222Sksewell@umich.edu // These help enumerate all the registers for dependence tracking. 2195222Sksewell@umich.edu const int FP_Base_DepTag = NumIntRegs; 2205222Sksewell@umich.edu const int Ctrl_Base_DepTag = FP_Base_DepTag + NumFloatRegs; 2215222Sksewell@umich.edu 2224661Sksewell@umich.edu // Enumerate names for 'Control' Registers in the CPU 2234661Sksewell@umich.edu // Reference MIPS32 Arch. for Programmers, Vol. III, Ch.8 2244661Sksewell@umich.edu // (Register Number-Register Select) Summary of Register 2254661Sksewell@umich.edu //------------------------------------------------------ 2264661Sksewell@umich.edu // The first set of names classify the CP0 names as Register Banks 2274661Sksewell@umich.edu // for easy indexing when using the 'RD + SEL' index combination 2284661Sksewell@umich.edu // in CP0 instructions. 2294661Sksewell@umich.edu enum MiscRegTags { 2305222Sksewell@umich.edu Index = Ctrl_Base_DepTag + 0, //Bank 0: 0 - 3 2314661Sksewell@umich.edu MVPControl, 2324661Sksewell@umich.edu MVPConf0, 2334661Sksewell@umich.edu MVPConf1, 2344661Sksewell@umich.edu 2355222Sksewell@umich.edu CP0_Random = Ctrl_Base_DepTag + 8, //Bank 1: 8 - 15 2364661Sksewell@umich.edu VPEControl, 2374661Sksewell@umich.edu VPEConf0, 2384661Sksewell@umich.edu VPEConf1, 2394661Sksewell@umich.edu YQMask, 2404661Sksewell@umich.edu VPESchedule, 2414661Sksewell@umich.edu VPEScheFBack, 2424661Sksewell@umich.edu VPEOpt, 2434661Sksewell@umich.edu 2445222Sksewell@umich.edu EntryLo0 = Ctrl_Base_DepTag + 16, //Bank 2: 16 - 23 2454661Sksewell@umich.edu TCStatus, 2464661Sksewell@umich.edu TCBind, 2474661Sksewell@umich.edu TCRestart, 2484661Sksewell@umich.edu TCHalt, 2494661Sksewell@umich.edu TCContext, 2504661Sksewell@umich.edu TCSchedule, 2514661Sksewell@umich.edu TCScheFBack, 2524661Sksewell@umich.edu 2535222Sksewell@umich.edu EntryLo1 = Ctrl_Base_DepTag + 24, // Bank 3: 24 2544661Sksewell@umich.edu 2555222Sksewell@umich.edu Context = Ctrl_Base_DepTag + 32, // Bank 4: 32 - 33 2564661Sksewell@umich.edu ContextConfig, 2574661Sksewell@umich.edu 2585222Sksewell@umich.edu PageMask = Ctrl_Base_DepTag + 40, //Bank 5: 40 - 41 2595222Sksewell@umich.edu PageGrain = Ctrl_Base_DepTag + 41, 2604661Sksewell@umich.edu 2615222Sksewell@umich.edu Wired = Ctrl_Base_DepTag + 48, //Bank 6:48-55 2624661Sksewell@umich.edu SRSConf0, 2634661Sksewell@umich.edu SRSConf1, 2644661Sksewell@umich.edu SRSConf2, 2654661Sksewell@umich.edu SRSConf3, 2664661Sksewell@umich.edu SRSConf4, 2674661Sksewell@umich.edu 2685222Sksewell@umich.edu HWRena = Ctrl_Base_DepTag + 56, //Bank 7: 56-63 2694661Sksewell@umich.edu 2705222Sksewell@umich.edu BadVAddr = Ctrl_Base_DepTag + 64, //Bank 8: 64-71 2714661Sksewell@umich.edu 2725222Sksewell@umich.edu Count = Ctrl_Base_DepTag + 72, //Bank 9: 72-79 2734661Sksewell@umich.edu 2745222Sksewell@umich.edu EntryHi = Ctrl_Base_DepTag + 80, //Bank 10: 80-87 2754661Sksewell@umich.edu 2765222Sksewell@umich.edu Compare = Ctrl_Base_DepTag + 88, //Bank 11: 88-95 2774661Sksewell@umich.edu 2785222Sksewell@umich.edu Status = Ctrl_Base_DepTag + 96, //Bank 12: 96-103 2794661Sksewell@umich.edu IntCtl, 2804661Sksewell@umich.edu SRSCtl, 2814661Sksewell@umich.edu SRSMap, 2824661Sksewell@umich.edu 2835222Sksewell@umich.edu Cause = Ctrl_Base_DepTag + 104, //Bank 13: 104-111 2844661Sksewell@umich.edu 2855222Sksewell@umich.edu EPC = Ctrl_Base_DepTag + 112, //Bank 14: 112-119 2864661Sksewell@umich.edu 2875222Sksewell@umich.edu PRId = Ctrl_Base_DepTag + 120, //Bank 15: 120-127, 2884661Sksewell@umich.edu EBase, 2894661Sksewell@umich.edu 2905222Sksewell@umich.edu Config = Ctrl_Base_DepTag + 128, //Bank 16: 128-135 2914661Sksewell@umich.edu Config1, 2924661Sksewell@umich.edu Config2, 2934661Sksewell@umich.edu Config3, 2944661Sksewell@umich.edu Config4, 2954661Sksewell@umich.edu Config5, 2964661Sksewell@umich.edu Config6, 2974661Sksewell@umich.edu Config7, 2984661Sksewell@umich.edu 2994661Sksewell@umich.edu 3005222Sksewell@umich.edu LLAddr = Ctrl_Base_DepTag + 136, //Bank 17: 136-143 3014661Sksewell@umich.edu 3025222Sksewell@umich.edu WatchLo0 = Ctrl_Base_DepTag + 144, //Bank 18: 144-151 3034661Sksewell@umich.edu WatchLo1, 3044661Sksewell@umich.edu WatchLo2, 3054661Sksewell@umich.edu WatchLo3, 3064661Sksewell@umich.edu WatchLo4, 3074661Sksewell@umich.edu WatchLo5, 3084661Sksewell@umich.edu WatchLo6, 3094661Sksewell@umich.edu WatchLo7, 3104661Sksewell@umich.edu 3115222Sksewell@umich.edu WatchHi0 = Ctrl_Base_DepTag + 152, //Bank 19: 152-159 3124661Sksewell@umich.edu WatchHi1, 3134661Sksewell@umich.edu WatchHi2, 3144661Sksewell@umich.edu WatchHi3, 3154661Sksewell@umich.edu WatchHi4, 3164661Sksewell@umich.edu WatchHi5, 3174661Sksewell@umich.edu WatchHi6, 3184661Sksewell@umich.edu WatchHi7, 3194661Sksewell@umich.edu 3205222Sksewell@umich.edu XCContext64 = Ctrl_Base_DepTag + 160, //Bank 20: 160-167 3214661Sksewell@umich.edu 3224661Sksewell@umich.edu //Bank 21: 168-175 3234661Sksewell@umich.edu 3244661Sksewell@umich.edu //Bank 22: 176-183 3254661Sksewell@umich.edu 3265222Sksewell@umich.edu Debug = Ctrl_Base_DepTag + 184, //Bank 23: 184-191 3274661Sksewell@umich.edu TraceControl1, 3284661Sksewell@umich.edu TraceControl2, 3294661Sksewell@umich.edu UserTraceData, 3304661Sksewell@umich.edu TraceBPC, 3314661Sksewell@umich.edu 3325222Sksewell@umich.edu DEPC = Ctrl_Base_DepTag + 192, //Bank 24: 192-199 3334661Sksewell@umich.edu 3345222Sksewell@umich.edu PerfCnt0 = Ctrl_Base_DepTag + 200, //Bank 25: 200-207 3354661Sksewell@umich.edu PerfCnt1, 3364661Sksewell@umich.edu PerfCnt2, 3374661Sksewell@umich.edu PerfCnt3, 3384661Sksewell@umich.edu PerfCnt4, 3394661Sksewell@umich.edu PerfCnt5, 3404661Sksewell@umich.edu PerfCnt6, 3414661Sksewell@umich.edu PerfCnt7, 3424661Sksewell@umich.edu 3435222Sksewell@umich.edu ErrCtl = Ctrl_Base_DepTag + 208, //Bank 26: 208-215 3444661Sksewell@umich.edu 3455222Sksewell@umich.edu CacheErr0 = Ctrl_Base_DepTag + 216, //Bank 27: 216-223 3464661Sksewell@umich.edu CacheErr1, 3474661Sksewell@umich.edu CacheErr2, 3484661Sksewell@umich.edu CacheErr3, 3494661Sksewell@umich.edu 3505222Sksewell@umich.edu TagLo0 = Ctrl_Base_DepTag + 224, //Bank 28: 224-231 3514661Sksewell@umich.edu DataLo1, 3524661Sksewell@umich.edu TagLo2, 3534661Sksewell@umich.edu DataLo3, 3544661Sksewell@umich.edu TagLo4, 3554661Sksewell@umich.edu DataLo5, 3564661Sksewell@umich.edu TagLo6, 3574661Sksewell@umich.edu DataLo7, 3584661Sksewell@umich.edu 3595222Sksewell@umich.edu TagHi0 = Ctrl_Base_DepTag + 232, //Bank 29: 232-239 3604661Sksewell@umich.edu DataHi1, 3614661Sksewell@umich.edu TagHi2, 3624661Sksewell@umich.edu DataHi3, 3634661Sksewell@umich.edu TagHi4, 3644661Sksewell@umich.edu DataHi5, 3654661Sksewell@umich.edu TagHi6, 3664661Sksewell@umich.edu DataHi7, 3674661Sksewell@umich.edu 3684661Sksewell@umich.edu 3695222Sksewell@umich.edu ErrorEPC = Ctrl_Base_DepTag + 240, //Bank 30: 240-247 3704661Sksewell@umich.edu 3715222Sksewell@umich.edu DESAVE = Ctrl_Base_DepTag + 248, //Bank 31: 248-256 3724661Sksewell@umich.edu 3735222Sksewell@umich.edu LLFlag = Ctrl_Base_DepTag + 257, 3744661Sksewell@umich.edu 3754661Sksewell@umich.edu NumControlRegs 3764661Sksewell@umich.edu }; 3774661Sksewell@umich.edu 3785222Sksewell@umich.edu const int TotalDataRegs = NumIntRegs + NumFloatRegs; 3795222Sksewell@umich.edu 3804661Sksewell@umich.edu const int NumMiscRegs = NumControlRegs; 3814661Sksewell@umich.edu 3824661Sksewell@umich.edu const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs; 3834661Sksewell@umich.edu 3844661Sksewell@umich.edu 3852023SN/A}; 3862023SN/A 3872447SN/Ausing namespace MipsISA; 3882447SN/A 3892028SN/A#endif // __ARCH_MIPS_ISA_TRAITS_HH__ 390