isa_traits.hh revision 5222
1/*
2 * Copyright N) 2007 MIPS Technologies, Inc.  All Rights Reserved
3 *
4 * This software is part of the M5 simulator.
5 *
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7 * DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING
8 * TO THESE TERMS AND CONDITIONS.
9 *
10 * Permission is granted to use, copy, create derivative works and
11 * distribute this software and such derivative works for any purpose,
12 * so long as (1) the copyright notice above, this grant of permission,
13 * and the disclaimer below appear in all copies and derivative works
14 * made, (2) the copyright notice above is augmented as appropriate to
15 * reflect the addition of any new copyrightable work in a derivative
16 * work (e.g., Copyright N) <Publication Year> Copyright Owner), and (3)
17 * the name of MIPS Technologies, Inc. ($(B!H(BMIPS$(B!I(B) is not used in any
18 * advertising or publicity pertaining to the use or distribution of
19 * this software without specific, written prior authorization.
20 *
21 * THIS SOFTWARE IS PROVIDED $(B!H(BAS IS.$(B!I(B  MIPS MAKES NO WARRANTIES AND
22 * DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR
23 * OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
24 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
25 * NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE.
26 * IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT,
27 * INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF
28 * ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT,
29 * THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY
30 * IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR
31 * STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE
32 * POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE.
33 *
34 * Authors: Gabe M. Black
35 *          Korey L. Sewell
36 *          Jaidev Patwardhan
37 */
38
39#ifndef __ARCH_MIPS_ISA_TRAITS_HH__
40#define __ARCH_MIPS_ISA_TRAITS_HH__
41
42#include "arch/mips/types.hh"
43#include "config/full_system.hh"
44#include "sim/host.hh"
45
46namespace LittleEndianGuest {};
47
48#define TARGET_MIPS
49
50class StaticInstPtr;
51
52namespace MipsISA
53{
54    using namespace LittleEndianGuest;
55
56    StaticInstPtr decodeInst(ExtMachInst);
57
58    // MIPS DOES have a delay slot
59    #define ISA_HAS_DELAY_SLOT 1
60
61    const Addr PageShift = 13;
62    const Addr PageBytes = ULL(1) << PageShift;
63    const Addr Page_Mask = ~(PageBytes - 1);
64    const Addr PageOffset = PageBytes - 1;
65
66
67    ////////////////////////////////////////////////////////////////////////
68    //
69    //  Translation stuff
70    //
71
72    const Addr PteShift = 3;
73    const Addr NPtePageShift = PageShift - PteShift;
74    const Addr NPtePage = ULL(1) << NPtePageShift;
75    const Addr PteMask = NPtePage - 1;
76
77    //// All 'Mapped' segments go through the TLB
78    //// All other segments are translated by dropping the MSB, to give
79    //// the corresponding physical address
80    // User Segment - Mapped
81    const Addr USegBase = ULL(0x0);
82    const Addr USegEnd = ULL(0x7FFFFFFF);
83
84    // Kernel Segment 0 - Unmapped
85    const Addr KSeg0End = ULL(0x9FFFFFFF);
86    const Addr KSeg0Base =  ULL(0x80000000);
87    const Addr KSeg0Mask = ULL(0x1FFFFFFF);
88
89    // Kernel Segment 1 - Unmapped, Uncached
90    const Addr KSeg1End = ULL(0xBFFFFFFF);
91    const Addr KSeg1Base = ULL(0xA0000000);
92    const Addr KSeg1Mask = ULL(0x1FFFFFFF);
93
94    // Kernel/Supervisor Segment - Mapped
95    const Addr KSSegEnd = ULL(0xDFFFFFFF);
96    const Addr KSSegBase = ULL(0xC0000000);
97
98    // Kernel Segment 3 - Mapped
99    const Addr KSeg3End = ULL(0xFFFFFFFF);
100    const Addr KSeg3Base = ULL(0xE0000000);
101
102
103    // For loading... XXX This maybe could be USegEnd?? --ali
104    const Addr LoadAddrMask = ULL(0xffffffffff);
105
106    inline Addr Phys2K0Seg(Addr addr)
107    {
108   //  if (addr & PAddrUncachedBit43) {
109//         addr &= PAddrUncachedMask;
110//         addr |= PAddrUncachedBit40;
111//     }
112        return addr | KSeg0Base;
113    }
114
115    ////////////////////////////////////////////////////////////////////////
116    //
117    //  Interrupt levels
118    //
119    enum InterruptLevels
120    {
121        INTLEVEL_SOFTWARE_MIN = 4,
122        INTLEVEL_SOFTWARE_MAX = 19,
123
124        INTLEVEL_EXTERNAL_MIN = 20,
125        INTLEVEL_EXTERNAL_MAX = 34,
126
127        INTLEVEL_IRQ0 = 20,
128        INTLEVEL_IRQ1 = 21,
129        INTINDEX_ETHERNET = 0,
130        INTINDEX_SCSI = 1,
131        INTLEVEL_IRQ2 = 22,
132        INTLEVEL_IRQ3 = 23,
133
134        INTLEVEL_SERIAL = 33,
135
136        NumInterruptLevels = INTLEVEL_EXTERNAL_MAX
137    };
138
139
140    // MIPS modes
141    enum mode_type
142    {
143        mode_kernel = 0,		// kernel
144        mode_supervisor = 1,	// supervisor
145        mode_user = 2,		// user mode
146        mode_debug = 3,         // debug mode
147        mode_number			// number of modes
148    };
149
150  inline mode_type getOperatingMode(MiscReg Stat)
151  {
152    if((Stat & 0x10000006) != 0 || (Stat & 0x18) ==0)
153      return mode_kernel;
154    else{
155      if((Stat & 0x18) == 0x8)
156        return mode_supervisor;
157      else if((Stat & 0x18) == 0x10)
158        return mode_user;
159      else return mode_number;
160    }
161  }
162
163
164    // return a no-op instruction... used for instruction fetch faults
165    const ExtMachInst NoopMachInst = 0x00000000;
166
167    // Constants Related to the number of registers
168    const int NumIntArchRegs = 32;
169    const int NumIntSpecialRegs = 9;
170    const int NumFloatArchRegs = 32;
171    const int NumFloatSpecialRegs = 5;
172
173    const int NumShadowRegSets = 16; // Maximum number of shadow register sets
174    const int NumIntRegs = NumIntArchRegs*NumShadowRegSets + NumIntSpecialRegs;        //HI & LO Regs
175    const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs;//
176
177    // Static instruction parameters
178    const int MaxInstSrcRegs = 10;
179    const int MaxInstDestRegs = 8;
180
181    // semantically meaningful register indices
182    const int ZeroReg = 0;
183    const int AssemblerReg = 1;
184    const int ReturnValueReg = 2;
185    const int ReturnValueReg1 = 2;
186    const int ReturnValueReg2 = 3;
187    const int ArgumentReg0 = 4;
188    const int ArgumentReg1 = 5;
189    const int ArgumentReg2 = 6;
190    const int ArgumentReg3 = 7;
191    const int KernelReg0 = 26;
192    const int KernelReg1 = 27;
193    const int GlobalPointerReg = 28;
194    const int StackPointerReg = 29;
195    const int FramePointerReg = 30;
196    const int ReturnAddressReg = 31;
197
198    const int ArgumentReg[] = {4, 5, 6, 7};
199    const int NumArgumentRegs = sizeof(ArgumentReg) / sizeof(const int);
200
201    const int SyscallNumReg = ReturnValueReg1;
202    const int SyscallPseudoReturnReg = ReturnValueReg2;
203    const int SyscallSuccessReg = ArgumentReg3;
204
205    const int LogVMPageSize = 13;	// 8K bytes
206    const int VMPageSize = (1 << LogVMPageSize);
207
208    const int BranchPredAddrShiftAmt = 2; // instructions are 4-byte aligned
209
210    const int MachineBytes = 4;
211    const int WordBytes = 4;
212    const int HalfwordBytes = 2;
213    const int ByteBytes = 1;
214
215    const int ANNOTE_NONE = 0;
216    const uint32_t ITOUCH_ANNOTE = 0xffffffff;
217
218    // These help enumerate all the registers for dependence tracking.
219    const int FP_Base_DepTag = NumIntRegs;
220    const int Ctrl_Base_DepTag = FP_Base_DepTag + NumFloatRegs;
221
222    // Enumerate names for 'Control' Registers in the CPU
223    // Reference MIPS32 Arch. for Programmers, Vol. III, Ch.8
224    // (Register Number-Register Select) Summary of Register
225    //------------------------------------------------------
226    // The first set of names classify the CP0 names as Register Banks
227    // for easy indexing when using the 'RD + SEL' index combination
228    // in CP0 instructions.
229    enum MiscRegTags {
230        Index = Ctrl_Base_DepTag + 0,       //Bank 0: 0 - 3
231        MVPControl,
232        MVPConf0,
233        MVPConf1,
234
235        CP0_Random = Ctrl_Base_DepTag + 8,      //Bank 1: 8 - 15
236        VPEControl,
237        VPEConf0,
238        VPEConf1,
239        YQMask,
240        VPESchedule,
241        VPEScheFBack,
242        VPEOpt,
243
244        EntryLo0 = Ctrl_Base_DepTag + 16,   //Bank 2: 16 - 23
245        TCStatus,
246        TCBind,
247        TCRestart,
248        TCHalt,
249        TCContext,
250        TCSchedule,
251        TCScheFBack,
252
253        EntryLo1 = Ctrl_Base_DepTag + 24,   // Bank 3: 24
254
255        Context = Ctrl_Base_DepTag + 32,    // Bank 4: 32 - 33
256        ContextConfig,
257
258        PageMask = Ctrl_Base_DepTag + 40, //Bank 5: 40 - 41
259        PageGrain = Ctrl_Base_DepTag + 41,
260
261        Wired = Ctrl_Base_DepTag + 48,          //Bank 6:48-55
262        SRSConf0,
263        SRSConf1,
264        SRSConf2,
265        SRSConf3,
266        SRSConf4,
267
268        HWRena = Ctrl_Base_DepTag + 56,         //Bank 7: 56-63
269
270        BadVAddr = Ctrl_Base_DepTag + 64,       //Bank 8: 64-71
271
272        Count = Ctrl_Base_DepTag + 72,          //Bank 9: 72-79
273
274        EntryHi = Ctrl_Base_DepTag + 80,        //Bank 10: 80-87
275
276        Compare = Ctrl_Base_DepTag + 88,        //Bank 11: 88-95
277
278        Status = Ctrl_Base_DepTag + 96,         //Bank 12: 96-103
279        IntCtl,
280        SRSCtl,
281        SRSMap,
282
283        Cause = Ctrl_Base_DepTag + 104,         //Bank 13: 104-111
284
285        EPC = Ctrl_Base_DepTag + 112,           //Bank 14: 112-119
286
287        PRId = Ctrl_Base_DepTag + 120,          //Bank 15: 120-127,
288        EBase,
289
290        Config = Ctrl_Base_DepTag + 128,        //Bank 16: 128-135
291        Config1,
292        Config2,
293        Config3,
294        Config4,
295        Config5,
296        Config6,
297        Config7,
298
299
300        LLAddr = Ctrl_Base_DepTag + 136,        //Bank 17: 136-143
301
302        WatchLo0 = Ctrl_Base_DepTag + 144,      //Bank 18: 144-151
303        WatchLo1,
304        WatchLo2,
305        WatchLo3,
306        WatchLo4,
307        WatchLo5,
308        WatchLo6,
309        WatchLo7,
310
311        WatchHi0 = Ctrl_Base_DepTag + 152,     //Bank 19: 152-159
312        WatchHi1,
313        WatchHi2,
314        WatchHi3,
315        WatchHi4,
316        WatchHi5,
317        WatchHi6,
318        WatchHi7,
319
320        XCContext64 = Ctrl_Base_DepTag + 160, //Bank 20: 160-167
321
322                           //Bank 21: 168-175
323
324                           //Bank 22: 176-183
325
326        Debug = Ctrl_Base_DepTag + 184,       //Bank 23: 184-191
327        TraceControl1,
328        TraceControl2,
329        UserTraceData,
330        TraceBPC,
331
332        DEPC = Ctrl_Base_DepTag + 192,        //Bank 24: 192-199
333
334        PerfCnt0 = Ctrl_Base_DepTag + 200,    //Bank 25: 200-207
335        PerfCnt1,
336        PerfCnt2,
337        PerfCnt3,
338        PerfCnt4,
339        PerfCnt5,
340        PerfCnt6,
341        PerfCnt7,
342
343        ErrCtl = Ctrl_Base_DepTag + 208,      //Bank 26: 208-215
344
345        CacheErr0 = Ctrl_Base_DepTag + 216,   //Bank 27: 216-223
346        CacheErr1,
347        CacheErr2,
348        CacheErr3,
349
350        TagLo0 = Ctrl_Base_DepTag + 224,      //Bank 28: 224-231
351        DataLo1,
352        TagLo2,
353        DataLo3,
354        TagLo4,
355        DataLo5,
356        TagLo6,
357        DataLo7,
358
359        TagHi0 = Ctrl_Base_DepTag + 232,      //Bank 29: 232-239
360        DataHi1,
361        TagHi2,
362        DataHi3,
363        TagHi4,
364        DataHi5,
365        TagHi6,
366        DataHi7,
367
368
369        ErrorEPC = Ctrl_Base_DepTag + 240,    //Bank 30: 240-247
370
371        DESAVE = Ctrl_Base_DepTag + 248,       //Bank 31: 248-256
372
373        LLFlag = Ctrl_Base_DepTag + 257,
374
375        NumControlRegs
376    };
377
378    const int TotalDataRegs = NumIntRegs + NumFloatRegs;
379
380    const int NumMiscRegs = NumControlRegs;
381
382    const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs;
383
384
385};
386
387using namespace MipsISA;
388
389#endif // __ARCH_MIPS_ISA_TRAITS_HH__
390