system.cc revision 10810
12567SN/A/* 210037SARM gem5 Developers * Copyright (c) 2010, 2012-2013 ARM Limited 37585SAli.Saidi@arm.com * All rights reserved 47585SAli.Saidi@arm.com * 57585SAli.Saidi@arm.com * The license below extends only to copyright in the software and shall 67585SAli.Saidi@arm.com * not be construed as granting a license to any other intellectual 77585SAli.Saidi@arm.com * property including but not limited to intellectual property relating 87585SAli.Saidi@arm.com * to a hardware implementation of the functionality of the software 97585SAli.Saidi@arm.com * licensed hereunder. You may use the software subject to the license 107585SAli.Saidi@arm.com * terms below provided that you ensure that this notice is replicated 117585SAli.Saidi@arm.com * unmodified and in its entirety in all distributions of the software, 127585SAli.Saidi@arm.com * modified or unmodified, in source code or in binary form. 137585SAli.Saidi@arm.com * 142567SN/A * Copyright (c) 2002-2006 The Regents of The University of Michigan 152567SN/A * All rights reserved. 162567SN/A * 172567SN/A * Redistribution and use in source and binary forms, with or without 182567SN/A * modification, are permitted provided that the following conditions are 192567SN/A * met: redistributions of source code must retain the above copyright 202567SN/A * notice, this list of conditions and the following disclaimer; 212567SN/A * redistributions in binary form must reproduce the above copyright 222567SN/A * notice, this list of conditions and the following disclaimer in the 232567SN/A * documentation and/or other materials provided with the distribution; 242567SN/A * neither the name of the copyright holders nor the names of its 252567SN/A * contributors may be used to endorse or promote products derived from 262567SN/A * this software without specific prior written permission. 272567SN/A * 282567SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292567SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302567SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312567SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322567SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332567SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342567SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352567SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362567SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372567SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382567SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392665SN/A * 402665SN/A * Authors: Ali Saidi 412567SN/A */ 422567SN/A 438229Snate@binkert.org#include <iostream> 448229Snate@binkert.org 456757SAli.Saidi@ARM.com#include "arch/arm/system.hh" 468286SAli.Saidi@ARM.com#include "base/loader/object_file.hh" 478286SAli.Saidi@ARM.com#include "base/loader/symtab.hh" 488286SAli.Saidi@ARM.com#include "cpu/thread_context.hh" 498286SAli.Saidi@ARM.com#include "mem/physical.hh" 508706Sandreas.hansson@arm.com#include "mem/fs_translating_port_proxy.hh" 5110037SARM gem5 Developers#include "sim/full_system.hh" 522567SN/A 537650SAli.Saidi@ARM.comusing namespace std; 547650SAli.Saidi@ARM.comusing namespace Linux; 552567SN/A 566757SAli.Saidi@ARM.comArmSystem::ArmSystem(Params *p) 5710037SARM gem5 Developers : System(p), bootldr(NULL), _haveSecurity(p->have_security), 5810037SARM gem5 Developers _haveLPAE(p->have_lpae), 5910037SARM gem5 Developers _haveVirtualization(p->have_virtualization), 6010037SARM gem5 Developers _haveGenericTimer(p->have_generic_timer), 6110537Sandreas.hansson@arm.com _genericTimer(nullptr), 6210037SARM gem5 Developers _highestELIs64(p->highest_el_is_64), 6310037SARM gem5 Developers _resetAddr64(p->reset_addr_64), 6410037SARM gem5 Developers _physAddrRange64(p->phys_addr_range_64), 6510037SARM gem5 Developers _haveLargeAsid64(p->have_large_asid_64), 6610037SARM gem5 Developers multiProc(p->multi_proc) 672567SN/A{ 6810037SARM gem5 Developers // Check if the physical address range is valid 6910037SARM gem5 Developers if (_highestELIs64 && ( 7010037SARM gem5 Developers _physAddrRange64 < 32 || 7110037SARM gem5 Developers _physAddrRange64 > 48 || 7210037SARM gem5 Developers (_physAddrRange64 % 4 != 0 && _physAddrRange64 != 42))) { 7310037SARM gem5 Developers fatal("Invalid physical address range (%d)\n", _physAddrRange64); 7410037SARM gem5 Developers } 7510037SARM gem5 Developers 768885SAli.Saidi@ARM.com if (p->boot_loader != "") { 778885SAli.Saidi@ARM.com bootldr = createObjectFile(p->boot_loader); 788885SAli.Saidi@ARM.com 798885SAli.Saidi@ARM.com if (!bootldr) 808885SAli.Saidi@ARM.com fatal("Could not read bootloader: %s\n", p->boot_loader); 818885SAli.Saidi@ARM.com 8210037SARM gem5 Developers if ((bootldr->getArch() == ObjectFile::Arm64) && !_highestELIs64) { 8310037SARM gem5 Developers warn("Highest ARM exception-level set to AArch32 but bootloader " 8410037SARM gem5 Developers "is for AArch64. Assuming you wanted these to match.\n"); 8510037SARM gem5 Developers _highestELIs64 = true; 8610037SARM gem5 Developers } else if ((bootldr->getArch() == ObjectFile::Arm) && _highestELIs64) { 8710037SARM gem5 Developers warn("Highest ARM exception-level set to AArch64 but bootloader " 8810037SARM gem5 Developers "is for AArch32. Assuming you wanted these to match.\n"); 8910037SARM gem5 Developers _highestELIs64 = false; 9010037SARM gem5 Developers } 9110037SARM gem5 Developers 928885SAli.Saidi@ARM.com bootldr->loadGlobalSymbols(debugSymbolTable); 938885SAli.Saidi@ARM.com 948885SAli.Saidi@ARM.com } 958885SAli.Saidi@ARM.com debugPrintkEvent = addKernelFuncEvent<DebugPrintkEvent>("dprintk"); 968706Sandreas.hansson@arm.com} 978706Sandreas.hansson@arm.com 988706Sandreas.hansson@arm.comvoid 998706Sandreas.hansson@arm.comArmSystem::initState() 1008706Sandreas.hansson@arm.com{ 1018706Sandreas.hansson@arm.com // Moved from the constructor to here since it relies on the 1028706Sandreas.hansson@arm.com // address map being resolved in the interconnect 1038706Sandreas.hansson@arm.com 1048706Sandreas.hansson@arm.com // Call the initialisation of the super class 1058706Sandreas.hansson@arm.com System::initState(); 1068706Sandreas.hansson@arm.com 1078706Sandreas.hansson@arm.com const Params* p = params(); 1082567SN/A 1098885SAli.Saidi@ARM.com if (bootldr) { 1108706Sandreas.hansson@arm.com bootldr->loadSections(physProxy); 1118286SAli.Saidi@ARM.com 11210037SARM gem5 Developers uint8_t jump_to_bl_32[] = 1138286SAli.Saidi@ARM.com { 11410037SARM gem5 Developers 0x07, 0xf0, 0xa0, 0xe1 // branch to r7 in aarch32 1158286SAli.Saidi@ARM.com }; 11610037SARM gem5 Developers 11710037SARM gem5 Developers uint8_t jump_to_bl_64[] = 11810037SARM gem5 Developers { 11910037SARM gem5 Developers 0xe0, 0x00, 0x1f, 0xd6 // instruction "br x7" in aarch64 12010037SARM gem5 Developers }; 12110037SARM gem5 Developers 12210037SARM gem5 Developers // write the jump to branch table into address 0 12310037SARM gem5 Developers if (!_highestELIs64) 12410037SARM gem5 Developers physProxy.writeBlob(0x0, jump_to_bl_32, sizeof(jump_to_bl_32)); 12510037SARM gem5 Developers else 12610037SARM gem5 Developers physProxy.writeBlob(0x0, jump_to_bl_64, sizeof(jump_to_bl_64)); 1278286SAli.Saidi@ARM.com 1288286SAli.Saidi@ARM.com inform("Using bootloader at address %#x\n", bootldr->entryPoint()); 1298286SAli.Saidi@ARM.com 1308286SAli.Saidi@ARM.com // Put the address of the boot loader into r7 so we know 1318286SAli.Saidi@ARM.com // where to branch to after the reset fault 1328286SAli.Saidi@ARM.com // All other values needed by the boot loader to know what to do 1338885SAli.Saidi@ARM.com if (!p->gic_cpu_addr || !p->flags_addr) 1348885SAli.Saidi@ARM.com fatal("gic_cpu_addr && flags_addr must be set with bootloader\n"); 1358885SAli.Saidi@ARM.com 1368286SAli.Saidi@ARM.com for (int i = 0; i < threadContexts.size(); i++) { 13710037SARM gem5 Developers if (!_highestELIs64) 13810037SARM gem5 Developers threadContexts[i]->setIntReg(3, (kernelEntry & loadAddrMask) + 13910037SARM gem5 Developers loadAddrOffset); 1408286SAli.Saidi@ARM.com threadContexts[i]->setIntReg(4, params()->gic_cpu_addr); 1418286SAli.Saidi@ARM.com threadContexts[i]->setIntReg(5, params()->flags_addr); 1428286SAli.Saidi@ARM.com threadContexts[i]->setIntReg(7, bootldr->entryPoint()); 1438286SAli.Saidi@ARM.com } 14410037SARM gem5 Developers inform("Using kernel entry physical address at %#x\n", 14510037SARM gem5 Developers (kernelEntry & loadAddrMask) + loadAddrOffset); 1468286SAli.Saidi@ARM.com } else { 1478286SAli.Saidi@ARM.com // Set the initial PC to be at start of the kernel code 14810037SARM gem5 Developers if (!_highestELIs64) 14910037SARM gem5 Developers threadContexts[0]->pcState((kernelEntry & loadAddrMask) + 15010037SARM gem5 Developers loadAddrOffset); 1518286SAli.Saidi@ARM.com } 1522567SN/A} 1532567SN/A 15410037SARM gem5 DevelopersGenericTimer::ArchTimer * 15510037SARM gem5 DevelopersArmSystem::getArchTimer(int cpu_id) const 15610037SARM gem5 Developers{ 15710037SARM gem5 Developers if (_genericTimer) { 15810037SARM gem5 Developers return _genericTimer->getArchTimer(cpu_id); 15910037SARM gem5 Developers } 16010037SARM gem5 Developers return NULL; 16110037SARM gem5 Developers} 16210037SARM gem5 Developers 16310037SARM gem5 DevelopersGenericTimer::SystemCounter * 16410037SARM gem5 DevelopersArmSystem::getSystemCounter() const 16510037SARM gem5 Developers{ 16610037SARM gem5 Developers if (_genericTimer) { 16710037SARM gem5 Developers return _genericTimer->getSystemCounter(); 16810037SARM gem5 Developers } 16910037SARM gem5 Developers return NULL; 17010037SARM gem5 Developers} 17110037SARM gem5 Developers 17210037SARM gem5 Developersbool 17310037SARM gem5 DevelopersArmSystem::haveSecurity(ThreadContext *tc) 17410037SARM gem5 Developers{ 17510037SARM gem5 Developers if (!FullSystem) 17610037SARM gem5 Developers return false; 17710037SARM gem5 Developers 17810037SARM gem5 Developers ArmSystem *a_sys = dynamic_cast<ArmSystem *>(tc->getSystemPtr()); 17910037SARM gem5 Developers assert(a_sys); 18010037SARM gem5 Developers return a_sys->haveSecurity(); 18110037SARM gem5 Developers} 18210037SARM gem5 Developers 18310037SARM gem5 Developers 1846757SAli.Saidi@ARM.comArmSystem::~ArmSystem() 1852567SN/A{ 1868286SAli.Saidi@ARM.com if (debugPrintkEvent) 1878286SAli.Saidi@ARM.com delete debugPrintkEvent; 1882567SN/A} 1892567SN/A 19010037SARM gem5 Developersbool 19110037SARM gem5 DevelopersArmSystem::haveLPAE(ThreadContext *tc) 19210037SARM gem5 Developers{ 19310037SARM gem5 Developers if (!FullSystem) 19410037SARM gem5 Developers return false; 1956757SAli.Saidi@ARM.com 19610037SARM gem5 Developers ArmSystem *a_sys = dynamic_cast<ArmSystem *>(tc->getSystemPtr()); 19710037SARM gem5 Developers assert(a_sys); 19810037SARM gem5 Developers return a_sys->haveLPAE(); 19910037SARM gem5 Developers} 20010037SARM gem5 Developers 20110037SARM gem5 Developersbool 20210037SARM gem5 DevelopersArmSystem::haveVirtualization(ThreadContext *tc) 20310037SARM gem5 Developers{ 20410037SARM gem5 Developers if (!FullSystem) 20510037SARM gem5 Developers return false; 20610037SARM gem5 Developers 20710037SARM gem5 Developers ArmSystem *a_sys = dynamic_cast<ArmSystem *>(tc->getSystemPtr()); 20810037SARM gem5 Developers assert(a_sys); 20910037SARM gem5 Developers return a_sys->haveVirtualization(); 21010037SARM gem5 Developers} 21110037SARM gem5 Developers 21210037SARM gem5 Developersbool 21310037SARM gem5 DevelopersArmSystem::highestELIs64(ThreadContext *tc) 21410037SARM gem5 Developers{ 21510037SARM gem5 Developers return dynamic_cast<ArmSystem *>(tc->getSystemPtr())->highestELIs64(); 21610037SARM gem5 Developers} 21710037SARM gem5 Developers 21810037SARM gem5 DevelopersExceptionLevel 21910037SARM gem5 DevelopersArmSystem::highestEL(ThreadContext *tc) 22010037SARM gem5 Developers{ 22110037SARM gem5 Developers return dynamic_cast<ArmSystem *>(tc->getSystemPtr())->highestEL(); 22210037SARM gem5 Developers} 22310037SARM gem5 Developers 22410037SARM gem5 DevelopersAddr 22510037SARM gem5 DevelopersArmSystem::resetAddr64(ThreadContext *tc) 22610037SARM gem5 Developers{ 22710037SARM gem5 Developers return dynamic_cast<ArmSystem *>(tc->getSystemPtr())->resetAddr64(); 22810037SARM gem5 Developers} 22910037SARM gem5 Developers 23010037SARM gem5 Developersuint8_t 23110037SARM gem5 DevelopersArmSystem::physAddrRange(ThreadContext *tc) 23210037SARM gem5 Developers{ 23310037SARM gem5 Developers return dynamic_cast<ArmSystem *>(tc->getSystemPtr())->physAddrRange(); 23410037SARM gem5 Developers} 23510037SARM gem5 Developers 23610037SARM gem5 DevelopersAddr 23710037SARM gem5 DevelopersArmSystem::physAddrMask(ThreadContext *tc) 23810037SARM gem5 Developers{ 23910037SARM gem5 Developers return dynamic_cast<ArmSystem *>(tc->getSystemPtr())->physAddrMask(); 24010037SARM gem5 Developers} 24110037SARM gem5 Developers 24210037SARM gem5 Developersbool 24310037SARM gem5 DevelopersArmSystem::haveLargeAsid64(ThreadContext *tc) 24410037SARM gem5 Developers{ 24510037SARM gem5 Developers return dynamic_cast<ArmSystem *>(tc->getSystemPtr())->haveLargeAsid64(); 24610037SARM gem5 Developers} 24710810Sbr@bsdpad.com 2486757SAli.Saidi@ARM.comArmSystem * 2496757SAli.Saidi@ARM.comArmSystemParams::create() 2502567SN/A{ 2516757SAli.Saidi@ARM.com return new ArmSystem(this); 2522567SN/A} 25310810Sbr@bsdpad.com 25410810Sbr@bsdpad.comvoid 25510810Sbr@bsdpad.comGenericArmSystem::initState() 25610810Sbr@bsdpad.com{ 25710810Sbr@bsdpad.com // Moved from the constructor to here since it relies on the 25810810Sbr@bsdpad.com // address map being resolved in the interconnect 25910810Sbr@bsdpad.com 26010810Sbr@bsdpad.com // Call the initialisation of the super class 26110810Sbr@bsdpad.com ArmSystem::initState(); 26210810Sbr@bsdpad.com} 26310810Sbr@bsdpad.com 26410810Sbr@bsdpad.comGenericArmSystem * 26510810Sbr@bsdpad.comGenericArmSystemParams::create() 26610810Sbr@bsdpad.com{ 26710810Sbr@bsdpad.com 26810810Sbr@bsdpad.com return new GenericArmSystem(this); 26910810Sbr@bsdpad.com} 270