mem.cc revision 12104
1/* 2 * Copyright (c) 2010, 2012 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2007-2008 The Florida State University 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Stephen Hines 41 */ 42 43#include "arch/arm/insts/mem.hh" 44 45#include "base/loader/symtab.hh" 46 47using namespace std; 48 49namespace ArmISA 50{ 51 52void 53MemoryReg::printOffset(std::ostream &os) const 54{ 55 if (!add) 56 os << "-"; 57 printIntReg(os, index); 58 if (shiftType != LSL || shiftAmt != 0) { 59 switch (shiftType) { 60 case LSL: 61 ccprintf(os, " LSL #%d", shiftAmt); 62 break; 63 case LSR: 64 ccprintf(os, " LSR #%d", (shiftAmt == 0) ? 32 : shiftAmt); 65 break; 66 case ASR: 67 ccprintf(os, " ASR #%d", (shiftAmt == 0) ? 32 : shiftAmt); 68 break; 69 case ROR: 70 if (shiftAmt == 0) { 71 ccprintf(os, " RRX"); 72 } else { 73 ccprintf(os, " ROR #%d", shiftAmt); 74 } 75 break; 76 } 77 } 78} 79 80string 81Swap::generateDisassembly(Addr pc, const SymbolTable *symtab) const 82{ 83 stringstream ss; 84 printMnemonic(ss); 85 printIntReg(ss, dest); 86 ss << ", "; 87 printIntReg(ss, op1); 88 ss << ", ["; 89 printIntReg(ss, base); 90 ss << "]"; 91 return ss.str(); 92} 93 94string 95RfeOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 96{ 97 stringstream ss; 98 switch (mode) { 99 case DecrementAfter: 100 printMnemonic(ss, "da"); 101 break; 102 case DecrementBefore: 103 printMnemonic(ss, "db"); 104 break; 105 case IncrementAfter: 106 printMnemonic(ss, "ia"); 107 break; 108 case IncrementBefore: 109 printMnemonic(ss, "ib"); 110 break; 111 } 112 printIntReg(ss, base); 113 if (wb) { 114 ss << "!"; 115 } 116 return ss.str(); 117} 118 119string 120SrsOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 121{ 122 stringstream ss; 123 switch (mode) { 124 case DecrementAfter: 125 printMnemonic(ss, "da"); 126 break; 127 case DecrementBefore: 128 printMnemonic(ss, "db"); 129 break; 130 case IncrementAfter: 131 printMnemonic(ss, "ia"); 132 break; 133 case IncrementBefore: 134 printMnemonic(ss, "ib"); 135 break; 136 } 137 printIntReg(ss, INTREG_SP); 138 if (wb) { 139 ss << "!"; 140 } 141 ss << ", #"; 142 switch (regMode) { 143 case MODE_USER: 144 ss << "user"; 145 break; 146 case MODE_FIQ: 147 ss << "fiq"; 148 break; 149 case MODE_IRQ: 150 ss << "irq"; 151 break; 152 case MODE_SVC: 153 ss << "supervisor"; 154 break; 155 case MODE_MON: 156 ss << "monitor"; 157 break; 158 case MODE_ABORT: 159 ss << "abort"; 160 break; 161 case MODE_HYP: 162 ss << "hyp"; 163 break; 164 case MODE_UNDEFINED: 165 ss << "undefined"; 166 break; 167 case MODE_SYSTEM: 168 ss << "system"; 169 break; 170 default: 171 ss << "unrecognized"; 172 break; 173 } 174 return ss.str(); 175} 176 177void 178Memory::printInst(std::ostream &os, AddrMode addrMode) const 179{ 180 printMnemonic(os); 181 printDest(os); 182 os << ", ["; 183 printIntReg(os, base); 184 if (addrMode != AddrMd_PostIndex) { 185 os << ", "; 186 printOffset(os); 187 os << "]"; 188 if (addrMode == AddrMd_PreIndex) { 189 os << "!"; 190 } 191 } else { 192 os << "] "; 193 printOffset(os); 194 195 } 196} 197 198} 199