ev5.hh revision 5568
111308Santhony.gutierrez@amd.com/* 211308Santhony.gutierrez@amd.com * Copyright (c) 2002-2005 The Regents of The University of Michigan 311308Santhony.gutierrez@amd.com * All rights reserved. 411308Santhony.gutierrez@amd.com * 511308Santhony.gutierrez@amd.com * Redistribution and use in source and binary forms, with or without 611308Santhony.gutierrez@amd.com * modification, are permitted provided that the following conditions are 711308Santhony.gutierrez@amd.com * met: redistributions of source code must retain the above copyright 811308Santhony.gutierrez@amd.com * notice, this list of conditions and the following disclaimer; 911308Santhony.gutierrez@amd.com * redistributions in binary form must reproduce the above copyright 1011308Santhony.gutierrez@amd.com * notice, this list of conditions and the following disclaimer in the 1111308Santhony.gutierrez@amd.com * documentation and/or other materials provided with the distribution; 1211308Santhony.gutierrez@amd.com * neither the name of the copyright holders nor the names of its 1311308Santhony.gutierrez@amd.com * contributors may be used to endorse or promote products derived from 1411308Santhony.gutierrez@amd.com * this software without specific prior written permission. 1511308Santhony.gutierrez@amd.com * 1611308Santhony.gutierrez@amd.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1711308Santhony.gutierrez@amd.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1811308Santhony.gutierrez@amd.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1911308Santhony.gutierrez@amd.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2011308Santhony.gutierrez@amd.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2111308Santhony.gutierrez@amd.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2211308Santhony.gutierrez@amd.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2311308Santhony.gutierrez@amd.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2411308Santhony.gutierrez@amd.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2511308Santhony.gutierrez@amd.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2611308Santhony.gutierrez@amd.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2711308Santhony.gutierrez@amd.com * 2811308Santhony.gutierrez@amd.com * Authors: Steve Reinhardt 2911308Santhony.gutierrez@amd.com * Nathan Binkert 3011308Santhony.gutierrez@amd.com * Ali Saidi 3111308Santhony.gutierrez@amd.com */ 3211308Santhony.gutierrez@amd.com 3311308Santhony.gutierrez@amd.com#ifndef __ARCH_ALPHA_EV5_HH__ 3411308Santhony.gutierrez@amd.com#define __ARCH_ALPHA_EV5_HH__ 3511308Santhony.gutierrez@amd.com 3611308Santhony.gutierrez@amd.com#include "config/alpha_tlaser.hh" 3711308Santhony.gutierrez@amd.com#include "arch/alpha/isa_traits.hh" 3811308Santhony.gutierrez@amd.com 3911308Santhony.gutierrez@amd.comnamespace AlphaISA { 4011308Santhony.gutierrez@amd.com 4111308Santhony.gutierrez@amd.com#if ALPHA_TLASER 4211308Santhony.gutierrez@amd.comconst uint64_t AsnMask = ULL(0x7f); 4311670Sandreas.hansson@arm.com#else 4411670Sandreas.hansson@arm.comconst uint64_t AsnMask = ULL(0xff); 4511308Santhony.gutierrez@amd.com#endif 4611308Santhony.gutierrez@amd.com 4711308Santhony.gutierrez@amd.comconst int VAddrImplBits = 43; 4811308Santhony.gutierrez@amd.comconst Addr VAddrImplMask = (ULL(1) << VAddrImplBits) - 1; 4911308Santhony.gutierrez@amd.comconst Addr VAddrUnImplMask = ~VAddrImplMask; 5011308Santhony.gutierrez@amd.cominline Addr VAddrImpl(Addr a) { return a & VAddrImplMask; } 5111308Santhony.gutierrez@amd.cominline Addr VAddrVPN(Addr a) { return a >> PageShift; } 5211308Santhony.gutierrez@amd.cominline Addr VAddrOffset(Addr a) { return a & PageOffset; } 5311308Santhony.gutierrez@amd.cominline Addr VAddrSpaceEV5(Addr a) { return a >> 41 & 0x3; } 5411308Santhony.gutierrez@amd.cominline Addr VAddrSpaceEV6(Addr a) { return a >> 41 & 0x7f; } 5511308Santhony.gutierrez@amd.com 5611308Santhony.gutierrez@amd.com#if ALPHA_TLASER 5711308Santhony.gutierrez@amd.cominline bool PAddrIprSpace(Addr a) { return a >= ULL(0xFFFFF00000); } 5811308Santhony.gutierrez@amd.comconst int PAddrImplBits = 40; 5911308Santhony.gutierrez@amd.com#else 6011308Santhony.gutierrez@amd.cominline bool PAddrIprSpace(Addr a) { return a >= ULL(0xFFFFFF00000); } 6111308Santhony.gutierrez@amd.comconst int PAddrImplBits = 44; // for Tsunami 6211308Santhony.gutierrez@amd.com#endif 6311308Santhony.gutierrez@amd.comconst Addr PAddrImplMask = (ULL(1) << PAddrImplBits) - 1; 6411308Santhony.gutierrez@amd.comconst Addr PAddrUncachedBit39 = ULL(0x8000000000); 6511308Santhony.gutierrez@amd.comconst Addr PAddrUncachedBit40 = ULL(0x10000000000); 6611308Santhony.gutierrez@amd.comconst Addr PAddrUncachedBit43 = ULL(0x80000000000); 6711308Santhony.gutierrez@amd.comconst Addr PAddrUncachedMask = ULL(0x807ffffffff); // Clear PA<42:35> 6811308Santhony.gutierrez@amd.cominline Addr Phys2K0Seg(Addr addr) 6911308Santhony.gutierrez@amd.com{ 7011308Santhony.gutierrez@amd.com#if !ALPHA_TLASER 7111308Santhony.gutierrez@amd.com if (addr & PAddrUncachedBit43) { 7211308Santhony.gutierrez@amd.com addr &= PAddrUncachedMask; 7311308Santhony.gutierrez@amd.com addr |= PAddrUncachedBit40; 7411308Santhony.gutierrez@amd.com } 7511308Santhony.gutierrez@amd.com#endif 7611308Santhony.gutierrez@amd.com return addr | K0SegBase; 7711308Santhony.gutierrez@amd.com} 7811308Santhony.gutierrez@amd.com 7911308Santhony.gutierrez@amd.cominline int DTB_ASN_ASN(uint64_t reg) { return reg >> 57 & AsnMask; } 8011308Santhony.gutierrez@amd.cominline Addr DTB_PTE_PPN(uint64_t reg) 8111308Santhony.gutierrez@amd.com{ return reg >> 32 & (ULL(1) << PAddrImplBits - PageShift) - 1; } 8211308Santhony.gutierrez@amd.cominline int DTB_PTE_XRE(uint64_t reg) { return reg >> 8 & 0xf; } 8311308Santhony.gutierrez@amd.cominline int DTB_PTE_XWE(uint64_t reg) { return reg >> 12 & 0xf; } 8411308Santhony.gutierrez@amd.cominline int DTB_PTE_FONR(uint64_t reg) { return reg >> 1 & 0x1; } 8511308Santhony.gutierrez@amd.cominline int DTB_PTE_FONW(uint64_t reg) { return reg >> 2 & 0x1; } 8611308Santhony.gutierrez@amd.cominline int DTB_PTE_GH(uint64_t reg) { return reg >> 5 & 0x3; } 8711308Santhony.gutierrez@amd.cominline int DTB_PTE_ASMA(uint64_t reg) { return reg >> 4 & 0x1; } 8811308Santhony.gutierrez@amd.com 8911308Santhony.gutierrez@amd.cominline int ITB_ASN_ASN(uint64_t reg) { return reg >> 4 & AsnMask; } 9011308Santhony.gutierrez@amd.cominline Addr ITB_PTE_PPN(uint64_t reg) 9111308Santhony.gutierrez@amd.com{ return reg >> 32 & (ULL(1) << PAddrImplBits - PageShift) - 1; } 9211308Santhony.gutierrez@amd.cominline int ITB_PTE_XRE(uint64_t reg) { return reg >> 8 & 0xf; } 9311308Santhony.gutierrez@amd.cominline bool ITB_PTE_FONR(uint64_t reg) { return reg >> 1 & 0x1; } 9411308Santhony.gutierrez@amd.cominline bool ITB_PTE_FONW(uint64_t reg) { return reg >> 2 & 0x1; } 9511308Santhony.gutierrez@amd.cominline int ITB_PTE_GH(uint64_t reg) { return reg >> 5 & 0x3; } 9611308Santhony.gutierrez@amd.cominline bool ITB_PTE_ASMA(uint64_t reg) { return reg >> 4 & 0x1; } 9711308Santhony.gutierrez@amd.com 9811308Santhony.gutierrez@amd.cominline uint64_t MCSR_SP(uint64_t reg) { return reg >> 1 & 0x3; } 9911308Santhony.gutierrez@amd.com 10011308Santhony.gutierrez@amd.cominline bool ICSR_SDE(uint64_t reg) { return reg >> 30 & 0x1; } 10111308Santhony.gutierrez@amd.cominline int ICSR_SPE(uint64_t reg) { return reg >> 28 & 0x3; } 10211308Santhony.gutierrez@amd.cominline bool ICSR_FPE(uint64_t reg) { return reg >> 26 & 0x1; } 10311308Santhony.gutierrez@amd.com 10411308Santhony.gutierrez@amd.cominline uint64_t ALT_MODE_AM(uint64_t reg) { return reg >> 3 & 0x3; } 10511308Santhony.gutierrez@amd.cominline uint64_t DTB_CM_CM(uint64_t reg) { return reg >> 3 & 0x3; } 10611308Santhony.gutierrez@amd.cominline uint64_t ICM_CM(uint64_t reg) { return reg >> 3 & 0x3; } 10711308Santhony.gutierrez@amd.com 10811308Santhony.gutierrez@amd.comconst uint64_t MM_STAT_BAD_VA_MASK = ULL(0x0020); 10911308Santhony.gutierrez@amd.comconst uint64_t MM_STAT_DTB_MISS_MASK = ULL(0x0010); 11011308Santhony.gutierrez@amd.comconst uint64_t MM_STAT_FONW_MASK = ULL(0x0008); 11111308Santhony.gutierrez@amd.comconst uint64_t MM_STAT_FONR_MASK = ULL(0x0004); 11211308Santhony.gutierrez@amd.comconst uint64_t MM_STAT_ACV_MASK = ULL(0x0002); 11311308Santhony.gutierrez@amd.comconst uint64_t MM_STAT_WR_MASK = ULL(0x0001); 11411308Santhony.gutierrez@amd.cominline int Opcode(MachInst inst) { return inst >> 26 & 0x3f; } 11511308Santhony.gutierrez@amd.cominline int Ra(MachInst inst) { return inst >> 21 & 0x1f; } 11611308Santhony.gutierrez@amd.com 11711308Santhony.gutierrez@amd.comconst Addr PalBase = 0x4000; 11811308Santhony.gutierrez@amd.comconst Addr PalMax = 0x10000; 11911308Santhony.gutierrez@amd.com 12011308Santhony.gutierrez@amd.com} // namespace AlphaISA 12111308Santhony.gutierrez@amd.com 12211308Santhony.gutierrez@amd.com#endif // __ARCH_ALPHA_EV5_HH__ 12311308Santhony.gutierrez@amd.com