ev5.hh revision 5568 
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 *          Nathan Binkert
30 *          Ali Saidi
31 */
32
33#ifndef __ARCH_ALPHA_EV5_HH__
34#define __ARCH_ALPHA_EV5_HH__
35
36#include "config/alpha_tlaser.hh"
37#include "arch/alpha/isa_traits.hh"
38
39namespace AlphaISA {
40
41#if ALPHA_TLASER
42const uint64_t AsnMask = ULL(0x7f);
43#else
44const uint64_t AsnMask = ULL(0xff);
45#endif
46
47const int VAddrImplBits = 43;
48const Addr VAddrImplMask = (ULL(1) << VAddrImplBits) - 1;
49const Addr VAddrUnImplMask = ~VAddrImplMask;
50inline Addr VAddrImpl(Addr a) { return a & VAddrImplMask; }
51inline Addr VAddrVPN(Addr a) { return a >> PageShift; }
52inline Addr VAddrOffset(Addr a) { return a & PageOffset; }
53inline Addr VAddrSpaceEV5(Addr a) { return a >> 41 & 0x3; }
54inline Addr VAddrSpaceEV6(Addr a) { return a >> 41 & 0x7f; }
55
56#if ALPHA_TLASER
57inline bool PAddrIprSpace(Addr a) { return a >= ULL(0xFFFFF00000); }
58const int PAddrImplBits = 40;
59#else
60inline bool PAddrIprSpace(Addr a) { return a >= ULL(0xFFFFFF00000); }
61const int PAddrImplBits = 44; // for Tsunami
62#endif
63const Addr PAddrImplMask = (ULL(1) << PAddrImplBits) - 1;
64const Addr PAddrUncachedBit39 = ULL(0x8000000000);
65const Addr PAddrUncachedBit40 = ULL(0x10000000000);
66const Addr PAddrUncachedBit43 = ULL(0x80000000000);
67const Addr PAddrUncachedMask = ULL(0x807ffffffff); // Clear PA<42:35>
68inline Addr Phys2K0Seg(Addr addr)
69{
70#if !ALPHA_TLASER
71    if (addr & PAddrUncachedBit43) {
72        addr &= PAddrUncachedMask;
73        addr |= PAddrUncachedBit40;
74    }
75#endif
76    return addr | K0SegBase;
77}
78
79inline int DTB_ASN_ASN(uint64_t reg) { return reg >> 57 & AsnMask; }
80inline Addr DTB_PTE_PPN(uint64_t reg)
81{ return reg >> 32 & (ULL(1) << PAddrImplBits - PageShift) - 1; }
82inline int DTB_PTE_XRE(uint64_t reg) { return reg >> 8 & 0xf; }
83inline int DTB_PTE_XWE(uint64_t reg) { return reg >> 12 & 0xf; }
84inline int DTB_PTE_FONR(uint64_t reg) { return reg >> 1 & 0x1; }
85inline int DTB_PTE_FONW(uint64_t reg) { return reg >> 2 & 0x1; }
86inline int DTB_PTE_GH(uint64_t reg) { return reg >> 5 & 0x3; }
87inline int DTB_PTE_ASMA(uint64_t reg) { return reg >> 4 & 0x1; }
88
89inline int ITB_ASN_ASN(uint64_t reg) { return reg >> 4 & AsnMask; }
90inline Addr ITB_PTE_PPN(uint64_t reg)
91{ return reg >> 32 & (ULL(1) << PAddrImplBits - PageShift) - 1; }
92inline int ITB_PTE_XRE(uint64_t reg) { return reg >> 8 & 0xf; }
93inline bool ITB_PTE_FONR(uint64_t reg) { return reg >> 1 & 0x1; }
94inline bool ITB_PTE_FONW(uint64_t reg) { return reg >> 2 & 0x1; }
95inline int ITB_PTE_GH(uint64_t reg) { return reg >> 5 & 0x3; }
96inline bool ITB_PTE_ASMA(uint64_t reg) { return reg >> 4 & 0x1; }
97
98inline uint64_t MCSR_SP(uint64_t reg) { return reg >> 1 & 0x3; }
99
100inline bool ICSR_SDE(uint64_t reg) { return reg >> 30 & 0x1; }
101inline int ICSR_SPE(uint64_t reg) { return reg >> 28 & 0x3; }
102inline bool ICSR_FPE(uint64_t reg) { return reg >> 26 & 0x1; }
103
104inline uint64_t ALT_MODE_AM(uint64_t reg) { return reg >> 3 & 0x3; }
105inline uint64_t DTB_CM_CM(uint64_t reg) { return reg >> 3 & 0x3; }
106inline uint64_t ICM_CM(uint64_t reg) { return reg >> 3 & 0x3; }
107
108const uint64_t MM_STAT_BAD_VA_MASK = ULL(0x0020);
109const uint64_t MM_STAT_DTB_MISS_MASK = ULL(0x0010);
110const uint64_t MM_STAT_FONW_MASK = ULL(0x0008);
111const uint64_t MM_STAT_FONR_MASK = ULL(0x0004);
112const uint64_t MM_STAT_ACV_MASK = ULL(0x0002);
113const uint64_t MM_STAT_WR_MASK = ULL(0x0001);
114inline int Opcode(MachInst inst) { return inst >> 26 & 0x3f; }
115inline int Ra(MachInst inst) { return inst >> 21 & 0x1f; }
116
117const Addr PalBase = 0x4000;
118const Addr PalMax = 0x10000;
119
120} // namespace AlphaISA
121
122#endif // __ARCH_ALPHA_EV5_HH__
123