fs.py revision 9827
17119Sgblack@eecs.umich.edu# Copyright (c) 2010-2013 ARM Limited 27119Sgblack@eecs.umich.edu# All rights reserved. 37120Sgblack@eecs.umich.edu# 47120Sgblack@eecs.umich.edu# The license below extends only to copyright in the software and shall 57120Sgblack@eecs.umich.edu# not be construed as granting a license to any other intellectual 67120Sgblack@eecs.umich.edu# property including but not limited to intellectual property relating 77120Sgblack@eecs.umich.edu# to a hardware implementation of the functionality of the software 87120Sgblack@eecs.umich.edu# licensed hereunder. You may use the software subject to the license 97120Sgblack@eecs.umich.edu# terms below provided that you ensure that this notice is replicated 107120Sgblack@eecs.umich.edu# unmodified and in its entirety in all distributions of the software, 117120Sgblack@eecs.umich.edu# modified or unmodified, in source code or in binary form. 127120Sgblack@eecs.umich.edu# 137120Sgblack@eecs.umich.edu# Copyright (c) 2006-2007 The Regents of The University of Michigan 147120Sgblack@eecs.umich.edu# All rights reserved. 157119Sgblack@eecs.umich.edu# 167119Sgblack@eecs.umich.edu# Redistribution and use in source and binary forms, with or without 177119Sgblack@eecs.umich.edu# modification, are permitted provided that the following conditions are 187119Sgblack@eecs.umich.edu# met: redistributions of source code must retain the above copyright 197119Sgblack@eecs.umich.edu# notice, this list of conditions and the following disclaimer; 207119Sgblack@eecs.umich.edu# redistributions in binary form must reproduce the above copyright 217119Sgblack@eecs.umich.edu# notice, this list of conditions and the following disclaimer in the 227119Sgblack@eecs.umich.edu# documentation and/or other materials provided with the distribution; 237119Sgblack@eecs.umich.edu# neither the name of the copyright holders nor the names of its 247119Sgblack@eecs.umich.edu# contributors may be used to endorse or promote products derived from 257119Sgblack@eecs.umich.edu# this software without specific prior written permission. 267119Sgblack@eecs.umich.edu# 277119Sgblack@eecs.umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 287119Sgblack@eecs.umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 297119Sgblack@eecs.umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 307119Sgblack@eecs.umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 317119Sgblack@eecs.umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 327119Sgblack@eecs.umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 337119Sgblack@eecs.umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 347119Sgblack@eecs.umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 357119Sgblack@eecs.umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 367119Sgblack@eecs.umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 377119Sgblack@eecs.umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 387119Sgblack@eecs.umich.edu# 397119Sgblack@eecs.umich.edu# Authors: Ali Saidi 407119Sgblack@eecs.umich.edu 417119Sgblack@eecs.umich.eduimport optparse 427119Sgblack@eecs.umich.eduimport sys 437119Sgblack@eecs.umich.edu 447205Sgblack@eecs.umich.eduimport m5 457205Sgblack@eecs.umich.edufrom m5.defines import buildEnv 467205Sgblack@eecs.umich.edufrom m5.objects import * 477205Sgblack@eecs.umich.edufrom m5.util import addToPath, fatal 487205Sgblack@eecs.umich.edu 497205Sgblack@eecs.umich.eduaddToPath('../common') 507205Sgblack@eecs.umich.edu 517205Sgblack@eecs.umich.edufrom FSConfig import * 527205Sgblack@eecs.umich.edufrom SysPaths import * 537205Sgblack@eecs.umich.edufrom Benchmarks import * 547205Sgblack@eecs.umich.eduimport Simulation 557205Sgblack@eecs.umich.eduimport CacheConfig 567205Sgblack@eecs.umich.edufrom Caches import * 577205Sgblack@eecs.umich.eduimport Options 587205Sgblack@eecs.umich.edu 597205Sgblack@eecs.umich.eduparser = optparse.OptionParser() 607205Sgblack@eecs.umich.eduOptions.addCommonOptions(parser) 617205Sgblack@eecs.umich.eduOptions.addFSOptions(parser) 627205Sgblack@eecs.umich.edu 637205Sgblack@eecs.umich.edu(options, args) = parser.parse_args() 647205Sgblack@eecs.umich.edu 657205Sgblack@eecs.umich.eduif args: 667205Sgblack@eecs.umich.edu print "Error: script doesn't take any positional arguments" 677205Sgblack@eecs.umich.edu sys.exit(1) 687205Sgblack@eecs.umich.edu 697205Sgblack@eecs.umich.edu# driver system CPU is always simple... note this is an assignment of 707205Sgblack@eecs.umich.edu# a class, not an instance. 717205Sgblack@eecs.umich.eduDriveCPUClass = AtomicSimpleCPU 727205Sgblack@eecs.umich.edudrive_mem_mode = 'atomic' 737205Sgblack@eecs.umich.edu 747205Sgblack@eecs.umich.edu# Check if KVM support has been enabled, we might need to do VM 757205Sgblack@eecs.umich.edu# configuration if that's the case. 767205Sgblack@eecs.umich.eduhave_kvm_support = 'BaseKvmCPU' in globals() 777205Sgblack@eecs.umich.edudef is_kvm_cpu(cpu_class): 787205Sgblack@eecs.umich.edu return have_kvm_support and cpu_class != None and \ 797205Sgblack@eecs.umich.edu issubclass(cpu_class, BaseKvmCPU) 807205Sgblack@eecs.umich.edu 817205Sgblack@eecs.umich.edu# system under test can be any CPU 827205Sgblack@eecs.umich.edu(TestCPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options) 837205Sgblack@eecs.umich.edu 847205Sgblack@eecs.umich.edu# Match the memories with the CPUs, the driver system always simple, 857205Sgblack@eecs.umich.edu# and based on the options for the test system 867205Sgblack@eecs.umich.eduDriveMemClass = SimpleMemory 877205Sgblack@eecs.umich.eduTestMemClass = Simulation.setMemClass(options) 887205Sgblack@eecs.umich.edu 897205Sgblack@eecs.umich.eduif options.benchmark: 907205Sgblack@eecs.umich.edu try: 917205Sgblack@eecs.umich.edu bm = Benchmarks[options.benchmark] 927205Sgblack@eecs.umich.edu except KeyError: 937205Sgblack@eecs.umich.edu print "Error benchmark %s has not been defined." % options.benchmark 947205Sgblack@eecs.umich.edu print "Valid benchmarks are: %s" % DefinedBenchmarks 957205Sgblack@eecs.umich.edu sys.exit(1) 967205Sgblack@eecs.umich.eduelse: 977205Sgblack@eecs.umich.edu if options.dual: 987205Sgblack@eecs.umich.edu bm = [SysConfig(disk=options.disk_image, mem=options.mem_size), SysConfig(disk=options.disk_image, mem=options.mem_size)] 997205Sgblack@eecs.umich.edu else: 1007205Sgblack@eecs.umich.edu bm = [SysConfig(disk=options.disk_image, mem=options.mem_size)] 1017205Sgblack@eecs.umich.edu 1027205Sgblack@eecs.umich.edunp = options.num_cpus 1037205Sgblack@eecs.umich.edu 1047205Sgblack@eecs.umich.eduif buildEnv['TARGET_ISA'] == "alpha": 1057205Sgblack@eecs.umich.edu test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0]) 1067205Sgblack@eecs.umich.eduelif buildEnv['TARGET_ISA'] == "mips": 1077205Sgblack@eecs.umich.edu test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0]) 1087205Sgblack@eecs.umich.eduelif buildEnv['TARGET_ISA'] == "sparc": 1097205Sgblack@eecs.umich.edu test_sys = makeSparcSystem(test_mem_mode, bm[0]) 1107205Sgblack@eecs.umich.eduelif buildEnv['TARGET_ISA'] == "x86": 1117205Sgblack@eecs.umich.edu test_sys = makeLinuxX86System(test_mem_mode, options.num_cpus, bm[0]) 1127205Sgblack@eecs.umich.eduelif buildEnv['TARGET_ISA'] == "arm": 1137205Sgblack@eecs.umich.edu test_sys = makeArmSystem(test_mem_mode, options.machine_type, bm[0], 1147205Sgblack@eecs.umich.edu options.dtb_filename, 1157205Sgblack@eecs.umich.edu bare_metal=options.bare_metal) 1167205Sgblack@eecs.umich.eduelse: 1177205Sgblack@eecs.umich.edu fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA']) 1187205Sgblack@eecs.umich.edu 1197205Sgblack@eecs.umich.edu# Create a top-level voltage domain 1207205Sgblack@eecs.umich.edutest_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage) 1217205Sgblack@eecs.umich.edu 1227205Sgblack@eecs.umich.edu# Create a source clock for the system and set the clock period 1237205Sgblack@eecs.umich.edutest_sys.clk_domain = SrcClockDomain(clock = options.sys_clock, 1247205Sgblack@eecs.umich.edu voltage_domain = test_sys.voltage_domain) 1257205Sgblack@eecs.umich.edu 1267205Sgblack@eecs.umich.edu# Create a CPU voltage domain 1277205Sgblack@eecs.umich.edutest_sys.cpu_voltage_domain = VoltageDomain() 1287205Sgblack@eecs.umich.edu 1297205Sgblack@eecs.umich.edu# Create a source clock for the CPUs and set the clock period 1307205Sgblack@eecs.umich.edutest_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock, 1317205Sgblack@eecs.umich.edu voltage_domain = 1327205Sgblack@eecs.umich.edu test_sys.cpu_voltage_domain) 1337205Sgblack@eecs.umich.edu 1347119Sgblack@eecs.umich.eduif options.kernel is not None: 1357119Sgblack@eecs.umich.edu test_sys.kernel = binary(options.kernel) 1367119Sgblack@eecs.umich.edu 1377119Sgblack@eecs.umich.eduif options.script is not None: 1387119Sgblack@eecs.umich.edu test_sys.readfile = options.script 1397119Sgblack@eecs.umich.edu 1407119Sgblack@eecs.umich.edutest_sys.init_param = options.init_param 1417119Sgblack@eecs.umich.edu 1427119Sgblack@eecs.umich.edu# For now, assign all the CPUs to the same clock domain 1437119Sgblack@eecs.umich.edutest_sys.cpu = [TestCPUClass(clk_domain=test_sys.cpu_clk_domain, cpu_id=i) 1447119Sgblack@eecs.umich.edu for i in xrange(np)] 1457119Sgblack@eecs.umich.edu 1467119Sgblack@eecs.umich.eduif is_kvm_cpu(TestCPUClass) or is_kvm_cpu(FutureClass): 1477119Sgblack@eecs.umich.edu test_sys.vm = KvmVM() 1487119Sgblack@eecs.umich.edu 1497119Sgblack@eecs.umich.eduif options.caches or options.l2cache: 1507119Sgblack@eecs.umich.edu # By default the IOCache runs at the system clock 1517119Sgblack@eecs.umich.edu test_sys.iocache = IOCache(addr_ranges = test_sys.mem_ranges) 1527119Sgblack@eecs.umich.edu test_sys.iocache.cpu_side = test_sys.iobus.master 1537119Sgblack@eecs.umich.edu test_sys.iocache.mem_side = test_sys.membus.slave 1547119Sgblack@eecs.umich.eduelse: 1557119Sgblack@eecs.umich.edu test_sys.iobridge = Bridge(delay='50ns', ranges = test_sys.mem_ranges) 1567119Sgblack@eecs.umich.edu test_sys.iobridge.slave = test_sys.iobus.master 1577119Sgblack@eecs.umich.edu test_sys.iobridge.master = test_sys.membus.slave 1587119Sgblack@eecs.umich.edu 1597119Sgblack@eecs.umich.edu# Sanity check 1607119Sgblack@eecs.umich.eduif options.fastmem: 1617120Sgblack@eecs.umich.edu if TestCPUClass != AtomicSimpleCPU: 1627120Sgblack@eecs.umich.edu fatal("Fastmem can only be used with atomic CPU!") 1637120Sgblack@eecs.umich.edu if (options.caches or options.l2cache): 1647120Sgblack@eecs.umich.edu fatal("You cannot use fastmem in combination with caches!") 1657120Sgblack@eecs.umich.edu 1667120Sgblack@eecs.umich.edufor i in xrange(np): 1677120Sgblack@eecs.umich.edu if options.fastmem: 1687120Sgblack@eecs.umich.edu test_sys.cpu[i].fastmem = True 1697120Sgblack@eecs.umich.edu if options.checker: 1707120Sgblack@eecs.umich.edu test_sys.cpu[i].addCheckerCpu() 1717120Sgblack@eecs.umich.edu test_sys.cpu[i].createThreads() 1727120Sgblack@eecs.umich.edu 1737120Sgblack@eecs.umich.eduCacheConfig.config_cache(options, test_sys) 1747120Sgblack@eecs.umich.edu 1757120Sgblack@eecs.umich.edu# Create the appropriate memory controllers and connect them to the 1767120Sgblack@eecs.umich.edu# memory bus 1777120Sgblack@eecs.umich.edutest_sys.mem_ctrls = [TestMemClass(range = r, conf_table_reported = True) 1787120Sgblack@eecs.umich.edu for r in test_sys.mem_ranges] 1797120Sgblack@eecs.umich.edufor i in xrange(len(test_sys.mem_ctrls)): 1807120Sgblack@eecs.umich.edu test_sys.mem_ctrls[i].port = test_sys.membus.master 1817120Sgblack@eecs.umich.edu 1827120Sgblack@eecs.umich.eduif len(bm) == 2: 1837120Sgblack@eecs.umich.edu if buildEnv['TARGET_ISA'] == 'alpha': 1847120Sgblack@eecs.umich.edu drive_sys = makeLinuxAlphaSystem(drive_mem_mode, bm[1]) 1857120Sgblack@eecs.umich.edu elif buildEnv['TARGET_ISA'] == 'mips': 1867120Sgblack@eecs.umich.edu drive_sys = makeLinuxMipsSystem(drive_mem_mode, bm[1]) 1877120Sgblack@eecs.umich.edu elif buildEnv['TARGET_ISA'] == 'sparc': 1887120Sgblack@eecs.umich.edu drive_sys = makeSparcSystem(drive_mem_mode, bm[1]) 1897120Sgblack@eecs.umich.edu elif buildEnv['TARGET_ISA'] == 'x86': 1907120Sgblack@eecs.umich.edu drive_sys = makeX86System(drive_mem_mode, np, bm[1]) 1917120Sgblack@eecs.umich.edu elif buildEnv['TARGET_ISA'] == 'arm': 1927120Sgblack@eecs.umich.edu drive_sys = makeArmSystem(drive_mem_mode, options.machine_type, bm[1]) 1937120Sgblack@eecs.umich.edu 1947120Sgblack@eecs.umich.edu # Create a top-level voltage domain 1957120Sgblack@eecs.umich.edu drive_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage) 1967120Sgblack@eecs.umich.edu 1977120Sgblack@eecs.umich.edu # Create a source clock for the system and set the clock period 1987120Sgblack@eecs.umich.edu drive_sys.clk_domain = SrcClockDomain(clock = options.sys_clock) 1997120Sgblack@eecs.umich.edu 2007120Sgblack@eecs.umich.edu # Create a CPU voltage domain 2017120Sgblack@eecs.umich.edu drive_sys.cpu_voltage_domain = VoltageDomain() 2027120Sgblack@eecs.umich.edu 2037120Sgblack@eecs.umich.edu # Create a source clock for the CPUs and set the clock period 2047120Sgblack@eecs.umich.edu drive_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock, 2057120Sgblack@eecs.umich.edu voltage_domain = 2067120Sgblack@eecs.umich.edu drive_sys.cpu_voltage_domain) 2077120Sgblack@eecs.umich.edu 2087120Sgblack@eecs.umich.edu drive_sys.cpu = DriveCPUClass(clk_domain=drive_sys.cpu_clk_domain, 2097120Sgblack@eecs.umich.edu cpu_id=0) 2107120Sgblack@eecs.umich.edu drive_sys.cpu.createThreads() 2117120Sgblack@eecs.umich.edu drive_sys.cpu.createInterruptController() 2127120Sgblack@eecs.umich.edu drive_sys.cpu.connectAllPorts(drive_sys.membus) 2137120Sgblack@eecs.umich.edu if options.fastmem: 2147120Sgblack@eecs.umich.edu drive_sys.cpu.fastmem = True 2157120Sgblack@eecs.umich.edu if options.kernel is not None: 2167120Sgblack@eecs.umich.edu drive_sys.kernel = binary(options.kernel) 2177120Sgblack@eecs.umich.edu 2187120Sgblack@eecs.umich.edu if is_kvm_cpu(DriveCPUClass): 2197120Sgblack@eecs.umich.edu drive_sys.vm = KvmVM() 2207120Sgblack@eecs.umich.edu 2217120Sgblack@eecs.umich.edu drive_sys.iobridge = Bridge(delay='50ns', 2227120Sgblack@eecs.umich.edu ranges = drive_sys.mem_ranges) 2237120Sgblack@eecs.umich.edu drive_sys.iobridge.slave = drive_sys.iobus.master 2247120Sgblack@eecs.umich.edu drive_sys.iobridge.master = drive_sys.membus.slave 2257120Sgblack@eecs.umich.edu 2267119Sgblack@eecs.umich.edu # Create the appropriate memory controllers and connect them to the 2277119Sgblack@eecs.umich.edu # memory bus 2287119Sgblack@eecs.umich.edu drive_sys.mem_ctrls = [DriveMemClass(range = r, conf_table_reported = True) 2297119Sgblack@eecs.umich.edu for r in drive_sys.mem_ranges] 2307119Sgblack@eecs.umich.edu for i in xrange(len(drive_sys.mem_ctrls)): 2317119Sgblack@eecs.umich.edu drive_sys.mem_ctrls[i].port = drive_sys.membus.master 2327119Sgblack@eecs.umich.edu 2337119Sgblack@eecs.umich.edu drive_sys.init_param = options.init_param 2347119Sgblack@eecs.umich.edu root = makeDualRoot(True, test_sys, drive_sys, options.etherdump) 2357119Sgblack@eecs.umich.eduelif len(bm) == 1: 2367119Sgblack@eecs.umich.edu root = Root(full_system=True, system=test_sys) 2377119Sgblack@eecs.umich.eduelse: 2387119Sgblack@eecs.umich.edu print "Error I don't know how to create more than 2 systems." 2397119Sgblack@eecs.umich.edu sys.exit(1) 2407119Sgblack@eecs.umich.edu 2417119Sgblack@eecs.umich.eduif options.timesync: 2427119Sgblack@eecs.umich.edu root.time_sync_enable = True 2437119Sgblack@eecs.umich.edu 2447119Sgblack@eecs.umich.eduif options.frame_capture: 2457119Sgblack@eecs.umich.edu VncServer.frame_capture = True 2467119Sgblack@eecs.umich.edu 2477119Sgblack@eecs.umich.eduSimulation.setWorkCountOptions(test_sys, options) 2487119Sgblack@eecs.umich.eduSimulation.run(options, root, test_sys, FutureClass) 2497119Sgblack@eecs.umich.edu