fs.py revision 9827
1# Copyright (c) 2010-2013 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license 9# terms below provided that you ensure that this notice is replicated 10# unmodified and in its entirety in all distributions of the software, 11# modified or unmodified, in source code or in binary form. 12# 13# Copyright (c) 2006-2007 The Regents of The University of Michigan 14# All rights reserved. 15# 16# Redistribution and use in source and binary forms, with or without 17# modification, are permitted provided that the following conditions are 18# met: redistributions of source code must retain the above copyright 19# notice, this list of conditions and the following disclaimer; 20# redistributions in binary form must reproduce the above copyright 21# notice, this list of conditions and the following disclaimer in the 22# documentation and/or other materials provided with the distribution; 23# neither the name of the copyright holders nor the names of its 24# contributors may be used to endorse or promote products derived from 25# this software without specific prior written permission. 26# 27# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 28# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 29# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 30# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 31# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 32# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 33# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 34# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 35# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 36# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 38# 39# Authors: Ali Saidi 40 41import optparse 42import sys 43 44import m5 45from m5.defines import buildEnv 46from m5.objects import * 47from m5.util import addToPath, fatal 48 49addToPath('../common') 50 51from FSConfig import * 52from SysPaths import * 53from Benchmarks import * 54import Simulation 55import CacheConfig 56from Caches import * 57import Options 58 59parser = optparse.OptionParser() 60Options.addCommonOptions(parser) 61Options.addFSOptions(parser) 62 63(options, args) = parser.parse_args() 64 65if args: 66 print "Error: script doesn't take any positional arguments" 67 sys.exit(1) 68 69# driver system CPU is always simple... note this is an assignment of 70# a class, not an instance. 71DriveCPUClass = AtomicSimpleCPU 72drive_mem_mode = 'atomic' 73 74# Check if KVM support has been enabled, we might need to do VM 75# configuration if that's the case. 76have_kvm_support = 'BaseKvmCPU' in globals() 77def is_kvm_cpu(cpu_class): 78 return have_kvm_support and cpu_class != None and \ 79 issubclass(cpu_class, BaseKvmCPU) 80 81# system under test can be any CPU 82(TestCPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options) 83 84# Match the memories with the CPUs, the driver system always simple, 85# and based on the options for the test system 86DriveMemClass = SimpleMemory 87TestMemClass = Simulation.setMemClass(options) 88 89if options.benchmark: 90 try: 91 bm = Benchmarks[options.benchmark] 92 except KeyError: 93 print "Error benchmark %s has not been defined." % options.benchmark 94 print "Valid benchmarks are: %s" % DefinedBenchmarks 95 sys.exit(1) 96else: 97 if options.dual: 98 bm = [SysConfig(disk=options.disk_image, mem=options.mem_size), SysConfig(disk=options.disk_image, mem=options.mem_size)] 99 else: 100 bm = [SysConfig(disk=options.disk_image, mem=options.mem_size)] 101 102np = options.num_cpus 103 104if buildEnv['TARGET_ISA'] == "alpha": 105 test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0]) 106elif buildEnv['TARGET_ISA'] == "mips": 107 test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0]) 108elif buildEnv['TARGET_ISA'] == "sparc": 109 test_sys = makeSparcSystem(test_mem_mode, bm[0]) 110elif buildEnv['TARGET_ISA'] == "x86": 111 test_sys = makeLinuxX86System(test_mem_mode, options.num_cpus, bm[0]) 112elif buildEnv['TARGET_ISA'] == "arm": 113 test_sys = makeArmSystem(test_mem_mode, options.machine_type, bm[0], 114 options.dtb_filename, 115 bare_metal=options.bare_metal) 116else: 117 fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA']) 118 119# Create a top-level voltage domain 120test_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage) 121 122# Create a source clock for the system and set the clock period 123test_sys.clk_domain = SrcClockDomain(clock = options.sys_clock, 124 voltage_domain = test_sys.voltage_domain) 125 126# Create a CPU voltage domain 127test_sys.cpu_voltage_domain = VoltageDomain() 128 129# Create a source clock for the CPUs and set the clock period 130test_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock, 131 voltage_domain = 132 test_sys.cpu_voltage_domain) 133 134if options.kernel is not None: 135 test_sys.kernel = binary(options.kernel) 136 137if options.script is not None: 138 test_sys.readfile = options.script 139 140test_sys.init_param = options.init_param 141 142# For now, assign all the CPUs to the same clock domain 143test_sys.cpu = [TestCPUClass(clk_domain=test_sys.cpu_clk_domain, cpu_id=i) 144 for i in xrange(np)] 145 146if is_kvm_cpu(TestCPUClass) or is_kvm_cpu(FutureClass): 147 test_sys.vm = KvmVM() 148 149if options.caches or options.l2cache: 150 # By default the IOCache runs at the system clock 151 test_sys.iocache = IOCache(addr_ranges = test_sys.mem_ranges) 152 test_sys.iocache.cpu_side = test_sys.iobus.master 153 test_sys.iocache.mem_side = test_sys.membus.slave 154else: 155 test_sys.iobridge = Bridge(delay='50ns', ranges = test_sys.mem_ranges) 156 test_sys.iobridge.slave = test_sys.iobus.master 157 test_sys.iobridge.master = test_sys.membus.slave 158 159# Sanity check 160if options.fastmem: 161 if TestCPUClass != AtomicSimpleCPU: 162 fatal("Fastmem can only be used with atomic CPU!") 163 if (options.caches or options.l2cache): 164 fatal("You cannot use fastmem in combination with caches!") 165 166for i in xrange(np): 167 if options.fastmem: 168 test_sys.cpu[i].fastmem = True 169 if options.checker: 170 test_sys.cpu[i].addCheckerCpu() 171 test_sys.cpu[i].createThreads() 172 173CacheConfig.config_cache(options, test_sys) 174 175# Create the appropriate memory controllers and connect them to the 176# memory bus 177test_sys.mem_ctrls = [TestMemClass(range = r, conf_table_reported = True) 178 for r in test_sys.mem_ranges] 179for i in xrange(len(test_sys.mem_ctrls)): 180 test_sys.mem_ctrls[i].port = test_sys.membus.master 181 182if len(bm) == 2: 183 if buildEnv['TARGET_ISA'] == 'alpha': 184 drive_sys = makeLinuxAlphaSystem(drive_mem_mode, bm[1]) 185 elif buildEnv['TARGET_ISA'] == 'mips': 186 drive_sys = makeLinuxMipsSystem(drive_mem_mode, bm[1]) 187 elif buildEnv['TARGET_ISA'] == 'sparc': 188 drive_sys = makeSparcSystem(drive_mem_mode, bm[1]) 189 elif buildEnv['TARGET_ISA'] == 'x86': 190 drive_sys = makeX86System(drive_mem_mode, np, bm[1]) 191 elif buildEnv['TARGET_ISA'] == 'arm': 192 drive_sys = makeArmSystem(drive_mem_mode, options.machine_type, bm[1]) 193 194 # Create a top-level voltage domain 195 drive_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage) 196 197 # Create a source clock for the system and set the clock period 198 drive_sys.clk_domain = SrcClockDomain(clock = options.sys_clock) 199 200 # Create a CPU voltage domain 201 drive_sys.cpu_voltage_domain = VoltageDomain() 202 203 # Create a source clock for the CPUs and set the clock period 204 drive_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock, 205 voltage_domain = 206 drive_sys.cpu_voltage_domain) 207 208 drive_sys.cpu = DriveCPUClass(clk_domain=drive_sys.cpu_clk_domain, 209 cpu_id=0) 210 drive_sys.cpu.createThreads() 211 drive_sys.cpu.createInterruptController() 212 drive_sys.cpu.connectAllPorts(drive_sys.membus) 213 if options.fastmem: 214 drive_sys.cpu.fastmem = True 215 if options.kernel is not None: 216 drive_sys.kernel = binary(options.kernel) 217 218 if is_kvm_cpu(DriveCPUClass): 219 drive_sys.vm = KvmVM() 220 221 drive_sys.iobridge = Bridge(delay='50ns', 222 ranges = drive_sys.mem_ranges) 223 drive_sys.iobridge.slave = drive_sys.iobus.master 224 drive_sys.iobridge.master = drive_sys.membus.slave 225 226 # Create the appropriate memory controllers and connect them to the 227 # memory bus 228 drive_sys.mem_ctrls = [DriveMemClass(range = r, conf_table_reported = True) 229 for r in drive_sys.mem_ranges] 230 for i in xrange(len(drive_sys.mem_ctrls)): 231 drive_sys.mem_ctrls[i].port = drive_sys.membus.master 232 233 drive_sys.init_param = options.init_param 234 root = makeDualRoot(True, test_sys, drive_sys, options.etherdump) 235elif len(bm) == 1: 236 root = Root(full_system=True, system=test_sys) 237else: 238 print "Error I don't know how to create more than 2 systems." 239 sys.exit(1) 240 241if options.timesync: 242 root.time_sync_enable = True 243 244if options.frame_capture: 245 VncServer.frame_capture = True 246 247Simulation.setWorkCountOptions(test_sys, options) 248Simulation.run(options, root, test_sys, FutureClass) 249