fs.py revision 11839
19665Sandreas.hansson@arm.com# Copyright (c) 2010-2013, 2016 ARM Limited 29665Sandreas.hansson@arm.com# All rights reserved. 39665Sandreas.hansson@arm.com# 49665Sandreas.hansson@arm.com# The license below extends only to copyright in the software and shall 59665Sandreas.hansson@arm.com# not be construed as granting a license to any other intellectual 69665Sandreas.hansson@arm.com# property including but not limited to intellectual property relating 79665Sandreas.hansson@arm.com# to a hardware implementation of the functionality of the software 89665Sandreas.hansson@arm.com# licensed hereunder. You may use the software subject to the license 99665Sandreas.hansson@arm.com# terms below provided that you ensure that this notice is replicated 109665Sandreas.hansson@arm.com# unmodified and in its entirety in all distributions of the software, 119665Sandreas.hansson@arm.com# modified or unmodified, in source code or in binary form. 129665Sandreas.hansson@arm.com# 135353Svilas.sridharan@gmail.com# Copyright (c) 2012-2014 Mark D. Hill and David A. Wood 143395Shsul@eecs.umich.edu# Copyright (c) 2009-2011 Advanced Micro Devices, Inc. 153395Shsul@eecs.umich.edu# Copyright (c) 2006-2007 The Regents of The University of Michigan 163395Shsul@eecs.umich.edu# All rights reserved. 173395Shsul@eecs.umich.edu# 183395Shsul@eecs.umich.edu# Redistribution and use in source and binary forms, with or without 193395Shsul@eecs.umich.edu# modification, are permitted provided that the following conditions are 203395Shsul@eecs.umich.edu# met: redistributions of source code must retain the above copyright 213395Shsul@eecs.umich.edu# notice, this list of conditions and the following disclaimer; 223395Shsul@eecs.umich.edu# redistributions in binary form must reproduce the above copyright 233395Shsul@eecs.umich.edu# notice, this list of conditions and the following disclaimer in the 243395Shsul@eecs.umich.edu# documentation and/or other materials provided with the distribution; 253395Shsul@eecs.umich.edu# neither the name of the copyright holders nor the names of its 263395Shsul@eecs.umich.edu# contributors may be used to endorse or promote products derived from 273395Shsul@eecs.umich.edu# this software without specific prior written permission. 283395Shsul@eecs.umich.edu# 293395Shsul@eecs.umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 303395Shsul@eecs.umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 313395Shsul@eecs.umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 323395Shsul@eecs.umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 333395Shsul@eecs.umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 343395Shsul@eecs.umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 353395Shsul@eecs.umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 363395Shsul@eecs.umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 373395Shsul@eecs.umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 383395Shsul@eecs.umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 393395Shsul@eecs.umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 403395Shsul@eecs.umich.edu# 418920Snilay@cs.wisc.edu# Authors: Ali Saidi 428920Snilay@cs.wisc.edu# Brad Beckmann 438920Snilay@cs.wisc.edu 448920Snilay@cs.wisc.eduimport optparse 457025SBrad.Beckmann@amd.comimport sys 469520SAndreas.Sandberg@ARM.com 479665Sandreas.hansson@arm.comimport m5 489520SAndreas.Sandberg@ARM.comfrom m5.defines import buildEnv 499520SAndreas.Sandberg@ARM.comfrom m5.objects import * 509520SAndreas.Sandberg@ARM.comfrom m5.util import addToPath, fatal 519520SAndreas.Sandberg@ARM.com 529520SAndreas.Sandberg@ARM.comaddToPath('../') 539665Sandreas.hansson@arm.com 549665Sandreas.hansson@arm.comfrom ruby import Ruby 559665Sandreas.hansson@arm.com 569665Sandreas.hansson@arm.comfrom common.FSConfig import * 578920Snilay@cs.wisc.edufrom common.SysPaths import * 588920Snilay@cs.wisc.edufrom common.Benchmarks import * 599520SAndreas.Sandberg@ARM.comfrom common import Simulation 609520SAndreas.Sandberg@ARM.comfrom common import CacheConfig 619520SAndreas.Sandberg@ARM.comfrom common import MemConfig 628920Snilay@cs.wisc.edufrom common import CpuConfig 639520SAndreas.Sandberg@ARM.comfrom common.Caches import * 648920Snilay@cs.wisc.edufrom common import Options 658920Snilay@cs.wisc.edu 668920Snilay@cs.wisc.edu 679827Sakash.bagdia@arm.com# Check if KVM support has been enabled, we might need to do VM 689827Sakash.bagdia@arm.com# configuration if that's the case. 699827Sakash.bagdia@arm.comhave_kvm_support = 'BaseKvmCPU' in globals() 709827Sakash.bagdia@arm.comdef is_kvm_cpu(cpu_class): 719790Sakash.bagdia@arm.com return have_kvm_support and cpu_class != None and \ 729790Sakash.bagdia@arm.com issubclass(cpu_class, BaseKvmCPU) 739790Sakash.bagdia@arm.com 749790Sakash.bagdia@arm.comdef cmd_line_template(): 759789Sakash.bagdia@arm.com if options.command_line and options.command_line_file: 769789Sakash.bagdia@arm.com print "Error: --command-line and --command-line-file are " \ 779789Sakash.bagdia@arm.com "mutually exclusive" 789800Snilay@cs.wisc.edu sys.exit(1) 799800Snilay@cs.wisc.edu if options.command_line: 809800Snilay@cs.wisc.edu return options.command_line 819800Snilay@cs.wisc.edu if options.command_line_file: 829800Snilay@cs.wisc.edu return open(options.command_line_file).read().strip() 839800Snilay@cs.wisc.edu return None 849800Snilay@cs.wisc.edu 859800Snilay@cs.wisc.edudef build_test_system(np): 869800Snilay@cs.wisc.edu cmdline = cmd_line_template() 879800Snilay@cs.wisc.edu if buildEnv['TARGET_ISA'] == "alpha": 8810145Sandreas.hansson@arm.com test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0], options.ruby, 899800Snilay@cs.wisc.edu cmdline=cmdline) 909800Snilay@cs.wisc.edu elif buildEnv['TARGET_ISA'] == "mips": 919836Sandreas.hansson@arm.com test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0], cmdline=cmdline) 929836Sandreas.hansson@arm.com elif buildEnv['TARGET_ISA'] == "sparc": 9310620Sandreas.hansson@arm.com test_sys = makeSparcSystem(test_mem_mode, bm[0], cmdline=cmdline) 9410620Sandreas.hansson@arm.com elif buildEnv['TARGET_ISA'] == "x86": 959800Snilay@cs.wisc.edu test_sys = makeLinuxX86System(test_mem_mode, options.num_cpus, bm[0], 969800Snilay@cs.wisc.edu options.ruby, cmdline=cmdline) 979800Snilay@cs.wisc.edu elif buildEnv['TARGET_ISA'] == "arm": 989800Snilay@cs.wisc.edu test_sys = makeArmSystem(test_mem_mode, options.machine_type, 9910037SARM gem5 Developers options.num_cpus, bm[0], options.dtb_filename, 10010037SARM gem5 Developers bare_metal=options.bare_metal, 10110037SARM gem5 Developers cmdline=cmdline, 10210613SMarco.Elver@ARM.com external_memory=options.external_memory_system, 10310613SMarco.Elver@ARM.com ruby=options.ruby) 1049800Snilay@cs.wisc.edu if options.enable_context_switch_stats_dump: 1059800Snilay@cs.wisc.edu test_sys.enable_context_switch_stats_dump = True 1069800Snilay@cs.wisc.edu else: 1079800Snilay@cs.wisc.edu fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA']) 1088920Snilay@cs.wisc.edu 1098920Snilay@cs.wisc.edu # Set the cache line size for the entire system 1108920Snilay@cs.wisc.edu test_sys.cache_line_size = options.cacheline_size 1118920Snilay@cs.wisc.edu 1128920Snilay@cs.wisc.edu # Create a top-level voltage domain 1138920Snilay@cs.wisc.edu test_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage) 1148920Snilay@cs.wisc.edu 1158920Snilay@cs.wisc.edu # Create a source clock for the system and set the clock period 1168920Snilay@cs.wisc.edu test_sys.clk_domain = SrcClockDomain(clock = options.sys_clock, 1178920Snilay@cs.wisc.edu voltage_domain = test_sys.voltage_domain) 1188920Snilay@cs.wisc.edu 1198920Snilay@cs.wisc.edu # Create a CPU voltage domain 1209800Snilay@cs.wisc.edu test_sys.cpu_voltage_domain = VoltageDomain() 1219800Snilay@cs.wisc.edu 1228920Snilay@cs.wisc.edu # Create a source clock for the CPUs and set the clock period 1233395Shsul@eecs.umich.edu test_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock, 1248920Snilay@cs.wisc.edu voltage_domain = 1259909Snilay@cs.wisc.edu test_sys.cpu_voltage_domain) 1269816Sjthestness@gmail.com 1279816Sjthestness@gmail.com if options.kernel is not None: 1289816Sjthestness@gmail.com test_sys.kernel = binary(options.kernel) 1299816Sjthestness@gmail.com 1309816Sjthestness@gmail.com if options.script is not None: 1319816Sjthestness@gmail.com test_sys.readfile = options.script 1329816Sjthestness@gmail.com 1339816Sjthestness@gmail.com if options.lpae: 1349816Sjthestness@gmail.com test_sys.have_lpae = True 1358920Snilay@cs.wisc.edu 1368920Snilay@cs.wisc.edu if options.virtualisation: 1378920Snilay@cs.wisc.edu test_sys.have_virtualization = True 1388920Snilay@cs.wisc.edu 1398920Snilay@cs.wisc.edu test_sys.init_param = options.init_param 14010159Sgedare@rtems.org 14110159Sgedare@rtems.org # For now, assign all the CPUs to the same clock domain 1428920Snilay@cs.wisc.edu test_sys.cpu = [TestCPUClass(clk_domain=test_sys.cpu_clk_domain, cpu_id=i) 1438920Snilay@cs.wisc.edu for i in xrange(np)] 1448920Snilay@cs.wisc.edu 1458920Snilay@cs.wisc.edu if is_kvm_cpu(TestCPUClass) or is_kvm_cpu(FutureClass): 1468920Snilay@cs.wisc.edu test_sys.kvm_vm = KvmVM() 1478920Snilay@cs.wisc.edu 1488920Snilay@cs.wisc.edu if options.ruby: 1498920Snilay@cs.wisc.edu # Check for timing mode because ruby does not support atomic accesses 1508920Snilay@cs.wisc.edu if not (options.cpu_type == "detailed" or options.cpu_type == "timing"): 1516776SBrad.Beckmann@amd.com print >> sys.stderr, "Ruby requires TimingSimpleCPU or O3CPU!!" 1529800Snilay@cs.wisc.edu sys.exit(1) 1539800Snilay@cs.wisc.edu 1549800Snilay@cs.wisc.edu Ruby.create_system(options, True, test_sys, test_sys.iobus, 1559800Snilay@cs.wisc.edu test_sys._dma_ports) 1569800Snilay@cs.wisc.edu 15710608Sdam.sunwoo@arm.com # Create a seperate clock domain for Ruby 15810608Sdam.sunwoo@arm.com test_sys.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock, 15910608Sdam.sunwoo@arm.com voltage_domain = test_sys.voltage_domain) 16010608Sdam.sunwoo@arm.com 16110608Sdam.sunwoo@arm.com # Connect the ruby io port to the PIO bus, 1629800Snilay@cs.wisc.edu # assuming that there is just one such port. 1638920Snilay@cs.wisc.edu test_sys.iobus.master = test_sys.ruby._io_port.slave 1648920Snilay@cs.wisc.edu 1658920Snilay@cs.wisc.edu for (i, cpu) in enumerate(test_sys.cpu): 1668920Snilay@cs.wisc.edu # 1679357Sandreas.hansson@arm.com # Tie the cpu ports to the correct ruby system ports 1688920Snilay@cs.wisc.edu # 1698920Snilay@cs.wisc.edu cpu.clk_domain = test_sys.cpu_clk_domain 1708920Snilay@cs.wisc.edu cpu.createThreads() 1718920Snilay@cs.wisc.edu cpu.createInterruptController() 1728920Snilay@cs.wisc.edu 1738920Snilay@cs.wisc.edu cpu.icache_port = test_sys.ruby._cpu_ports[i].slave 1748920Snilay@cs.wisc.edu cpu.dcache_port = test_sys.ruby._cpu_ports[i].slave 1758920Snilay@cs.wisc.edu 1768920Snilay@cs.wisc.edu if buildEnv['TARGET_ISA'] in ("x86", "arm"): 1778920Snilay@cs.wisc.edu cpu.itb.walker.port = test_sys.ruby._cpu_ports[i].slave 1788920Snilay@cs.wisc.edu cpu.dtb.walker.port = test_sys.ruby._cpu_ports[i].slave 1798920Snilay@cs.wisc.edu 1808920Snilay@cs.wisc.edu if buildEnv['TARGET_ISA'] in "x86": 1818920Snilay@cs.wisc.edu cpu.interrupts[0].pio = test_sys.ruby._cpu_ports[i].master 1828920Snilay@cs.wisc.edu cpu.interrupts[0].int_master = test_sys.ruby._cpu_ports[i].slave 1839736Sandreas@sandberg.pp.se cpu.interrupts[0].int_slave = test_sys.ruby._cpu_ports[i].master 1848920Snilay@cs.wisc.edu 1853395Shsul@eecs.umich.edu else: 1865361Srstrong@cs.ucsd.edu if options.caches or options.l2cache: 1878920Snilay@cs.wisc.edu # By default the IOCache runs at the system clock 1888920Snilay@cs.wisc.edu test_sys.iocache = IOCache(addr_ranges = test_sys.mem_ranges) 1898920Snilay@cs.wisc.edu test_sys.iocache.cpu_side = test_sys.iobus.master 1909151Satgutier@umich.edu test_sys.iocache.mem_side = test_sys.membus.slave 1919151Satgutier@umich.edu elif not options.external_memory_system: 1929151Satgutier@umich.edu test_sys.iobridge = Bridge(delay='50ns', ranges = test_sys.mem_ranges) 1939151Satgutier@umich.edu test_sys.iobridge.slave = test_sys.iobus.master 1949151Satgutier@umich.edu test_sys.iobridge.master = test_sys.membus.slave 1959151Satgutier@umich.edu 1969562Ssaidi@eecs.umich.edu # Sanity check 1978920Snilay@cs.wisc.edu if options.fastmem: 1988920Snilay@cs.wisc.edu if TestCPUClass != AtomicSimpleCPU: 1998920Snilay@cs.wisc.edu fatal("Fastmem can only be used with atomic CPU!") 2008920Snilay@cs.wisc.edu if (options.caches or options.l2cache): 2018920Snilay@cs.wisc.edu fatal("You cannot use fastmem in combination with caches!") 2028920Snilay@cs.wisc.edu 2038920Snilay@cs.wisc.edu if options.simpoint_profile: 2048920Snilay@cs.wisc.edu if not options.fastmem: 2058920Snilay@cs.wisc.edu # Atomic CPU checked with fastmem option already 2068920Snilay@cs.wisc.edu fatal("SimPoint generation should be done with atomic cpu and fastmem") 2078920Snilay@cs.wisc.edu if np > 1: 2088920Snilay@cs.wisc.edu fatal("SimPoint generation not supported with more than one CPUs") 2098920Snilay@cs.wisc.edu 2108920Snilay@cs.wisc.edu for i in xrange(np): 2118920Snilay@cs.wisc.edu if options.fastmem: 2128920Snilay@cs.wisc.edu test_sys.cpu[i].fastmem = True 2138920Snilay@cs.wisc.edu if options.simpoint_profile: 21410037SARM gem5 Developers test_sys.cpu[i].addSimPointProbe(options.simpoint_interval) 21510037SARM gem5 Developers if options.checker: 21610037SARM gem5 Developers test_sys.cpu[i].addCheckerCpu() 21710037SARM gem5 Developers test_sys.cpu[i].createThreads() 21810037SARM gem5 Developers 21910037SARM gem5 Developers # If elastic tracing is enabled when not restoring from checkpoint and 22010037SARM gem5 Developers # when not fast forwarding using the atomic cpu, then check that the 22110037SARM gem5 Developers # TestCPUClass is DerivO3CPU or inherits from DerivO3CPU. If the check 2228920Snilay@cs.wisc.edu # passes then attach the elastic trace probe. 2238920Snilay@cs.wisc.edu # If restoring from checkpoint or fast forwarding, the code that does this for 2248920Snilay@cs.wisc.edu # FutureCPUClass is in the Simulation module. If the check passes then the 2258920Snilay@cs.wisc.edu # elastic trace probe is attached to the switch CPUs. 2268920Snilay@cs.wisc.edu if options.elastic_trace_en and options.checkpoint_restore == None and \ 2278920Snilay@cs.wisc.edu not options.fast_forward: 2288920Snilay@cs.wisc.edu CpuConfig.config_etrace(TestCPUClass, test_sys.cpu, options) 2298920Snilay@cs.wisc.edu 2308920Snilay@cs.wisc.edu CacheConfig.config_cache(options, test_sys) 2318920Snilay@cs.wisc.edu 2328920Snilay@cs.wisc.edu MemConfig.config_mem(options, test_sys) 2338920Snilay@cs.wisc.edu 2348920Snilay@cs.wisc.edu return test_sys 2358920Snilay@cs.wisc.edu 2368920Snilay@cs.wisc.edudef build_drive_system(np): 2378920Snilay@cs.wisc.edu # driver system CPU is always simple, so is the memory 2388920Snilay@cs.wisc.edu # Note this is an assignment of a class, not an instance. 2398920Snilay@cs.wisc.edu DriveCPUClass = AtomicSimpleCPU 2408920Snilay@cs.wisc.edu drive_mem_mode = 'atomic' 2418920Snilay@cs.wisc.edu DriveMemClass = SimpleMemory 2428920Snilay@cs.wisc.edu 2438920Snilay@cs.wisc.edu cmdline = cmd_line_template() 2448920Snilay@cs.wisc.edu if buildEnv['TARGET_ISA'] == 'alpha': 2458920Snilay@cs.wisc.edu drive_sys = makeLinuxAlphaSystem(drive_mem_mode, bm[1], cmdline=cmdline) 2468920Snilay@cs.wisc.edu elif buildEnv['TARGET_ISA'] == 'mips': 2478920Snilay@cs.wisc.edu drive_sys = makeLinuxMipsSystem(drive_mem_mode, bm[1], cmdline=cmdline) 2488920Snilay@cs.wisc.edu elif buildEnv['TARGET_ISA'] == 'sparc': 2498920Snilay@cs.wisc.edu drive_sys = makeSparcSystem(drive_mem_mode, bm[1], cmdline=cmdline) 2508920Snilay@cs.wisc.edu elif buildEnv['TARGET_ISA'] == 'x86': 2518920Snilay@cs.wisc.edu drive_sys = makeLinuxX86System(drive_mem_mode, np, bm[1], 2528920Snilay@cs.wisc.edu cmdline=cmdline) 25310512SAli.Saidi@ARM.com elif buildEnv['TARGET_ISA'] == 'arm': 2549539Satgutier@umich.edu drive_sys = makeArmSystem(drive_mem_mode, options.machine_type, np, 2559539Satgutier@umich.edu bm[1], options.dtb_filename, cmdline=cmdline) 2569539Satgutier@umich.edu 2579935Sdam.sunwoo@arm.com # Create a top-level voltage domain 2589935Sdam.sunwoo@arm.com drive_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage) 2599935Sdam.sunwoo@arm.com 2609935Sdam.sunwoo@arm.com # Create a source clock for the system and set the clock period 2618920Snilay@cs.wisc.edu drive_sys.clk_domain = SrcClockDomain(clock = options.sys_clock, 2628920Snilay@cs.wisc.edu voltage_domain = drive_sys.voltage_domain) 2638920Snilay@cs.wisc.edu 2648920Snilay@cs.wisc.edu # Create a CPU voltage domain 2658920Snilay@cs.wisc.edu drive_sys.cpu_voltage_domain = VoltageDomain() 2668920Snilay@cs.wisc.edu 2678920Snilay@cs.wisc.edu # Create a source clock for the CPUs and set the clock period 2688920Snilay@cs.wisc.edu drive_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock, 2698920Snilay@cs.wisc.edu voltage_domain = 2708920Snilay@cs.wisc.edu drive_sys.cpu_voltage_domain) 2718920Snilay@cs.wisc.edu 2728920Snilay@cs.wisc.edu drive_sys.cpu = DriveCPUClass(clk_domain=drive_sys.cpu_clk_domain, 2738956Sjayneel@cs.wisc.edu cpu_id=0) 2748956Sjayneel@cs.wisc.edu drive_sys.cpu.createThreads() 2758956Sjayneel@cs.wisc.edu drive_sys.cpu.createInterruptController() 2768956Sjayneel@cs.wisc.edu drive_sys.cpu.connectAllPorts(drive_sys.membus) 27710697SCurtis.Dunham@arm.com if options.fastmem: 27810697SCurtis.Dunham@arm.com drive_sys.cpu.fastmem = True 27910594Sgabeblack@google.com if options.kernel is not None: 28010594Sgabeblack@google.com drive_sys.kernel = binary(options.kernel) 28110594Sgabeblack@google.com 28210594Sgabeblack@google.com if is_kvm_cpu(DriveCPUClass): 28310594Sgabeblack@google.com drive_sys.kvm_vm = KvmVM() 28410594Sgabeblack@google.com 28510594Sgabeblack@google.com drive_sys.iobridge = Bridge(delay='50ns', 28610594Sgabeblack@google.com ranges = drive_sys.mem_ranges) 287 drive_sys.iobridge.slave = drive_sys.iobus.master 288 drive_sys.iobridge.master = drive_sys.membus.slave 289 290 # Create the appropriate memory controllers and connect them to the 291 # memory bus 292 drive_sys.mem_ctrls = [DriveMemClass(range = r) 293 for r in drive_sys.mem_ranges] 294 for i in xrange(len(drive_sys.mem_ctrls)): 295 drive_sys.mem_ctrls[i].port = drive_sys.membus.master 296 297 drive_sys.init_param = options.init_param 298 299 return drive_sys 300 301# Add options 302parser = optparse.OptionParser() 303Options.addCommonOptions(parser) 304Options.addFSOptions(parser) 305 306# Add the ruby specific and protocol specific options 307if '--ruby' in sys.argv: 308 Ruby.define_options(parser) 309 310(options, args) = parser.parse_args() 311 312if args: 313 print "Error: script doesn't take any positional arguments" 314 sys.exit(1) 315 316# system under test can be any CPU 317(TestCPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options) 318 319# Match the memories with the CPUs, based on the options for the test system 320TestMemClass = Simulation.setMemClass(options) 321 322if options.benchmark: 323 try: 324 bm = Benchmarks[options.benchmark] 325 except KeyError: 326 print "Error benchmark %s has not been defined." % options.benchmark 327 print "Valid benchmarks are: %s" % DefinedBenchmarks 328 sys.exit(1) 329else: 330 if options.dual: 331 bm = [SysConfig(disk=options.disk_image, rootdev=options.root_device, 332 mem=options.mem_size, os_type=options.os_type), 333 SysConfig(disk=options.disk_image, rootdev=options.root_device, 334 mem=options.mem_size, os_type=options.os_type)] 335 else: 336 bm = [SysConfig(disk=options.disk_image, rootdev=options.root_device, 337 mem=options.mem_size, os_type=options.os_type)] 338 339np = options.num_cpus 340 341test_sys = build_test_system(np) 342if len(bm) == 2: 343 drive_sys = build_drive_system(np) 344 root = makeDualRoot(True, test_sys, drive_sys, options.etherdump) 345elif len(bm) == 1 and options.dist: 346 # This system is part of a dist-gem5 simulation 347 root = makeDistRoot(test_sys, 348 options.dist_rank, 349 options.dist_size, 350 options.dist_server_name, 351 options.dist_server_port, 352 options.dist_sync_repeat, 353 options.dist_sync_start, 354 options.ethernet_linkspeed, 355 options.ethernet_linkdelay, 356 options.etherdump); 357elif len(bm) == 1: 358 root = Root(full_system=True, system=test_sys) 359else: 360 print "Error I don't know how to create more than 2 systems." 361 sys.exit(1) 362 363if options.timesync: 364 root.time_sync_enable = True 365 366if options.frame_capture: 367 VncServer.frame_capture = True 368 369Simulation.setWorkCountOptions(test_sys, options) 370Simulation.run(options, root, test_sys, FutureClass) 371