fs.py revision 11839
110152Satgutier@umich.edu# Copyright (c) 2010-2013, 2016 ARM Limited 210152Satgutier@umich.edu# All rights reserved. 310152Satgutier@umich.edu# 410152Satgutier@umich.edu# The license below extends only to copyright in the software and shall 510234Syasuko.eckert@amd.com# not be construed as granting a license to any other intellectual 610152Satgutier@umich.edu# property including but not limited to intellectual property relating 710152Satgutier@umich.edu# to a hardware implementation of the functionality of the software 810152Satgutier@umich.edu# licensed hereunder. You may use the software subject to the license 910152Satgutier@umich.edu# terms below provided that you ensure that this notice is replicated 1010152Satgutier@umich.edu# unmodified and in its entirety in all distributions of the software, 1110152Satgutier@umich.edu# modified or unmodified, in source code or in binary form. 1210152Satgutier@umich.edu# 1310152Satgutier@umich.edu# Copyright (c) 2012-2014 Mark D. Hill and David A. Wood 1410152Satgutier@umich.edu# Copyright (c) 2009-2011 Advanced Micro Devices, Inc. 1510152Satgutier@umich.edu# Copyright (c) 2006-2007 The Regents of The University of Michigan 1610152Satgutier@umich.edu# All rights reserved. 1710152Satgutier@umich.edu# 1810152Satgutier@umich.edu# Redistribution and use in source and binary forms, with or without 1910152Satgutier@umich.edu# modification, are permitted provided that the following conditions are 2010152Satgutier@umich.edu# met: redistributions of source code must retain the above copyright 2110152Satgutier@umich.edu# notice, this list of conditions and the following disclaimer; 2210152Satgutier@umich.edu# redistributions in binary form must reproduce the above copyright 2310152Satgutier@umich.edu# notice, this list of conditions and the following disclaimer in the 2410152Satgutier@umich.edu# documentation and/or other materials provided with the distribution; 2510152Satgutier@umich.edu# neither the name of the copyright holders nor the names of its 2610152Satgutier@umich.edu# contributors may be used to endorse or promote products derived from 2710152Satgutier@umich.edu# this software without specific prior written permission. 2810152Satgutier@umich.edu# 2910234Syasuko.eckert@amd.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 3010152Satgutier@umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 3110152Satgutier@umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 3210152Satgutier@umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 3310152Satgutier@umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3410152Satgutier@umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3510152Satgutier@umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3610152Satgutier@umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3710152Satgutier@umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3810152Satgutier@umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3910152Satgutier@umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 4010152Satgutier@umich.edu# 4110152Satgutier@umich.edu# Authors: Ali Saidi 4210152Satgutier@umich.edu# Brad Beckmann 4310152Satgutier@umich.edu 4410152Satgutier@umich.eduimport optparse 4510152Satgutier@umich.eduimport sys 4610152Satgutier@umich.edu 4710152Satgutier@umich.eduimport m5 4810152Satgutier@umich.edufrom m5.defines import buildEnv 4910152Satgutier@umich.edufrom m5.objects import * 5010152Satgutier@umich.edufrom m5.util import addToPath, fatal 5110152Satgutier@umich.edu 5210152Satgutier@umich.eduaddToPath('../') 5310152Satgutier@umich.edu 5410234Syasuko.eckert@amd.comfrom ruby import Ruby 5510234Syasuko.eckert@amd.com 5610152Satgutier@umich.edufrom common.FSConfig import * 5710152Satgutier@umich.edufrom common.SysPaths import * 5810152Satgutier@umich.edufrom common.Benchmarks import * 5910152Satgutier@umich.edufrom common import Simulation 6010152Satgutier@umich.edufrom common import CacheConfig 6110152Satgutier@umich.edufrom common import MemConfig 6210152Satgutier@umich.edufrom common import CpuConfig 6310234Syasuko.eckert@amd.comfrom common.Caches import * 6410234Syasuko.eckert@amd.comfrom common import Options 6510152Satgutier@umich.edu 6610234Syasuko.eckert@amd.com 6710234Syasuko.eckert@amd.com# Check if KVM support has been enabled, we might need to do VM 6810234Syasuko.eckert@amd.com# configuration if that's the case. 6910234Syasuko.eckert@amd.comhave_kvm_support = 'BaseKvmCPU' in globals() 7010234Syasuko.eckert@amd.comdef is_kvm_cpu(cpu_class): 7110234Syasuko.eckert@amd.com return have_kvm_support and cpu_class != None and \ 7210234Syasuko.eckert@amd.com issubclass(cpu_class, BaseKvmCPU) 7310234Syasuko.eckert@amd.com 7410234Syasuko.eckert@amd.comdef cmd_line_template(): 7510234Syasuko.eckert@amd.com if options.command_line and options.command_line_file: 7610234Syasuko.eckert@amd.com print "Error: --command-line and --command-line-file are " \ 7710234Syasuko.eckert@amd.com "mutually exclusive" 7810234Syasuko.eckert@amd.com sys.exit(1) 7910234Syasuko.eckert@amd.com if options.command_line: 8010234Syasuko.eckert@amd.com return options.command_line 8110152Satgutier@umich.edu if options.command_line_file: 8210152Satgutier@umich.edu return open(options.command_line_file).read().strip() 8310152Satgutier@umich.edu return None 8410152Satgutier@umich.edu 8510152Satgutier@umich.edudef build_test_system(np): 8610152Satgutier@umich.edu cmdline = cmd_line_template() 8710152Satgutier@umich.edu if buildEnv['TARGET_ISA'] == "alpha": 8810234Syasuko.eckert@amd.com test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0], options.ruby, 8910234Syasuko.eckert@amd.com cmdline=cmdline) 9010152Satgutier@umich.edu elif buildEnv['TARGET_ISA'] == "mips": 9110152Satgutier@umich.edu test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0], cmdline=cmdline) 9210152Satgutier@umich.edu elif buildEnv['TARGET_ISA'] == "sparc": 9310152Satgutier@umich.edu test_sys = makeSparcSystem(test_mem_mode, bm[0], cmdline=cmdline) 9410152Satgutier@umich.edu elif buildEnv['TARGET_ISA'] == "x86": 9510234Syasuko.eckert@amd.com test_sys = makeLinuxX86System(test_mem_mode, options.num_cpus, bm[0], 9610234Syasuko.eckert@amd.com options.ruby, cmdline=cmdline) 9710234Syasuko.eckert@amd.com elif buildEnv['TARGET_ISA'] == "arm": 9810234Syasuko.eckert@amd.com test_sys = makeArmSystem(test_mem_mode, options.machine_type, 9910234Syasuko.eckert@amd.com options.num_cpus, bm[0], options.dtb_filename, 10010152Satgutier@umich.edu bare_metal=options.bare_metal, 10110152Satgutier@umich.edu cmdline=cmdline, 10210152Satgutier@umich.edu external_memory=options.external_memory_system, 10310152Satgutier@umich.edu ruby=options.ruby) 10410152Satgutier@umich.edu if options.enable_context_switch_stats_dump: 10510234Syasuko.eckert@amd.com test_sys.enable_context_switch_stats_dump = True 10610152Satgutier@umich.edu else: 10710152Satgutier@umich.edu fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA']) 10810152Satgutier@umich.edu 10910152Satgutier@umich.edu # Set the cache line size for the entire system 11010152Satgutier@umich.edu test_sys.cache_line_size = options.cacheline_size 11110152Satgutier@umich.edu 11210152Satgutier@umich.edu # Create a top-level voltage domain 11310152Satgutier@umich.edu test_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage) 11410152Satgutier@umich.edu 11510152Satgutier@umich.edu # Create a source clock for the system and set the clock period 11610152Satgutier@umich.edu test_sys.clk_domain = SrcClockDomain(clock = options.sys_clock, 11710152Satgutier@umich.edu voltage_domain = test_sys.voltage_domain) 11810152Satgutier@umich.edu 11910152Satgutier@umich.edu # Create a CPU voltage domain 12010234Syasuko.eckert@amd.com test_sys.cpu_voltage_domain = VoltageDomain() 12110234Syasuko.eckert@amd.com 12210152Satgutier@umich.edu # Create a source clock for the CPUs and set the clock period 12310152Satgutier@umich.edu test_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock, 12410234Syasuko.eckert@amd.com voltage_domain = 12510234Syasuko.eckert@amd.com test_sys.cpu_voltage_domain) 12610152Satgutier@umich.edu 12710152Satgutier@umich.edu if options.kernel is not None: 12810152Satgutier@umich.edu test_sys.kernel = binary(options.kernel) 12910152Satgutier@umich.edu 13010152Satgutier@umich.edu if options.script is not None: 13110152Satgutier@umich.edu test_sys.readfile = options.script 13210152Satgutier@umich.edu 13310152Satgutier@umich.edu if options.lpae: 13410152Satgutier@umich.edu test_sys.have_lpae = True 13510152Satgutier@umich.edu 13610152Satgutier@umich.edu if options.virtualisation: 13710152Satgutier@umich.edu test_sys.have_virtualization = True 13810152Satgutier@umich.edu 13910152Satgutier@umich.edu test_sys.init_param = options.init_param 14010152Satgutier@umich.edu 14110152Satgutier@umich.edu # For now, assign all the CPUs to the same clock domain 14210152Satgutier@umich.edu test_sys.cpu = [TestCPUClass(clk_domain=test_sys.cpu_clk_domain, cpu_id=i) 14310152Satgutier@umich.edu for i in xrange(np)] 14410152Satgutier@umich.edu 14510152Satgutier@umich.edu if is_kvm_cpu(TestCPUClass) or is_kvm_cpu(FutureClass): 14610152Satgutier@umich.edu test_sys.kvm_vm = KvmVM() 14710152Satgutier@umich.edu 14810152Satgutier@umich.edu if options.ruby: 14910152Satgutier@umich.edu # Check for timing mode because ruby does not support atomic accesses 15010152Satgutier@umich.edu if not (options.cpu_type == "detailed" or options.cpu_type == "timing"): 15110152Satgutier@umich.edu print >> sys.stderr, "Ruby requires TimingSimpleCPU or O3CPU!!" 15210152Satgutier@umich.edu sys.exit(1) 15310152Satgutier@umich.edu 15410152Satgutier@umich.edu Ruby.create_system(options, True, test_sys, test_sys.iobus, 15510152Satgutier@umich.edu test_sys._dma_ports) 15610152Satgutier@umich.edu 15710152Satgutier@umich.edu # Create a seperate clock domain for Ruby 15810152Satgutier@umich.edu test_sys.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock, 15910152Satgutier@umich.edu voltage_domain = test_sys.voltage_domain) 16010152Satgutier@umich.edu 16110152Satgutier@umich.edu # Connect the ruby io port to the PIO bus, 16210152Satgutier@umich.edu # assuming that there is just one such port. 16310152Satgutier@umich.edu test_sys.iobus.master = test_sys.ruby._io_port.slave 16410152Satgutier@umich.edu 16510152Satgutier@umich.edu for (i, cpu) in enumerate(test_sys.cpu): 16610152Satgutier@umich.edu # 16710152Satgutier@umich.edu # Tie the cpu ports to the correct ruby system ports 16810152Satgutier@umich.edu # 16910152Satgutier@umich.edu cpu.clk_domain = test_sys.cpu_clk_domain 17010152Satgutier@umich.edu cpu.createThreads() 17110152Satgutier@umich.edu cpu.createInterruptController() 17210152Satgutier@umich.edu 17310152Satgutier@umich.edu cpu.icache_port = test_sys.ruby._cpu_ports[i].slave 17410152Satgutier@umich.edu cpu.dcache_port = test_sys.ruby._cpu_ports[i].slave 17510152Satgutier@umich.edu 17610152Satgutier@umich.edu if buildEnv['TARGET_ISA'] in ("x86", "arm"): 17710152Satgutier@umich.edu cpu.itb.walker.port = test_sys.ruby._cpu_ports[i].slave 17810152Satgutier@umich.edu cpu.dtb.walker.port = test_sys.ruby._cpu_ports[i].slave 17910152Satgutier@umich.edu 18010152Satgutier@umich.edu if buildEnv['TARGET_ISA'] in "x86": 18110152Satgutier@umich.edu cpu.interrupts[0].pio = test_sys.ruby._cpu_ports[i].master 18210152Satgutier@umich.edu cpu.interrupts[0].int_master = test_sys.ruby._cpu_ports[i].slave 18310152Satgutier@umich.edu cpu.interrupts[0].int_slave = test_sys.ruby._cpu_ports[i].master 18410234Syasuko.eckert@amd.com 18510152Satgutier@umich.edu else: 18610234Syasuko.eckert@amd.com if options.caches or options.l2cache: 18710152Satgutier@umich.edu # By default the IOCache runs at the system clock 18810152Satgutier@umich.edu test_sys.iocache = IOCache(addr_ranges = test_sys.mem_ranges) 18910234Syasuko.eckert@amd.com test_sys.iocache.cpu_side = test_sys.iobus.master 19010152Satgutier@umich.edu test_sys.iocache.mem_side = test_sys.membus.slave 19110234Syasuko.eckert@amd.com elif not options.external_memory_system: 19210152Satgutier@umich.edu test_sys.iobridge = Bridge(delay='50ns', ranges = test_sys.mem_ranges) 19310152Satgutier@umich.edu test_sys.iobridge.slave = test_sys.iobus.master 19410152Satgutier@umich.edu test_sys.iobridge.master = test_sys.membus.slave 19510152Satgutier@umich.edu 19610152Satgutier@umich.edu # Sanity check 19710152Satgutier@umich.edu if options.fastmem: 19810152Satgutier@umich.edu if TestCPUClass != AtomicSimpleCPU: 19910152Satgutier@umich.edu fatal("Fastmem can only be used with atomic CPU!") 20010152Satgutier@umich.edu if (options.caches or options.l2cache): 20110152Satgutier@umich.edu fatal("You cannot use fastmem in combination with caches!") 20210152Satgutier@umich.edu 20310152Satgutier@umich.edu if options.simpoint_profile: 20410152Satgutier@umich.edu if not options.fastmem: 20510152Satgutier@umich.edu # Atomic CPU checked with fastmem option already 20610234Syasuko.eckert@amd.com fatal("SimPoint generation should be done with atomic cpu and fastmem") 20710234Syasuko.eckert@amd.com if np > 1: 20810234Syasuko.eckert@amd.com fatal("SimPoint generation not supported with more than one CPUs") 20910234Syasuko.eckert@amd.com 21010234Syasuko.eckert@amd.com for i in xrange(np): 21110234Syasuko.eckert@amd.com if options.fastmem: 21210234Syasuko.eckert@amd.com test_sys.cpu[i].fastmem = True 21310152Satgutier@umich.edu if options.simpoint_profile: 21410152Satgutier@umich.edu test_sys.cpu[i].addSimPointProbe(options.simpoint_interval) 21510152Satgutier@umich.edu if options.checker: 21610234Syasuko.eckert@amd.com test_sys.cpu[i].addCheckerCpu() 21710234Syasuko.eckert@amd.com test_sys.cpu[i].createThreads() 21810234Syasuko.eckert@amd.com 21910234Syasuko.eckert@amd.com # If elastic tracing is enabled when not restoring from checkpoint and 22010234Syasuko.eckert@amd.com # when not fast forwarding using the atomic cpu, then check that the 22110234Syasuko.eckert@amd.com # TestCPUClass is DerivO3CPU or inherits from DerivO3CPU. If the check 22210234Syasuko.eckert@amd.com # passes then attach the elastic trace probe. 22310234Syasuko.eckert@amd.com # If restoring from checkpoint or fast forwarding, the code that does this for 22410234Syasuko.eckert@amd.com # FutureCPUClass is in the Simulation module. If the check passes then the 22510234Syasuko.eckert@amd.com # elastic trace probe is attached to the switch CPUs. 22610234Syasuko.eckert@amd.com if options.elastic_trace_en and options.checkpoint_restore == None and \ 22710234Syasuko.eckert@amd.com not options.fast_forward: 22810234Syasuko.eckert@amd.com CpuConfig.config_etrace(TestCPUClass, test_sys.cpu, options) 22910234Syasuko.eckert@amd.com 23010234Syasuko.eckert@amd.com CacheConfig.config_cache(options, test_sys) 23110234Syasuko.eckert@amd.com 23210234Syasuko.eckert@amd.com MemConfig.config_mem(options, test_sys) 23310234Syasuko.eckert@amd.com 23410234Syasuko.eckert@amd.com return test_sys 23510234Syasuko.eckert@amd.com 23610234Syasuko.eckert@amd.comdef build_drive_system(np): 23710234Syasuko.eckert@amd.com # driver system CPU is always simple, so is the memory 23810234Syasuko.eckert@amd.com # Note this is an assignment of a class, not an instance. 23910234Syasuko.eckert@amd.com DriveCPUClass = AtomicSimpleCPU 24010234Syasuko.eckert@amd.com drive_mem_mode = 'atomic' 24110234Syasuko.eckert@amd.com DriveMemClass = SimpleMemory 24210234Syasuko.eckert@amd.com 24310234Syasuko.eckert@amd.com cmdline = cmd_line_template() 24410234Syasuko.eckert@amd.com if buildEnv['TARGET_ISA'] == 'alpha': 24510234Syasuko.eckert@amd.com drive_sys = makeLinuxAlphaSystem(drive_mem_mode, bm[1], cmdline=cmdline) 24610234Syasuko.eckert@amd.com elif buildEnv['TARGET_ISA'] == 'mips': 24710234Syasuko.eckert@amd.com drive_sys = makeLinuxMipsSystem(drive_mem_mode, bm[1], cmdline=cmdline) 24810234Syasuko.eckert@amd.com elif buildEnv['TARGET_ISA'] == 'sparc': 24910234Syasuko.eckert@amd.com drive_sys = makeSparcSystem(drive_mem_mode, bm[1], cmdline=cmdline) 25010234Syasuko.eckert@amd.com elif buildEnv['TARGET_ISA'] == 'x86': 25110234Syasuko.eckert@amd.com drive_sys = makeLinuxX86System(drive_mem_mode, np, bm[1], 25210234Syasuko.eckert@amd.com cmdline=cmdline) 25310234Syasuko.eckert@amd.com elif buildEnv['TARGET_ISA'] == 'arm': 25410234Syasuko.eckert@amd.com drive_sys = makeArmSystem(drive_mem_mode, options.machine_type, np, 25510234Syasuko.eckert@amd.com bm[1], options.dtb_filename, cmdline=cmdline) 25610234Syasuko.eckert@amd.com 25710234Syasuko.eckert@amd.com # Create a top-level voltage domain 25810234Syasuko.eckert@amd.com drive_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage) 25910234Syasuko.eckert@amd.com 26010234Syasuko.eckert@amd.com # Create a source clock for the system and set the clock period 26110234Syasuko.eckert@amd.com drive_sys.clk_domain = SrcClockDomain(clock = options.sys_clock, 26210234Syasuko.eckert@amd.com voltage_domain = drive_sys.voltage_domain) 26310234Syasuko.eckert@amd.com 26410234Syasuko.eckert@amd.com # Create a CPU voltage domain 26510234Syasuko.eckert@amd.com drive_sys.cpu_voltage_domain = VoltageDomain() 26610234Syasuko.eckert@amd.com 26710234Syasuko.eckert@amd.com # Create a source clock for the CPUs and set the clock period 26810234Syasuko.eckert@amd.com drive_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock, 26910234Syasuko.eckert@amd.com voltage_domain = 27010234Syasuko.eckert@amd.com drive_sys.cpu_voltage_domain) 27110234Syasuko.eckert@amd.com 27210234Syasuko.eckert@amd.com drive_sys.cpu = DriveCPUClass(clk_domain=drive_sys.cpu_clk_domain, 27310234Syasuko.eckert@amd.com cpu_id=0) 27410234Syasuko.eckert@amd.com drive_sys.cpu.createThreads() 27510234Syasuko.eckert@amd.com drive_sys.cpu.createInterruptController() 27610234Syasuko.eckert@amd.com drive_sys.cpu.connectAllPorts(drive_sys.membus) 27710234Syasuko.eckert@amd.com if options.fastmem: 27810234Syasuko.eckert@amd.com drive_sys.cpu.fastmem = True 27910234Syasuko.eckert@amd.com if options.kernel is not None: 28010234Syasuko.eckert@amd.com drive_sys.kernel = binary(options.kernel) 28110234Syasuko.eckert@amd.com 28210234Syasuko.eckert@amd.com if is_kvm_cpu(DriveCPUClass): 28310234Syasuko.eckert@amd.com drive_sys.kvm_vm = KvmVM() 28410234Syasuko.eckert@amd.com 28510234Syasuko.eckert@amd.com drive_sys.iobridge = Bridge(delay='50ns', 28610234Syasuko.eckert@amd.com ranges = drive_sys.mem_ranges) 28710234Syasuko.eckert@amd.com drive_sys.iobridge.slave = drive_sys.iobus.master 28810234Syasuko.eckert@amd.com drive_sys.iobridge.master = drive_sys.membus.slave 28910234Syasuko.eckert@amd.com 29010234Syasuko.eckert@amd.com # Create the appropriate memory controllers and connect them to the 29110234Syasuko.eckert@amd.com # memory bus 29210234Syasuko.eckert@amd.com drive_sys.mem_ctrls = [DriveMemClass(range = r) 29310234Syasuko.eckert@amd.com for r in drive_sys.mem_ranges] 29410234Syasuko.eckert@amd.com for i in xrange(len(drive_sys.mem_ctrls)): 29510234Syasuko.eckert@amd.com drive_sys.mem_ctrls[i].port = drive_sys.membus.master 29610234Syasuko.eckert@amd.com 29710234Syasuko.eckert@amd.com drive_sys.init_param = options.init_param 29810234Syasuko.eckert@amd.com 29910234Syasuko.eckert@amd.com return drive_sys 30010234Syasuko.eckert@amd.com 30110234Syasuko.eckert@amd.com# Add options 30210234Syasuko.eckert@amd.comparser = optparse.OptionParser() 30310234Syasuko.eckert@amd.comOptions.addCommonOptions(parser) 30410234Syasuko.eckert@amd.comOptions.addFSOptions(parser) 30510234Syasuko.eckert@amd.com 30610234Syasuko.eckert@amd.com# Add the ruby specific and protocol specific options 30710234Syasuko.eckert@amd.comif '--ruby' in sys.argv: 30810152Satgutier@umich.edu Ruby.define_options(parser) 30910152Satgutier@umich.edu 31010152Satgutier@umich.edu(options, args) = parser.parse_args() 31110234Syasuko.eckert@amd.com 31210234Syasuko.eckert@amd.comif args: 31310152Satgutier@umich.edu print "Error: script doesn't take any positional arguments" 31410152Satgutier@umich.edu sys.exit(1) 31510152Satgutier@umich.edu 31610152Satgutier@umich.edu# system under test can be any CPU 31710152Satgutier@umich.edu(TestCPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options) 31810152Satgutier@umich.edu 31910152Satgutier@umich.edu# Match the memories with the CPUs, based on the options for the test system 32010152Satgutier@umich.eduTestMemClass = Simulation.setMemClass(options) 32110152Satgutier@umich.edu 32210152Satgutier@umich.eduif options.benchmark: 32310152Satgutier@umich.edu try: 32410152Satgutier@umich.edu bm = Benchmarks[options.benchmark] 32510152Satgutier@umich.edu except KeyError: 32610152Satgutier@umich.edu print "Error benchmark %s has not been defined." % options.benchmark 32710152Satgutier@umich.edu print "Valid benchmarks are: %s" % DefinedBenchmarks 32810152Satgutier@umich.edu sys.exit(1) 32910152Satgutier@umich.eduelse: 33010152Satgutier@umich.edu if options.dual: 33110152Satgutier@umich.edu bm = [SysConfig(disk=options.disk_image, rootdev=options.root_device, 33210152Satgutier@umich.edu mem=options.mem_size, os_type=options.os_type), 33310152Satgutier@umich.edu SysConfig(disk=options.disk_image, rootdev=options.root_device, 33410152Satgutier@umich.edu mem=options.mem_size, os_type=options.os_type)] 33510152Satgutier@umich.edu else: 33610234Syasuko.eckert@amd.com bm = [SysConfig(disk=options.disk_image, rootdev=options.root_device, 33710152Satgutier@umich.edu mem=options.mem_size, os_type=options.os_type)] 33810152Satgutier@umich.edu 33910152Satgutier@umich.edunp = options.num_cpus 34010152Satgutier@umich.edu 34110152Satgutier@umich.edutest_sys = build_test_system(np) 34210152Satgutier@umich.eduif len(bm) == 2: 34310152Satgutier@umich.edu drive_sys = build_drive_system(np) 34410152Satgutier@umich.edu root = makeDualRoot(True, test_sys, drive_sys, options.etherdump) 34510234Syasuko.eckert@amd.comelif len(bm) == 1 and options.dist: 34610234Syasuko.eckert@amd.com # This system is part of a dist-gem5 simulation 34710152Satgutier@umich.edu root = makeDistRoot(test_sys, 34810152Satgutier@umich.edu options.dist_rank, 34910234Syasuko.eckert@amd.com options.dist_size, 35010234Syasuko.eckert@amd.com options.dist_server_name, 35110234Syasuko.eckert@amd.com options.dist_server_port, 35210234Syasuko.eckert@amd.com options.dist_sync_repeat, 35310234Syasuko.eckert@amd.com options.dist_sync_start, 35410234Syasuko.eckert@amd.com options.ethernet_linkspeed, 35510234Syasuko.eckert@amd.com options.ethernet_linkdelay, 35610234Syasuko.eckert@amd.com options.etherdump); 35710234Syasuko.eckert@amd.comelif len(bm) == 1: 35810234Syasuko.eckert@amd.com root = Root(full_system=True, system=test_sys) 35910234Syasuko.eckert@amd.comelse: 36010234Syasuko.eckert@amd.com print "Error I don't know how to create more than 2 systems." 36110234Syasuko.eckert@amd.com sys.exit(1) 36210234Syasuko.eckert@amd.com 36310234Syasuko.eckert@amd.comif options.timesync: 36410234Syasuko.eckert@amd.com root.time_sync_enable = True 36510234Syasuko.eckert@amd.com 36610234Syasuko.eckert@amd.comif options.frame_capture: 36710234Syasuko.eckert@amd.com VncServer.frame_capture = True 36810234Syasuko.eckert@amd.com 36910234Syasuko.eckert@amd.comSimulation.setWorkCountOptions(test_sys, options) 37010234Syasuko.eckert@amd.comSimulation.run(options, root, test_sys, FutureClass) 37110234Syasuko.eckert@amd.com