Caches.py revision 13774
19288Sandreas.hansson@arm.com# Copyright (c) 2012 ARM Limited 29288Sandreas.hansson@arm.com# All rights reserved. 39288Sandreas.hansson@arm.com# 49288Sandreas.hansson@arm.com# The license below extends only to copyright in the software and shall 59288Sandreas.hansson@arm.com# not be construed as granting a license to any other intellectual 69288Sandreas.hansson@arm.com# property including but not limited to intellectual property relating 79288Sandreas.hansson@arm.com# to a hardware implementation of the functionality of the software 89288Sandreas.hansson@arm.com# licensed hereunder. You may use the software subject to the license 99288Sandreas.hansson@arm.com# terms below provided that you ensure that this notice is replicated 109288Sandreas.hansson@arm.com# unmodified and in its entirety in all distributions of the software, 119288Sandreas.hansson@arm.com# modified or unmodified, in source code or in binary form. 129288Sandreas.hansson@arm.com# 134444Ssaidi@eecs.umich.edu# Copyright (c) 2006-2007 The Regents of The University of Michigan 143395Shsul@eecs.umich.edu# All rights reserved. 153395Shsul@eecs.umich.edu# 163395Shsul@eecs.umich.edu# Redistribution and use in source and binary forms, with or without 173395Shsul@eecs.umich.edu# modification, are permitted provided that the following conditions are 183395Shsul@eecs.umich.edu# met: redistributions of source code must retain the above copyright 193395Shsul@eecs.umich.edu# notice, this list of conditions and the following disclaimer; 203395Shsul@eecs.umich.edu# redistributions in binary form must reproduce the above copyright 213395Shsul@eecs.umich.edu# notice, this list of conditions and the following disclaimer in the 223395Shsul@eecs.umich.edu# documentation and/or other materials provided with the distribution; 233395Shsul@eecs.umich.edu# neither the name of the copyright holders nor the names of its 243395Shsul@eecs.umich.edu# contributors may be used to endorse or promote products derived from 253395Shsul@eecs.umich.edu# this software without specific prior written permission. 263395Shsul@eecs.umich.edu# 273395Shsul@eecs.umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 283395Shsul@eecs.umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 293395Shsul@eecs.umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 303395Shsul@eecs.umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 313395Shsul@eecs.umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 323395Shsul@eecs.umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 333395Shsul@eecs.umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 343395Shsul@eecs.umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 353395Shsul@eecs.umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 363395Shsul@eecs.umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 373395Shsul@eecs.umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 383395Shsul@eecs.umich.edu# 393395Shsul@eecs.umich.edu# Authors: Lisa Hsu 403395Shsul@eecs.umich.edu 4113774Sandreas.sandberg@arm.comfrom __future__ import print_function 4213774Sandreas.sandberg@arm.comfrom __future__ import absolute_import 4313774Sandreas.sandberg@arm.com 4411763Sandreas.sandberg@arm.comfrom m5.defines import buildEnv 453395Shsul@eecs.umich.edufrom m5.objects import * 463395Shsul@eecs.umich.edu 479310Sandreas.hansson@arm.com# Base implementations of L1, L2, IO and TLB-walker caches. There are 489310Sandreas.hansson@arm.com# used in the regressions and also as base components in the 499310Sandreas.hansson@arm.com# system-configuration scripts. The values are meant to serve as a 509310Sandreas.hansson@arm.com# starting point, and specific parameters can be overridden in the 519310Sandreas.hansson@arm.com# specific instantiations. 529310Sandreas.hansson@arm.com 5311053Sandreas.hansson@arm.comclass L1Cache(Cache): 543395Shsul@eecs.umich.edu assoc = 2 5511722Ssophiane.senni@gmail.com tag_latency = 2 5611722Ssophiane.senni@gmail.com data_latency = 2 579288Sandreas.hansson@arm.com response_latency = 2 589310Sandreas.hansson@arm.com mshrs = 4 598631Schander.sudanthi@arm.com tgts_per_mshr = 20 603395Shsul@eecs.umich.edu 6110884Sandreas.hansson@arm.comclass L1_ICache(L1Cache): 6210884Sandreas.hansson@arm.com is_read_only = True 6311199Sandreas.hansson@arm.com # Writeback clean lines as well 6411199Sandreas.hansson@arm.com writeback_clean = True 6510884Sandreas.hansson@arm.com 6610884Sandreas.hansson@arm.comclass L1_DCache(L1Cache): 6710884Sandreas.hansson@arm.com pass 6810884Sandreas.hansson@arm.com 6911053Sandreas.hansson@arm.comclass L2Cache(Cache): 703668Srdreslin@umich.edu assoc = 8 7111722Ssophiane.senni@gmail.com tag_latency = 20 7211722Ssophiane.senni@gmail.com data_latency = 20 739288Sandreas.hansson@arm.com response_latency = 20 749321Sandreas.hansson@arm.com mshrs = 20 759321Sandreas.hansson@arm.com tgts_per_mshr = 12 769310Sandreas.hansson@arm.com write_buffers = 8 779310Sandreas.hansson@arm.com 7811053Sandreas.hansson@arm.comclass IOCache(Cache): 799310Sandreas.hansson@arm.com assoc = 8 8011722Ssophiane.senni@gmail.com tag_latency = 50 8111722Ssophiane.senni@gmail.com data_latency = 50 829310Sandreas.hansson@arm.com response_latency = 50 833668Srdreslin@umich.edu mshrs = 20 849310Sandreas.hansson@arm.com size = '1kB' 853668Srdreslin@umich.edu tgts_per_mshr = 12 863668Srdreslin@umich.edu 8711053Sandreas.hansson@arm.comclass PageTableWalkerCache(Cache): 887868Sgblack@eecs.umich.edu assoc = 2 8911722Ssophiane.senni@gmail.com tag_latency = 2 9011722Ssophiane.senni@gmail.com data_latency = 2 919288Sandreas.hansson@arm.com response_latency = 2 927868Sgblack@eecs.umich.edu mshrs = 10 937868Sgblack@eecs.umich.edu size = '1kB' 947868Sgblack@eecs.umich.edu tgts_per_mshr = 12 9511331Sandreas.hansson@arm.com 9610884Sandreas.hansson@arm.com # the x86 table walker actually writes to the table-walker cache 9710884Sandreas.hansson@arm.com if buildEnv['TARGET_ISA'] == 'x86': 9810884Sandreas.hansson@arm.com is_read_only = False 9910884Sandreas.hansson@arm.com else: 10010884Sandreas.hansson@arm.com is_read_only = True 10111199Sandreas.hansson@arm.com # Writeback clean lines as well 10211199Sandreas.hansson@arm.com writeback_clean = True 103