Caches.py revision 13774 
1# Copyright (c) 2012 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
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7# to a hardware implementation of the functionality of the software
8# licensed hereunder.  You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Copyright (c) 2006-2007 The Regents of The University of Michigan
14# All rights reserved.
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17# modification, are permitted provided that the following conditions are
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27# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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38#
39# Authors: Lisa Hsu
40
41from __future__ import print_function
42from __future__ import absolute_import
43
44from m5.defines import buildEnv
45from m5.objects import *
46
47# Base implementations of L1, L2, IO and TLB-walker caches. There are
48# used in the regressions and also as base components in the
49# system-configuration scripts. The values are meant to serve as a
50# starting point, and specific parameters can be overridden in the
51# specific instantiations.
52
53class L1Cache(Cache):
54    assoc = 2
55    tag_latency = 2
56    data_latency = 2
57    response_latency = 2
58    mshrs = 4
59    tgts_per_mshr = 20
60
61class L1_ICache(L1Cache):
62    is_read_only = True
63    # Writeback clean lines as well
64    writeback_clean = True
65
66class L1_DCache(L1Cache):
67    pass
68
69class L2Cache(Cache):
70    assoc = 8
71    tag_latency = 20
72    data_latency = 20
73    response_latency = 20
74    mshrs = 20
75    tgts_per_mshr = 12
76    write_buffers = 8
77
78class IOCache(Cache):
79    assoc = 8
80    tag_latency = 50
81    data_latency = 50
82    response_latency = 50
83    mshrs = 20
84    size = '1kB'
85    tgts_per_mshr = 12
86
87class PageTableWalkerCache(Cache):
88    assoc = 2
89    tag_latency = 2
90    data_latency = 2
91    response_latency = 2
92    mshrs = 10
93    size = '1kB'
94    tgts_per_mshr = 12
95
96    # the x86 table walker actually writes to the table-walker cache
97    if buildEnv['TARGET_ISA'] == 'x86':
98        is_read_only = False
99    else:
100        is_read_only = True
101        # Writeback clean lines as well
102        writeback_clean = True
103