xref: /gem5/configs/common/Caches.py

# Copyright (c) 2012 ARM Limited
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# Copyright (c) 2006-2007 The Regents of The University of Michigan
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# Authors: Lisa Hsu

from m5.objects import *

# Base implementations of L1, L2, IO and TLB-walker caches. There are
# used in the regressions and also as base components in the
# system-configuration scripts. The values are meant to serve as a
# starting point, and specific parameters can be overridden in the
# specific instantiations.

class L1Cache(Cache):
    assoc = 2
    hit_latency = 2
    response_latency = 2
    mshrs = 4
    tgts_per_mshr = 20

class L1_ICache(L1Cache):
    is_read_only = True
    # Writeback clean lines as well
    writeback_clean = True

class L1_DCache(L1Cache):
    pass

class L2Cache(Cache):
    assoc = 8
    hit_latency = 20
    response_latency = 20
    mshrs = 20
    tgts_per_mshr = 12
    write_buffers = 8

class IOCache(Cache):
    assoc = 8
    hit_latency = 50
    response_latency = 50
    mshrs = 20
    size = '1kB'
    tgts_per_mshr = 12
    forward_snoops = False

class PageTableWalkerCache(Cache):
    assoc = 2
    hit_latency = 2
    response_latency = 2
    mshrs = 10
    size = '1kB'
    tgts_per_mshr = 12
    forward_snoops = False
    # the x86 table walker actually writes to the table-walker cache
    if buildEnv['TARGET_ISA'] == 'x86':
        is_read_only = False
    else:
        is_read_only = True
        # Writeback clean lines as well
        writeback_clean = True