Caches.py revision 11199
1# Copyright (c) 2012 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license 9# terms below provided that you ensure that this notice is replicated 10# unmodified and in its entirety in all distributions of the software, 11# modified or unmodified, in source code or in binary form. 12# 13# Copyright (c) 2006-2007 The Regents of The University of Michigan 14# All rights reserved. 15# 16# Redistribution and use in source and binary forms, with or without 17# modification, are permitted provided that the following conditions are 18# met: redistributions of source code must retain the above copyright 19# notice, this list of conditions and the following disclaimer; 20# redistributions in binary form must reproduce the above copyright 21# notice, this list of conditions and the following disclaimer in the 22# documentation and/or other materials provided with the distribution; 23# neither the name of the copyright holders nor the names of its 24# contributors may be used to endorse or promote products derived from 25# this software without specific prior written permission. 26# 27# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 28# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 29# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 30# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 31# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 32# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 33# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 34# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 35# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 36# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 38# 39# Authors: Lisa Hsu 40 41from m5.objects import * 42 43# Base implementations of L1, L2, IO and TLB-walker caches. There are 44# used in the regressions and also as base components in the 45# system-configuration scripts. The values are meant to serve as a 46# starting point, and specific parameters can be overridden in the 47# specific instantiations. 48 49class L1Cache(Cache): 50 assoc = 2 51 hit_latency = 2 52 response_latency = 2 53 mshrs = 4 54 tgts_per_mshr = 20 55 56class L1_ICache(L1Cache): 57 is_read_only = True 58 # Writeback clean lines as well 59 writeback_clean = True 60 61class L1_DCache(L1Cache): 62 pass 63 64class L2Cache(Cache): 65 assoc = 8 66 hit_latency = 20 67 response_latency = 20 68 mshrs = 20 69 tgts_per_mshr = 12 70 write_buffers = 8 71 72class IOCache(Cache): 73 assoc = 8 74 hit_latency = 50 75 response_latency = 50 76 mshrs = 20 77 size = '1kB' 78 tgts_per_mshr = 12 79 forward_snoops = False 80 81class PageTableWalkerCache(Cache): 82 assoc = 2 83 hit_latency = 2 84 response_latency = 2 85 mshrs = 10 86 size = '1kB' 87 tgts_per_mshr = 12 88 forward_snoops = False 89 # the x86 table walker actually writes to the table-walker cache 90 if buildEnv['TARGET_ISA'] == 'x86': 91 is_read_only = False 92 else: 93 is_read_only = True 94 # Writeback clean lines as well 95 writeback_clean = True 96