/gem5/src/arch/x86/insts/ |
H A D | microfpop.cc | 59 std::stringstream response; local 61 printMnemonic(response, instMnem, mnemonic); 62 printDestReg(response, 0, dataSize); 63 response << ", "; 64 printSrcReg(response, 0, dataSize); 65 response << ", "; 66 printSrcReg(response, 1, dataSize); 67 return response.str();
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H A D | microldstop.cc | 50 std::stringstream response; local 52 printMnemonic(response, instMnem, mnemonic); 54 printDestReg(response, 0, dataSize); 56 printSrcReg(response, 2, dataSize); 57 response << ", "; 58 printMem(response, segment, scale, index, base, disp, 60 return response.str(); 66 std::stringstream response; local 68 printMnemonic(response, instMnem, mnemonic); 70 response << "["; [all...] |
H A D | micromediaop.cc | 42 std::stringstream response; local 44 printMnemonic(response, instMnem, mnemonic); 45 printDestReg(response, 0, destSize); 46 response << ", "; 47 printSrcReg(response, 0, srcSize); 48 response << ", "; 49 printSrcReg(response, 1, srcSize); 50 return response.str(); 56 std::stringstream response; local 58 printMnemonic(response, instMne [all...] |
H A D | microregop.cc | 84 std::stringstream response; local 86 printMnemonic(response, instMnem, mnemonic); 87 printDestReg(response, 0, dataSize); 88 response << ", "; 89 printSrcReg(response, 0, dataSize); 90 response << ", "; 91 printSrcReg(response, 1, dataSize); 92 return response.str(); 98 std::stringstream response; local 100 printMnemonic(response, instMne [all...] |
/gem5/src/arch/sparc/insts/ |
H A D | trap.cc | 40 std::stringstream response; local 42 printMnemonic(response, mnemonic); 43 ccprintf(response, " "); 44 printReg(response, _srcRegIdx[0]); 45 ccprintf(response, ", 0x%x", trapNum); 46 ccprintf(response, ", or "); 47 printReg(response, _srcRegIdx[1]); 48 return response.str();
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H A D | mem.cc | 41 std::stringstream response; local 45 printMnemonic(response, mnemonic); 47 printReg(response, _srcRegIdx[0]); 48 ccprintf(response, ", "); 50 ccprintf(response, "["); 52 printSrcReg(response, !store ? 0 : 1); 53 ccprintf(response, " + "); 55 printSrcReg(response, !store ? 1 : 2); 56 ccprintf(response, "]"); 58 ccprintf(response, ", "); 68 std::stringstream response; local [all...] |
H A D | blockmem.cc | 40 std::stringstream response; local 44 printMnemonic(response, mnemonic); 46 printReg(response, _srcRegIdx[0]); 47 ccprintf(response, ", "); 49 ccprintf(response, "[ "); 50 printReg(response, _srcRegIdx[!save ? 0 : 1]); 51 ccprintf(response, " + "); 52 printReg(response, _srcRegIdx[!save ? 1 : 2]); 53 ccprintf(response, " ]"); 55 ccprintf(response, ", "); 65 std::stringstream response; local [all...] |
H A D | priv.cc | 42 std::stringstream response; local 44 printMnemonic(response, mnemonic); 46 return response.str(); 52 std::stringstream response; local 54 printMnemonic(response, mnemonic); 56 ccprintf(response, " %%%s, ", regName); 57 printDestReg(response, 0); 59 return response.str(); 65 std::stringstream response; local 67 printMnemonic(response, mnemoni 85 std::stringstream response; local [all...] |
H A D | branch.cc | 49 std::stringstream response; local 51 printMnemonic(response, mnemonic); 52 printRegArray(response, _srcRegIdx, _numSrcRegs); 54 response << ", "; 55 printDestReg(response, 0); 57 return response.str(); 63 std::stringstream response; local 65 printMnemonic(response, mnemonic); 66 printRegArray(response, _srcRegIdx, _numSrcRegs); 68 response << ", "; 80 std::stringstream response; local [all...] |
H A D | micro.cc | 39 std::stringstream response; local 40 printMnemonic(response, mnemonic); 41 return response.str();
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H A D | integer.cc | 85 std::stringstream response; local 87 if (printPseudoOps(response, pc, symtab)) 88 return response.str(); 89 printMnemonic(response, mnemonic); 90 printRegArray(response, _srcRegIdx, _numSrcRegs); 92 response << ", "; 93 printDestReg(response, 0); 94 return response.str(); 100 std::stringstream response; local 102 if (printPseudoOps(response, p 118 std::stringstream response; local [all...] |
H A D | nop.hh | 67 std::stringstream response; variable 68 printMnemonic(response, mnemonic); 69 return response.str();
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H A D | nop.cc | 68 std::stringstream response; local 69 printMnemonic(response, mnemonic); 70 return response.str();
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/gem5/src/cpu/minor/ |
H A D | fetch1.cc | 186 /* Submit the translation request. The response will come 234 /* This FetchRequest becomes SenderState to allow the response to be 253 Fetch1::handleTLBResponse(FetchRequestPtr response) argument 257 if (response->fault != NoFault) { 260 response->fault->name(), 261 (response->request->hasPaddr() ? 262 response->request->getPaddr() : 0), 263 response->request->getVaddr()); 266 minorTraceResponseLine(name(), response); local 268 DPRINTF(Fetch, "Got ITLB response\ 417 recvTimingResp(PacketPtr response) argument 539 processResponse(Fetch1::FetchRequestPtr response, ForwardLineData &line) argument 670 Fetch1::FetchRequestPtr response = transfers.front(); local [all...] |
H A D | lsq.cc | 268 DPRINTFS(MinorMem, (&port), "Received translation response for" 306 /* Submit the translation request. The response will come through 338 DPRINTFS(MinorMem, (&port), "Received translation response for fragment" 575 /* Might as well make the overall/response packet here */ 624 LSQ::SplitDataRequest::retireResponse(PacketPtr response) 631 response->req->getVaddr(), response->req->getSize(), 632 request->getVaddr() - response->req->getVaddr(), 641 } else if (response->isError()) { 645 packet->copyError(response); 1287 recvTimingResp(PacketPtr response) argument 1512 popResponse(LSQ::LSQRequestPtr response) argument [all...] |
H A D | fetch1.hh | 117 RequestIssuing, /* Issued to memory, must wait for response */ 139 * picking apart the response packet */ 332 /** Convert a response to a ForwardLineData */ 333 void processResponse(FetchRequestPtr response, 369 /** Handle pushing a TLB response onto the right queue */ 370 void handleTLBResponse(FetchRequestPtr response); 376 /** Print the appropriate MinorLine line for a fetch response */ 378 FetchRequestPtr response) const;
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H A D | execute.hh | 233 LSQ::LSQRequestPtr response, BranchData &branch,
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H A D | execute.cc | 322 LSQ::LSQRequestPtr response, BranchData &branch, Fault &fault) 329 PacketPtr packet = response->packet; 363 DPRINTF(MinorMem, "Trying to commit error response: %s\n", 366 fatal("Received error response packet for inst: %s\n", *inst); 370 DPRINTF(MinorMem, "Memory response inst: %s addr: 0x%x size: %d\n", 390 if (response->needsToBeSentToStoreBuffer()) 391 lsq.sendStoreToStoreBuffer(response); 398 lsq.popResponse(response); 921 * handleMemResponse -- handles the response packet, done by 927 * memory queues. When a response come 321 handleMemResponse(MinorDynInstPtr inst, LSQ::LSQRequestPtr response, BranchData &branch, Fault &fault) argument [all...] |
H A D | lsq.hh | 232 * (!sentAllPackets) and by retiring response using retireResponse */ 245 /** Retire a response packet into the LSQRequest packet possibly 303 /** Keep the given packet as the response packet 370 /** Keep the given packet as the response packet 415 /** TLB response interface */ 454 /** For loads, paste the response data into the main 455 * response packet */ 573 * Execute::commitInst can pick up the memory response for a request 657 * cascaded on the end of a memory response/TLB response even [all...] |
/gem5/ext/googletest/googlemock/scripts/ |
H A D | upload.py | 201 response = self.opener.open(req) 202 response_body = response.read() 230 response = self.opener.open(req) 232 response = e 233 if (response.code != 302 or 234 response.info()["location"] != continue_location): 235 raise urllib2.HTTPError(req.get_full_url(), response.code, response.msg, 236 response.headers, response [all...] |
/gem5/ext/googletest/googletest/scripts/ |
H A D | upload.py | 201 response = self.opener.open(req) 202 response_body = response.read() 230 response = self.opener.open(req) 232 response = e 233 if (response.code != 302 or 234 response.info()["location"] != continue_location): 235 raise urllib2.HTTPError(req.get_full_url(), response.code, response.msg, 236 response.headers, response [all...] |
/gem5/configs/common/ |
H A D | HMC.py | 157 # Latency to forward a response via the interconnect [1](two levels of 159 parser.add_argument("--xbar-response-latency", default=2, action="store", 177 # Number of packets (not flits) to store at the response side of the serial 181 response side of the serial link") 260 # size of response buffer within crossbar, used for modelling extra latency 261 # when the response received from non-local vault 264 response side of the crossbar")
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/gem5/src/mem/ |
H A D | packet.hh | 156 NeedsResponse, //!< Requester needs response from target 162 IsError, //!< Error response 177 /// Corresponding response for requests; InvalidCmd if no 178 /// response is applicable. 179 const Command response; member in struct:MemCmd::CommandInfo 235 return commandInfo[cmd].response; 392 * packet's response so that the SimObject in question can quickly 400 * predecessing SenderState is restored when the response comes 478 * to a request. A response packet must return the sender state 537 // we should never check if a response needsWritabl [all...] |