Searched refs:res0 (Results 1 - 5 of 5) sorted by relevance
/gem5/util/term/ |
H A D | term.c | 114 struct addrinfo *res, *res0; local 120 res0 = res; 122 if ((s = socket(res0->ai_family, res0->ai_socktype, 123 res0->ai_protocol)) < 0) 126 if (connect(s, res0->ai_addr, res0->ai_addrlen) == 0) 131 } while ((res0 = res0->ai_next) != NULL);
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/gem5/src/dev/arm/ |
H A D | gic_v3_cpu_interface.hh | 105 Bitfield<63, 1> res0; member in class:Gicv3CPUInterface 110 Bitfield<63, 1> res0; member in class:Gicv3CPUInterface 115 Bitfield<63, 2> res0; member in class:Gicv3CPUInterface 121 Bitfield<63, 3> res0; member in class:Gicv3CPUInterface 128 Bitfield<63, 4> res0; member in class:Gicv3CPUInterface 136 Bitfield<63, 4> res0; member in class:Gicv3CPUInterface 246 Bitfield<63, 8> res0; member in class:Gicv3CPUInterface
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/gem5/src/arch/arm/ |
H A D | miscregs.cc | 3177 .res0(0x8d22c600) 3201 .res0(0xff40) // [31:16], [6] 3209 .res0(0x0512c7c0 | (EnDB ? 0 : 0x2000) 3615 .res0(0x1f); 3977 .res0( 0x20440 | (EnDB ? 0 : 0x2000) 3994 .res0(0x0512c7c0 | (EnDB ? 0 : 0x2000) 4021 .res0(0x0512c7c0 | (EnDB ? 0 : 0x2000) 4355 .res0(0x7ff) 4507 .res0(0xffffff00) // [31:8] 4520 .res0( [all...] |
H A D | isa.hh | 126 uint64_t res0() const { return _res0; } function in struct:ArmISA::ISA::MiscRegLUTEntry 147 chain res0(uint64_t mask) const { function in class:ArmISA::ISA::MiscRegLUTEntryInitializer
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H A D | isa.cc | 439 if (val & reg.res0()) { 440 DPRINTF(MiscRegs, "Reading MiscReg %s with set res0 bits: %#x\n", 441 miscRegName[misc_reg], val & reg.res0());
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