/gem5/src/arch/riscv/ |
H A D | types.hh | 77 return npc() != pc() + sizeof(MachInst)/2 || 80 return npc() != pc() + sizeof(MachInst) ||
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H A D | decoder.cc | 103 nextPC.npc(nextPC.instAddr() + sizeof(MachInst) / 2); 105 nextPC.npc(nextPC.instAddr() + sizeof(MachInst));
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H A D | utility.hh | 110 retPC.pc(curPC.npc());
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/gem5/src/arch/sparc/ |
H A D | remote_gdb.cc | 181 r.npc = htobe((uint32_t)pc.npc()); 197 r.npc = htobe(pc.npc()); 215 pc.npc(r.npc); 216 pc.nnpc(pc.npc() + sizeof(MachInst)); 221 // All registers other than the pc, npc and int regs 231 pc.npc(r.npc); [all...] |
H A D | remote_gdb.hh | 63 uint32_t npc; member in struct:SparcISA::RemoteGDB::SPARCGdbRegCache::__anon7 87 uint64_t npc; member in struct:SparcISA::RemoteGDB::SPARC64GdbRegCache::__anon8
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H A D | nativetrace.cc | 75 regVal = pc.npc(); 82 checkReg("npc", regVal, realRegVal);
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H A D | utility.hh | 51 ret.pc(curPC.npc());
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H A D | faults.cc | 337 tc->setMiscRegNoEffect(MISCREG_TNPC, pc.npc() & pcMask); 420 tc->setMiscRegNoEffect(MISCREG_TNPC, pc.npc() & pcMask); 553 pc.npc(NPC); 596 pc.npc(NPC);
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/gem5/src/arch/generic/ |
H A D | types.hh | 151 Addr npc() const { return _npc; } function in class:GenericISA::SimplePCState 152 void npc(Addr val) { _npc = val; } function in class:GenericISA::SimplePCState 158 npc(val + sizeof(MachInst)); 164 npc(val); 173 return this->npc() != this->pc() + sizeof(MachInst); 189 ccprintf(os, "(%#x=>%#x)", pc.pc(), pc.npc()); 231 return this->npc() != this->pc() + sizeof(MachInst) || 288 pc.pc(), pc.npc(), pc.upc(), pc.nupc()); 319 return !(this->nnpc() == this->npc() + sizeof(MachInst) && 320 (this->npc() [all...] |
/gem5/src/arch/arm/ |
H A D | types.hh | 242 npc(val + (thumb() ? 2 : 4)); 297 return ((this->pc() + this->size()) != this->npc()); 391 npc(pc() + (thumb() ? 2 : 4)); 437 npc(val); // AArch64 doesn't force PC alignment, a PC 440 npc(val &~ mask(nextThumb() ? 1 : 2)); 446 return npc(); 475 npc(newPC);
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H A D | decoder.cc | 182 pc.npc(pc.pc() + inst_size);
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H A D | nativetrace.cc | 115 newState[STATE_PC] = tc->pcState().npc();
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/gem5/util/statetrace/arch/sparc/ |
H A D | tracechild.hh | 81 //while this equals npc for most instructions, it doesn't for all of 83 int getTargets(uint32_t inst, uint64_t pc, uint64_t npc,
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H A D | tracechild.cc | 207 SparcTraceChild::getTargets(uint32_t inst, uint64_t pc, uint64_t npc, argument 230 target1 = npc; 231 target2 = npc + 4; 253 target1 = npc + 4; 255 target1 = npc; 258 target1 = npc;
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/gem5/src/arch/mips/ |
H A D | utility.hh | 52 ret.pc(curPC.npc());
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H A D | faults.cc | 122 bool delay_slot = pc.pc() + sizeof(MachInst) != pc.npc();
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H A D | mt.hh | 144 tc->setMiscReg(MISCREG_TC_RESTART, pc.npc()); 148 pc.pc(), pc.npc());
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/gem5/src/arch/x86/ |
H A D | types.hh | 320 return (this->npc() != this->pc() + size()) ||
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H A D | decoder.hh | 338 nextPC.npc(nextPC.pc() + size);
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H A D | nativetrace.cc | 90 rip = tc->pcState().npc();
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H A D | process.cc | 157 pc.npc(vsyscallPage.base + vsyscallPage.vsysexitOffset);
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/gem5/src/arch/alpha/ |
H A D | stacktrace.cc | 146 Addr pc = tc->pcState().npc();
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